Display driving device, source driver and display device

Abstract

The invention provides a display driving device, a source driver and a display device. The display driving device includes a level shifter and a digital-to-analog converter (DAC). The level shifter is configured to receive image data and a bias control signal, generate decoded image data including a plurality of bits by level-shifting the image data, and control an output bias current of the decoded image data based on the bias control signal. The DAC is configured to receive decoded image data and a plurality of gamma voltages, select one of the plurality of gamma voltages based on the decoded image data, and output the selected gamma voltage.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0117900 filed in the Korean Intellectual Property Office on September 5, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a display driving device, a source driver and a display device. Background Art

[0003] Generally, a display panel displays an image to provide various visual information to a user. The display panel includes a plurality of pixels, and each pixel represents light of a specific brightness to display an image. A display driver integrated circuit (DDI) is used to drive the pixels.

[0004] As the number of bits of data representing gray levels increases, the number of level shifters required for one channel may increase, and as the number of DDI channels increases to drive a high-resolution display panel, the number of DDI level shifters operating together may increase in a short time. Since multiple level shifters operate together in a short time, the level of peak current may increase. Ground bounce, which indicates a temporary increase in ground voltage due to a high level of peak current, may affect adjacent circuits, modules, and interfaces. Summary of the invention

[0005] The present disclosure relates to a display driving device, a source driver, and a display device including the same. The display driving device includes a display driving device that generates a low-level peak current and a display driving device that displays a high-resolution image with a high grayscale expression.

[0006] Generally, according to some aspects, a display driving device includes: a level shifter configured to: receive image data and a bias control signal, generate decoded image data including a plurality of bits by level shifting the image data, and control an output bias current of the decoded image data based on the bias control signal; and a digital-to-analog converter (DAC) configured to: receive the decoded image data and a plurality of gamma voltages, select one of the plurality of gamma voltages based on the decoded image data, and output the selected gamma voltage.

[0007] Generally, according to some aspects, a source driver includes: multiple amplifier regions, each amplifier region includes: a level shifter configured to output multiple bits of decoded image data, a digital-to-analog converter (DAC) configured to select one of multiple gamma voltages based on the decoded image data, and an amplifier configured to output a data signal obtained by amplifying the selected gamma voltage to a corresponding source line among multiple source lines; and a source driver includes: a bias circuit configured to generate a bias control signal that limits an output bias current of a level shifter included in each of the multiple amplifier regions.

[0008] Generally, according to some aspects, a display device includes: a pixel array configured to include a plurality of pixels; a timing controller configured to: receive an image signal and a driving control signal from the outside, generate a plurality of image data by dividing the image signal, and generate a bias start signal based on the driving control signal; a plurality of amplifier regions configured to: receive image data and a bias control signal, generate decoded image data by level-shifting the image data, control a level of an output bias current of the decoded image data based on a level of the bias control signal, receive the decoded image data and a plurality of gamma voltages, select one of the plurality of gamma voltages based on the decoded image data, and output the selected gamma voltage; and a bias circuit configured to: receive a bias start signal that controls a bias control signal to be output at a first level, and generate a bias control signal of a second level different from the first level with reference to data stored in a one-time programmable (OTP) memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example block diagram of a display device is shown.

[0010] Figure 2 Some components of an example of a source driver are shown.

[0011] Figure 3 A circuit diagram schematically illustrating a buffer and level shift circuit of an example of a source driver is shown.

[0012] Figure 4 Graphs of output voltage and discharge current showing an example of a level shifter are shown.

[0013] Figure 5 A circuit diagram showing an example of restoration for a level shifter is shown.

[0014] Figure 6 Graphs of output voltage and discharge current showing another example of a level shifter are shown.

[0015] Figure 7A block diagram showing an example of a level shifter is shown.

[0016] Figure 8 A circuit diagram for recovery of another example of a level shifter is shown.

[0017] Fig. 9 Graphs of output voltage and discharge current showing another example of a level shifter are shown.

[0018] Fig.10 A block diagram showing another example of a level shifter is shown.

[0019] Fig.11 A circuit diagram for recovery of another example of a level shifter is shown.

[0020] Fig.12 Graphs of output voltage and discharge current showing another example of a level shifter are shown.

[0021] Fig.13 A block diagram showing another example of a level shifter is shown.

[0022] Fig.14 A block diagram showing another example of a level shifter is shown.

[0023] Fig.15 A circuit diagram for recovery of another example of a level shifter is shown.

[0024] Fig.16 A circuit diagram schematically illustrating a buffer and a level shift circuit of another example of a source driver is shown.

[0025] Fig.17 A circuit diagram schematically illustrating a buffer and a level shift circuit of another example of a source driver is shown.

[0026] Fig.18 Graphs showing simulation results of output voltage and discharge current for an example of a level shifter are shown.

[0027] Fig.19 Graphs showing simulation results of output voltage and discharge current of another example of a level shifter are shown.

[0028] Fig. 20 A diagram for describing an example of a display system is shown. DETAILED DESCRIPTION

[0029] In the following detailed description, certain embodiments of the present disclosure have been shown and described by way of illustration. As those skilled in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit and scope of the present disclosure.

[0030] Figure 1 An example block diagram of a display device is shown.

[0031] Reference Figure 1 The display device 100 includes a pixel array 110 , a gate driver 120 , a source driver 130 and a timing controller 140 .

[0032] A plurality of pixels PX for displaying an image may be located in the pixel array 110. Each pixel PX may be connected to a corresponding source line SL among a plurality of source lines and a corresponding gate line GL among a plurality of gate lines. If a gate signal is provided to the gate line GL, the pixel PX may receive a data signal from the source line SL. The pixel PX may represent light of a specific brightness corresponding to the input data signal. The pixel PX may display an image in units of one frame.

[0033] If the display device 100 is an organic light emitting diode display, each pixel PX may include a plurality of transistors each including a driving transistor and an organic light emitting diode. The driving transistor included in the pixel PX may supply a current corresponding to a data signal to the organic light emitting diode, and thus the organic light emitting diode may emit light having a predetermined brightness. If the display device 100 is a liquid crystal display, each pixel PX may include a switching transistor and a liquid crystal capacitor. The pixel PX may control the transmittance of the liquid crystal in response to the data signal so that light of a specific brightness is provided to the outside.

[0034] exist Figure 1 , the pixel PX is shown as being connected to one source line SL and one gate line GL, and the connection structure of the signal line of the pixel PX of the display device is not limited thereto. For example, various signal lines may be additionally connected in response to the circuit structure of the pixel PX. In some embodiments, the pixel PX may be implemented in various currently known forms.

[0035] The gate driver 120 may provide a plurality of gate signals G1, G2, ..., and Gh. The gate signals G1, G2, ..., and Gh may be pulse signals having an enable level and a disable level. The gate signals G1, G2, ..., and Gh may be applied to a plurality of gate lines GL. If a gate signal of an enable level is applied to the gate line GL connected to the pixel PX, a data signal applied to the source line SL connected to the pixel PX may be transmitted to the pixel PX. The gate driver 120 may provide the gate signals G1, G2, ..., and Gh during a plurality of horizontal periods. One frame may include a plurality of horizontal periods.

[0036] The source driver 130 may receive data DATA in the form of a digital signal from the timing controller 140, and may convert the data DATA into data signals S1, S2, ..., Sk in the form of an analog signal. Here, the data DATA may include grayscale information corresponding to each pixel PX for displaying the image signal IS on the pixel array 110. The source driver 130 may transmit a plurality of data signals S1, S2, ..., and Sk to the pixel array 110 according to a source driver control signal CONT2 provided from the timing controller 140. The source driver 130 may be referred to as a data driver.

[0037] The source driver 130 may be electrically connected to the plurality of source lines SL. The source driver 130 may transmit a plurality of data signals S1, S2, . . . , and Sk to the source lines SL electrically connected thereto.

[0038] The source driver 130 may include a shift register 131, a plurality of amplifier regions 132a, 132b, . . . , and 132j, a bias circuit 136, and a gamma voltage generator 138. Each component included in the source driver 130 is not limited to Figure 1 , and additional components may be included in the source driver 130 .

[0039] The shift register 131 may sample the data DATA in response to the horizontal synchronization signal HSYNC, and may provide the sampled image data LD1, ..., and LDk to the amplifier regions 132a, 132b, ..., and 132j. The data DATA may include a plurality of source data corresponding to the source lines SL, and each source data may include a plurality of bits. The shift register 131 may generate image data LD1, ..., and LDk having a plurality of bits by sampling each bit of the data DATA. The horizontal synchronization signal HSYNC may be a signal having a predetermined period, and may be a signal determining a scanning period of the pixels PX connected to the respective gate lines GL.

[0040] Each of the amplifier regions 132a, 132b, . . . , and 132j ​​may include a level shifter 133, a digital-to-analog converter (DAC) 134, and an amplifier (AMP) 135. Hereinafter, description will be made with reference to the amplifier region 132a that outputs the data signal S1.

[0041] The level shifter 133 may level-shift the image data LD1. The level shifter 133 may receive the image data LD1 at a low voltage level and output decoded image data HD1 at a high voltage level to the DAC 134. In some embodiments, the image data LD1 may include a plurality of bits, and the level shifter 133 may generate decoded image data HD1 having a plurality of bits by level-shifting the bits of the image data LD1. The level shifter 133 may receive the digital signal LD1 to provide the DAC 134 with the decoded image data HD1 having a level that has been shifted to swing between target voltage levels.

[0042] In some embodiments, the level shifter 133 may control the output bias current of the decoded image data HD1 based on the bias control signal IB. When the output bias current is controlled, the conversion rate of the decoded image data HD1 may be controlled. In some embodiments, the level shifter 133 may control the output bias currents of the bits of the decoded image data HD1 to have the same size or different sizes. For example, the level shifter 133 may control the output bias current of the first bit of the decoded image data HD1 and the output bias current of the second bit higher than the first bit to be a first level. Alternatively, the level shifter 133 may control the output bias current of the first bit of the decoded image data HD1 to be a first level, and may control the output bias current of the second bit higher than the first bit to be a second level higher than the first level. In some embodiments, the level shifter 133 may control the output bias current of at least one bit among the bits of the decoded image data HD1. For example, the level shifter 133 may control the output bias current of the bits other than the most significant bit (MSB). In some embodiments, the level shifters 133 included in the amplifier regions 132a, 132b, ..., and 132j ​​may collectively control the output bias current of the same bit based on the bias control signal IB. That is, the level shifters 133 included in the amplifier regions 132a, 132b, ..., and 132j ​​and outputting the first bit among the bits of the decoded image data HD1 may receive the same bias control signal IB. The level shifters 133 outputting the first bit may control the output bias current of the first bit of the decoded image data HD1 to be the same value.

[0043] The DAC 134 may output an analog signal AD1 corresponding to the decoded image data HD1. The DAC 134 may receive a plurality of gamma voltages GV and the decoded image data HD1. The gamma voltages GV may be provided by the gamma voltage generator 138. The DAC 134 may select at least some of the gamma voltages GV from among the gamma voltages GV based on the decoded image data HD1 to transmit them as input voltages to the amplifier 135 through the output port.

[0044] The amplifier 135 may output the input voltage transferred from the DAC 134 as the data signal Si to the pixel connected to the corresponding source line.

[0045] The bias circuit 136 may supply the bias control signal IB to the level shifter 133 of the amplifier regions 132a, 132b, ..., and 132j. The bias circuit 136 may output the bias control signal IB and / or may control the size of the bias control signal IB based on the bias start signal C1 included in the source driver control signal CONT2. In some embodiments, the bias circuit 136 may include a one-time programmable (OTP) memory 137. The bias circuit 136 may control the size of the bias control signal IB with reference to data stored in the OTP memory 137. For example, if the bias start signal CI is input, the bias circuit 136 outputting the bias control signal IB of the first level may output the bias control signal IB of the second level different from the first level with reference to the data stored in the OTP memory 137. That is, the bias circuit 136 may perform bias fine adjustment with reference to the data stored in the OTP memory 137. In some embodiments, the data stored in the OTP memory 137 may have different values ​​for each source driver 130. That is, the source driver 130 manufactured through the same process may store different values ​​in the OTP memory 137 according to on-chip variation (OCV).

[0046] The gamma voltage generator 138 may determine the number of gamma voltages GV based on the number of bits of the decoded image data HD1, and may determine the size of each gamma voltage GV based on the operating conditions of the display device 100, the setting of the gamma voltage register, etc. In some embodiments, the number of gamma voltages GV may be determined according to the number of bits of the image data. For example, if the decoded image data HD1 is 8-bit data, the number of gamma voltages GV may be 2. 8 or less, and if the decoded image data HD1 is 10-bit data, the number of gamma voltages GV may be 2 10 That is, if the decoded image data HD1 is data having n bits, the gamma voltage GV may have 2 n The gamma voltage generator 138 may determine the size of each of the gamma voltages GV by selecting at least some of the plurality of reference voltages.

[0047] The timing controller 140 may receive an image signal IS and a driving control signal CTRL from a host device, and may control the gate driver 120 and the source driver 130. Here, the host device may be a computing device or system that externally controls the display device 100 to display an image desired by a user on the pixel array 110. The driving control signal CTRL provided from the host device may include a control command, setting data, etc. for controlling the gate driver 120 and the source driver 130. The timing controller 140 may control the gate driver 120 and the source driver 130 based on the driving control signal CTRL. For example, the driving control signal CTRL may include a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, a main clock signal MCLK, and a data enable signal DE. The timing controller 140 may divide the image data IS in units of one frame based on the vertical synchronization signal VSYNC, and may generate data DATA by dividing the image data IS in units of gate lines GL based on the horizontal synchronization signal HSYNC. The timing controller 140 may perform control to synchronize operations of the source driver 130 and the gate driver 120 by transmitting the gate driver control signal CONT1 and the source driver control signal CONT2 to the gate driver 120 and the source driver 130 , respectively.

[0048] The pixel array 110 and the gate driver 120 may be implemented on the same substrate, and the source driver 130 and the timing controller 140 may be configured as a single chip. In some embodiments, the pixel array 110, the gate driver 120, the source driver 130, and the timing controller 140 may be implemented on the same substrate. In some embodiments, the gate driver 120, the source driver 130, and the timing controller 140 may be configured as a single chip. The gate driver 120 may be implemented as a separate semiconductor die, chip, or module connected to the pixel array 110. Additionally, a portion of the gate driver 120 may be located on the substrate where the pixel array 110 is located, and the remaining portion may be included in a separate chip.

[0049] Figure 2 Some components of an example of a source driver are shown.

[0050] Reference Figure 2 , one level shifter 210 and one DAC 220 corresponding to one source line are shown. The level shifter 210 receives 3-bit image data LD[2:0] and outputs 3-bit decoded image data HD[2:0]A and HD[2:0]B. The DAC 220 receives 3-bit decoded image data HD[2:0]A and HD[2:0]B and outputs 2-bit decoded image data HD[2:0]A and HD[2:0]B based on the 3-bit decoded image data HD[2:0]A and HD[2:0]B. 3(=8) gamma voltages GV0, ..., and GV7 are used as analog signals AD. Hereinafter, an example of outputting analog signals AD based on 3-bit image data LD[2:0] will be described, but the present disclosure is applicable even when outputting analog signals based on n-bit image data and is not limited to the following example. Fig.14 In the embodiment of the present invention, a level shifter which receives 5-bit image data and outputs 5-bit decoded image data will be described. The 5-bit decoded image data will be used to select 2 5 One of (=32) gamma voltages is used as an analog signal.

[0051] The level shifter 210 may be connected to the DAC 220 and may output decoded image data HD[2:0]A and HD[2:0]B to the DAC 220. The level shifter 210 may include a plurality of level shift circuits 211a, 211b, and 211c and a plurality of buffers 212a, 212b, and 212c.

[0052] The level shift circuits 211a, 211b, and 211c may receive the image data LD[2:0], may level-shift the image data LD[2:0] to the first voltage VM or the second voltage VL, and may supply the level-shifted data MD[2:0] to the buffers 212a, 212b, and 212c.

[0053] The buffers 212a, 212b, and 212c receive the data MD[2:0], may level-shift the data MD[2:0] to the third voltage VDD or the fourth voltage VSS, and may output the level-shifted decoded image data HD[2:0]A and HD[2:0]B. The buffers 212a, 212b, and 212c may output the decoded image data HD[2:0]A obtained by inverting the data MD[2:0] and the decoded image data HD[2:0]B obtained by inverting the decoded image data HD[2:0]A. In some embodiments, the third voltage VDD may be higher than the first voltage VM, and the fourth voltage VSS may be lower than the second voltage VL.

[0054] Buffers 212a, 212b, and 212c may output upper bits HD[2]A and HD[2]B, middle bits HD[1]A and HD[1]B, and lower bits HD[0]A and HD[0]B, respectively.

[0055] The DAC 220 may output one of a plurality of gamma voltages GV0, . . . , and GV7 as an analog signal AD based on the input decoded image data HD[2:0]A and HD[2:0]B.

[0056] The DAC 220 may include a plurality of stages STA2, STA1, and STA0. The stages STA2, STA1, and STA0 may input high bits HD[2]A and HD[2]B, middle bits HD[1]A and HD[1]B, and low bits HD[0]A and HD[0]B, respectively. The output terminal of each of the stages STA2, STA1, and STA0 may be connected to the input terminal of the next stage. For example, the output terminal of the stage STA2 may be connected to the input terminal of the next stage STA1.

[0057] The level STA2 receiving the high bits HD[2]A and HD[2]B may include receiving 2 3 The gamma voltages GV0, ..., and GV7 are 2 2 A decoder (DEC) 221a is provided. The decoder 221a may receive two gamma voltages GV0 and GV7, GV2 and GV5, GV1 and GV6, or GV3 and GV4, and may output a gamma voltage according to the bit HD[2] of the decoded image data. The decoder 221a may include a P-type decoder (PDEC) 223a and an N-type decoder (NDEC) 222a. The bit HD[2]A of the decoded image data is provided to the gate of the transistor included in the P-type decoder 223a, and the bit HD[2]B of the decoded image data may be provided to the gate of the transistor included in the N-type decoder 222a. At least one of the P-type decoder 223a and the N-type decoder 222a included in the same decoder 221a may output one of the two input gamma voltages GV0 and GV7, GV2 and GV5, GV1 and GV6, or GV3 and GV4.

[0058] The stage STA1 receiving the middle bits HD[1]A and HD[1]B may include receiving the 2 bits outputted from the previous stage STA2. 2 2 of the gamma voltage 1 The decoder 221b may receive two gamma voltages and may output a gamma voltage according to the bit HD[1] of the decoded image data. The decoder 221b may include a P-type decoder 223b and an N-type decoder 222b. The bit HD[1]A of the decoded image data is provided to the gate of the transistor included in the P-type decoder 223b, and the bit HD[1]B of the decoded image data may be provided to the gate of the transistor included in the N-type decoder 222b.

[0059] The stage STA0 receiving the lower bits HD[0]A and HD[0]B may include receiving the 2 bits outputted from the previous stage STA1. 1 2 of the gamma voltage 0The decoder 221c may receive two gamma voltages and may output a gamma voltage according to the bit HD[0] of the decoded image data. The decoder 221c may include a P-type decoder 223c and an N-type decoder 222b. The bit HD[0]A of the decoded image data may be provided to the gate of the transistor included in the P-type decoder 223c, and the bit HD[0]B of the decoded image data may be provided to the gate of the transistor included in the N-type decoder 222c.

[0060] Will refer to Figure 3 The level shift circuits 211a, 211b, and 211c and the buffers 212a, 212b, and 212c are described.

[0061] Figure 3 A circuit diagram schematically illustrating a buffer and level shift circuit of an example of a source driver is shown.

[0062] Reference Figure 3 The level shift circuit 310 includes cross-connected inverters, and the cross-connected inverters include transistors T1 and T2 connected in series between a first voltage VM and a second voltage VL, and transistors T3 and T4 connected in series between the first voltage VM and the second voltage VL.

[0063] The bit LD[2]A of the image data may be provided to the gate of the transistor T2, and the bit LD[2]B in which the bit LD[2]A is inverted may be provided to the gate of the transistor T4. The bit MD[2]A in which the bit LD[2]A of the image data is inverted and amplified may be output from the output terminal OUT1.

[0064] The buffer 320 may include 2-stage inverters 321a and 321b. The first-stage inverter 321a may include transistors PT1 and NT1 connected in series between the third voltage VDD and the fourth voltage VSS, and the second-stage inverter 321b may include transistors PT2 and NT2 connected in series between the third voltage VDD and the fourth voltage VSS. The input terminal of the first-stage inverter 321a may be connected to the output terminal OUT1 of the level shift circuit 310. The output terminal OUT2 may be connected to the gate of the transistor of the P-type decoder 223a included in the decoder 221a. The input terminal of the second-stage inverter 321b may be connected to the output terminal OUT2 of the first-stage inverter 321a.

[0065] The bit MD[2]A inverted and amplified by the level shift circuit 310 may be input to the input terminal of the first stage inverter 321a. The bit HD[2]A inverted and amplified by the bit MD[2]A may be output from the output terminal OUT2 of the first stage inverter 321a.

[0066] The bit HD[2]A inverted and amplified by the first-stage inverter 321a may be input to the input terminal of the second-stage inverter 321b. The bit HD[2]B inverted and amplified by the bit HD[2]A may be output from the output terminal OUT3 of the second-stage inverter 321b. The output terminal OUT3 may be connected to the gate of the transistor of the N-type decoder 222a included in the decoder 221a. If the bit LD[2]A of the image data is changed from the first level V1 to the second level V2, the bit MD[2]A may be changed from the first voltage VM to the second voltage VL. Thereafter, the transistor PT1 of the first-stage inverter 321a may be turned on, and in order to charge the input capacitor C1 of the gate of the transistor of the P-type decoder 223a, the charging current IC may flow from the third voltage VDD to the input capacitor C1 through the transistor PT1. When the input capacitor C1 is charged, the bit HD[2]A may be changed from the fourth voltage VSS to the third voltage VDD. Afterwards, the transistor NT2 of the second-stage inverter 321b may be turned on, and in order to discharge the input capacitor C2 of the gate of the transistor of the N-type decoder 222a, the discharge current ID may flow from the input capacitor C2 to the fourth voltage VSS through the transistor NT2. When the input capacitor C2 is discharged, the bit HD[2]B may be converted from the third voltage VDD to the fourth voltage VSS.

[0067] The bit HD[2]A of the decoded image data may be provided to the gates of the transistors of the four P-type decoders 223a, the bit HD[1]A of the decoded image data may be provided to the gates of the transistors of the two P-type decoders 223b, and the bit HD[0]A of the decoded image data may be provided to the gates of the transistors of the one P-type decoder 223c. Therefore, the time for charging the four input capacitors C1 to which the bit HD[2]A of the decoded image data is applied is the longest. The bit HD[2]B of the decoded image data may be provided to the gates of the transistors of the four N-type decoders 222a, the bit HD[1]B of the decoded image data may be provided to the gates of the transistors of the two N-type decoders 222b, and the bit HD[0]B of the decoded image data may be provided to the gates of the transistors of the one N-type decoder 222c. Therefore, the time for discharging the four input capacitors C2 to which the bit HD[2]B of the decoded image data is applied is the longest. Therefore, the time for outputting the analog signal AD may be determined by the time when the bits HD[2]A and HD[2]B of the decoded image data are switched. In addition, the period between the times when bits HD[0]A and HD[0]B and bits HD[1]A and HD[1]B of the decoded image data are switched when the absolute amount difference of the input capacitance load is relatively small may be shorter than the period between the times when bits HD[2]A and HD[2]B and bits HD[1]A and HD[1]B of the decoded image data are switched. The period between the times when bits HD[1]B and bits HD[0]B are switched is relatively short, so a ground bounce in which the fourth voltage VSS is temporarily increased due to the discharge current ID may occur. This will be referred to as Figure 4 Give a description.

[0068] Figure 4 Graphs of output voltage and discharge current showing an example of a level shifter are shown.

[0069] like Figure 4 As shown in FIG. 2 , the bit HD[0:2]B transitions from the third voltage VDD to the fourth voltage VSS at time point t1. The transition of the bit HD[2]B is completed at time point t2 after the transitions of the bit HD[1]B and the bit HD[0]B are completed. Therefore, the analog signal AD output from the DAC 220 depends on the bit HD[2]B having the lowest conversion rate.

[0070] The period between the time when the bit HD[1]B and the bit HD[0]B are changed is short compared to the period between the time when the bit HD[2]B and the bit HD[1]B are changed, so the discharge currents ID[1] and ID[0] may be generated in a relatively close time. All the discharge currents ID[1] and ID[0] flow in the wire to which the fourth voltage VSS is applied, and the maximum value MC of the total discharge current IDG0 flowing in the wire to which the fourth voltage VSS is applied may exceed the reference value TLC. The fourth voltage VSS may temporarily increase due to the total discharge current IDG0 exceeding the reference value TLC. That is, ground bounce may occur due to the total discharge current IDG0. This affects the buffers 212a, 212b, and 212c receiving the same fourth voltage VSS, and may also cause noise due to coupling in the interface physically adjacent to the wire supplying the fourth voltage VSS.

[0071] In some embodiments, the buffers 212a, 212b, and 212c may control the output bias current of the decoded image data HD[2:0]A and HD[2:0]B based on the same bias control signal IB. Figure 5 Give a description.

[0072] Figure 5 A circuit diagram showing an example of restoration for a level shifter is shown.

[0073] Reference Figure 5 , a plurality of buffers 510a, 510b, and 510c output decoded image data HD[2:0]A and HD[2:0]B. The buffers 510a, 510b, and 510c include 2-stage inverters 511a and 511b, 512a and 512b, and 513a and 513b, respectively. The buffer 510a outputs the upper bits HD[2]A and HD[2]B of the decoded image data, the buffer 510b outputs the middle bits HD[1]A and HD[1]B of the decoded image data, and the buffer 510c outputs the lower bits HD[0]A and HD[0]B of the decoded image data. In some embodiments, the buffers 510a, 510b, and 510c may receive the level-shifted data MD[2]A, MD[1]A, and MD[0]A, respectively.

[0074] The input terminal of the first stage inverter (511a / 512a / 513a) can be connected to the level shift circuit ( Figure 2 The output terminal OUTa of the first-stage inverter (511a / 512a / 513a) may be connected to the gate of the transistor of the P-type decoder (223a / 223b / 223c). Each of the first-stage inverters 511a, 512a, and 513a may include transistors PT1 and NT1 connected in series between the third voltage VDD and the fourth voltage VSS.

[0075] The input terminal of the second-stage inverter (511b / 512b / 513b) may be connected to the output terminal OUTa of the first-stage inverter (511a / 512a / 513a). The output terminal OUTb of the second-stage inverter (511b / 512b / 513b) may be connected to the gate of the transistor of the N-type decoder (222a / 222b / 222c). Each of the second-stage inverters 511b, 512b, and 513b may include transistors PT2, NT2, and BT0a / BT0b / BT0c connected in series between the third voltage VDD and the fourth voltage VSS. For example, transistors PT2 and NT2 may be connected in an inverter structure, the gates of transistors PT2 and NT2 may be connected to the output terminal OUTa of the first-stage inverter (511a / 512a / 513a), and the drains of transistors PT2 and NT2 may be connected to the output terminal OUTb. The bias transistor (BT0a / BT0b / BT0c) may be connected between the source of the transistor NT2 and the fourth voltage VSS. The bias transistor (BT0a / BT0b / BT0c) included in the buffers 510a, 510b, and 510c may be located in an amplifier region corresponding to one source line SL. Additionally, the bias transistor (BT0a / BT0b / BT0c) may be located between an amplifier region including the buffers 510a, 510b, and 510c and an amplifier region adjacent to the amplifier region. This will be described later. Fig.13 In some embodiments, the bias transistors (BT0a / BT0b / BT0c) may have different sizes.

[0076] In some embodiments, the bias transistors (BT0a / BT0b / BT0c) may be located between the N-type decoder ( Figure 2 The bias control signal IB may be input to the gate of the bias transistor (BT0a / BT0b / BT0c). The bias transistor (BT0a / BT0b / BT0c) may limit the discharge current (ID[2] / ID[1] / ID[0]) based on the voltage level of the bias control signal IB. This will refer to Figure 6 describe.

[0077] Figure 6 Graphs of output voltage and discharge current showing another example of a level shifter are shown.

[0078] exist Figure 6 The thin line indicates Figure 4 The output voltage and discharge current of the level shifter in Figure 5 The output voltage and discharge current of the level shifter in Figure 6As shown in FIG. 1 , bit HD[0:2]B changes from the third voltage VDD to the fourth voltage VSS at time point t11. The change of bit HD[2]B is completed at time point t12 after the change of bit HD[1]B and bit HD[0]B is completed. Therefore, from DAC 220 ( Figure 2 ) outputs an analog signal AD that depends on the bit HD[2]B with the lowest conversion rate. Due to the limitation of the discharge current ID[2] by the bias transistor BT0a, the time point t12 is later than the time t2, which is Figure 4 The transition completion time of bit HD[2]B in .

[0079] Due to the limitations of discharge current ID[2], ID[1] and ID[0], Figure 4 Compared with the embodiment of the present invention, the conversion rate of the bit HD[2]B, the bit HD[1]B, and the bit HD[0]B can be lower. As the conversion rate of the bit HD[2]B, the bit HD[1]B, and the bit HD[0]B is reduced, the difference between the period between the time when the bit HD[1]B and the bit HD[0]B are converted and the period between the time when the bit HD[2]B and the bit HD[1]B are converted can be reduced. That is, by limiting the amount of the discharge currents ID[2], ID[1], and ID[0], the maximum value MC0 of the total discharge current IDG1 flowing through the conductive line to which the fourth voltage VSS is applied can be less than or equal to the reference value TLC.

[0080] Therefore, the ground bounce caused by the total discharge current IDG1 can be reduced. This can reduce the influence on the buffers 510a, 510b and 510c receiving the same fourth voltage VSS and the noise caused to the interface physically adjacent to the wire supplying the fourth voltage VSS.

[0081] Figure 7 A block diagram showing an example of a level shifter is shown.

[0082] Reference Figure 7 , the level shifter 700 receives the 3-bit image data LD[2:0] and outputs the 3-bit decoded image data HD[2:0]A and HD[2:0]B. The level shifter 700 is connected to the DAC 220 ( Figure 2 ), and outputs the decoded image data HD[2:0]A and HD[2:0]B to the DAC 220. The level shifter 700 includes a plurality of level shift circuits 711a, 711b, 711c and a plurality of buffers 712a, 712b, 712c.

[0083] The level shift circuits 711a, 711b, and 711c may receive the image data LD[2:0], may level-shift the image data LD[2:0] to the first voltage VM or the second voltage VL, and may supply the level-shifted data MD[2:0] to the buffers 712a, 712b, and 712c.

[0084] The buffers 712a, 712b, and 712c receive the data MD[2:0], may level-shift the data MD[2:0] to the third voltage VDD or the fourth voltage VSS, and may output the level-shifted decoded image data HD[2:0]A and HD[2:0]B. The buffers 712a, 712b, and 712c may output the decoded image data HD[2:0]A obtained by inverting the data MD[2:0] and the decoded image data HD[2:0]B obtained by inverting the decoded image data HD[2:0]A. The buffers 712a, 712b, and 712c may output the upper bits HD[2]A and HD[2]B, the middle bits HD[1]A and HD[1]B, and the lower bits HD[0]A and HD[0]B, respectively.

[0085] In some embodiments, buffers 712b and 712c may control the output bias current of some bits HD[1:0] of the decoded image data based on the same bias control signal IB. The bias control signal IB may not be applied to buffer 712a that outputs the high bit HD[2]. This will refer to Figure 8 describe.

[0086] Figure 8 A circuit diagram for recovery of another example of a level shifter is shown.

[0087] Reference Figure 8 , multiple buffers 810a, 810b and 810c output decoded image data HD[2:0]A and HD[2:0]B. Figure 5 The description of the buffers 510a, 510b, and 510c shown in FIG. 8 is the same as or similar to the description of the buffers 810a, 810b, and 810c. In some embodiments, the plurality of buffers 810a, 810b, and 810c may include first stage inverters 811a, 812a, and 813a.

[0088] Among the second-stage inverters 811b, 812b, and 813b, the second-stage inverters 812b and 813b that receive some bits of data MD[1:0] may include transistors PT2, NT2, and BT0b / BT0c connected in series between a third voltage VDD and a fourth voltage VSS. In some embodiments, some bits MD[1:0] may be bits other than the high bit MD[2]. For example, transistors PT2 and NT2 may be connected in an inverter structure, the gates of transistors PT2 and NT2 may be connected to the output terminal OUTa of the first-stage inverter (812a / 813a), and the drains of transistors PT2 and NT2 may be connected to the output terminal OUTb. A bias transistor (BT0b / BT0c) may be connected between the source of transistor NT2 and the fourth voltage VSS. In some embodiments, the bias transistor (BT0b / BT0c) may be located at the N-type decoder ( Figure 2 The bias control signal IB may be input to the gate of the bias transistor (BT0b / BT0c). The bias transistor (BT0b / BT0c) may limit the discharge current (ID[1] / ID[0]) based on the voltage level of the bias control signal IB. This will refer to Fig. 9 describe.

[0089] Fig. 9 Graphs of output voltage and discharge current showing another example of a level shifter are shown.

[0090] exist Fig. 9 The thin line indicates Figure 4 The output voltage and discharge current of the level shifter in Figure 8 The output voltage and discharge current of the level shifter in Fig. 9 As shown in FIG, bit HD[0:2]B changes from the third voltage VDD to the fourth voltage VSS at time point t21. The change of bit HD[2]B is completed at time point t22 after the change of bit HD[1]B and bit HD[0]B is completed. Therefore, from DAC 220 ( Figure 2 ) output analog signal AD depends on the bit with the lowest conversion rate (HD[2]B). Since the discharge current ID[2] is not limited, the time point t22 can be used as Figure 4 The time point t2 at which the transition of bit HD[2]B is completed is basically the same.

[0091] The discharge currents ID[1] and ID[0] can be limited to the same current amount LC. Due to the limitation of the discharge currents ID[1] and ID[0], Figure 4By limiting the amount of discharge currents ID[1] and ID[0], the maximum value MC1 of the total discharge current IDG2 flowing through the wire to which the fourth voltage VSS is applied can be less than or equal to the reference value TLC.

[0092] Therefore, the ground bounce caused by the total discharge current IDG2 can be reduced. This can reduce the influence on the buffers 810a, 810b and 810c receiving the same fourth voltage VSS and the noise caused to the interface physically adjacent to the wire supplying the fourth voltage VSS.

[0093] Fig.10 A block diagram showing another example of a level shifter is shown.

[0094] Reference Fig.10 , the level shifter 1000 receives the 3-bit image data LD[2:0] and outputs the 3-bit decoded image data HD[2:0]A and HD[2:0]B. The level shifter 1000 is connected to the DAC 220 ( Figure 2 ), and outputs the decoded image data HD[2:0]A and HD[2:0]B to the DAC 220. Figure 7 The description of the level shifter 700 shown in FIG. 1 is the same as or similar to the description of the level shifter 1000 .

[0095] In some embodiments, the buffers 1012b and 1012c may control the output bias current of some bits HD[1:0] of the decoded image data based on different bias control signals IB1 and IB0. The bias control signals IB1 and IB0 may not be applied to the buffer 1012a that outputs the high bit HD[2]. This will refer to Fig.11 describe.

[0096] Fig.11 A circuit diagram for recovery of another example of a level shifter is shown.

[0097] Reference Fig.11 , multiple buffers 1110a, 1110b and 1110c output decoded image data HD[2:0]A and HD[2:0]B. Figure 5 The description of the buffers 510a, 510b, and 510c shown in FIG. 1 is the same as or similar to the description of the buffers 1110a, 1110b, and 1110c. In some embodiments, the plurality of buffers 1110a, 1110b, and 1110c may include first stage inverters 1111a, 1112a, and 1113a.

[0098] Among the second-stage inverters 1111b, 1112b, and 1113b, the second-stage inverters 1112b and 1113b that receive some bits of data MD[1:0] may include transistors PT2, NT2, and BT0b / BT0c connected in series between a third voltage VDD and a fourth voltage VSS. In some embodiments, some bits MD[1:0] may be bits other than the high bit MD[2]. For example, transistors PT2 and NT2 may be connected in an inverter structure, the gates of transistors PT2 and NT2 may be connected to the output terminal OUTa of the first-stage inverter (1112a / 1113a), and the drains of transistors PT2 and NT2 may be connected to the output terminal OUTb. A bias transistor (BT0b / BT0c) may be connected between the source of transistor NT2 and the fourth voltage VSS. In some embodiments, the bias transistor (BT0b / BT0c) may be located at the N-type decoder ( Figure 2 222b / 222c) in the path for discharging the input capacitor of the transistor BT0b. The bias control signal IB1 may be input to the gate of the bias transistor BT0b. The bias control signal IB0 may be input to the gate of the bias transistor BT0c. The bias transistor (BT0b / BT0c) may limit the discharge current (ID[1] / ID[0]) based on the voltage level of the bias control signal (IB1 / IB0). In some embodiments, the discharge current ID[0] flowing in the second-stage inverter 1113b outputting the low bit HD[0]B may be more limited than the discharge current ID[1] flowing in the second-stage inverter 1112b outputting the middle bit HD[1]B. For example, the voltage level of the bias control signal IB0 may be lower than the voltage level of the bias control signal IB1. This will refer to Fig.12 describe.

[0099] Fig.12 Graphs of output voltage and discharge current showing another example of a level shifter are shown.

[0100] exist Fig.12 The thin line indicates Figure 4 The output voltage and discharge current of the level shifter in Fig.11 The output voltage and discharge current of the level shifter in Fig.12 As shown in FIG, bit HD[0:2]B changes from the third voltage VDD to the fourth voltage VSS at time point t31. The change of bit HD[2]B is completed at time point t32 after the change of bit HD[1]B and bit HD[0]B is completed. Therefore, from DAC 220 ( Figure 2 ) output analog signal AD depends on the bit HD[2]B with the lowest conversion rate. Since the discharge current ID[2] is not limited, the time point t32 can be used as Figure 4The time point t2 at which the transition of bit HD[2]B is completed is basically the same.

[0101] The discharge currents ID[1] and ID[0] can be limited to different current amounts LC1 and LC0. Figure 4 Compared with the implementation of the present invention, the conversion rate of bit HD[1]B and bit HD[0]B can be lower. In addition, due to the limitation of discharge current ID[0], Fig. 9 Compared with the embodiment of the present invention, the conversion rate of the bit HD[0]B can be lower. Since the capacity of the input capacitor of the transistor connected to the output terminal OUTb of the inverter 1113b that outputs the low bit HD[0]B is smaller than the capacity of the input capacitor of the transistor connected to the output terminal OUTb of the inverter 1112b that outputs the middle bit HD[1]B, the discharge current ID[0] can be limited to a current amount smaller than the current amount of the discharge current ID[1]. By limiting the amounts of the discharge currents ID[1] and ID[0], the maximum value MC1 of the total discharge current IDG2 flowing through the conductive line to which the fourth voltage VSS is applied can be less than or equal to the reference value TLC.

[0102] Therefore, the ground bounce caused by the total discharge current IDG2 can be reduced. This can reduce the influence on the buffers 1110a, 1110b and 1110c receiving the same fourth voltage VSS and the noise caused to the interface physically adjacent to the wire supplying the fourth voltage VSS.

[0103] Fig.13 A block diagram showing another example of a level shifter is shown.

[0104] like Fig.13 As shown in FIG. 1 , a plurality of level shifters 1310 and 1320 are included in different amplifier regions ( Figure 1 132a, 132b, ..., and 132j). Each of the level shifters 1310 and 1320 is connected to a different source line SL. Each of the level shifters 1310 and 1320 receives 3-bit image data (LD1[2:0] / LD2[2:0]) and outputs 3-bit decoded image data HD1[2:0]A, HD1[2:0]B / HD2[2:0]A, HD2[2:0]B. Each of the level shifters 1310 and 1320 is connected to the DAC 220 ( Figure 2 ), and outputs the decoded image data HD1[2:0]A, HD1[2:0]B / HD2[2:0]A, HD2[2:0]B to DAC 220. Figure 7The description of the level shifter 700 shown in FIG. 1 is the same as or similar to the description of the level shifter 1300. In some embodiments, the plurality of level shifters 1310 and 1320 may include level shifting circuits 1311a, 1311b, 1311c, 1321c, 1321b, and 1321a.

[0105] At least one bias transistor BT2b and BT2c may be located in a region 1330 between the level shifters 1310 and 1320. For example, at least one bias transistor BT2b and BT2c may be located in a region 1330 between two adjacent level shifters 1310 and 1320. In some embodiments, the region 1330 between the level shifters 1310 and 1320 may be a region where a repeater is located to send a signal from one amplifier region to another amplifier region. That is, the repeater region may be located between a plurality of amplifier regions. For example, the repeater may be located to perform amplification, inversion, and / or buffering so that a signal applied to a first group including the level shifter 1310 may also be applied to a second group including the level shifter 1320. At least one bias transistor (BT2b, BT2c) connected to the first group including the level shifter 1310 and the second group including the level shifter 1320 may be located in the region 1330 where the repeater is located.

[0106] The first end of the bias transistor (BT2b / BT2c) may be connected to the corresponding buffers 1312b, 1322b / 1312c, and 1322c. The second end of the bias transistor (BT2b / BT2c) may be connected to the fourth voltage VSS. The bias control signal (IB1 / IB0) may be input to the gate of the bias transistor (BT2b / BT2c). For example, the bias control signal IB1 for controlling the discharge current for outputting the middle bit HD[1]B may be applied to the buffers 1312b and 1322b, and the bias control signal IB0 for controlling the discharge current for outputting the low bit HD[0]B may be applied to the buffers 1312c and 1322c. The buffers 1312b and 1312c and the buffers 1322b and 1322c may be included in different level shifters 1310 and 1320. That is, buffers included in different level shifters 1310 and 1320 and used to output the same bit may be connected to the same bias transistor. The bias transistors (BT2b / BT2c) may limit the discharge current of the buffers 1312b, 1322b / 1312c, and 1322c based on the voltage level of the bias control signal (IB1 / IB0). That is, the output bias current of some bits HD[1] of the decoded image data may be controlled by the same bias transistor BT2b. The output bias current of some bits HD[0] of the decoded image data may be controlled by the same bias transistor BT2c. The bias transistors may not be connected to the buffers 1312a and 1322a that output the high bits HD1[2]B and HD2[2]B.

[0107] Fig.14 A block diagram showing another example of a level shifter is shown.

[0108] Reference Fig.14 , the level shifter 1400 receives the 5-bit image data LD[4:0] and outputs the 5-bit decoded image data HD[4:0]A and HD[4:0]B. The level shifter 1400 is connected to the DAC 220 ( Figure 2 ), and outputs the decoded image data HD[4:0]A and HD[4:0]B to the DAC 220. Figure 7 The description of the level shifter 700 shown in FIG. 1 is the same as or similar to the description of the level shifter 1400. In some embodiments, the plurality of level shifters 1400 can include level shifting circuits 1411a, 1411b, 1411c, 1411d, and 1411e.

[0109] In some embodiments, the plurality of buffers 1412a, ..., and 1412e may be grouped into a plurality of groups. A group may include buffers that output adjacent bits. For example, buffers 1412b and 1412c included in a first group may output bits HD[3:2], and buffers 1412d and 1412e included in a second group may output bits HD[1:0].

[0110] Different bias control signals IB1 and IB0 may be applied to the buffers 1412b and 1412c included in the first group and the buffers 1412d and 1412e included in the second group. The buffers 1412b and 1412c included in the first group may control the output bias current of some bits HD[3:2] of the decoded image data based on the same bias control signal IB1. The buffers 1412d and 1412e included in the second group may control the output bias current of some bits HD[1:0] of the decoded image data based on the same bias control signal IB0. For example, the bias control signal IB1 applied to the buffers 1412b and 1412c included in the first group corresponding to the upper bits may have a higher voltage level than the bias control signal IB0 applied to the buffers 1412d and 1412e included in the second group corresponding to the lower bits. Therefore, the output bias current of the buffers 1412b and 1412c included in the first group may be greater than the output bias current of the buffers 1412d and 1412e included in the second group. The bias control signals IB1 and IB0 are not applied to the buffer 1412a outputting the high bit HD[4].

[0111] Fig.15 A circuit diagram for recovery of another example of a level shifter is shown.

[0112] Reference Fig.15 , multiple buffers 1510a, 1510b and 1510c output decoded image data HD[2:0]A and HD[2:0]B. Figure 5 The descriptions of buffers 510a, 510b, and 510c shown in FIG. 5 are the same as or similar to the descriptions of buffers 1510a, 1510b, and 1510c.

[0113] Each of the first-stage inverters 1511 a , 1512 a , and 1513 a may include transistors PT1 and NT1 connected in series between a third voltage VDD and a fourth voltage VSS.

[0114] The input terminal of the second-stage inverter (1511b / 1512b / 1513b) may be connected to the output terminal OUTa of the first-stage inverter (1511a / 1512a / 1513a). The output terminal OUTb of the second-stage inverter (1511b / 1512b / 1513b) may be connected to the gate of the transistor of the N-type decoder (222a / 222b / 222c). Each of the second-stage inverters 1511b, 1512b, and 1513b may include transistors PT2 and NT2 connected in series between the third voltage VDD and the fourth voltage VSS.

[0115] The size (W / L) of transistors PT2 and NT2 included in inverters 1512b and 1513b outputting the remaining bits may be smaller than the size (W / L) of transistors PT2 and NT2 included in inverter 1511b outputting the high bits. Therefore, the size of discharge currents ID[1] and ID[0] may be smaller than that of discharge current ID[2].

[0116] In addition, the size (W / L) of the transistors PT2 and NT2 included in the inverter 1513b outputting the low bit may be smaller than the size (W / L) of the transistors PT2 and NT2 included in the inverters 1511b and 1512b outputting the remaining bits. Therefore, the size of the discharge current ID[0] of the inverter 1513b outputting the low bit ID[0] may be minimized. Therefore, the ground bounce caused by the total discharge current of the second-stage inverters 1511b, 1512b, and 1513b may be reduced. This may reduce the impact on the buffers 1510a, 1510b, and 1510c receiving the same fourth voltage VSS, and the noise caused to the interface physically adjacent to the wire supplying the fourth voltage VSS.

[0117] In some embodiments, each of the inverters 1511b, 1512b, and 1513b may further include a bias transistor. Therefore, in addition to the size (W / L) of the transistor, the inverters 1511b, 1512b, and 1513b may also control the discharge current ID[2:0] through a bias control signal.

[0118] Fig.16 A circuit diagram schematically illustrating a buffer and a level shift circuit of another example of a source driver is shown.

[0119] Reference Fig.16 The level shift circuit 1610 includes cross-connected inverters, and the cross-connected inverters include transistors T1 and T2 connected in series between a first voltage VM and a second voltage VL, and transistors T3 and T4 connected in series between the first voltage VM and the second voltage VL. The buffer 1620 includes two-stage inverters 1621a and 1621b and a single-stage inverter 1621c.

[0120] Description of the level shift circuit 1610 and the buffer 1620 that are the same as or similar to the description of the level shift circuit 310 and the buffer 320 shown in FIG. 3 will be omitted.

[0121] The buffer 1620 may include 2-stage inverters 1621a and 1621b. The first-stage inverter 1621a may include transistors PT1 and NT1 connected in series between a third voltage VDD and a fourth voltage VSS. An input terminal of the first-stage inverter 1621a may be connected to an output terminal OUT1 of the level shift circuit 1610. The bit MD[2]A inverted and amplified by the level shift circuit 1610 may be input to the input terminal of the first-stage inverter 1621a. The bit HD[2]A inverted and amplified by the bit MD[2]A may be output from the output terminal OUT2 of the first-stage inverter 1621a.

[0122] The second-stage inverter 1621b may include transistors PT2, NT2, and BTB connected in series between a third voltage VDD and a fourth voltage VSS. For example, transistors PT2 and NT2 may be connected in an inverter structure, the gates of transistors PT2 and NT2 may be connected to the output terminal OUT2 of the first-stage inverter 1621a, and the drains of transistors PT2 and NT2 may be connected to the output terminal OUT3. The bias transistor BTB may be connected between the source of transistor NT2 and the fourth voltage VSS. The bit HD[2]A inverted and amplified by the first-stage inverter 1621a may be input to the input terminal of the second-stage inverter 1621b. The bit HD[2]B inverted and amplified by the bit HD[2]A may be output from the output terminal OUT3 of the second-stage inverter 1621b. The output terminal OUT3 may be connected to the decoder 221a ( Figure 2 ) in the N-type decoder 222a. In some embodiments, the bias transistor BTB may be located on a path for discharging an input capacitor of the transistor of the N-type decoder 222a.

[0123] The bias control signal IB may be input to the gate of the bias transistor BTB. The bias transistor BTB may limit the discharge current ID[2]B based on the voltage level of the bias control signal IB.

[0124] The single-stage inverter 1621c may include transistors PT3, NT3, and BTA connected in series between a third voltage VDD and a fourth voltage VSS. For example, transistors PT3 and NT3 may be connected in an inverter structure, the gates of transistors PT3 and NT3 may be connected to the output terminal OUT1, and the drains of transistors PT3 and NT3 may be connected to the output terminal OUT4. A bias transistor BTA may be connected between the source of transistor NT3 and the fourth voltage VSS. Bit MD[2]A inverted and amplified by the level shift circuit 1610 may be input to the input terminal of the single-stage inverter 1621c. Bit HD[2]A inverted and amplified by bit MD[2]A may be output from the output terminal OUT4 of the single-stage inverter 1621c. The output terminal OUT4 may be connected to the gate of a transistor of a P-type decoder 223a included in the decoder 221a. In some embodiments, the bias transistor BTA may be located on a path for discharging an input capacitor of a transistor of the P-type decoder 223a.

[0125] The bias control signal IB may be input to the gate of the bias transistor BTA. The bias transistor BTA may limit the discharge current ID[2]A based on the voltage level of the bias control signal IB.

[0126] Reference Figures 5 to 15 The described embodiments may be applied to Fig.16 Buffer 1620.

[0127] Fig.17 A circuit diagram schematically illustrating a buffer and a level shift circuit of another example of a source driver is shown.

[0128] Reference Fig.17 The level shift circuit 1710 includes cross-connected inverters, and the cross-connected inverters include transistors T1 and T2 connected in series between a first voltage VM and a second voltage VL, and transistors T3 and T4 connected in series between the first voltage VM and the second voltage VL. The buffer 1720 includes single-stage inverters 1721a and 1721b.

[0129] Will omit Figure 3 The descriptions of the level shift circuit 310 and the buffer 320 shown in FIG. 1 are the same as or similar to the descriptions of the level shift circuit 1710 and the buffer 1720 .

[0130] The bit LD[2]A of the image data may be provided to the gate of the transistor T2, and the bit LD[2]B in which the bit LD[2]A is inverted may be provided to the gate of the transistor T4. The bit MD[2]A in which the bit LD[2]A of the image data is inverted and amplified may be output from the output terminal OUT1A. The bit MD[2]B in which the bit LD[2]B of the image data is inverted and amplified may be output from the output terminal OUT1B.

[0131] The buffer 1720 may include single-stage inverters 1721a and 1721b. The first inverter 1721a may include transistors PT1, NT1, and BTA connected in series between a third voltage VDD and a fourth voltage VSS. For example, transistors PT1 and NT1 may be connected in an inverter structure, the gates of transistors PT1 and NT1 may be connected to an output terminal OUT1A, and the drains of transistors PT1 and NT1 may be connected to an output terminal OUT2. A bias transistor BTA may be connected between a source of transistor NT1 and the fourth voltage VSS. Bit MD[2]A inverted and amplified by the level shift circuit 1710 may be input to an input terminal of the single-stage inverter 1721a. Bit HD[2]A inverted and amplified by bit MD[2]A may be output from an output terminal OUT2 of the single-stage inverter 1721a. The output terminal OUT2 may be connected to a decoder 221a ( Figure 2 ) is a gate of a transistor of the P-type decoder 223a. In some embodiments, the bias transistor BTA may be located on a path for discharging an input capacitor of the transistor of the P-type decoder 223a.

[0132] The bias control signal IB may be input to the gate of the bias transistor BTA. The bias transistor BTA may limit the discharge current ID[2]A based on the voltage level of the bias control signal IB.

[0133] The second inverter 1721b may include transistors PT2, NT2, and BTB connected in series between the third voltage VDD and the fourth voltage VSS. For example, the transistors PT2 and NT2 may be connected in an inverter structure, the gates of the transistors PT2 and NT2 may be connected to the output terminal OUT1B, and the drains of the transistors PT2 and NT2 may be connected to the output terminal OUT3. The bias transistor BTB may be connected between the source of the transistor NT2 and the fourth voltage VSS. The bit MD[2]B inverted and amplified by the level shift circuit 1710 may be input to the input terminal of the second inverter 1721b. The bit HD[2]B inverted and amplified by the bit MD[2]B may be output from the output terminal OUT3 of the second inverter 1721b. The output terminal OUT3 may be connected to the gate of the transistor of the N-type decoder 222a included in the decoder 221a. In some embodiments, the bias transistor BTB may be located on a path for discharging the input capacitor of the transistor of the N-type decoder 222a.

[0134] The bias control signal IB may be input to the gate of the bias transistor BTB. The bias transistor BTB may limit the discharge current ID[2]B based on the voltage level of the bias control signal IB.

[0135] Reference Figures 5 to 15The described embodiments may be applied to Fig.17 Buffer 1720.

[0136] Fig.18 shows a graph showing simulation results of output voltage and discharge current of an example of a level shifter, and Fig.19 Graphs showing simulation results of output voltage and discharge current of another example of a level shifter are shown.

[0137] like Fig.18 As shown in FIG. 1 , bits 1810 and 1812 transition from the third voltage VDD to the fourth voltage VSS at time point t1A. The transition of the highest bit 1812 is completed at time point t2 after the transition of the lower bit 1810 is completed.

[0138] While the transition of the lower bit 1810 is being performed, the discharge current 1820 corresponding to the lower bit 1810 may have a maximum value at a time adjacent to each other. Therefore, while the lower bit 1810 is transitioning, a maximum value MC1 of the total discharge current 1830 may be formed. In some embodiments, the discharge current 1822 corresponding to the highest bit 1812 may have a maximum value at a time point before time t2.

[0139] like Fig.19 As shown in FIG. 1 , bits 1910 and 1912 transition from the third voltage VDD to the fourth voltage VSS at time point t1B. The transition of the highest bit 1912 is completed at time point t2 after the transition of the lowest bit 1910 is completed.

[0140] The discharge currents 1920 and 1921 corresponding to the low bit 1910 may be limited to different current amounts LC0 and LC1, respectively. The current amount is limited, and thus the conversion rate of the bit 1910 may be reduced. In addition, by limiting the amount of the discharge currents 1920 and 1921, the maximum value MC2 of the total discharge current 1930 flowing through the wire to which the fourth voltage VSS is applied may be less than the maximum value MC1. Therefore, based on the display driving device, the source driver, and the display device including them according to some embodiments, the ground bounce caused by the total discharge current 1930 may be reduced, and the impact of the ground bounce on adjacent circuits, modules, interfaces, etc. may be reduced. In some embodiments, the discharge current 1922 corresponding to the highest bit 1912 may have a maximum value at a time point before time t2.

[0141] Fig. 20 Diagrams for explaining an example of a display system are shown.

[0142] Reference Fig. 20 , the display system 2000 includes a processor 2010 , a memory 2020 , a display device 2030 , and a peripheral device 2040 , which are electrically connected to a system bus 2050 .

[0143] The processor 2010 may control input and output of data of the memory 2020 , the display device 2030 , and the peripheral device 2040 , and may perform image processing of image data transmitted between corresponding devices.

[0144] The memory 2020 may include a volatile memory such as a dynamic random access memory (DRAM) and / or a non-volatile memory such as a flash memory. The memory 2020 may include a DRAM, a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a NOR flash memory, a NAND flash memory, and a fusion flash memory (e.g., a memory in which a static random access memory (SRAM) buffer, a NAND flash memory, and a NOR interface logic are combined). The memory 2020 may store image data acquired from the peripheral device 2040 or an image signal processed by the processor 2010.

[0145] The display device 2030 may include a driving circuit (DC) 2031 and a display panel (DP) 2032, and the driving circuit 2031 may display image data applied through the system bus 2050 on the display panel 2032. The driving circuit 2031 may include a level shifter that shifts the image data level to a higher voltage level to transmit it to the DAC. The level shifter according to some embodiments may control a discharge current that discharges the input capacitor of the DAC. For example, the level shifter may limit the size of the discharge current corresponding to the bit other than the high bit. In some embodiments, the level shifter may limit the discharge current to the same or different sizes. The level shifter may limit the discharge current that discharges the input capacitor of the DAC connected to different source lines to the same amount.

[0146] The peripheral device 2040 may be a device that converts a moving picture or a still image (such as a moving picture or a still image of a camera, a scanner, or a webcam) into an electrical signal. The image data acquired by the peripheral device 2040 may be stored in the memory 2020, or may be displayed on the panel 2032 in real time.

[0147] The display system 2000 may be provided in a mobile electronic product such as a smart phone, but the present disclosure is not limited thereto and may be provided in various types of electronic products that display an image.

[0148] In some embodiments, reference Figures 1 to 20 Each component described or a combination of two or more components may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), and the like.

[0149] Although this specification contains many specific implementation details, these implementation details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Specific features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in a particular combination, in some cases, one or more features from a combination may be deleted from the combination, and a combination may refer to a sub-combination or a variant of a sub-combination.

[0150] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display driving device, comprising: Level shifters, configured as: Receive image data and bias control signals, level-shifting the image data to generate decoded image data, the decoded image data comprising a plurality of bits, and controlling an output bias current of the decoded image data based on a bias control signal; as well as The digital-to-analog converter is configured as: receiving decoded image data and a plurality of gamma voltages, selecting one of the plurality of gamma voltages based on the decoded image data, and Outputs the selected gamma voltage.

2. The display driving device according to claim 1, wherein: The level shifter includes: A plurality of level shifting circuits are configured as follows: receiving image data, and level-shifting the image data using a first voltage and a second voltage different from the first voltage; and Multiple buffers, configured as: receiving the level-shifted image data, and The level-shifted image data is level-shifted using a third voltage and a fourth voltage to generate decoded image data, wherein the third voltage is higher than the first voltage and the fourth voltage is lower than the second voltage, and The bias control signal is transmitted to at least one buffer among the plurality of buffers.

3. The display driving device according to claim 2, wherein: The digital-to-analog converter comprises a plurality of stages, the plurality of stages comprising a plurality of decoders, wherein the number of the plurality of decoders corresponds to the plurality of bits, The plurality of buffers are connected to the plurality of stages, and According to the plurality of decoders included in the plurality of stages, bias control signals are transmitted to the plurality of buffers at a plurality of different voltage levels.

4. The display driving device according to claim 3, wherein: The plurality of decoders included in the plurality of stages include at least one transistor including a gate through which the plurality of bits are input, and The output bias current is a current that discharges an input capacitor of the gate of the at least one transistor.

5. The display driving device according to claim 3, wherein: The plurality of buffers include a first buffer connected to a stage including a first number of decoders and a second buffer connected to a stage including a second number of decoders, the second number being less than the first number, and The bias control signal is transmitted to the first buffer and the second buffer at different levels so that an output bias current of the first buffer is greater than an output bias current of the second buffer.

6. The display driving device according to claim 3, wherein: The bias control signal is transmitted to at least one buffer connected to at least one stage to control an output bias current of the at least one stage, the at least one stage being not a stage including a maximum number of decoders.

7. The display driving device according to claim 2, wherein: At least one buffer of the plurality of buffers comprises: an inverter configured to receive the level-shifted image data and output decoded image data, and A bias transistor is configured to connect the inverter to a fourth voltage, the bias transistor including a gate configured to receive a bias control signal.

8. The display driving device according to claim 7, wherein: At least two buffers among the plurality of buffers include inverters and bias transistors, and The bias transistor included in one of the at least two buffers has a size different from that of the bias transistor included in another of the at least two buffers.

9. The display driving device according to claim 1, wherein: The level shifter is configured to control the plurality of output bias currents of the plurality of bits to have the same magnitude based on a bias control signal.

10. The display driving device according to claim 1, wherein: The level shifter is configured to control the plurality of output bias currents of the plurality of bits to have different magnitudes based on a bias control signal.

11. The display driving device according to claim 1, wherein: The level shifter is configured to control an output bias current of a higher bit among the plurality of bits to be lower than an output bias current of a lower bit among the plurality of bits based on a bias control signal.

12. The display driving device according to claim 1, wherein: The level shifter is configured to control an output bias current of at least one bit based on a bias control signal, the at least one bit not being a highest bit among the plurality of bits.

13. The display driving device according to claim 1, wherein: The level shifter is configured to control a plurality of output bias currents of a plurality of upper bits among the plurality of bits and a plurality of output bias currents of a plurality of lower bits among the plurality of bits to different sizes based on a bias control signal.

14. The display driving device according to claim 13, wherein: The level shifter is configured to control the plurality of output bias currents of the plurality of upper bits to be of the same first magnitude, and to control the plurality of output bias currents of the plurality of lower bits to be of the same second magnitude.

15. The display driving device according to claim 1, comprising: The bias circuit is configured as: receiving a bias start signal, the bias start signal being configured to control the bias control signal to be output at a first level, and A bias control signal of a second level different from the first level is generated with reference to data stored in the one-time programmable memory.

16. A source driver, comprising: A plurality of amplifier regions, each amplifier region of the plurality of amplifier regions comprising: a level shifter configured to output a plurality of bits of decoded image data, a digital-to-analog converter configured to select one of a plurality of gamma voltages based on the decoded image data, and an amplifier configured to amplify the selected gamma voltage to obtain a data signal, and output the data signal to a corresponding source line among the plurality of source lines; and A bias circuit is configured to generate a bias control signal configured to limit an output bias current of a level shifter included in each of the plurality of amplifier regions.

17. The source driver according to claim 16, wherein: The bias control signal includes: a first bias control signal and a second bias control signal, the first bias control signal being configured to limit an output bias current of a first bit among the plurality of bits output by the plurality of level shifters included in the plurality of amplifier regions, and the second bias control signal being configured to limit an output bias current of a second bit among the plurality of bits output by the plurality of level shifters included in the plurality of amplifier regions.

18. The source driver according to claim 16, comprising: A repeater region includes a bias transistor including a gate configured to receive a bias control signal, the repeater region being located between the plurality of amplifier regions.

19. A display device comprising: a pixel array comprising a plurality of pixels; The timing controller is configured as: receiving an image signal and a driving control signal from outside the display device, dividing the image signal to generate a plurality of image data, and generating a bias start signal based on the drive control signal; Multiple amplifier zones, configured as: receiving the plurality of image data and a bias control signal, level-shifting the plurality of image data to generate decoded image data, controlling the level of the output bias current of the decoded image data based on the level of the bias control signal, receiving decoded image data and a plurality of gamma voltages, selecting one of the plurality of gamma voltages based on the decoded image data, and Output selected gamma voltage; as well as The bias circuit is configured as: receiving a bias start signal, the bias start signal being configured to control the bias control signal to be output at a first level, and A bias control signal of a second level different from the first level is generated with reference to data stored in the one-time programmable memory.

20. The display device according to claim 19, wherein: The decoded image data comprises a plurality of bits, and The bias circuit is configured to generate a bias control signal to make the plurality of conversion rates of the plurality of bits different.

Images