Column click update address calculation method, column click update address calculation circuit, and semiconductor memory device

Abstract

The embodiment of the invention provides a column click update address calculation method, a calculation circuit and a semiconductor storage device, and provides a calculation method, a calculation circuit and a semiconductor storage device which can perform column click update address RHA at a small circuit scale and high speed. A control unit of an RHA calculation circuit controls the order of calculation units, and when a seed address is updated, an address obtained by a calculation with a small amount of calculation is preferentially calculated as an adjacent RHA among adjacent RHAs on both sides of the updated seed address, or an address obtained by a calculation with a small amount of calculation is preferentially calculated as an adjacent RHA among re-adjacent RHAs on both sides of the updated seed address. An address obtained by a calculation with a small amount of calculation is preferentially calculated as a re-adjacent RHA. In a calculation unit, a calculation circuit is implemented that finds the possibility that a word line entity configuration and a column address allocated thereto are trained as a last specific logic, finds the calculation logic of an adjacent RHA and a re-adjacent RHA with the minimum amount of calculation on the basis of this possibility, and optimizes the order control of calculation.

Description

Technical Field

[0001] The present application relates to a semiconductor storage device that additionally implements column thumping update in order to save data in the field of semiconductor storage devices such as dynamic random access memory (DRAM) that require update actions, as well as a column thumping update address calculation method and calculation circuit. Background Art

[0002] Due to the needs of the circuit architecture, dynamic random access memory must perform a refresh operation every once in a while to refresh the data stored in the memory cell. Among them, the column address that is frequently accessed is called RHA. In the memory cell of the column address close to the RHA, the memory array noise generated by the access action, or minority carriers or rare device defects, causes leakage current.

[0003] As semiconductor memory devices are miniaturized, this type of leakage current increases significantly, making it difficult to maintain data using only traditional refresh operations. Therefore, there is a situation where frequently accessed column addresses are recorded as column hammer addresses (RHA), and additional refreshes are performed on the column hammer address, the column addresses on the two sides adjacent to the column hammer address, and the two column addresses adjacent to the column addresses on the two sides adjacent to the column addresses. However, the calculation of the above-mentioned column address becomes complicated, and the calculation time becomes longer, and the circuit scale also becomes large. Summary of the invention

[0004] The present application provides an RHA calculation circuit, which is a column thump update address calculation circuit for calculating a column thump update address, comprising: a calculation unit, in a memory array including a plurality of storage cells arranged in rows and columns, complementarily calculating an upper side adjacent column thump update address and a lower side adjacent column thump update address by a first operation or a second operation whose operation amount is larger than the first operation, wherein the upper side adjacent column thump update address corresponds to a word line adjacent to the upper side of a word line assigned to a seed address, and the lower side adjacent column thump update address corresponds to a word line adjacent to the lower side of a word line assigned to the seed address, and, complementarily calculating an upper side re-adjacent column thump update address and a lower side re-adjacent column thump update address by a third operation or a fourth operation whose operation amount is larger than the third operation, wherein the upper side re-adjacent column thump update address corresponds to a word line adjacent to the lower side of a word line assigned to the seed address. The upper side adjacent word line of the word line to which the address is assigned, the lower side adjacent column thump update address corresponds to the lower side adjacent word line of the word line assigned relative to the seed address; and a control unit, which controls the action of the calculation unit, so that when the seed address is updated as an opportunity, among the upper side adjacent column thump update address and the lower side adjacent column thump update address corresponding to the updated seed address, the address obtained by the first operation is used as the priority adjacent column thump update address, and the first operation is preferentially calculated; and when the seed address is updated as an opportunity, among the upper side adjacent column thump update address and the lower side adjacent column thump update address corresponding to the updated seed address, the address obtained by the third operation is used as the priority adjacent column thump update address, and the third operation is preferentially calculated.

[0005] The present application provides a semiconductor memory device, comprising: the memory array, comprising a plurality of memory cells arranged in rows and columns; and the column thump update address calculation circuit of the above invention; wherein a plurality of memory cells corresponding to word lines having the column thump update address calculated by the column thump update address calculation circuit are updated.

[0006] The present application provides a column thump update address calculation method, which is a column thump update address calculation method for calculating a column thump update address, comprising: a calculation step, in a memory array including a plurality of memory cells arranged in rows and columns, calculating an upper side adjacent column thump update address and a lower side adjacent column thump update address by a first operation or a second operation with a larger amount of operation than the first operation, wherein the upper side adjacent column thump update address corresponds to a word line adjacent to the upper side of a word line assigned to a seed address, and the lower side adjacent column thump update address corresponds to a word line adjacent to the lower side of a word line assigned to the seed address, and calculating an upper side re-adjacent column thump update address and a lower side re-adjacent column thump update address by a third operation or a fourth operation with a larger amount of operation than the third operation, wherein the upper side re-adjacent column thump update address corresponds to a word line adjacent to the lower side of a word line assigned to the seed address. The upper side adjacent word line of the word line to which the address is assigned, the lower side adjacent column thump update address corresponds to the lower side adjacent word line of the word line assigned relative to the seed address; and a control step, controlling the calculation step, taking the update of the seed address as an opportunity, among the upper side adjacent column thump update address and the lower side adjacent column thump update address corresponding to the updated seed address, the address obtained by the first operation is used as the priority adjacent column thump update address to be preferentially calculated by the first operation, and taking the update of the seed address as an opportunity, among the upper side adjacent column thump update address and the lower side adjacent column thump update address corresponding to the updated seed address, the address obtained by the third operation is used as the priority adjacent column thump update address to be preferentially calculated by the third operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0008] Figure 1 FIG. 4 is a block diagram showing a semiconductor memory device according to an embodiment of the present application.

[0009] Figure 2 To display Figure 1 A block diagram showing the structure of the i-th storage block 101 - i is shown.

[0010] Figure 3 To display Figure 2 The column hammer shown is a block diagram of the structure of the update address calculation unit.

[0011] Figure 4To display and Figure 2 The column thumping shown is a timing diagram of signals associated with the address calculation unit.

[0012] Figure 5 It is a schematic diagram showing the configuration pattern of a portion corresponding to 16 column lines in a memory array of a semiconductor memory device according to an embodiment of the present application.

[0013] Figure 6 A schematic diagram showing the correspondence between the seed address and the column hammer update address.

[0014] Figure 7 To display Figure 3 A circuit diagram of an example configuration of a calculation unit shown.

[0015] Figure 8 (a) is a chart showing the correspondence between the seed address and the adjacent column thump update address in an embodiment of the present application; (b) is a chart showing the correspondence between the seed address and the adjacent column thump update address in an embodiment of the present application; (c) is a chart showing the correspondence between the physical address and the logical address in an embodiment of the present application.

[0016] Fig. 9 The following is a diagram showing the signals and data required to switch the priority adjacent column thump update address, the non-priority adjacent column thump update address, the priority re-adjacent column thump update address, and the non-priority re-adjacent column thump update address, and the combination of the above.

[0017] Fig.10 To display Figure 7 The circuit diagram of the modified 4-bit addition unit configuration example is shown.

[0018] Fig.11 FIG. 1 is a logical expression that conditionally displays the logical operation performed in the column thump update address calculation unit according to the second embodiment of the present application.

[0019] Fig.12 It is a circuit diagram showing the structure of a column thump update address calculation unit according to the second embodiment of the present application.

[0020] Fig.13 It is a circuit diagram showing the structure of a column thump update address calculation unit according to the third embodiment of the present application.

[0021] Fig.14 It is a circuit diagram showing the structure of the column thump update address calculation unit in the first connection state according to the fourth embodiment of the present application.

[0022] Fig.15 It is a circuit diagram showing the structure of the column thump update address calculation unit in the second connection state according to the fourth embodiment of the present application.

[0023] [Explanation of symbols]

[0024] 100: semiconductor storage device;

[0025] 101-1 to 101-N: memory blocks;

[0026] 201: Update control unit;

[0027] 203: column hammer update address calculation unit;

[0028] 205: column address selector;

[0029] 207: column decoder and memory bank logic unit;

[0030] 209: NOT gate;

[0031] 211 to 215, 233, 235: AND gate;

[0032] 217: OR gate;

[0033] 221: row address decoder;

[0034] 223: I / O gates and DM logic;

[0035] 225: memory array;

[0036] 227: character driver;

[0037] 229: sensing amplifier;

[0038] 231: Random number generating unit;

[0039] 237, 239, 241: latch;

[0040] 243, 245: selector;

[0041] 247: Control department;

[0042] 249: Computing Department;

[0043] RHA: Column Hammer Update Address;

[0044] ACT, PREC, RFIP, RHR, XRED Match: signal;

[0045] RHR2nd: priority switching signal;

[0046] PM2: distance switching signal;

[0047] Seed: seed address;

[0048] XADD2, XADDS, XRED: column address;

[0049] Sample: the first sampling signal;

[0050] Sample2: the second sampling signal;

[0051] EN,EN2: signal;

[0052] S1, S2: seed addresses. DETAILED DESCRIPTION

[0053] Hereinafter, a column thump update address calculation circuit and a semiconductor memory device and a column thump update address calculation method according to an embodiment of the present application will be described with reference to the accompanying drawings. However, this embodiment is only an example and the present application is not limited thereto.

[0054] Figure 1 FIG. 1 is a block diagram of a semiconductor memory device 100 according to a first embodiment of the present application. In addition, in the present embodiment, although the semiconductor memory device 100 is described as a DRAM, the semiconductor memory device 100 may also be, for example, a pseudo-static random access memory (psram) configured to control an internal refresh operation.

[0055] Reference Figure 1 The semiconductor memory device 100 includes: memory blocks 101-1 to 101-N (N is an integer greater than or equal to 2), an address input buffer 103, an address decoder 105, a row address counter and latch 107, a block address control logic 109, an instruction input buffer 111, an instruction decoder 113, a clock input buffer 115, an internal clock generation unit 117, a mode register and a fuse ROM unit 119, a global input and output gate 121, a DQ input and output buffer 123, a temperature sensor 125, and an internal power generation unit 127.

[0056] Data DQ input from the outside is supplied to the global input / output gate 121 via the DQ input / output buffer 123 , and data supplied from the global input / output gate 121 to the DQ input / output buffer 123 is output to the outside as data DQ.

[0057] The global I / O gate 121 deselects data input from the DQ I / O buffer 123 and provides the data to the memory blocks 101 - 1 to 101 -N. In addition, the global I / O gate 121 selects data provided from the memory blocks 101 - 1 to 101 -N and provides the data to the DQ I / O buffer 123 .

[0058] Each of the memory blocks 101-1 to 101-N includes a plurality of memory cells arranged in rows and columns. Each memory cell is designated by a column address and a row address. In the memory cell designated by the column address and the row address of the memory block 101-i (i=1 to N) designated by the block select signal BS_i (i=1 to N), data input from the outside is written in accordance with the write signal WT via the global input / output gate 121 and the DQ input / output buffer 123. In addition, the data written in the memory cell designated by the column address and the row address of the memory block 101-i designated by the block select signal BS_i is read in accordance with the read signal RD via the global input / output gate 121 and the DQ input / output buffer 123.

[0059] An address input from the outside is provided to the address decoder 105 , the command decoder 113 , and the mode register and fuse ROM section 119 via the address input buffer 103 .

[0060] The address decoder 105 decodes the input address and outputs the decoding result as a block address BA, a column address XADD, and a row address YADD.

[0061] The row address counter and latch 107 mainly latches the row address YADD and provides it to the memory blocks 101 - 1 to 101 -N as the row address YADD1 .

[0062] The block address control logic 109 decodes the block address BA and provides decoded block selection signals BS_1 to BS_N to the memory blocks 101 - 1 to 101 -N, respectively.

[0063] The command COM input from the outside is supplied to the command decoder 113 via the command input buffer 111 .

[0064] The instruction decoder 113 decodes the instruction, calculates signals ACT, PREC, RFIP_1 to RFIP_N, a read signal RD, a write signal WT, and a signal MRS based on the decoding result and the address, and provides them to the memory blocks 101 - 1 to 101 -N.

[0065] Complementary clocks CK and CKB input from the outside are converted into a clock ICLK by the clock input buffer 115 , and are supplied to the command decoder 113 , the address decoder 105 , and the internal clock generation unit 117 .

[0066] The internal clock generating section 117 generates an internal clock LCLK based on the signal CKE and the clock ICLK supplied from the command input buffer 111 . The internal clock LCLK is supplied to the DQ input / output buffer 123 .

[0067] The mode register and fuse ROM section 119 calculates signals TMRHR and TMRS based on the signal MRS and the address, and provides the signals to the memory blocks 101 - 1 to 101 -N.

[0068] The temperature sensor 125 measures the temperature of the semiconductor memory device 100 , outputs temperature data TS indicating the measurement result, and provides the temperature data TS to the memory blocks 101 - 1 to 101 -N.

[0069] The internal power supply generating unit 127 generates internal power supplies VPP, VBB, VBLH, VOD, and VINT, etc., which are supplied to various parts of the semiconductor memory device 100 , based on power supplies VDD and VSS input from the outside.

[0070] Figure 2 To display Figure 1 The block diagram of the structure of the i-th storage block 101-i is shown. The i-th storage block 101-i includes: an update control unit 201, a column thump update address calculation unit 203, a column address selector 205, a column decoder and a memory bank logic unit 207, a NOT gate 209, AND gates 211, 213, 215, an OR gate 217, a row address decoder 221, an I / O gate and a DM logic 223, a memory array 225, a word driver 227, and a sense amplifier 229. In addition, the column thump update address calculation unit 203 corresponds to the "column thump update address calculation circuit" of the present application.

[0071] The refresh control unit 201 receives input signals TMRS, TMRHR, ACT, PREC, temperature data TS, and clock RFIP_i, and calculates a normal refresh address RFA, a signal CBRSLOT, and a signal RHRSLOT based on these signals.

[0072] The column thump update address calculation unit 203 calculates the column thump update address RHA (hereinafter referred to as “RHA”) based on the column address XADD2. The column address XADD2 is provided by the column address selector 205 to the column decoder and bank logic unit 207 for accessing (writing, reading or updating) the memory array 255.

[0073] However, if the memory cell located in the X redundant area is used to replace the memory cell located in the column specified by the column address XADD2, the signal XRED Match is activated. At this time, the column address XRED of the X redundant area is used instead of the column address XADD2 as the reference address for RHA calculation. Here, the column address XRED is the column address of the memory cell actually accessed, and the column hammer update address calculation unit 203 inputs the column address XRED from the column decoder and memory bank logic unit 207.

[0074] In addition, the column thump update address calculation unit 203 also uses the signals ACT, PREC, and RHR when calculating RHA.

[0075] The column address selector 205 selects any one of the column address XADD1 , the normal update address RFA, and the column thump update address RHA as the column address XADD2 based on the signals CBR and RHR. The column address XADD2 is provided to the column decoder and bank logic unit 207 .

[0076] The signal CBR has a logic level that is a logical inversion signal of the signal RHRSLOT and a logical sum operation result of the signal CBRSLOT and the clock RFIP_i, and is obtained by passing these signals through the NOT gates 209 and 211 .

[0077] The signal RHR has a logic level that is a result of a logical AND operation of the signal RHRSLOT and the clock RFIP_i, and is calculated by connecting the signal RHRSLOT and the clock RFIP_i through an AND gate 213 .

[0078] The signal RFEXE has a logic level of a logical OR operation result of the signals CBRSLOT and RHRSLOT and a logical AND operation result of the clock RFIP_i, and is calculated by passing the signals CBRSLOT, RHRSLOT, and the clock RFIP_i through an OR gate 217 and an AND gate 215 .

[0079] When the block select signal BS_i selects the own memory block 101 - i, the column decoder and bank logic unit 207 decodes the column address XADD2 and selects a word line WL to be driven by the word driver 227 from among each column word line WL provided in the memory array 225 .

[0080] When the block selection signal BS_i selects the own memory block 101-i, the row address decoder 221 decodes the row address YADD1 and selects the sense amplifier 229 of the bit line BL to be sensed from among the sense amplifiers 229 provided for each bit line BL of the memory array 225. The selected sense amplifier 229 senses the corresponding bit line BL at the timing according to the signal SAEn.

[0081] The I / O gate and DM logic 223 exist between the memory input / output bus MIO and the row input / output bus LIO, and control the input / output direction of data based on a write signal WT and a read signal RD.

[0082] Figure 3 To display Figure 2 The column hammer update address calculation unit 203 is a block diagram of the structure shown. Figure 4 2 is a timing diagram showing signals associated with the column thumping update address calculation unit 203. Figure 3 The column hammer update address calculation unit 203 includes: a random number generation unit 231, AND gates 233, 235, latches 237, 239, 241, selectors 243, 245, a control unit 247 and a calculation unit 249.

[0083] The signal EN generated by the random number generator 231 at a random timing is logically ANDed with the signal PREC by the AND gate 233, as shown in FIG. Figure 4 In addition, the signal EN2 generated in the random number generator 231 independently of the signal EN in the random timing is subjected to a logic AND operation with the signal PREC through the AND gate 235, as shown in FIG. Figure 4 As shown, the second sampling signal Sample2 is calculated at a random timing.

[0084] The column address XADD2 is provided to the selector 243 from the column address selector 205 via the column decoder and the bank logic unit 207 . In addition, the column address XRED and the signal XREDMatch are provided to the selector 243 from the column decoder and the bank logic unit 207 .

[0085] The selector 243 selects any one of the column address XADD2 and the column address XRED as the column address XADDS according to the signal XRED Match.

[0086] The latch 237 outputs a signal randomly sampling the column address XADDS by the first sampling signal Sample as the seed address S1 of the A-seed.

[0087] The latch 239 outputs a signal randomly sampling the column address XADDS by the second sampling signal Sample2 as the seed address S2 of the B seed.

[0088] The control unit 247 calculates the distance switching signal PM2 and the priority switching signal RHR2nd based on the RHR signal. Here, the distance switching signal PM2 is an example of the "first identification signal" of the present application, and the priority switching signal RHR2nd is an example of the "second identification signal" of the present application.

[0089] Reference Figure 4 , the pulse of the clock RFIP continues periodically. The signal RHRSLOT has a period corresponding to the update rate. In each of the periods, the logic level of the signal RHRSLOT becomes H only during the period corresponding to the length of two periods of the clock RFIP. The signal RHR is obtained by the logical AND operation of the clock RFIP and the signal RHRSLOT. Therefore, two consecutive pulses of the signal RHR are generated in each of the periods of the signal RHRSLOT.

[0090] The logic level of the priority switching signal RHR2nd changes from L to H by the first pulse of two consecutive pulses of the signal RHR, and the logic level of the priority switching signal RHR2nd changes from H to L by the second pulse.

[0091] In addition, although the logic level of the distance switching signal PM2 is basically inverted by the second pulse among two consecutive pulses of the signal RHR, there are cases where it is not inverted. This will be described in detail later.

[0092] The period from the falling edge of the priority switching signal RHR2nd to the next falling edge is 1 unit period. At the beginning of this unit period, the priority switching signal RHR2nd becomes L, and then when the first pulse of the two consecutive pulses of the signal RHR occurs, the priority switching signal RHR2nd becomes H. Thereafter, when the second pulse of the two consecutive pulses of the signal RHR occurs, the priority switching signal RHR2nd becomes L again, and the unit period ends.

[0093] The distance switching signal PM2 does not change in the unit period. The distance switching signal PM2 is basically inverted in each unit period, but it may not be inverted.

[0094] When the logic level of the distance switching signal PM2 is L, in the configuration of the word lines in the memory array, the two addresses assigned to the two adjacent word lines on both sides of the word line assigned to the seed address of the A seed are designated as the upper side adjacent RHA and the lower side adjacent RHA. In addition, when the logic level of the distance switching signal PM2 is H, in the configuration of the word lines in the memory array, the two addresses assigned to the two adjacent word lines on both sides of the word line assigned to the seed address adjacent to the B seed are designated as the upper side re-adjacent RHA and the lower side re-adjacent RHA. Here, "upper" and "lower" are the arrangement order of the configuration of the word lines in the memory array.

[0095] When the logic level of the priority switching signal RHR2nd is L, the RHA that is calculated earlier in time (i.e., the priority RHA) is designated among the two RHAs calculated based on the same seed address (the same seed address of the A seed or the same seed address of the B seed). On the other hand, when the logic level is H, the RHA that is calculated later in time (i.e., the non-priority RHA) is designated.

[0096] Therefore, when the distance switching signal PM2 is L and the priority switching signal RHR2nd is L, the priority adjacent RHA is designated as the RHA, when the distance switching signal PM2 is L and the priority switching signal RHR2nd is H, the non-priority adjacent RHA is designated as the RHA, when the distance switching signal PM2 is H and the priority switching signal RHR2nd is L, the priority re-adjacent RHA is designated as the RHA, and when the distance switching signal PM2 is H and the priority switching signal RHR2nd is H, the non-priority re-adjacent RHA is designated as the RHA.

[0097] The selector 245 selects the seed address S1 of the A seed as the seed address when the logic level of the distance switching signal PM2 is L, and selects the seed address S2 of the B seed as the seed address when the logic level of the distance switching signal PM2 is H.

[0098] When the logic level of the priority switching signal RHR2nd is L, the latch 241 directly outputs the seed address provided from the selector 245 as the seed address Seed, and when the logic level of the priority switching signal RHR2nd is H, directly continues to output the seed address Seed immediately before it becomes H.

[0099] The calculation unit 249 calculates and outputs four types of RHA based on the seed address Seed according to the combination of the distance switching signal PM2 and the priority switching signal RHR2nd.

[0100] In addition, the seed address S1 of the A seed randomly sampled by the latch 237 and the seed address S2 of the B seed randomly sampled by the latch 239 are synthesized into one seed address Seed by the selector 245. Here, in fact, when the logic level of the distance switching signal PM2 is L, the seed address of the A seed is selected as the seed address Seed, and on the other hand, when the logic level of the distance switching signal PM2 is H, the seed address of the B seed is selected as the seed address Seed.

[0101] Therefore, when the logic levels of the distance switching signal PM2 and the priority switching signal RHR2nd are L and L, the calculation unit 249 calculates the priority adjacent RHA selected from the upper adjacent RHA and the lower adjacent RHA by the first operation based on the seed address of the seed A. In addition, when the logic levels of the distance switching signal PM2 and the priority switching signal RHR2nd are L and H, the non-priority adjacent RHA selected from the upper adjacent RHA and the lower adjacent RHA is calculated by the second operation based on the seed address of the seed A.

[0102] Furthermore, when the logic levels of the distance switching signal PM2 and the priority switching signal RHR2nd are H and L, the priority re-adjacent RHA selected from the upper re-adjacent RHA and the lower re-adjacent RHA is calculated by the third operation based on the seed address of the B seed. In addition, when the logic levels of the distance switching signal PM2 and the priority switching signal RHR2nd are H and H, the non-priority re-adjacent RHA selected from the upper re-adjacent RHA and the lower re-adjacent RHA is calculated by the fourth operation based on the seed address of the B seed.

[0103] Here, the amount of computation of the second operation is larger than that of the first operation, and the amount of computation of the fourth operation is larger than that of the third operation.

[0104] In addition, the latch 237 and the latch 239 are examples of the “sampling unit” of the present application.

[0105] Refer to Figure 4 As described above, the logic level of the signal RHRSLOT periodically becomes H only during a period including two clocks. In addition, the signal RHRSLOT is calculated in the refresh control unit 201, and in particular, the period of the signal RHRSLOT depends on the temperature indicated by the temperature data TS.

[0106] During a period in which the logic level of the signal RHRSLOT is H, the signal RHR is generated as two consecutive pulses synchronized with the clock RFIP.

[0107] Before time t5, the logic levels of the priority switching signal RHR2nd and the distance switching signal PM2 are L, L. During the period from time t5 to time t6, the logic levels of the priority switching signal RHR2nd and the distance switching signal PM2 are H, L. During the period from time t6 to time t15, the logic levels of the priority switching signal RHR2nd and the distance switching signal PM2 are L, H. During the period from time t15 to time t16, the logic levels of the priority switching signal RHR2nd and the distance switching signal PM2 are H, H. Subsequently, similarly, the logic levels of the priority switching signal RHR2nd and the distance switching signal PM2 repeat in principle (L, L), (H, L), (L, H), (H, H).

[0108] However, for example, at time t16, the logic level of the distance switching signal PM2 does not change from L to H. In such a case, the logic levels of the priority switching signal RHR2nd and the distance switching signal PM2 repeat (L, L), (H, L) and then (L, L). Similarly, although not shown in the figure, even at the timing when the logic level of the distance switching signal PM2 normally changes from H to L, the logic level of the distance switching signal PM2 may not change from H to L. In such a case, the logic levels of the priority switching signal RHR2nd and the distance switching signal PM2 repeat (L, H), (H, H) and then (L, H). The content of this part will be described in detail later.

[0109] The first sampling signal Sample is generated at time ts11, ts12, ..., ts16, and at these times, the seed address S1 of the A seed is updated. Figure 4 As shown, the seed address S1 corresponding to the updated A seed at time ts11, ts12, ..., ts16 is set to S1(1), S1(2), ...S1(6).

[0110] The second sampling signal Sample is generated at time ts21 and ts22, and at these times, the seed address S2 of the B seed is updated. Figure 4 As shown, the seed address S2 of the B seed corresponding to the update at time ts21 and ts22 is set to S2(2) and S2(3), and the seed address S2 of the B seed before time ts21 is set to S2(1).

[0111] Next, the actions are explained according to the flow of time.

[0112] At time ts11, the seed address S1 of the A seed is updated to S1(1) by the first sampling signal Sample. Since the logic level of the distance switching signal PM2 is L, the seed address of the A seed is selected as the seed address Seed. In addition, since the logic level of the distance switching signal PM2 is L and the logic level of the priority switching signal RHR2nd is L, the priority adjacent RHA S1(1)±1 1st is calculated as RHA based on the seed address S1(1) of the A seed by the first operation.

[0113] At time t5, the logic level of the priority switching signal RHR2nd changes from L to H, and then changes from H to L at time t6. Therefore, the seed address S1(1) of the A seed immediately before time t5 is maintained as the seed address Seed until time t6, and starting from time t5, the non-priority adjacent RHA S1(1)±1 2nd is calculated as RHA by the second operation based on the seed address S1(1) of the A seed.

[0114] In particular, Figure 4 In the example, the seed address S1(1) of the A seed is not updated between time t5 and t6; however, since the logic level of the priority switching signal RHR2nd has changed from L to H at time t5, even if the seed address S1(1) of the A seed is updated between time t5 and t6, the seed address S1(1) of the A seed at the moment before time t5 will be maintained as the seed address Seed until time t6.

[0115] Since the priority neighbor RHA S1(1)±11st is calculated by the first operation based on the seed address S1(1) of the same A seed, and the non-priority neighbor RHA S1(1)±1 2nd is calculated by the second operation, since the amount of calculation of the second operation is greater than that of the first operation, a certain degree of delay period is required until all bits of the non-priority neighbor RHA S1(1)±1 2nd are determined. However, the non-priority neighbor RHA S1(1)±1 2nd can be calculated synchronously with the pulse corresponding to the signal RHR.

[0116] At time t6, the logic level of the distance switching signal PM2 changes from L to H, and the logic level of the priority switching signal RHR2nd changes from H to L. Therefore, the seed address S2(1) of the B seed is selected as the seed address Seed. At the same time, the priority re-adjacent RHA S2(1)±2 1st is calculated as RHA by the third operation based on the seed address S2(1) of the B seed. This continues until time ts21. In addition, the seed address S2(1) of the B seed has been determined at time t1.

[0117] At time ts21, the seed address S2(1) of the seed B is updated to S2(2) by the second sampling signal Sample2. At this time, since the logic level of the distance switching signal PM2 remains H and the logic level of the priority switching signal RHR2nd remains L, the updated seed address S2(2) of the seed B is selected as the seed address Seed. At the same time, the priority adjacent RHA S2(2)±2 1st is calculated as RHA based on the seed address S2(2) of the seed B by the third operation.

[0118] At time t15, the logic level of the priority switching signal RHR2nd changes from L to H, and at time t16 changes from H to L. Therefore, the seed address S2(2) of the B seed immediately before time t15 is maintained as the seed address Seed until time t16, and starting from time t15, the non-priority re-adjacent RHAS2(2)±2 2nd is calculated as RHA by the fourth operation based on the seed address S2(2) of the B seed.

[0119] In particular, Figure 4 In the example, the seed address S2(2) of the B seed is not updated between time t15 and t16; however, since the logic level of the priority switching signal RHR2nd has changed from L to H at time t15, even if the seed address S2(2) of the B seed is updated between time t15 and t16, the seed address S2(2) of the B seed at the moment before time t15 will be maintained as the seed address Seed until time t16.

[0120] Here, since the computational complexity of the fourth operation is greater than that of the third operation, a certain delay period is required until all bits of the non-priority re-adjacent RHA S2(2)±2 2nd are determined. However, the non-priority re-adjacent RHA S2(2)±2 2nd can be calculated synchronously with the pulse corresponding to the signal RHR.

[0121] At time t16, the logic level of the distance switching signal PM2 changes from H to L, and the logic level of the priority switching signal RHR2nd changes from H to L. Therefore, the seed address S1(2) of the A seed is selected as the seed address Seed. At the same time, the priority adjacent RHA S1(2)±1 1st is calculated by the first operation based on the seed address S1(2) of the A seed as RHA. In addition, the seed address of the A seed has been updated to S1(2) by the first sampling signal Sample at time ts12.

[0122] At time ts13, the seed address S1(2) of the A seed is updated to the seed address S1(3) of the A seed by the first sampling signal Sample. At this time, since the logic level of the distance switching signal PM2 is L and the logic level of the priority switching signal RHR2nd remains L, the updated seed address S1(3) of the A seed is selected as the seed address Seed. At the same time, the priority adjacent RHA S1(3)±1 1st is calculated as RHA based on the updated seed address S1(3) of the A seed by the first operation.

[0123] Next, at time ts14, the seed address S1(3) of the A seed is updated to S1(4) by the first sampling signal Sample. At this time, since the logic level of the distance switching signal PM2 is L and the logic level of the priority switching signal RHR2nd remains L, the updated seed address S1(4) of the A seed is selected as the seed address Seed. At the same time, the priority adjacent RHA S1(4)±1 1st is calculated as RHA based on the updated seed address S1(4) of the A seed by the first operation.

[0124] Next, at time ts15, the seed address S1(4) of the A seed is updated to S1(5) by the first sampling signal Sample. At this time, since the logic level of the distance switching signal PM2 is L and the logic level of the priority switching signal RHR2nd remains L, the updated seed address S1(5) of the A seed is selected as the seed address Seed. At the same time, the priority adjacent RHA S1(5)±1 1st is calculated as RHA based on the updated seed address S1(5) of the A seed by the first operation.

[0125] Thereafter, at time t25, the logic level of the priority switching signal RHR2nd changes from L to H, and at time t26 changes from H to L. Therefore, the seed address S1(5) of the A seed immediately before time t25 is maintained as the seed address Seed until time t26, and starting from time t25, the non-priority adjacent RHA S1(5)±1 2nd is calculated as RHA by the second operation based on the seed address S1(5) of the A seed.

[0126] In particular, Figure 4 In the example, although the seed address S1(5) of the A seed is updated to S1(6) through the first sampling signal Sample at time ts16 between times t25 and t26, since the priority switching signal RHR2nd has changed from L to H at time t25, the non-priority adjacent RHA S1(5)±1 2nd is directly calculated as RHA based on the original seed address S1(5) of the A seed by the second operation.

[0127] Then, at time t26, the logic level of the distance switching signal PM2 changes from L to H. In addition, at this time, the logic level of the priority switching signal RHR2nd is still maintained at L. Therefore, the updated seed address S1(6) of the A seed is selected as the seed address Seed. At the same time, based on the seed address S1(6) of the A seed, the priority adjacent RHA is recalculated by the first operation as S1(6)±11st as RHA.

[0128] It is worth mentioning that although the logic level of the distance switching signal PM2 usually changes from L to H at time t26, since the first sampling signal Sample is generated at time ts16 between time t25 and t26 (i.e., the period when the logic level of the priority switching signal RHR2nd is H), the logic level of the distance switching signal PM2 is maintained at L to re-execute the calculation of RHA based on the newly sampled address.

[0129] In addition, although not shown in the figure, Figure 4The example shown also includes an operation example of replacing the adjacent RHA and the re-adjacent RHA. At this time, the second sampling signal is generated at the timing of generating the first sampling signal, and the first sampling signal is generated at the timing of generating the second sampling signal. Therefore, the seed address S1 of the A seed and the seed address S2 of the B seed are replaced. In addition, the polarity of the distance switching signal PM2 is reversed. Then, the timing of the adjacent RHA S1(i)±1 is replaced by the timing of the re-adjacent RHA S2(i)±2, and the timing of the re-adjacent RHA S2(j)±2 is replaced by the timing of the adjacent RHA S1(j)±1.

[0130] Figure 5 The arrangement pattern of the portion of the memory array 225 corresponding to 16 column lines is shown. This arrangement pattern is repeated in the memory array 225. Figure 5 In the memory array 225, eight selection lines FXL corresponding to the decoding results of the lower 3 bits of the column address and a plurality of selection lines MWL corresponding to the decoding results of the higher bits of the column address are wired.

[0131] The sub-word driver 305 selected by both the activated selection line MWL and the activated selection line FXL is activated, and the column line SWL connected thereto is activated.

[0132] The sub-word drivers 305 arranged on the lower side of the column straight line are arranged every two columns, and the sub-word drivers 305 arranged on the upper side of the straight line are also arranged every two columns. These are alternately arranged on the column straight line.

[0133] Four selection lines FXL among the eight selection lines FXL are correspondingly arranged at the lower side of the lower sub-word driver 305 , and the remaining four selection lines FXL are correspondingly arranged at the upper side of the upper sub-word driver 305 .

[0134] The four selection lines FXL on the lower side are arranged in the order of the so-called last 4 digits of the logical column address from the back to the front 000, 010, 100 and 110. In addition, the four selection lines FXL on the upper side are arranged in the order of the so-called last 4 digits of the logical column address from the back to the front 001, 011, 101 and 111. Therefore, the four selection lines FXL corresponding to the even-numbered logical column address are arranged on the lower side, and the four selection lines FXL corresponding to the odd-numbered logical column address are arranged on the upper side.

[0135] Focusing on the four lower selection lines FXL, the selection lines FXL and the wirings 309 are arranged so that intersections 311 of the wirings 309 connecting each selection line FXL and each sub-word driver 305 form a zigzag pattern at a cycle of eight sub-word drivers 305 .

[0136] Similarly, focusing on the four upper selection lines FXL, the selection lines FXL and the wirings 309 are arranged so that intersections 311 of the wirings 309 connecting each selection line FXL and each sub-word driver 305 form a zigzag pattern at a cycle of eight sub-word drivers 305 .

[0137] The intersections 311-0 to 311-f corresponding to the values ​​of the last 4 digits of the column address expressed in binary from 0 to f are arranged as follows: Figure 5 In addition, the sub-word drivers 305-0 to 305-f corresponding to the values ​​of the last 4 digits of the column address expressed in binary from 0 to f are arranged as shown in FIG. Figure 5 Each sub-word driver 305 is connected to the selection line FXL via the intersection 311 and the wiring 309. Therefore, when the remainder when the column address is divided by 16 is expressed as a hexadecimal number from 0 to f, the word line assigned to the column address with a remainder of 0 to the word line assigned to the column address with a remainder of f is as shown in FIG. Figure 5 That is, when the remainder of the column address assigned to the word line is presented by dividing by 16 (when presented by the hexadecimal number of the lower 4 bits of the corresponding column address), the word line in the memory array 225 is

[0138] Arranged in the order of “0,1,2,3,4,5,6,7,e,f,c,d,a,b,8,9”.

[0139] Therefore, the sequence assigned to the word lines according to the order of word lines configured in the memory array 225 is called a physical column address. In addition, if the column decoder simply called a column address and the column address XADD2 input by the memory bank logic unit 207 are called a logical column address, the corresponding relationship between the lower 4 bits of the physical column address and the lower 4 bits of the logical column address is also as follows: Figure 5 As shown, it becomes:

[0140]

[0141] As described above, the column lines SWL in the memory array 255 are arranged in the order of the physical column addresses. Therefore, two randomly selected column lines SWL are separated from each other by a distance corresponding to the difference between the two physical column addresses corresponding to them.

[0142] Furthermore, refer to Figure 5, a physical address (0) is assigned to the word line assigned to the logical column address 0. A physical address (1) is assigned to the word line assigned to the logical column address 1. A physical address (2) is assigned to the word line assigned to the logical column address 2. A physical address (3) is assigned to the word line assigned to the logical column address 3. A physical address (4) is assigned to the word line assigned to the logical column address 4. A physical address (5) is assigned to the word line assigned to the logical column address 5. A physical address (6) is assigned to the word line assigned to the logical column address 6. A physical address (7) is assigned to the word line assigned to the logical column address 7. A physical address (e) is assigned to the word line assigned to the logical column address 8. A physical address (f) is assigned to the word line assigned to the logical column address 9. A physical address (c) is assigned to the word line assigned to the logical column address a. A physical address (d) is assigned to the word line assigned to the logical column address b. A physical address (a) is assigned to the word line assigned to the logical column address c. A physical address (b) is assigned to the word line assigned to the logical column address d. A physical address (8) is assigned to a word line to which a logical column address e is assigned. A physical address (9) is assigned to a word line to which a logical column address f is assigned.

[0143] In reverse reference, the word line to which the physical address (0) is assigned is assigned the logical column address 0. The word line to which the physical address (1) is assigned is assigned the logical column address 1. The word line to which the physical address (2) is assigned is assigned the logical column address 2. The word line to which the physical address (3) is assigned is assigned the logical column address 3. The word line to which the physical address (4) is assigned is assigned the logical column address 4. The word line to which the physical address (5) is assigned is assigned the logical column address 5. The word line to which the physical address (6) is assigned is assigned the logical column address 6. The word line to which the physical address (7) is assigned is assigned the logical column address 7. The word line to which the physical address (8) is assigned is assigned the logical column address e. The word line to which the physical address (9) is assigned is assigned the logical column address f. The word line to which the physical address (a) is assigned is assigned the logical column address c. The word line to which the physical address (b) is assigned is assigned the logical column address d. The word line to which the physical address (c) is assigned is assigned the logical column address a. The word line to which the physical address (d) is assigned is assigned a logical column address b. The word line to which the physical address (e) is assigned is assigned a logical column address 8. The word line to which the physical address (f) is assigned is assigned a logical column address 9.

[0144] Therefore, for example, if logical column address 2 is selected as the seed address of A seed (logical seed address of A seed), the corresponding physical address (physical seed address) is (2), and the logical column addresses of the adjacent RHA are 1 and 3, and the physical addresses corresponding to the adjacent RHA are (1) and (3) adjacent to (2).

[0145] In addition, for example, if the logical column address 7 is selected as the seed address of A seed, the corresponding physical address is (7), and the logical column addresses of the adjacent RHA are 6 and e, and the physical addresses corresponding to the adjacent RHA are (6) and (8) adjacent to (7).

[0146] Furthermore, for example, if the logical column address b is selected as the seed address of the A seed (the logical seed address of the A seed), the physical address (physical seed address) corresponding to it is (d). Next, the physical address (physical RHA) corresponding to the adjacent RHA (logical adjacent RHA) is (c) and (8) adjacent to (d), and the adjacent RHA (logical adjacent RHA) is a and 8.

[0147] Furthermore, for example, if the logical column address 2 is selected as the seed address of the B seed (logical seed address of the B seed), the physical address (physical seed address) corresponding to it is (2). Next, the physical address (physical RHA) corresponding to the re-adjacent RHA (logical re-adjacent RHA) is (0) and (4) re-adjacent to (2), and the re-adjacent RHA (logical re-adjacent RHA) is 0 and 4.

[0148] Furthermore, for example, if the logical column address e is selected as the seed address of the B seed (logical seed address of the B seed), the physical address (physical seed address) corresponding to it is (8). Next, the physical address (physical RHA) corresponding to the re-adjacent RHA (logical re-adjacent RHA) is (6) and (a) which are re-adjacent to (8), and the re-adjacent RHA (logical re-adjacent RHA) is 6 and c.

[0149] Furthermore, for example, if the logical column address b is selected as the seed address of the B seed (logical seed address of the B seed), the physical address (physical seed address) corresponding to it is (d). Next, the physical address (physical RHA) corresponding to the re-adjacent RHA (logical re-adjacent RHA) is (b) and (f) re-adjacent to (d), and the re-adjacent RHA (logical re-adjacent RHA) is d and 9.

[0150] Figure 6 Schematic diagram showing the correspondence between seed addresses and column hammer update addresses. The left side shows the correspondence between the seed address of seed A and the adjacent RHA, and the right side shows the correspondence between the seed address of seed B and the adjacent RHA. Figure 6 In the display, only the lower 4 bits are displayed.

[0151] Reference Figure 6On the left side, it can be seen that by inverting only the lowest bit of the logical seed address 2 of the A seed from 0 to 1, the logical neighbor RHA 3 can be calculated. In addition, it can be seen that by inverting only the lowest bit of the logical seed address 7 of the A seed from 1 to 0, the logical neighbor RHA 6 can be calculated. Furthermore, by inverting only the lowest bit of the logical seed address b of the A seed from 1 to 0, the logical neighbor RHA a can be calculated. This operation corresponds to the first operation.

[0152] However, the logical adjacent RHA 8 cannot be calculated by simply inverting the lowest bit of the logical seed address b of the A seed. In order to calculate the logical adjacent RHA 8 from the logical seed address b of the A seed, in addition to inverting the lowest bit from 1 to 0, it is necessary to invert the second lowest bit from 1 to 0. For this purpose, a certain degree of complex calculation such as carry processing is required. This operation corresponds to the second operation.

[0153] Therefore, the priority neighbor RHA corresponding to the logical seed address b of the A seed is a, and the non-priority neighbor RHA is 8.

[0154] Reference Figure 6 On the right side of , it can be seen that by only inverting the second low bit of the logical seed address 2 of the B seed from 1 to 0, the logical re-adjacent RHA 0 can be calculated. In addition, it can be seen that by only inverting the second low bit of the logical seed address e of the B seed from 1 to 0, the logical re-adjacent RHA c can be calculated. Furthermore, by only inverting the second low bit of the logical seed address b of the B seed from 1 to 0, the logical re-adjacent RHA 9 can be calculated. This operation corresponds to the third operation.

[0155] However, the logical re-adjacent RHA d cannot be calculated from the logical seed address b by simply inverting the second lower bit of the logical seed address b of the B seed. In order to calculate the logical re-adjacent RHA d from the logical seed address b of the B seed, in addition to inverting the second lower bit from 1 to 0, the third lower bit needs to be inverted from 0 to 1. For this purpose, a certain degree of complex calculation such as carry processing is required. This operation corresponds to the fourth operation.

[0156] Therefore, the priority re-adjacent RHA corresponding to the logical seed address b of the B seed is 9, and the non-priority re-adjacent RHA is d.

[0157] In addition, by adding 1 or subtracting 1 to the physical seed address of the logical seed address corresponding to the A seed, the physical RHA of the logical RHA corresponding to the A seed can be obtained. Therefore, in order to obtain the logical adjacent address from the logical seed address of the A seed, for example, the following steps can be performed: (SA1) obtain the physical seed address from the logical seed address of the A seed (perform forward conversion). (SA2) obtain the physical adjacent RHA by adding 1 or subtracting 1 to the physical seed address (shift the physical address). (SA3) obtain the logical adjacent RHA from the physical adjacent RHA (perform reverse conversion).

[0158] Similarly, by adding 2 or subtracting 2 to the physical seed address of the logical seed address corresponding to the B seed, the physical RHA of the logical RHA corresponding to the B seed can be obtained. Therefore, in order to obtain the logical re-adjacent address from the logical seed address of the B seed, for example, the following steps can be performed: (SB1) obtain the physical seed address from the logical seed address of the B seed (perform forward conversion). (SB2) obtain the physical re-adjacent RHA by adding 2 or subtracting 2 to the physical seed address (shift the physical address). (SB3) obtain the logical re-adjacent RHA from the physical re-adjacent RHA (perform reverse conversion).

[0159] Here, in order to obtain the physical seed address from the logical seed address by forward conversion, in addition to referring to the correspondence table between the two, the following bit operation may be performed, for example.

[0160] Logical seed address:

[0161] (Ain<n:3+1> ,

[0162] Ain <3> ,Ain <2> ,Ain <1> ,Ain <0> )

[0163] Entity seed address:

[0164] (APin<n:3+1> ,

[0165] APin <3> ,APin <2> ,APin <1> ,APin <0> )

[0166] Operation:

[0167] APin <0> =Ain <0>

[0168] APin <1> =Ain <1> ^APin <1> =Ain <1> Ain <3>

[0169] APin <2> =Ain <2> ^APin <2> =Ain <2> Ain <3>

[0170] APin <3> =Ain <3>

[0171] APin<n:3+1> =Ain<n:3+1>

[0172] The operator ^ displays the logical exclusive OR operation.

[0173] Similarly, in order to obtain the logical adjacent RHA from the physical adjacent RHA by reverse conversion, in addition to referring to the correspondence table between the two, the following bit operation may be performed, for example.

[0174] Physical RHA:

[0175] (APout<n:3+1> ,

[0176] APout <3> ,APout <2> ,APout <1> ,APout <0> )

[0177] Logic RHA:

[0178] (Aout<n:3+1> ,

[0179] Aout <3> ,Aout <2> ,Aout <1> ,Aout <0> )

[0180] Operation:

[0181] Aout <0> =APout <0>

[0182] Aout <1> =APiut <1> ^Aout <1> =APout <1> APout <3>

[0183] Aout <2> =AOiyt <2> ^Aout <2> =APout <2> APout <3>

[0184] Aout <3> =APout <3>

[0185] Aout<n:3+1> =APout<n:3+1>

[0186] The operator ^ displays the logical exclusive OR operation.

[0187] The logical re-adjacency RHA can also be obtained from the physical re-adjacency RHA in the same way.

[0188] Figure 7 To display Figure 3 1 is a circuit diagram showing the configuration of the calculation unit 249. As described above, the calculation unit 249 calculates and outputs four types of RHA based on the seed address Seed according to the combination of the distance switching signal PM2 and the priority switching signal RHR2nd.

[0189] The calculation unit 249 includes a modified 4-bit addition unit 401, which calculates the lower 4 bits Aout<3:0> of RHA, the carry C<3:0>, and the lower 4 bits Ain<3:0> of the seed address, the distance switching signal PM2, and the priority switching signal RHR2nd. <3> In addition, the calculation unit 249 further includes m half adders 411, which use the lower 4 bits of the seed address to calculate the positive and negative switching signals based on the high bit portion Ain. <n-1:4>, Carry C <3> The positive and negative switching signal SWPM calculates the higher bit portion Aout than the lower 4 bits of RHA <n:4>Here, if the number of bits constituting RHA is set to n, m is n-4.

[0190] To explain in more detail, the modified 4-bit adder 401 calculates the lower 4 bits Aout<3:0>, carry C<3:0>, and the logic RHA (i.e., RHA) corresponding to the lower 4 bits Ain<3:0> of the logic seed address Seed while referring to the distance switching signal PM2 and the priority switching signal RHR2nd. <3> and a positive / negative switching signal SWPM. The structure of the modified 4-bit adder 401 will be described later.

[0191] As described above, the distance switching signal PM2 is a signal for specifying the calculation of the adjacent RHA or the calculation of the re-adjacent RHA. In addition, the priority switching signal RHR2nd is a signal for specifying the calculation of the priority RHA (priority adjacent RHA or priority re-adjacent RHA) or the calculation of the non-priority RHA (non-priority adjacent RHA or non-priority re-adjacent RHA) for the same seed address. The positive and negative switching signal SWPM is a signal for specifying the calculation of the upper side RHA or the calculation of the lower side RHA in the order of the physical addresses for the same seed address.

[0192] The half adder 411 includes logical exclusive OR gates 412 and 413 and an AND gate 414. The half adder 411 is also provided in each bit in the modified 4-bit addition unit 401 (see Fig.10 ). The logic exclusive OR gate 412 operates the corresponding bit Ain of the input address. (here, i=4 to n-1) and the carry input C from the lower bit <i-1>The logical exclusive OR is used as the output address Aout In addition, the logical exclusive OR gate 413 operates the corresponding bit Ain of the input address. (here, i=4 to n-1) and the logic exclusive OR of the positive and negative switching signal SWPM. Furthermore, the AND gate 414 inputs the carry from the low bit to C <i-1>The result of the logical exclusive operation by the logical exclusive OR gate 412 is used as the carry output C Output.

[0193] The positive / negative switching signal SWPM is calculated inside the modified 4-bit adder 401 as described below.

[0194] Reference Fig. 9 When the distance switching signal PM2 is L, the priority switching signal RHR2nd and the bit Ain <0> The combination of the logic levels of the positive and negative switching signal SWPM determines the logic level of the positive and negative switching signal. When the priority switching signal RHR2nd is L, the bit Ain <0> The logic level of the positive and negative switching signal SWPM directly becomes the logic level of the positive and negative switching signal; when the priority switching signal RHR2nd is H, the bit Ain <0> The inverted logic level of the logic level becomes the logic level of the positive-negative switching signal SWPM.

[0195] Therefore, when the adjacent RHA is designated (PM2 = L) and the priority RHA is designated (RHR2nd = L), when the lowest bit Ain of the seed address <0> Specify +1 for L. When the lowest bit of the seed address Ain <0> On the other hand, when the adjacent RHA is specified (PM2 = L) and the non-priority RHA is specified (RHR2nd = H), when the lowest bit Ain of the seed address <0> Specify -1 for L. When the lowest bit of the seed address Ain <0> Specifies the operation of +1 for H.

[0196] Here, the "-1 operation" is an operation for calculating the RHA (upper-side adjacent RHA) to which only the wiring that is 1 away from the upper side is assigned to the wiring to which the seed address of the A seed is assigned in the order of the physical address. In addition, the "+1 operation" is an operation for calculating the RHA (lower-side adjacent RHA) to which only the wiring that is 1 away from the lower side is assigned to the wiring to which the seed address of the A seed is assigned in the order of the physical address.

[0197] Please go back Fig. 9 When the distance switching signal PM2 is H, the priority switching signal RHR2nd and the bit Ain <1> With Bit Ain <3> The combination of the results of the logical exclusive OR operation determines the positive and negative switching signal SWPM. When the priority switching signal RHR2nd is L, the bit Ain <1> With Bit Ain <3> The logic level of the result of the logical exclusive OR operation directly becomes the logic level of the positive and negative switching signal SWPM; when the priority switching signal RHR2nd is H, the bit Ain <1> With Bit Ain <3> The inverted logic level of the result of the logical exclusive OR operation becomes the logic level of the positive-negative switching signal SWPM.

[0198] In addition, as mentioned above, the bit Ain of the seed address <1> With Ain <3> The result of the logical exclusive OR operation is combined with the bit APin of the physical seed address. <1> correspond.

[0199] Therefore, when the next adjacent RHA is designated (PM2 = H) and the priority RHA is designated (RHR2nd = L), when the bit Ain of the seed address <1> With Ain <3> The result of the logical exclusive OR operation is the operation specified by L + 2. When the bit Ain of the seed address <1> With Ain <3> The result of the logical exclusive OR operation is the operation of H specifying -2; on the other hand, when the next adjacent RHA is specified (PM2 = L) and the non-priority RHA is specified (RHR2nd = H), when the bit Ain of the seed address <1> With Ain <3> The result of the logical exclusive OR operation is L-2. When the bit Ain of the seed address <1> With Ain <3> The result of the logical exclusive OR operation is the operation specified by H + 2.

[0200] Here, the "-2 operation" is an operation for calculating the RHA assigned to the wiring that is 2 away from the upper side only (the upper side adjacent RHA) relative to the wiring assigned to the seed address of the B seed in the order of the physical address. In addition, the "+2 operation" is an operation for calculating the RHA assigned to the wiring that is 2 away from the lower side only (the lower side adjacent RHA) relative to the wiring assigned to the seed address of the B seed in the order of the physical address.

[0201] Here, the seed address of seed A, the upper side neighbor RHA, the lower side neighbor RHA, the priority neighbor RHA, and the non-priority neighbor RHA are summarized as follows: Figure 8 In addition, the seed address of seed B, the upper side neighbor RHA, the lower side neighbor RHA, the priority neighbor RHA and the non-priority neighbor RHA are summarized as follows: Figure 8 As shown in (b) in the figure. The corresponding relationship between the physical address and the logical address is as follows Figure 8 Here, although Figure 8 (a) and Figure 8 The addresses shown in the table (b) are all logical addresses and can be referenced by Figure 8 In (c), find the corresponding entity address.

[0202] To obtain the upper-side neighbor RHA of the logical address corresponding to the A seed, refer to Figure 8 In the table (c), the physical address of seed A is obtained from the logical address of seed A, and the physical address that is 1 less than the physical address of seed A is obtained as the physical upper-side adjacent RHA. Then, the logical address corresponding to the physical upper-side adjacent RHA is the upper-side adjacent RHA.

[0203] To obtain the lower-side adjacent RHA of the logical address corresponding to the A seed, refer to Figure 8 In the table (c), the physical address of seed A is obtained from the logical address of seed A, and the physical address that is only 1 more than the physical address of seed A is obtained as the physical lower-side adjacent RHA. Then, the logical address corresponding to the physical lower-side adjacent RHA is the lower-side adjacent RHA.

[0204] To find the upper-side adjacent RHA of the logical address corresponding to the B seed, refer to Figure 8 In the table (c), the physical address of seed B is obtained from the logical address of seed B, and the physical address that is less than the physical address of seed B by 2 is obtained as the physical upper-side re-adjacent RHA. Then, the logical address corresponding to the physical upper-side re-adjacent RHA is the upper-side re-adjacent RHA.

[0205] To obtain the lower-side adjacent RHA of the logical address corresponding to the B seed, refer to Figure 8 In the table (c), the physical address of seed B is obtained from the logical address of seed B, and the physical address that is only 2 more than the physical address of seed B is obtained as the physical lower-side re-adjacent RHA. Then, the logical address corresponding to the physical lower-side re-adjacent RHA is the lower-side re-adjacent RHA.

[0206] Fig.10 To display Figure 7 FIG. 4 is a circuit diagram of a configuration example of the modified 4-bit adder 401. As described above, the modified 4-bit adder 401 includes four half adders 411, each corresponding to each bit of Ain<3:0> of the RHA to be calculated.

[0207] Please refer to Fig.10 , the 4-bit addition unit 401 is modified to convert the seed address Seed into a physical seed address, including the bit Ain of the seed address Seed <1> The corresponding logical exclusive OR gate 432 and the bit Ain of the seed address Seed <2> The corresponding logical exclusive OR gate 433. The logical exclusive OR gate 432 converts the bit Ain of the seed address Seed <1> With Bit Ain <3> The result of the logical exclusive OR operation is used as the bit APin of the physical seed address. <1> Similarly, the logical exclusive OR gate 433 converts the bit Ain of the seed address Seed to <2> With Bit Ain <3> The result of the logical exclusive OR operation is used as the bit APin of the physical seed address. <2> Output.

[0208] In addition, the physical seed address bit APin <n-1:3>and APin <0> and the bit Ain of the seed address <n-1:3>and Ain <0> same.

[0209] Here, the logical exclusive OR gates 432 and 433 constitute the key of the conversion unit from the seed address Seed to the physical seed address (corresponding to the "forward address conversion unit" of the present application).

[0210] Please refer to Fig.10 , the modified 4-bit adder 401 further includes a bit Aout corresponding to RHA in order to inversely convert the physical RHA to RHA <1> The logical exclusive OR gate 482 and the corresponding bit Aout of RHA <2> The logical exclusive OR gate 483. The logical exclusive OR gate 482 converts the bit APout of the physical RHA <1> and bit APout <3> The result of the logical exclusive OR operation is used as the bit Aout of RHA. <1> Similarly, logical exclusive OR gate 483 converts the bit APout of physical RHA to <2> and bit APout <3> The result of the logical exclusive OR operation is used as the bit Aout of RHA. <2> Output.

[0211] In addition, RHA's bit Aout <n-1:3>and Aout <0> APout with physical RHA <n-1:3>and APout <0> same.

[0212] Here, the logical exclusive OR gates 482 and 483 constitute the key of the conversion unit from physical RHA to RHA (corresponding to the "reverse address conversion unit" of the present application).

[0213] Furthermore, the modified 4-bit adder 401 includes a NOT gate 431 for calculating a signal EN1 which inverts the distance switching signal PM2 .

[0214] Furthermore, the modified 4-bit adder 401 includes a selector 434 and a logical exclusive OR gate 435. The logical exclusive OR gates 432, 435 and the selector 434 are used to refer to Fig. 9 The combination of the described signals calculates the positive and negative switching signal SWPM.

[0215] Furthermore, the modified 4-bit adder 401 includes a selector 481. The selector 481 is controlled by the distance switching signal PM2 to output the carry output C of the half adder 411 corresponding to the signal of logic level H or the least significant bit. <0> Output as signal EN2.

[0216] Here, from the corresponding least significant bit <0> The half adder 411 is used to store the most significant bit. <n-1>The half adder 411 and the selector 481 correspond to the "physical address shift unit" of the present application.

[0217] Next, the operation is described. When the logic level of the distance switching signal PM2 is L, the signal EN1 with a logic level of H is input to the carry input terminal (the input terminal shared by the logical exclusive OR gate 412 and the AND gate 414) of the half adder 411 corresponding to the lowest bit when the seed address based on the A seed is specified to calculate the adjacent RHA. <0> The reverse logic level of the logic level becomes the bit Aout of RHA <0> logic level.

[0218] In addition, the logic level of the distance switching signal PM2 is L. Therefore, when the adjacent RHA is specified to be calculated based on the seed address of the A seed, and the logic level of the priority switching signal RHR2nd is L, therefore, when the priority adjacent RHA is specified to be calculated among the two adjacent RHAs, the positive and negative switching signal SWPM becomes Ain through the selector 434 and the logical exclusive OR gate 435. <0> At this time, RHA is calculated as follows.

[0219] If the seed address bit Ain of the A seed <0> is L, the positive-negative switching signal SWPM becomes L, and the lower adjacent (+1) RHA is calculated as the priority adjacent RHA among the two adjacent RHAs. On the other hand, if the bit Ain of the seed address of the A seed <0> =H, the positive and negative switching signal SWPM becomes H, and the upper adjacent (-1) RHA is calculated as the priority adjacent RHA among the two adjacent RHAs. In these cases, the only operation required is to invert the lowest bit Ain. <0> The carry process is not required in any half adder 411 included in the calculation unit 249. However, the operation is performed in the logical exclusive OR gates 432, 433, 482 and 483.

[0220] In addition, the logic level of the distance switching signal PM2 is L, so when the adjacent RHA is specified to be calculated based on the seed address of the A seed, and the logic level of the priority switching signal RHR2nd is H, so when the non-priority adjacent RHA is specified to be calculated among the two adjacent RHAs, the positive and negative switching signal SWPM becomes an inverted Ain through the selector 434 and the logical exclusive OR gate 435. <0> At this time, RHA is calculated as follows.

[0221] If the seed address bit Ain of the A seed <0> is L, the positive and negative switching signal SWPM becomes H, and the upper adjacent (-1) RHA is calculated as the non-priority adjacent RHA among the two adjacent RHAs. On the other hand, if the bit Ain of the seed address of the A seed <0> =H, the positive and negative switching signal SWPM becomes L, and the lower adjacent (+1) RHA is calculated as the non-priority adjacent RHA among the two adjacent RHAs. In these cases, the required operation is not only to invert the lowest bit Ain <0> The operation of . In at least a part of the half adder 411 included in the calculation unit 249, the processing including the carry processing needs to be performed. In addition, the operation is also performed in the logical exclusive OR gates 432, 433, 482 and 483.

[0222] In addition, the logic level of the distance switching signal PM2 is H. Therefore, when the seed address based on the B seed is specified to calculate the re-adjacent RHA, and the logic level of the priority switching signal RHR2nd is L, therefore, when the priority re-adjacent RHA is specified to be calculated among the two re-adjacent RHAs, the positive and negative switching signal SWPM becomes Ain through the selector 434 and the logic exclusive OR gate 435. <1> With Ain <3> The logical mutually exclusive or logic level (that is, the second low bit APin of the physical address of the physical address of the seed address of the B seed) <1> At this time, RHA is calculated as follows.

[0223] If the seed address bit Ain of seed B <1> With Ain <3> The result of the logical exclusive OR operation (that is, the second low bit APin of the physical address of the physical address of the seed address of the B seed) <1> ) is L, the positive-negative switching signal SWPM becomes L, and the lower-order re-adjacent (+2) RHA is calculated as the priority re-adjacent RHA among the two re-adjacent RHAs. On the other hand, if the bit Ain of the seed address of the B seed <1> With Ain <3> The result of the logical exclusive OR operation (that is, the second low bit APin of the physical address of the physical address of the seed address of the B seed) <1> ) is H, the positive and negative switching signal SWPM becomes H, and the upper side re-adjacent (-2) RHA is calculated as the priority re-adjacent RHA among the two re-adjacent RHAs. In these cases, the only operation required is to invert the second low bit APin of the seed address of the B seed. <1> The carry process is not required in any half adder 411 included in the calculation unit 249. However, the operation is performed in the logical exclusive OR gates 432, 433, 482 and 483.

[0224] In addition, the logic level of the distance switching signal PM2 is H. Therefore, when the seed address based on the B seed is specified to calculate the re-adjacent RHA, and the logic level of the priority switching signal RHR2nd is H, therefore, when the non-priority re-adjacent RHA is specified to be calculated among the two re-adjacent RHAs, the positive and negative switching signal SWPM becomes an inverted Ain through the selector 434 and the logic exclusive OR gate 435. <1> With Ain <3> The logical mutually exclusive or logic level of the seed address of the seed B is inverted. <1> At this time, RHA is calculated as follows.

[0225] If the seed address bit Ain of seed B <1> With Ain <3> The result of the logical exclusive OR operation (that is, the second low bit APin of the physical address of the physical address of the seed address of the B seed) <1> ) is L, the positive and negative switching signal SWPM becomes H, and the upper side re-adjacent (-2) RHA is calculated as the non-priority re-adjacent RHA among the two re-adjacent RHAs. On the other hand, if the seed address Ain of the B seed <1> With Ain <3> The result of the logical exclusive OR operation (that is, the second low bit APin of the physical address of the physical address of the seed address of the B seed) <1> ) is H, the positive and negative switching signal SWPM becomes L, and the lower side re-adjacent (+2) RHA is calculated as the priority re-adjacent RHA among the two re-adjacent RHAs. In these cases, the required operation is not only to invert the second low bit APin of the seed address of the B seed. <1> The operation of . In at least a part of the half adder 411 included in the calculation unit 249, the processing including the carry processing needs to be performed. In addition, the operation is also performed in the logical exclusive OR gates 432, 433, 482 and 483.

[0226] Although some of the instructions are repeated here, please refer to Figure 4 , during the period when the logic levels of the priority switching signal RHR2nd and the distance switching signal PM2 are L, it becomes possible to update the adjacent RHA of the A seed by inverting only the lowest bit of the seed address S1 immediately after the seed address S1 of the A seed is updated by the first sampling signal Sample. This is because one of the two adjacent RHAs (the upper side adjacent RHA and the lower side adjacent RHA) is selected as the priority adjacent RHA by the above logic.

[0227] In addition, while the logic level of the distance switching signal PM2 is maintained at L, if the logic level of the priority switching signal RHR2nd changes from L to H, the priority adjacent RHA is switched to the non-priority adjacent RHA synchronously therewith. That is, if the upper side adjacent address is selected as the priority adjacent RHA, it is switched to the lower side adjacent address as the non-priority adjacent RHA. On the contrary, if the lower side adjacent address is selected as the priority adjacent RHA, it is switched to the upper side adjacent address as the non-priority adjacent RHA.

[0228] In addition, during the period when the logic level of the distance switching signal PM2 is L and the logic level of the priority switching signal RHR2nd is H, even if the seed address S1 of the A seed is updated by the first sampling signal Sample, since the seed address Seed provided to the calculation unit 249 is held by the latch 241 controlled by the priority switching signal RHR2nd, the updating of RHA during this period can be avoided. That is, during the period when the logic level of the distance switching signal PM2 is L and the logic level of the priority switching signal RHR2nd is H, the updating of RHA by the processing including the carry processing based on the new seed address can be avoided.

[0229] Similarly, during the period when the logic level of the priority switching signal RHR2nd is L and the logic level of the distance switching signal PM2 is H, the physical address of the corresponding RHA can be updated immediately after the seed address S2 of the B seed is updated by the second sampling signal Sample2 by inverting only the second lower bit of the physical address corresponding to the seed address S2 of the B seed when viewed from a set of half adders 411. This is because one of the two re-adjacent RHAs (the upper re-adjacent RHA and the lower re-adjacent RHA) is selected as the priority re-adjacent RHA by the above logic.

[0230] In addition, while the logic level of the distance switching signal PM2 is maintained at H, if the logic level of the priority switching signal RHR2nd changes from L to H, the priority re-adjacent RHA is switched to the non-priority re-adjacent RHA synchronously therewith. That is, if the upper side re-adjacent address is selected as the priority re-adjacent RHA, it is switched to the lower side re-adjacent address. On the contrary, if the lower side re-adjacent address is selected as the priority re-adjacent RHA, it is switched to the upper side adjacent address.

[0231] In addition, during the period when the logic level of the distance switching signal PM2 is H and the logic level of the priority switching signal RHR2nd is H, even if the seed address S2 of the B seed is updated by the second sampling signal Sample2, since the seed address Seed provided to the calculation unit 249 is held by the latch 241 controlled by the priority switching signal RHR2nd, the updating of RHA during this period can be avoided. That is, during the period when the logic level of the distance switching signal PM2 is H and the logic level of the priority switching signal RHR2nd is H, the updating of RHA by the processing including the carry processing based on the new seed address can be avoided.

[0232] The second embodiment of the present application is described below. The second embodiment has the same basic structure as the first embodiment, so repeated descriptions are omitted. Compared with the first embodiment, in the second embodiment, the structure of the modified 4-bit adder 401 included in the calculation unit 249 is different. In addition, in the second embodiment, the modified 4-bit adder 401 is based on Fig.11 The truth table calculation shown.

[0233] Although Fig.11 The truth table shown records repetition. If the lower 4 bits of the seed address (logical seed address) are presented as A<3:0>, the lower 4 bits of RHA (logical RHA) are presented as B<3:0>, and the carry output of the third lower bit from the inside of the calculation unit 249 is presented as C3, the bits B3 to B0 contained in the lower 4 bits B<3:0> of RHA and the carry output C3 can be calculated based on the bits A3 to A0 contained in the lower 4 bits A<3:0> of the seed address through operations 1 to 4 with the following logical expressions.

[0234] (Operation 1) Prioritize adjacent RHA (PM2 = L, RHR2nd = L)

[0235] B0=!A0

[0236] B1=A1

[0237] B2=A2

[0238] B3=A3

[0239] C3=0

[0240] (Operation 2) Non-priority adjacent RHA (PM2 = L, RHR2nd = H)

[0241] B0=!A0

[0242] B1=A1^{(A0^A1^A3)|(A1^A2)}

[0243] B2=A2^! {(A0^A1^A3)|(A1^A2)}

[0244] B3=A3^! {(A0^A1^A3)|(A1^A2)}

[0245] C3=(!A0^A3)&(A1|A2)

[0246] (Operation 3) Prioritize the adjacent RHA (PM2 = H, RHR2nd = L)

[0247] B0=A0

[0248] B1=!A1

[0249] B2=A2

[0250] B3=A3

[0251] C3=0

[0252] (Operation 3) Non-priority re-adjacent RHA (PM2 = H, RHR2nd = H)

[0253] B0=A0

[0254] B1=A2

[0255] B2=A1

[0256] B3=A3^! (A1^A2)

[0257] C3=!(A1|A2)

[0258] Here, for

[0259] ! :NOT

[0260] |:OR

[0261] &: AND

[0262] ^

[0263] :OR.

[0264] Here, in addition to the formula related to bit B0, by replacing A0 included in the formula corresponding to the adjacent non-priority RHA with A1^A3, the formula corresponding to the re-adjacent non-priority RHA can be obtained.

[0265] To perform the above calculations, for example, one can use Fig.12 The modified 4-bit adder 401 is shown. The modified 4-bit adder 401 may include a calculation unit 501 corresponding to the above calculation (1), a calculation unit 502 corresponding to the above calculation (2), a calculation unit 503 corresponding to the above calculation (3), a calculation unit 504 corresponding to the above calculation (4), and a selection circuit 505 for selecting output signals from the calculation units 501, 502, 503 and 504 as outputs according to the distance switching signal PM2 and the priority switching signal RHR2nd.

[0266] The third embodiment of the present application is described below. The basic structure of the third embodiment is the same as that of the first embodiment, and repeated descriptions are omitted here. Compared with the first embodiment, the structure of the modified 4-bit addition unit 401 included in the calculation unit 249 in the third embodiment is different. In addition, in the second embodiment, the selection circuit 505 is operated as a functional block. In contrast, in the third embodiment, after the logic circuit inside the selection circuit 505 is concretized, the logic circuits related to each bit B0 to B3 of the RHA and the carry C0 are integrated into one. That is, in the third embodiment, the logic circuits included in the operation units 501 to 504 and the selection circuit 505 are integrated into one.

[0267] Reference Fig.13 The circuit shown calculates and outputs the priority adjacent RHA, non-priority adjacent RHA, priority re-adjacent RHA, or non-priority re-adjacent RHA corresponding to the seed address for the lower 4 bits according to the combination of the distance switching signal PM2 and the priority switching signal RHR2nd.

[0268] In addition, operations corresponding to the above-mentioned operations i (i=1 to 4) and operations corresponding to the selection may be regarded as the operation i.

[0269] The fourth embodiment of the present application is described below. The fourth embodiment has the same basic structure as the first embodiment, so repeated descriptions are omitted. Compared with the first embodiment, the structure of the modified 4-bit adder 401 included in the calculation unit 249 of the fourth embodiment is different. In addition, in the second embodiment, the selection circuit 505 is operated as a functional block. In contrast, in the fourth embodiment, after the logic circuit inside the selection circuit 505 is concretized, the logic circuits of each bit B0 to B3 of RHA and the carry C0 are integrated into one. That is, in the fourth embodiment, Fig.14 As shown, the logic circuits included in the operation units 501 to 504 and the selection circuit 505 are integrated into one. Here, the modified 4-bit adder 401 of the fourth embodiment is common to the modified 4-bit adder 401 of the third embodiment.

[0270] Unlike the modified 4-bit adder 401 of the third embodiment, the modified 4-bit adder 401 of the fourth embodiment has interchangeability as described below.

[0271] like Fig.14 As shown in FIG. 1 , the logic circuit of the fourth embodiment has a form in which the first part 511 is combined with the second part 513. Here, Fig.15 As shown, it can be Fig.14 The first part 511 and the third part 515 are exchanged, and the third part 515 is connected to the second part 513. In addition, while the first part 511 and the second part 513 include a combinational circuit, the third part 515 does not include a combinational circuit and is composed only of wiring.

[0272] like Fig.14 As shown, when the modified 4-bit adder 401 is configured to combine the first part 511 and the second part 513, the modified 4-bit adder 401 outputs the adjacent RHA and the re-adjacent RHA. On the other hand, when the modified 4-bit adder 401 is configured to combine the third part 515 and the second part 513, the modified 4-bit adder 401 does not output the adjacent RHA and the re-adjacent RHA.

[0273] More specifically, the first part 511 inputs the lowest bit Ain of the seed address <0> , the second lowest bit Ain <1> 、4th low bit Ain <3> , distance switching signal PM2 and priority switching signal RHR2nd. In addition, when the distance switching signal PM2 indicates that the current unit period is the A seed period, the first part 511 directly maintains and outputs the lowest bit Ain of the seed address. <0> , the second lowest bit Ain <1> Furthermore, when the distance switching signal PM2 indicates that the current unit period is the B seed period, the first part 511 outputs the lowest bit Ain of the seed address. <0> , the second lowest bit Ain <1> 、4th low bit Ain <3> , the distance switching signal PM2 and the priority switching signal RHR2nd are signals obtained by the first combinational circuit included in the first part 511.

[0274] That is, when the distance switching signal PM2 indicates that the current unit period is the A seed period, the signal A0p and the signal A0d output by the first part 511 have the same lowest bit Ain as the seed address. <0> The signal A1p output by the first part 511 has the same logic level as the second low bit Ain of the seed address. <1> same logic level.

[0275] In addition, when the distance switching signal PM2 indicates that the current unit period is the B seed period, the logic level of the signal A0p output by the first part 511 is the least significant bit Ain of the inverted seed address. <0> The logic level of the signal A0d has the lowest bit Ain of the seed address. <0> and the 4th low bit Ain <3> The logically exclusive OR of the logic levels.

[0276] When the distance switching signal PM2 indicates that the current unit period is the B seed period and the priority switching signal RHR2nd indicates the priority period, the signal A1p has the second low bit Ain of the inverted seed address. <1> On the other hand, when the distance switching signal PM2 indicates that the current unit period is the B seed period and the priority switching signal RHR2nd indicates that it is a non-priority period, the signal A1p has the same logic level as the second low bit Ain of the seed address. <1> same logic level.

[0277] In the second part 513, the signal A0p is input to the least significant bit Aout corresponding to RHA. <0> The signal A0d is input to the bit Aout<3:0> of RHA and the logical exclusive OR gate 527 and the NOT gate 529 associated with the signal SWPM. The signal A1p is input to the second lower bit Aout corresponding to RHA. <1> In the logical exclusive OR gate 523.

[0278] Reference Fig.15 , in section 3 515, the bit Ain of the seed address <0> Directly become signal A0p and signal A0d, seed address bit Ain <1> Directly becomes signal A1p.

[0279] This configuration can achieve interchangeability. That is, when only the adjacent RHA is required to be calculated, the third part 515 and the second part 513 are combined to form the modified 4-bit adder 401. When both the adjacent RHA and the re-adjacent RHA are required to be calculated, the first part 511 and the second part 513 are combined to form the modified 4-bit adder 401.

[0280] In addition, if it is not necessary to exchange the first part 511 and the third part 515 for interchangeability, Fig.14 In the circuit of , the first part 511 can also always be combined with the second part 513. Similarly, in Fig.15 In the circuit, the third part 515 can also be combined with the second part 513.

[0281] It is particularly noted that, according to the second to fourth embodiments, the conversion from the seed address to the physical seed address does not require the conversion from the physical RHA to the RHA.

[0282] As described above, according to the RHA calculation circuit of this embodiment, the calculation of the column thump update address can be performed with a small circuit scale.

[0283] The embodiments described above are recorded to make the present application easier to understand and are not intended to limit the present application. Therefore, the elements disclosed in the embodiments described above are intended to include all design changes or equivalents within the technical scope of the present application.

[0284] For example, in the above embodiments, although the Figure 5 The corresponding relationship between the logical address and the physical address of the wiring and the configuration of the sub-word driver shown in the figure is taken as a premise, but the corresponding relationship with other configurations can also be taken as a premise. For example, if the circuit calculation of at least one of the two adjacent RHAs corresponding to various sub-addresses can be simplified, the RHA of that side can be set as the priority RHA. Similarly, if the circuit calculation of at least one of the two adjacent RHAs corresponding to various sub-addresses can be simplified, the RHA of that side can be set as the priority RHA.

Claims

1. A column thump update address calculation circuit, which is a column thump update address calculation circuit for calculating a column thump update address, characterized in that: include: a calculation unit that, in a memory array including a plurality of memory cells arranged in rows and columns, complementarily calculates an upper-side adjacent column thump update address and a lower-side adjacent column thump update address by a first operation or a second operation whose operation amount is larger than the first operation, wherein the upper-side adjacent column thump update address corresponds to a word line that is adjacent to the upper side of a word line assigned to a seed address, and the lower-side adjacent column thump update address corresponds to a word line that is adjacent to the lower side of the word line assigned to the seed address, and complementarily calculates an upper-side re-adjacent column thump update address and a lower-side re-adjacent column thump update address by a third operation or a fourth operation whose operation amount is larger than the third operation, wherein the upper-side re-adjacent column thump update address corresponds to a word line that is adjacent to the upper side of the word line assigned to the seed address, and the lower-side re-adjacent column thump update address corresponds to a word line that is adjacent to the lower side of the word line assigned to the seed address; as well as A control unit controls the operation of the calculation unit, and takes the updating of the seed address as an opportunity to use the address obtained by the first operation as a priority adjacent column thump update address among the upper side adjacent column thump update address and the lower side adjacent column thump update address corresponding to the updated seed address, and the first operation is used for priority calculation; and, taking the updating of the seed address as an opportunity to use the address obtained by the third operation as a priority adjacent column thump update address among the upper side re-adjacent column thump update address and the lower side re-adjacent column thump update address corresponding to the updated seed address, and the third operation is used for priority calculation.

2. The column thumping update address calculation circuit according to claim 1, characterized in that: The control unit provides the calculation unit with a first identification signal and a second identification signal, the first identification signal being used to identify that the current unit period is a seed address based on an A seed, and the A seed period for calculating the upper side adjacent column thumping update address or the lower side adjacent column thumping update address, and the B seed period for calculating the upper side adjacent column thumping update address or the lower side adjacent column thumping update address based on a B seed seed address, the second identification signal being used to identify which of the priority period and the non-priority period the current period belongs to in each unit period, the priority period being used to generate the priority column thumping update address starting from the beginning of the unit period, and the non-priority period being used to generate the non-priority column thumping update address starting from the middle of the unit period; The calculation unit calculates the priority adjacent column thump update address based on the first identification signal and the second identification signal by the first operation during the A seed period and the priority period based on the seed address of the A seed, and calculates the priority adjacent column thump update address by the third operation based on the seed address of the B seed during the B seed period and the priority period.

3. The column thumping update address calculation circuit according to claim 2, characterized in that: The calculation unit calculates a non-priority adjacent column thump update address by the second operation based on the seed address of the A seed during a period that is the A seed period and the non-priority period.

4. The column thumping update address calculation circuit according to claim 3, characterized in that: The calculation unit calculates a non-priority re-adjacent column thump update address by the fourth operation based on the seed address of the B seed during a period that is the B seed period and the non-priority period.

5. The column thumping update address calculation circuit according to claim 2, characterized in that: The control unit, when the seed address of the A seed is updated during the A seed period and the non-priority period, causes the additional A seed period to continue after the current A seed period ends; The calculation unit calculates the priority adjacent column thump update address by the first operation in a period that follows the A seed period and is the priority period, based on the seed address of the A seed updated in a period that is the A seed period and is the non-priority period.

6. The column thumping update address calculation circuit according to claim 2, characterized in that: The control unit, if the seed address of the A seed is not updated during the A seed period and the non-priority period, causes the B seed period to continue after the current A seed period ends; The calculation unit calculates the priority re-adjacent column thump update address by the third operation based on the seed address of the B seed during the updated B seed period which is the priority period.

7. The column thumping update address calculation circuit according to claim 2, characterized in that: The calculation unit calculates the non-priority re-adjacent column thump update address by the fourth operation based on the seed address of the B seed used when calculating the priority re-adjacent column thump update address output before the change during the B seed period if the priority period is changed to the non-priority period.

8. The column thumping update address calculation circuit according to claim 2, characterized in that: The control unit, when the seed address of the B seed is updated during the B seed period and the non-priority period, causes the additional B seed period to continue after the current B seed period ends; The calculation unit calculates the priority re-adjacent column thump update address by the third operation based on the seed address of the B seed updated in a period that is the B seed period and the non-priority period, during a period that is the subsequent B seed period and the priority period.

9. The column thumping update address calculation circuit according to claim 2, characterized in that: The control unit, if the seed address of the B seed is not updated during the B seed period and the non-priority period, continues the A seed period after the current B seed period ends; The calculation unit calculates the priority adjacent column thump update address by the first operation based on the seed address of the A seed during the updated A seed period that is the priority period.

10. The column thump update address calculation circuit according to any one of claims 2 to 9, characterized in that: The seed address of the A seed is obtained by sampling the column address used in accessing the memory array through a second sampling signal, wherein the second sampling signal is generated in a random timing sequence and is independent of the first sampling signal; The seed address of the B seed is obtained by sampling the column address used in accessing the memory array through a second sampling signal, and the second sampling signal is generated in a random timing and is independent of the first sampling signal.

11. The column thump update address calculation circuit according to claim 1, characterized in that: The calculation unit includes: A forward address conversion unit converts the seed address in the logical address space into a physical address according to the physical configuration of a specific storage unit or the physical configuration information of a word line; A physical address shifting unit calculates any one of the physical column thumping update addresses described in the first to fourth sections by adding or subtracting ±1 or ±2 based on the seed address converted into the physical address; The reverse address conversion unit reversely converts the first to fourth physical column thump update addresses into logical addresses based on the physical configuration of the specific storage unit or the physical configuration information of the word line, as any one of the upper side adjacent column thump update address, the lower side adjacent column thump update address, the upper side re-adjacent column thump update address and the lower side re-adjacent column thump update address in the logical address space.

12. The column thump update address calculation circuit according to any one of claims 2 to 9, characterized in that: The calculation unit comprises: The first part inputs the least significant bit, the second least significant bit, and the fourth least significant bit of the seed address as well as the first identification signal and the second identification signal, and when the first identification signal indicates that the current unit period is the A seed period, outputs a signal maintaining the logic level of the least significant bit and the second least significant bit of the seed address, and when the first identification signal indicates that the current unit period is the B seed period, outputs a signal obtained by passing the least significant bit, the second least significant bit, and the fourth least significant bit of the seed address as well as the first identification signal and the second identification signal through the first combinational circuit included in the first part of the part; and The second part outputs the lower 4 bits of the column hammer update address obtained by passing the signal input from the first part, the third lower bit of the seed address, the fourth lower bit, and the second identification signal through the second combinational circuit included in the second part of the second part; When the first part is connected to the second part, the part of the calculation unit and the control unit related to the adjacent column thump update address and the part related to the re-adjacent column thump update address are configured in the own column thump update address calculation circuit; The lowest bit and the second lowest bit of the seed address are input, and when the third part that outputs the signal maintaining the logic level of the lowest bit and the second lowest bit of the seed address is connected to the second part, the second part outputs the lower 4 bits of the column thump update address obtained by passing the signal input from the third part, the third lowest bit and the fourth lowest bit of the seed address, and the second identification signal through the second combinational circuit included in the second part of itself, the calculation unit and the control unit are configured in the calculation circuit corresponding to the column thump update address calculation circuit of itself, The part related to the adjacent column thump update address.

13. A semiconductor storage device, characterized in that: include: A memory array comprising a plurality of memory cells arranged in rows and columns; as well as The column thump update address calculation circuit according to any one of claims 1 to 12; A plurality of memory cells corresponding to a word line having the column thump update address calculated by the column thump update address calculation circuit as a column address are updated.

14. A column thump update address calculation method, which is a column thump update address calculation method for calculating a column thump update address, characterized in that: include: A calculation step, in a memory array including a plurality of memory cells arranged in rows and columns, calculating an upper side adjacent column thump update address and a lower side adjacent column thump update address by a first operation or a second operation with a larger amount of operation than the first operation, the upper side adjacent column thump update address corresponding to a word line adjacent to the upper side of a word line assigned to a seed address, and the lower side adjacent column thump update address corresponding to a word line adjacent to the lower side of the word line assigned to the seed address, and calculating an upper side re-adjacent column thump update address and a lower side re-adjacent column thump update address by a third operation or a fourth operation with a larger amount of operation than the third operation, the upper side re-adjacent column thump update address corresponding to a word line adjacent to the upper side of the word line assigned to the seed address, and the lower side re-adjacent column thump update address corresponding to a word line adjacent to the lower side of the word line assigned to the seed address; as well as A control step, controlling the calculation step, taking the updating of the seed address as an opportunity, among the upper side adjacent column thumping update address and the lower side adjacent column thumping update address corresponding to the updated seed address, the address obtained by the first operation is used as the priority adjacent column thumping update address to be preferentially calculated by the first operation, and taking the updating of the seed address as an opportunity, among the upper side re-adjacent column thumping update address and the lower side re-adjacent column thumping update address corresponding to the updated seed address, the address obtained by the third operation is used as the priority re-adjacent column thumping update address to be preferentially calculated by the third operation.

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