A semiconductor test management system

Abstract

The application discloses a kind of semiconductor test management systems, it is related to semiconductor testing technical field, it solves the technical problems that lack of detection and evaluation to performance in different stages of wafer production, it is difficult to detect whether there is performance anomaly in production stage to wafer;Through node early warning module, according to the stage performance evaluation coefficient of each node semiconductor wafer, the stage performance anomaly of semiconductor wafer is early warned, and the comprehensive performance coefficient of semiconductor wafer is analyzed, and the semiconductor wafer that does not meet standard is early warned;Through real-time monitoring and analysis stage performance coefficient, the semiconductor wafer that does not meet standard is quickly identified, measures are taken in advance, to avoid greater loss in subsequent process. Through detecting whether there is performance anomaly in production stage to wafer, can reasonably allocate resources, and the wafer with problem is concentratedly handled or reevaluated, instead of wasting time and material on possibly failed product.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor testing, and particularly relates to a semiconductor test management system. BACKGROUND

[0002] A semiconductor test management system (STMS) is an integrated software platform designed to support testing, data collection, analysis, and quality control in the semiconductor manufacturing process. The system can effectively manage various testing processes from wafer level to packaging level, including but not limited to electrical testing, optical detection, defect analysis, etc. STMS is usually combined with production equipment, automation systems, and data analysis tools to achieve real-time monitoring, fault warning, and performance optimization. With the development of big data and artificial intelligence, the semiconductor industry is gradually transforming towards data-driven decision-making. Enterprises need to effectively collect, store, and analyze large amounts of data to optimize production processes and improve yield.

[0003] Most existing semiconductor test management systems usually perform various tests on completed semiconductor wafers, lack performance detection and evaluation at different stages of wafer production, and are difficult to detect performance abnormalities in wafers in a timely manner during the production stage. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art; for this purpose, the present application proposes a semiconductor test management system to solve the technical problem of lacking performance detection and evaluation at different stages of wafer production, and being difficult to detect performance abnormalities in wafers in a timely manner during the production stage.

[0005] To solve the above problems, the first aspect of the present application provides a semiconductor test management system, comprising:

[0006] An information management module: used to obtain and store the basic information of the generated semiconductor wafer, including: material type, size, doping type, doping concentration, crystal structure and performance standard, and set detection nodes for the production process of the semiconductor wafer, including: lithography node, etching node, ion implantation node and thin film deposition node;

[0007] A test data acquisition module: for the lithography node and the etching node, respectively detecting three-dimensional point cloud data after lithography and etching, for the ion implantation node, collecting X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation, for the thin film deposition node, collecting electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition through the test machine, and setting basic information tags for the data collected at each node;

[0008] The intelligent scheduling module is used for detecting the use state of the current node test machine, and matching the test machine for the thin film deposition node semiconductor wafer after thin film deposition according to the current test machine state and the basic information of the semiconductor wafer, and testing the semiconductor wafer after thin film deposition.

[0009] The data analysis module is used for analyzing the stage performance evaluation coefficient of the semiconductor wafer of each node according to the detection data of each node collected by the test data collection module.

[0010] The node early warning module is used for early warning the semiconductor wafer with stage performance anomaly according to the stage performance evaluation coefficient of the semiconductor wafer of each node, and analyzing the comprehensive performance coefficient of the semiconductor wafer, and early warning the semiconductor wafer not meeting the standard.

[0011] As a further scheme of the present application, the test data collection module collects the electrical test data, three-dimensional point cloud data and deposited thin film thickness data of the semiconductor wafer after thin film deposition through the test machine for the thin film deposition node, and comprises the following steps:

[0012] For the thin film deposition node, the semiconductor wafer is classified into fixed detection temperature type semiconductor wafer and self-setting detection temperature type semiconductor wafer according to the material type data of the semiconductor wafer in the basic information label of the semiconductor wafer, wherein the fixed detection temperature type semiconductor wafer includes monocrystalline silicon semiconductor wafer, gallium arsenide semiconductor wafer, gallium nitride semiconductor wafer and silicon carbide semiconductor wafer.

[0013] For the fixed detection temperature type semiconductor wafer, high temperature detection temperature, medium temperature detection temperature and low temperature detection temperature are set for the fixed detection temperature type semiconductor wafer.

[0014] For the self-setting detection temperature type semiconductor wafer, the test temperature of the self-setting detection temperature type semiconductor wafer is manually input.

[0015] Under different detection temperatures, the electrical test data, surface high-definition image and infrared detection image of the packaged semiconductor wafer are collected through the test machine, wherein the electrical test data includes threshold voltage, leakage current, saturation current and conductivity.

[0016] As a further scheme of the present application, the test data collection module sets a basic information label for the data collected by each node, and comprises the following steps:

[0017] The basic information data of the semiconductor wafer is obtained, and the data of material type, size, doping type, doping concentration and performance standard in the basic information data is extracted.

[0018] A unique code is generated for each semiconductor wafer. Based on the extracted material type, size, and coding information of the semiconductor wafer, the key fields of the semiconductor wafer's code, material type, and size are used as basic information tags.

[0019] Based on the extracted data on the doping type, doping concentration, and performance standards of the semiconductor wafer, a parameter list for the semiconductor wafer is constructed and stored in each node.

[0020] Set corresponding key-value pairs for each type of data in the parameter list of semiconductor wafers, and add key-value pairs corresponding to doping type, doping concentration, crystal structure and performance standard data types to the basic information label.

[0021] As a further aspect of the present invention: the intelligent scheduling module detects the usage status of the current node test equipment, and based on the current test equipment status and the basic information of the semiconductor wafer, performs testing of the semiconductor wafer after thin film deposition on a test equipment matched to the semiconductor wafer of the thin film deposition node, including the following steps:

[0022] The test equipment for thin film deposition nodes is statistically analyzed, including: sorting machine, probe station and scanning test station, and the test equipment for thin film deposition nodes is numbered. The scanning test station includes: SEM scanning electron microscope and optical interferometer.

[0023] The current node test equipment status is detected. For probe stations, the status is collected, including the number of wafers to be tested and the size of the last wafer to be tested. For scanning test stations, the number of wafers to be tested is collected.

[0024] Based on the current status of the testing equipment and the size information in the basic information of the semiconductor wafers, select 2 to 3 probe stations with the fewest wafers to be tested.

[0025] The size of the last test wafer of the selected probe station is detected. The probe station whose area is closest to the area of ​​the semiconductor wafer after thin film deposition is selected. If there are multiple probe stations that meet the requirements, one probe station that meets the requirements is randomly selected as the test station for electrical testing. The test station number is sent to the sorting machine, which then transfers the semiconductor wafer after thin film deposition to the corresponding probe station.

[0026] After electrical testing by the probe station, the scanning test station with the fewest wafers to be tested is selected as the testing station for 3D point cloud data detection and thin film thickness data detection. The testing station number is sent to the sorting machine, which then transfers the electrically tested semiconductor wafers to the corresponding scanning test station.

[0027] As a further scheme of the present application: the data analysis module analyzes the performance evaluation coefficient of the semiconductor wafer at each node according to the detection data of each node collected by the test data collection module, including the following steps:

[0028] For the lithography node and the etching node, three-dimensional point cloud data after lithography and etching are acquired;

[0029] Through the three-dimensional point cloud data after the completion of the wafer lithography process, it is detected whether the lithography pattern of the lithography node wafer is consistent with the preset lithography pattern, if consistent, the lithography node detection is qualified, if inconsistent, the lithography node detection is unqualified, and a quality warning signal is generated for the corresponding coded wafer;

[0030] Through the three-dimensional point cloud data after the completion of the wafer etching process, it is detected whether the depth and shape of the etching position of the wafer of the etching node are consistent with the preset etching depth and shape, if consistent, the etching node detection is qualified, if inconsistent, the etching node detection is unqualified, and a quality warning signal is generated for the corresponding coded wafer;

[0031] For the ion implantation node, according to the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation, the performance evaluation coefficient of the semiconductor wafer at the ion implantation stage is analyzed;

[0032] For the thin film deposition node, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition collected by the test machine are acquired, it is detected whether the corresponding semiconductor wafer at the node is qualified, a quality warning signal is generated for the corresponding coded wafer at the unqualified node, and the performance evaluation coefficient of the semiconductor wafer at the thin film deposition stage is analyzed if the semiconductor wafer at the node is qualified.

[0033] As a further scheme of the present application: according to the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation, the performance evaluation coefficient of the semiconductor wafer at the ion implantation stage is analyzed, including the following steps:

[0034] The X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation are acquired;

[0035] The doping type and doping concentration data of the wafer are extracted through the basic information label of the wafer;

[0036] The Fourier transform infrared spectrum of the n-type doped wafer and the p-type doped wafer in the historical data is acquired, and the position, width and frequency range of the absorption peak of the Fourier transform infrared spectrum of the n-type doped wafer and the p-type doped wafer are labeled;

[0037] The deep learning model is trained through the Fourier transform infrared spectrum after labeling, and the doping type of the wafer is identified;

[0038] The Fourier transform infrared spectrum collected by the ion implantation node in real time is input into the trained deep learning model, and the wafer is identified as an n-type doped wafer or a p-type doped wafer;

[0039] According to the X-ray fluorescence spectrum of the semiconductor wafer, the characteristic peaks in the X-ray fluorescence spectrum are extracted, and the area of the characteristic peaks in the X-ray fluorescence spectrum is calculated as the characteristic peak intensity;

[0040] Select several groups of wafers of the same doping type to be tested, obtain the actual doping concentration data of the several groups of wafers, and detect the characteristic peak intensity of the several groups of wafers;

[0041] The ion implantation stage performance evaluation coefficient of the semiconductor wafer is calculated by the following formula:

[0042]

[0043] Wherein: α is the ion implantation stage performance evaluation coefficient of the semiconductor wafer, C std is the standard doping concentration data of the wafer, C sample is the doping concentration of the ion implantation stage of the semiconductor wafer, C i is the mean value of the actual doping concentration of the i-th group of wafers, I sample is the characteristic peak intensity of the ion implantation stage of the semiconductor wafer, I i is the mean value of the characteristic peak intensity of the X-ray fluorescence spectrum of the i-th group of wafers;

[0044] As a further scheme of the present application: for the thin film deposition node, obtain the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer collected by the test machine after thin film deposition, detect whether the corresponding semiconductor wafer in the node is detected qualified, and generate a quality warning signal for the corresponding coded wafer in the node if the detection is not qualified, comprising the following steps:

[0045] For the thin film deposition node, obtain the electrical test data of the semiconductor wafer collected by the test machine after thin film deposition, detect whether the electrical test data exceeds the preset threshold range, if it exceeds, the thin film deposition node is detected unqualified, and a quality warning signal is generated for the corresponding coded wafer, otherwise, the three-dimensional point cloud data and the deposited film thickness data are detected;

[0046] Detect whether the difference between the highest position and the lowest thickness of the deposited film position of the three-dimensional point cloud data is greater than the preset maximum threshold, if it exceeds, the thin film deposition node is detected unqualified, and a quality warning signal is generated for the corresponding coded wafer, otherwise, the deposited film thickness data is detected;

[0047] detecting whether the deposited thin film thickness data belongs to a preset threshold range, if not, the thin film deposition node detection is unqualified, a wafer generation quality warning signal corresponding to the code is generated, otherwise, the thin film deposition stage performance evaluation coefficient of the semiconductor wafer is analyzed;

[0048] As a further scheme of the present application: the thin film deposition stage performance evaluation coefficient of the semiconductor wafer is analyzed, including the following steps:

[0049] The distance from each point on the surface of the non-etching position to the preset detection surface is detected through the three-dimensional point cloud data of the wafer.

[0050] The standard values of threshold voltage, leakage current, saturation current and conductivity are extracted from the performance standard data of the basic information of the semiconductor wafer.

[0051] The electrical test data of the semiconductor wafer is obtained, and the mean values of the threshold voltage, leakage current, saturation current and conductivity under different detection temperatures are calculated respectively.

[0052] According to the electrical test data of the semiconductor wafer and the distance from each point on the surface of the non-etching position to the preset detection surface, the thin film deposition stage performance evaluation coefficient is calculated by the following formula:

[0053]

[0054] Wherein, β is the thin film deposition stage performance evaluation coefficient, Vth is the mean value of the threshold voltage in the electrical test data of the semiconductor wafer, Id is the mean value of the leakage current in the electrical test data of the semiconductor wafer, Isat is the mean value of the saturation current in the electrical test data of the semiconductor wafer, σ1 is the mean value of the conductivity in the electrical test data of the semiconductor wafer; V0 is the standard value of the threshold voltage in the electrical test data of the semiconductor wafer, Id0 is the standard value of the leakage current in the electrical test data of the semiconductor wafer, Isat0 is the standard value of the saturation current in the electrical test data of the semiconductor wafer, σ0 is the standard value of the conductivity in the electrical test data of the semiconductor wafer; S is the variance of the distance from each point on the surface of the non-etching position to the preset detection surface, σ0 is the mean value of the distance from each point on the surface of the non-etching position to the preset detection surface.

[0055] As a further scheme of the present application: the node warning module performs stage warning on the semiconductor wafer with stage performance anomaly according to the stage performance evaluation coefficient of the semiconductor wafer of each node, including the following steps:

[0056] According to the wafer generation quality warning signal corresponding to the code generated by the data analysis module, the semiconductor wafer with stage performance anomaly in the corresponding node is warned in stages;

[0057] According to the stage performance evaluation results of the semiconductor wafers of each node, if the ion implantation stage performance evaluation coefficient or the thin film deposition stage performance evaluation coefficient of the semiconductor wafer exceeds the preset threshold value, the semiconductor wafer with the node stage performance anomaly is subjected to stage early warning.

[0058] As a further scheme of the application, the node early warning module analyzes the comprehensive performance coefficient of the semiconductor wafer, and early warns the semiconductor wafer that does not meet the standard, including the following steps:

[0059] According to the stage performance evaluation coefficient of the semiconductor wafer of each node, for the wafer that does not appear stage early warning, the comprehensive performance coefficient of the semiconductor wafer is analyzed, and the following formula is used:

[0060] K=e - (α+β)

[0061] Wherein, K is the comprehensive performance coefficient of the semiconductor wafer, alpha is the ion implantation stage performance evaluation coefficient of the semiconductor wafer, and beta is the thin film deposition stage performance evaluation coefficient.

[0062] If the comprehensive performance coefficient of the semiconductor wafer is less than the preset threshold value, the corresponding semiconductor wafer has a quality risk, and the semiconductor wafer with the quality risk is early warned.

[0063] Compared with the prior art, the application has the following beneficial effects:

[0064] The application collects the electrical test data, three-dimensional point cloud data and deposited thin film thickness data of the semiconductor wafer after thin film deposition through a test machine, sets basic information tags for the data collected by each node, monitors the data of each node, understands whether the process parameters in the wafer production process are within the set range in time, adjusts the process conditions in time, ensures product quality, marks and archives the data of each node, provides complete production test records, traces the problem source, helps quality management and improvement.

[0065] The application carries out stage performance early warning on the semiconductor wafer with stage performance abnormality according to the stage performance evaluation coefficient of each node, and analyzes the comprehensive performance coefficient of the semiconductor wafer, and carries out early warning on the semiconductor wafer not meeting the standard; through real-time monitoring and analysis of the stage performance coefficient, the semiconductor wafer not meeting the standard can be quickly identified, and measures can be taken in advance to avoid greater loss in the subsequent process. It is convenient to identify potential defects in the early stage, reduce the outflow of unqualified products, improve the overall yield, and reduce the production cost. By detecting whether the wafer has performance abnormality in the production stage, resources can be reasonably allocated, and the wafer with problems can be concentrated or re-evaluated, instead of wasting time and materials on possibly failed products. The stage early warning mechanism enhances the quality control in the production process, so that each link can maintain high standards, which is helpful to the consistency and reliability of the final product. BRIEF DESCRIPTION OF DRAWINGS

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0067] Fig. 1 The figure is a schematic diagram of the system framework of the present application.

[0068] Fig. 2 The figure is a flow chart of the method for analyzing the stage performance evaluation coefficient of the semiconductor wafer of each node. DETAILED DESCRIPTION

[0069] The technical solutions of the present application will be described in detail below with reference to the embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0070] Please refer to Figs. 1-2 The first aspect of the present application provides a semiconductor test management system, which comprises:

[0071] The information management module is used to acquire and store the basic information of the generated semiconductor wafer, including material type, size, doping type, doping concentration, crystal structure and performance standard, and set detection nodes for the production process of the semiconductor wafer, including photolithography node, etching node, ion implantation node and thin film deposition node.

[0072] The test data acquisition module: for the photolithography node and the etching node, respectively detecting the three-dimensional point cloud data after photolithography and etching, for the ion implantation node, collecting the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation, for the thin film deposition node, collecting the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition by the test machine, and setting basic information tags for the data collected at each node;

[0073] The intelligent scheduling module: for detecting the use state of the current node test machine, and matching the test machine for the semiconductor wafer after thin film deposition for the test of the semiconductor wafer after thin film deposition according to the current test machine state and the basic information of the semiconductor wafer;

[0074] The data analysis module: analyzing the stage performance evaluation coefficient of the semiconductor wafer at each node according to the detection data of each node collected by the test data acquisition module;

[0075] The node early warning module: for early warning the semiconductor wafer with stage performance anomaly according to the stage performance evaluation coefficient of the semiconductor wafer at each node, and analyzing the comprehensive performance coefficient of the semiconductor wafer, and early warning the semiconductor wafer not meeting the standard.

[0076] Specifically, in the embodiment, the test data acquisition module detects the three-dimensional point cloud data after photolithography and etching for the photolithography node and the etching node respectively, collects the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation for the ion implantation node, and collects the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition by the test machine for the thin film deposition node, and sets basic information tags for the data collected at each node. Through the data monitoring of each node, it is convenient to know whether the process parameters in the wafer production process are within the set range in time, so as to adjust the process conditions in time and ensure the product quality. Marking and archiving the data of each node can provide complete production detection records, facilitate tracking the problem source, and help quality management and improvement.

[0077] The three-dimensional point cloud data can help identify surface defects or unevenness, and early detection of problems can reduce scrap rates and reduce production costs. At the same time, different types of data such as spectrum, three-dimensional point cloud, electrical test, etc. are collected, which provides a basis for multi-dimensional analysis and helps to comprehensively evaluate the process effect and material properties.

[0078] The intelligent scheduling module detects the use state of the current node test machine, and according to the current test machine state and the basic information of the semiconductor wafer, the test machine matched with the semiconductor wafer after film deposition of the film deposition node is determined to test the semiconductor wafer after film deposition;

[0079] By monitoring the use state of the test machine in real time, the equipment can be effectively allocated and utilized, avoiding idle or overload of the equipment, and improving the overall production efficiency. Through intelligent scheduling, the waiting time is reduced, thereby speeding up the overall process of the semiconductor wafer from deposition to test, and shortening the production cycle. The intelligent scheduling system can automatically adjust the plan according to real-time data, making the production process more flexible to cope with unexpected situations or order changes. Automatic scheduling reduces the need for manual intervention, thereby reducing labor costs and reducing the workload of the operator.

[0080] The node early warning module evaluates the stage performance coefficient of the semiconductor wafer of each node, performs stage early warning on the semiconductor wafer with stage performance abnormality, analyzes the comprehensive performance coefficient of the semiconductor wafer, and performs early warning on the semiconductor wafer that does not meet the standard. By monitoring and analyzing the stage performance coefficient in real time, the semiconductor wafer that does not meet the standard can be quickly identified, and measures can be taken in advance to avoid greater losses in subsequent processes. Early warning facilitates the identification of potential defects at an early stage, reduces the outflow of unqualified products, improves the overall yield, and reduces production costs. By detecting whether the wafer has performance abnormalities during the production stage, resources can be reasonably allocated, and problematic wafers can be concentrated for processing or re-evaluation, rather than wasting time and materials on potentially failed products. The stage early warning mechanism enhances quality control during the production process, ensuring that each link maintains high standards, which helps to ensure the consistency and reliability of the final product.

[0081] In one embodiment of the present application, the test data acquisition module for the film deposition node acquires electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after film deposition through the test machine, including the following steps:

[0082] For the film deposition node, according to the material type data of the semiconductor wafer in the basic information label of the semiconductor wafer, the semiconductor wafer is classified into fixed detection temperature type semiconductor wafer and self-setting detection temperature type semiconductor wafer, wherein the fixed detection temperature type semiconductor wafer includes single crystal silicon semiconductor wafer, gallium arsenide semiconductor wafer, gallium nitride semiconductor wafer and silicon carbide semiconductor wafer.

[0083] For the fixed detection temperature type semiconductor wafer, high temperature detection temperature, medium temperature detection temperature and low temperature detection temperature are set for the fixed detection temperature type semiconductor wafer.

[0084] For the self-setting detection temperature type semiconductor wafer, the test temperature of the self-setting detection temperature type semiconductor wafer is manually inputted;

[0085] At different detection temperatures, the electrical test data, the surface high-definition image and the infrared detection image of the packaged semiconductor wafer are collected by the test machine, wherein the electrical test data includes threshold voltage, leakage current, saturation current and conductivity.

[0086] Specifically, in the embodiment, for the common monocrystalline silicon semiconductor wafer, gallium arsenide semiconductor wafer, gallium nitride semiconductor wafer and silicon carbide semiconductor wafer, fixed detection temperatures are set, as shown below.

[0087] For the monocrystalline silicon semiconductor wafer, the high-temperature detection temperature is set to 80℃, the medium-temperature detection temperature is set to 20℃ and the low-temperature detection temperature is set to -10℃.

[0088] For the gallium arsenide semiconductor wafer, the high-temperature detection temperature is set to 40℃, the medium-temperature detection temperature is set to 20℃ and the low-temperature detection temperature is set to 0℃.

[0089] For the gallium nitride semiconductor wafer, the high-temperature detection temperature is set to 100℃, the medium-temperature detection temperature is set to 20℃ and the low-temperature detection temperature is set to 0℃.

[0090] For the silicon carbide semiconductor wafer, the high-temperature detection temperature is set to 150℃, the medium-temperature detection temperature is set to 40℃ and the low-temperature detection temperature is set to -20℃.

[0091] The wafer that needs to set the detection temperature by itself is classified as the self-setting detection temperature type semiconductor wafer, and for the self-setting detection temperature type semiconductor wafer, the test temperature of the self-setting detection temperature type semiconductor wafer is manually inputted.

[0092] In one embodiment of the present application, the test data collection module sets basic information tags for the data collected by each node, including the following steps:

[0093] The basic information data of the semiconductor wafer is acquired, and the data of the material type, size, doping type, doping concentration and performance standard in the basic information data is extracted;

[0094] A unique code is generated for the semiconductor wafer, and the code, material type and size of the semiconductor wafer are used as basic information tags according to the extracted material type, size and code information of the semiconductor wafer;

[0095] According to the extracted data of the doping type, doping concentration and performance standard of the semiconductor wafer, a parameter list of the semiconductor wafer is constructed, and the parameter list of the semiconductor wafer is stored in each node;

[0096] Set a corresponding key-value pair for each type of data in the parameter list of the semiconductor wafer, and add key-value pairs corresponding to the doping type, doping concentration, crystal structure, and performance standard data type to the basic information tag.

[0097] In one embodiment of the present application, the intelligent scheduling module detects the use state of the current node test machine, and according to the current test machine state and the basic information of the semiconductor wafer, matches the test machine for testing the semiconductor wafer after film deposition of the thin film deposition node, including the following steps:

[0098] The test machines of the thin film deposition node include a handler, a probe station, and a scan test station, and the test machines of the thin film deposition node are numbered, wherein the scan test station includes a SEM scanning electron microscope and an optical interferometer;

[0099] For the probe station, the use state of the probe station includes the number of wafers to be tested and the size of the last wafer to be tested, and for the scan test station, the number of wafers to be tested is collected;

[0100] According to the current test machine state and the size information in the basic information of the semiconductor wafer, 2 to 3 probe stations with the least number of wafers to be tested are selected from the probe stations;

[0101] The size of the last wafer to be tested in the selected probe station is detected, and the probe station with the closest area to the area of the semiconductor wafer after film deposition is selected, and if there are multiple probe stations meeting the requirements, a probe station meeting the requirements is randomly selected as a test machine for electrical testing, and the number of the test machine is sent to the handler, and the handler transmits the semiconductor wafer after film deposition to the corresponding probe station;

[0102] After electrical testing by the probe station, the scan test station with the least number of wafers to be tested is selected as a test machine for three-dimensional point cloud data detection and deposition film thickness data detection, and the number of the test machine is sent to the handler, and the handler transmits the semiconductor wafer after electrical testing to the corresponding scan test station.

[0103] In one embodiment of the present application, the data analysis module analyzes the stage performance evaluation coefficient of the semiconductor wafer of each node according to the detection data of each node collected by the test data collection module, including the following steps:

[0104] For the lithography node and the etching node, three-dimensional point cloud data after lithography and etching are obtained;

[0105] The three-dimensional point cloud data after the wafer lithography process is completed, whether the lithography pattern of the lithography node wafer is consistent with the preset lithography pattern is detected, if consistent, the lithography node detection is qualified, if inconsistent, the lithography node detection is unqualified, and a quality warning signal of the corresponding coded wafer is generated;

[0106] The three-dimensional point cloud data after the wafer etching process is completed, whether the etching position depth and shape of the etching node wafer are consistent with the preset etching depth and shape are detected, if consistent, the etching node detection is qualified, if inconsistent, the etching node detection is unqualified, and a quality warning signal of the corresponding coded wafer is generated;

[0107] For the ion implantation node, the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation are analyzed to obtain the ion implantation stage performance evaluation coefficient of the semiconductor wafer.

[0108] For the thin film deposition node, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition are collected, whether the corresponding semiconductor wafer is qualified in the node is detected, a quality warning signal of the corresponding coded wafer is generated in the unqualified node, and the thin film deposition stage performance evaluation coefficient of the semiconductor wafer is analyzed when the semiconductor wafer is qualified in the node.

[0109] In one embodiment of the present application, the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation are analyzed to obtain the ion implantation stage performance evaluation coefficient of the semiconductor wafer, including the following steps:

[0110] Obtain the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation;

[0111] The doping type and doping concentration data of the wafer are extracted through the basic information label of the wafer;

[0112] In the historical data, the Fourier transform infrared spectrum of the n-type doped wafer and the p-type doped wafer is obtained, and the position, width and frequency range of the Fourier transform infrared spectrum absorption peak of the n-type doped wafer and the p-type doped wafer are labeled;

[0113] The labeled Fourier transform infrared spectrum is used to train a deep learning model to identify the doping type of the wafer;

[0114] The Fourier transform infrared spectrum collected in real time by the ion implantation node is input into the trained deep learning model to identify whether the wafer is an n-type doped wafer or a p-type doped wafer;

[0115] According to the X-ray fluorescence spectrum of the semiconductor wafer, the characteristic peaks in the X-ray fluorescence spectrum are extracted, and the area of the characteristic peaks in the X-ray fluorescence spectrum is calculated as the characteristic peak intensity;

[0116] A plurality of groups of semiconductor wafers of the same doping type to be detected are selected, actual doping concentration data of the plurality of groups of semiconductor wafers are obtained, and the characteristic peak intensity of the plurality of groups of semiconductor wafers is detected;

[0117] The ion implantation stage performance evaluation coefficient of the semiconductor wafer is calculated by the following formula:

[0118]

[0119] Wherein, α is the ion implantation stage performance evaluation coefficient of the semiconductor wafer, C std is the standard doping concentration data of the wafer, C sample is the doping concentration of the ion implantation stage of the semiconductor wafer, C i is the mean value of the actual doping concentration of the i-th group of wafers, I sample is the characteristic peak intensity of the ion implantation stage of the semiconductor wafer, I i is the mean value of the characteristic peak intensity of the X-ray fluorescence spectrum of the i-th group of wafers;

[0120] In one embodiment of the present application, for the thin film deposition node, the test machine collects the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition, detects whether the corresponding semiconductor wafer at the node is detected to be qualified, and generates a quality warning signal for the corresponding coded wafer if the node is detected to be unqualified, including the following steps:

[0121] For the thin film deposition node, the test machine collects the electrical test data of the semiconductor wafer after thin film deposition, detects whether the electrical test data exceeds the preset threshold range, if it exceeds, the thin film deposition node is detected to be unqualified, a quality warning signal is generated for the corresponding coded wafer, otherwise, the three-dimensional point cloud data and the deposited film thickness data are detected;

[0122] Detect whether the difference between the highest position and the lowest thickness of the deposited film position of the three-dimensional point cloud data is greater than the preset maximum threshold, if it exceeds, the thin film deposition node is detected to be unqualified, a quality warning signal is generated for the corresponding coded wafer, otherwise, the deposited film thickness data is detected;

[0123] Detect whether the deposited film thickness data belongs to the preset threshold range, if it does not belong, the thin film deposition node is detected to be unqualified, a quality warning signal is generated for the corresponding coded wafer, otherwise, the thin film deposition stage performance evaluation coefficient of the semiconductor wafer is analyzed;

[0124] In one of the embodiments of the present application, the method for analyzing the performance evaluation coefficient of the thin film deposition stage of the semiconductor wafer comprises the following steps:

[0125] The distance from each point on the surface of the non-etching position to the preset detection surface is detected through the three-dimensional point cloud data of the wafer.

[0126] The standard values of the threshold voltage, the leakage current, the saturation current and the conductivity are extracted from the performance standard data of the basic information of the semiconductor wafer.

[0127] The mean values of the threshold voltage, the leakage current, the saturation current and the conductivity at different detection temperatures are calculated respectively according to the electrical test data of the semiconductor wafer.

[0128] The performance evaluation coefficient of the thin film deposition stage is calculated according to the electrical test data of the semiconductor wafer and the distance from each point on the surface of the non-etching position to the preset detection surface through the following formula:

[0129]

[0130] Wherein, β is the performance evaluation coefficient of the thin film deposition stage, Vth is the mean value of the threshold voltage in the electrical test data of the semiconductor wafer, Id is the mean value of the leakage current in the electrical test data of the semiconductor wafer, Isat is the mean value of the saturation current in the electrical test data of the semiconductor wafer, σ1 is the mean value of the conductivity in the electrical test data of the semiconductor wafer; V0 is the standard value of the threshold voltage in the electrical test data of the semiconductor wafer, Id0 is the standard value of the leakage current in the electrical test data of the semiconductor wafer, Isat0 is the standard value of the saturation current in the electrical test data of the semiconductor wafer, σ0 is the standard value of the conductivity in the electrical test data of the semiconductor wafer; S is the variance of the distance from each point on the surface of the non-etching position to the preset detection surface, σ0 is the mean value of the distance from each point on the surface of the non-etching position to the preset detection surface.

[0131] In one of the embodiments of the present application, the node early warning module performs stage performance early warning on the semiconductor wafer with stage performance anomaly according to the stage performance evaluation coefficient of the semiconductor wafer of each node, comprising the following steps:

[0132] The wafer generation quality early warning signal corresponding to the code generated by the data analysis module is generated to perform stage performance early warning on the semiconductor wafer with stage performance anomaly corresponding to the node;

[0133] According to the stage performance evaluation results of the semiconductor wafer of each node, if the ion implantation stage performance evaluation coefficient or the thin film deposition stage performance evaluation coefficient of the semiconductor wafer exceeds the preset threshold value, the semiconductor wafer with stage performance anomaly corresponding to the node is performed stage performance early warning.

[0134] Specifically, in the embodiment, the ion implantation stage performance evaluation coefficient or the thin film deposition stage performance evaluation coefficient of the semiconductor wafer at the corresponding stage node is counted for a large number of qualified wafers, and if the ion implantation stage performance evaluation coefficient of the semiconductor wafer is greater than 0.8% or the thin film deposition stage performance evaluation coefficient of the semiconductor wafer is greater than 0.6%, the semiconductor wafer with the stage performance anomaly at the node is subjected to stage pre-warning.

[0135] In one embodiment of the present application, the node pre-warning module analyzes the comprehensive performance coefficient of the semiconductor wafer, and pre-warns the semiconductor wafer that does not meet the standard, including the following steps:

[0136] According to the stage performance evaluation coefficient of the semiconductor wafer at each node, for the wafer that does not appear stage pre-warning, the comprehensive performance coefficient of the semiconductor wafer is analyzed, and the following formula is used:

[0137] K=e -(α+β)

[0138] Wherein, K is the comprehensive performance coefficient of the semiconductor wafer, and α is the ion implantation stage performance evaluation coefficient of the semiconductor wafer, and β is the thin film deposition stage performance evaluation coefficient.

[0139] If the comprehensive performance coefficient of the semiconductor wafer is less than the preset threshold value, the corresponding semiconductor wafer has a quality risk, and the semiconductor wafer with the quality risk is pre-warned.

[0140] Specifically, in the embodiment, the comprehensive performance coefficient of a large number of qualified semiconductor wafers is counted, and if the comprehensive performance coefficient of the semiconductor wafer is less than 1, the corresponding semiconductor wafer has a quality risk, and the semiconductor wafer with the quality risk is pre-warned.

[0141] The above embodiments are only used to illustrate the technical method of the present application and not to limit it. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical method of the present application.

Claims

1. A semiconductor test management system, characterized by, The information management module is used to acquire and store the basic information of the generated semiconductor wafer, including material type, size, doping type, doping concentration, crystal structure and performance standard, and sets detection nodes for the production process of the semiconductor wafer, including photolithography node, etching node, ion implantation node and thin film deposition node. The test data acquisition module detects the three-dimensional point cloud data after photolithography and etching for the photolithography node and etching node respectively, collects the X-ray fluorescence spectrum and Fourier transform infrared spectrum of the semiconductor wafer after ion implantation for the ion implantation node, and collects the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition through the test machine for the thin film deposition node, and sets basic information tags for the data collected at each node. The intelligent scheduling module is used to detect the use state of the current node test machine, and according to the current test machine state and the basic information of the semiconductor wafer, matches the test machine for the semiconductor wafer after thin film deposition for the test of the semiconductor wafer after thin film deposition. The data analysis module analyzes the stage performance evaluation coefficient of the semiconductor wafer at each node according to the detection data collected by the test data acquisition module. The node early warning module is used to perform stage early warning on the semiconductor wafer with stage performance anomaly according to the stage performance evaluation coefficient of the semiconductor wafer at each node, and analyzes the comprehensive performance coefficient of the semiconductor wafer, and performs early warning on the semiconductor wafer that does not meet the standard. The test data acquisition module collects the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition through the test machine for the thin film deposition node, including the following steps: For the thin film deposition node, according to the material type data of the semiconductor wafer in the basic information tag of the semiconductor wafer, the semiconductor wafer is classified into fixed detection temperature type semiconductor wafer and self-setting detection temperature type semiconductor wafer, wherein the fixed detection temperature type semiconductor wafer includes single crystal silicon semiconductor wafer, gallium arsenide semiconductor wafer, gallium nitride semiconductor wafer and silicon carbide semiconductor wafer. For the fixed detection temperature type semiconductor wafer, high temperature detection temperature, medium temperature detection temperature and low temperature detection temperature are set for the fixed detection temperature type semiconductor wafer. For the self-setting detection temperature type semiconductor wafer, the test temperature of the self-setting detection temperature type semiconductor wafer is manually inputted. Under different detection temperatures, the electrical test data, surface high-definition image and infrared detection image of the packaged semiconductor wafer are collected through the test machine, wherein the electrical test data includes threshold voltage, leakage current, saturation current and conductivity. The data analysis module analyzes the stage performance evaluation coefficient of the semiconductor wafer at each node according to the detection data collected by the test data acquisition module, including the following steps: For the photolithography node and etching node, the three-dimensional point cloud data after photolithography and etching are obtained. ​ The three-dimensional point cloud data after the wafer lithography process is completed, whether the lithography pattern of the lithography node wafer is consistent with the preset lithography pattern is detected, if consistent, the lithography node detection is qualified, if not consistent, the lithography node detection is unqualified, and the quality warning signal of the corresponding coded wafer is generated; Through the three-dimensional point cloud data after the wafer etching process is completed, whether the depth and shape of the etching position of the wafer of the etching node meet the preset etching depth and shape is detected, if consistent, the etching node detection is qualified, if not consistent, the etching node detection is unqualified, and the quality warning signal of the corresponding coded wafer is generated; For the ion implantation node, the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation are analyzed to obtain the ion implantation stage performance evaluation coefficient of the semiconductor wafer; For the thin film deposition node, the electrical test data, three-dimensional point cloud data and deposited film thickness data of the semiconductor wafer after thin film deposition are collected by the test machine, whether the corresponding semiconductor wafer is detected qualified at the node is detected, and the quality warning signal of the corresponding coded wafer is generated at the node which is not detected qualified; if the corresponding semiconductor wafer is detected qualified at the node, the thin film deposition stage performance evaluation coefficient of the semiconductor wafer is analyzed; According to the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation, the ion implantation stage performance evaluation coefficient of the semiconductor wafer is analyzed, including the following steps: Obtain the X-ray fluorescence spectrum and the Fourier transform infrared spectrum of the semiconductor wafer after ion implantation; Extract the doping type and doping concentration data of the wafer through the basic information label of the wafer; Obtain the Fourier transform infrared spectrum of the n-type doped wafer and the p-type doped wafer in the historical data, and label the position, width and frequency range of the absorption peak of the Fourier transform infrared spectrum of the n-type doped wafer and the p-type doped wafer; Train a deep learning model through the labeled Fourier transform infrared spectrum to identify the doping type of the wafer; Input the Fourier transform infrared spectrum collected in real time by the ion implantation node into the trained deep learning model to identify whether the wafer is an n-type doped wafer or a p-type doped wafer; According to the X-ray fluorescence spectrum of the semiconductor wafer, the characteristic peak in the X-ray fluorescence spectrum is extracted, and the area sum of the characteristic peak in the X-ray fluorescence spectrum is calculated as the characteristic peak intensity; Select several groups of wafers of the same doping type to be tested, obtain the actual doping concentration data of the several groups of wafers, and detect the characteristic peak intensity of the several groups of wafers; The ion implantation stage performance evaluation coefficient of the semiconductor wafer is calculated by the following formula: ； ； wherein: a is a performance evaluation coefficient of the ion implantation stage of the semiconductor wafer, C std to extract standard doping concentration data of the wafer, C sample is the doping concentration of the ion implantation stage of the semiconductor wafer, C i is the mean value of the actual doping concentration of the i-th group of wafers, I sample is the characteristic peak intensity of the ion implantation stage of the semiconductor wafer, I i is the mean value of the characteristic peak intensity of the X-ray fluorescence spectrum of the i-th group of wafers.

2. The semiconductor test management system of claim 1, wherein, The test data acquisition module sets basic information labels for the data collected by each node, including the following steps: Obtain the basic information data of the semiconductor wafer, extract the material type, size, doping type, doping concentration and performance standard data in the basic information data; Generate a unique code for the semiconductor wafer, and according to the extracted material type, size and code information of the semiconductor wafer, the key fields of the code, material type and size of the semiconductor wafer are taken as the basic information label; According to the extracted data of the doping type, doping concentration and performance standard of the semiconductor wafer, a parameter list of the semiconductor wafer is constructed, and the parameter list of the semiconductor wafer is stored in each node; A corresponding key-value pair is set for each type of data in the parameter list of the semiconductor wafer, and the key-value pairs corresponding to the doping type, doping concentration, crystal structure and performance standard data type are added to the basic information tag.

3. The semiconductor test management system of claim 1, wherein, The intelligent scheduling module detects the use state of the test machine of the current node, and according to the current test machine state and the basic information of the semiconductor wafer, the test machine for testing the semiconductor wafer after thin film deposition of the thin film deposition node is matched, including the following steps: The test machines of the thin film deposition node are counted, including a sorting machine, a probe station and a scanning test station, and the test machines of the thin film deposition node are numbered, wherein the scanning test station includes a SEM scanning electron microscope and an optical interferometer; The use state of the test machine of the current node is detected, and for the probe station, the use state of the probe station includes the number of test wafers of the probe station and the size of the last test wafer of the probe station, and for the scanning test station, the number of test wafers of the scanning test station is collected; According to the current test machine state and the size information in the basic information of the semiconductor wafer, 2 to 3 probe stations with the least number of test wafers are selected from the probe stations; The size of the last test wafer of the selected probe station is detected, the probe station with the area of the last test wafer closest to the area of the semiconductor wafer after thin film deposition is selected, if there are multiple probe stations meeting the requirements, a probe station meeting the requirements is randomly selected as a test machine for electrical testing, and the number of the test machine is sent to the sorting machine, and the sorting machine transmits the semiconductor wafer after thin film deposition to the corresponding probe station; After the electrical testing by the probe station, the scanning test station with the least number of test wafers is selected as a test machine for three-dimensional point cloud data detection and deposition thin film thickness data detection, and the number of the test machine is sent to the sorting machine, and the sorting machine transmits the semiconductor wafer after electrical testing to the corresponding scanning test station.

4. The semiconductor test management system of claim 1, wherein, For the thin film deposition node, the test machine collects the electrical testing data, three-dimensional point cloud data and deposition thin film thickness data of the semiconductor wafer after thin film deposition, and detects whether the corresponding semiconductor wafer in the node is qualified, and generates a quality warning signal for the corresponding coded wafer if the node is unqualified, including the following steps: For the thin film deposition node, the test machine collects the electrical testing data of the semiconductor wafer after thin film deposition, and detects whether the electrical testing data exceeds the preset threshold range, if it exceeds, the thin film deposition node is unqualified, and a quality warning signal is generated for the corresponding coded wafer, otherwise, three-dimensional point cloud data and deposition thin film thickness data detection are performed; It is detected whether the difference between the highest position and the lowest thickness of the deposition thin film position of the three-dimensional point cloud data is greater than the preset maximum threshold, if it exceeds, the thin film deposition node is unqualified, and a quality warning signal is generated for the corresponding coded wafer, otherwise, deposition thin film thickness data detection is performed; The thickness data of the deposited film is detected to determine whether it is within a preset threshold range. If not, the film deposition node is detected as unqualified, and a wafer generation quality warning signal corresponding to the code is generated. Otherwise, the film deposition stage performance evaluation coefficient of the semiconductor wafer is analyzed.

5. The semiconductor test management system of claim 4, wherein, The film deposition stage performance evaluation coefficient of the semiconductor wafer is analyzed, including the following steps: Detect the distance from each point on the surface of the non-etching position to the preset detection surface through the three-dimensional point cloud data of the wafer. Extract the standard values of threshold voltage, leakage current, saturation current, and conductivity from the performance standard data of the basic information of the semiconductor wafer. Obtain the electrical test data of the semiconductor wafer, and calculate the mean values of threshold voltage, leakage current, saturation current, and conductivity at different detection temperatures. According to the electrical test data of the semiconductor wafer and the distance from each point on the surface of the non-etching position to the preset detection surface, the film deposition stage performance evaluation coefficient is calculated by the following formula: ； Where β is the film deposition stage performance evaluation coefficient, Vth is the mean value of the threshold voltage in the electrical test data of the semiconductor wafer, Id is the mean value of the leakage current in the electrical test data of the semiconductor wafer, Isat is the mean value of the saturation current in the electrical test data of the semiconductor wafer, σ1 is the mean value of the conductivity in the electrical test data of the semiconductor wafer; V0 is the standard value of the threshold voltage in the electrical test data of the semiconductor wafer, Id0 is the standard value of the leakage current in the electrical test data of the semiconductor wafer, Isat0 is the standard value of the saturation current in the electrical test data of the semiconductor wafer, σ0 is the standard value of the conductivity in the electrical test data of the semiconductor wafer; S is the variance of the distance from each point on the surface of the non-etching position to the preset detection surface, and σ0 is the mean value of the distance from each point on the surface of the non-etching position to the preset detection surface.

6. The semiconductor test management system of claim 1, wherein, The node warning module performs stage performance warning on semiconductor wafers with stage performance abnormalities according to the stage performance evaluation coefficients of the semiconductor wafers of each node, including the following steps: According to the wafer generation quality warning signal corresponding to the code generated by the data analysis module, the stage performance of the semiconductor wafer with stage performance abnormalities is warned. According to the stage performance evaluation results of the semiconductor wafers of each node, if the ion implantation stage performance evaluation coefficient or the film deposition stage performance evaluation coefficient of the semiconductor wafer exceeds the preset threshold, the stage performance of the semiconductor wafer with stage performance abnormalities is warned.

7. The semiconductor test management system of claim 6, wherein, The node warning module analyzes the comprehensive performance coefficient of the semiconductor wafer, and warns the semiconductor wafer that does not meet the standard, including the following steps: For wafers that have not appeared stage warning, the comprehensive performance coefficient of the semiconductor wafer is analyzed according to the stage performance evaluation coefficients of the semiconductor wafers of each node, and the following formula is used: ； Where K is the comprehensive performance coefficient of the semiconductor wafer, α is the ion implantation stage performance evaluation coefficient of the semiconductor wafer, and β is the film deposition stage performance evaluation coefficient. If the comprehensive performance coefficient of the semiconductor wafer is less than the preset threshold, the corresponding semiconductor wafer has quality risk, and the semiconductor wafer with quality risk is warned.

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