Performance evaluation method and device for field effect transistor containing black phosphorus

Abstract

The invention discloses a performance evaluation method and device for a field effect transistor containing black phosphorus. The method specifically comprises the following steps: preparing the field effect transistor containing black phosphorus; providing a transmission model of the field effect transistor by measuring the electrical characteristics of the first controllable environment variable; acquiring bias temperature instability data, and analyzing a failure behavior; the transmission model of the field effect transistor is optimized and the failure behavior is analyzed in combination with the characterization of the channel defect and the surface potential; and in combination with the optimized transmission model and the analysis of the failure behavior, the performance evaluation of the field effect transistor containing black phosphorus is realized. According to the invention, electrical characteristic measurement, failure analysis of bias temperature instability data and characterization of defects and surface potential are fused, and an optimized transmission model and failure behavior analysis are given. And the selection of heterojunction materials in the field effect transistor containing black phosphorus, the structural design of the field effect transistor and the optimization of the preparation process can be more effectively guided.

Description

Technical Field

[0001] The present invention belongs to the technical field of field effect transistors, and in particular relates to a performance evaluation method and device for a field effect transistor containing black phosphorus. Background Art

[0002] With the continuous miniaturization of electronic devices, two-dimensional materials have triggered extensive research and application since graphene was first peeled off with its atomic-level ultra-thin sheet-like nanostructure. Although graphene has extremely high mobility, its lack of a band gap makes it unsuitable for transistor switches. Transition-Metal Dichalcogenides (TMDs) in two-dimensional materials, especially MoS 2 , is a hot topic in the research of field-effect transistor (FET) channel materials. The ultra-thin FETs formed by them effectively prevent the short channel effect. However, the carrier mobility of most reported TMDs transistors is much lower than that of graphene and traditional semiconductors.

[0003] Studies have shown that black phosphorus has a high mobility (close to 1000cm 2 / Vs), high current switching ratio and adjustable bandgap width. Black phosphorus (BP) is a new type of two-dimensional material, which is formed by the stacking of van der Waals (vdW) interactions between two-dimensional atomic layers. Using black phosphorus as the channel material of field effect transistors meets the requirements of low-power integrated complementary metal oxide semiconductors (CMOS) and thin film transistors (TFT), and has broad prospects for application in p-type field effect transistors (p-FETs).

[0004] However, black phosphorus lacks stability in air environments, and stripped black phosphorus will oxidize when exposed to air and water, causing its electrical and optical properties to degrade rapidly. On the one hand, it is very challenging to prepare black phosphorus-containing field-effect transistors that have both environmental stability and high performance (such as the most important performance parameters: high mobility and high current switching ratio, etc.).

[0005] For example, patent CN107644906A provides a black phosphorus field effect transistor and a manufacturing method thereof, including: providing a semiconductor substrate; forming a mask layer on the semiconductor substrate, the mask layer having an opening pattern; forming a black phosphorus sheet in the opening; performing a heat treatment to convert the black phosphorus sheet into a red phosphorus layer covering the bottom of the opening; converting the red phosphorus layer into a black phosphorus layer covering the bottom of the opening; and removing the mask layer. The manufacturing method of the black phosphorus field effect transistor proposed in this scheme can improve the performance of the black phosphorus field effect transistor.

[0006] On the other hand, the characterization of the basic device characteristics of black phosphorus field-effect transistors is also crucial. However, the current device characterization only focuses on one or several parameters, and lacks research on the overall reliability of the device.

[0007] The reliability of black phosphorus field-effect transistors is of great significance for device design, process optimization and improvement, and evaluation of actual service performance. Research on the reliability of black phosphorus field-effect transistors is necessary for the development of ultra-thin two-dimensional material FET technology and has important scientific significance.

[0008] Therefore, in the research field of black phosphorus field-effect transistors, it is urgent to carry out the design of schemes for the reliability evaluation of their devices, so as to provide guidance for the selection of heterojunction materials, the structural design of field-effect transistor devices and the optimization of preparation processes in field-effect transistors containing black phosphorus. Summary of the invention

[0009] In view of the defects existing in the above-mentioned prior art, the present invention provides a performance evaluation method and device for field effect transistors containing black phosphorus, and the method specifically includes the following steps: preparing a field effect transistor containing black phosphorus; providing a transmission model of the field effect transistor by measuring the electrical characteristics under the first controllable environmental variable; obtaining bias temperature instability data and analyzing failure behavior; optimizing the transmission model of the field effect transistor and the analysis of failure behavior in combination with the characterization of channel defects and surface potential; combining the optimized transmission model and the analysis of failure behavior to achieve performance evaluation of field effect transistors containing black phosphorus. The present invention integrates the electrical characteristics measurement, the failure analysis of the bias temperature instability data, and the characterization of defects and surface potential, and provides an optimized transmission model and failure behavior analysis, which can more effectively guide the selection of heterojunction materials, the design of field effect transistor device structure, and the optimization of preparation process in field effect transistors containing black phosphorus.

[0010] In a first aspect, the present invention provides a method for evaluating the performance of a field effect transistor containing black phosphorus, which specifically comprises the following steps:

[0011] Preparation of field effect transistors containing black phosphorus;

[0012] By measuring the electrical characteristics in the first controllable environmental variable, a transmission model of the field effect transistor is provided;

[0013] Obtain bias temperature instability data and analyze failure behavior;

[0014] Combined with the characterization of channel defects and surface potential, optimization of field effect transistor transfer models and analysis of failure behavior;

[0015] Combined with the optimized transfer model and the analysis of failure behavior, the performance evaluation of field effect transistors containing black phosphorus is achieved.

[0016] Furthermore, the field effect transistor containing black phosphorus uses a material containing black phosphorus as a channel of the field effect transistor, and the material containing black phosphorus includes pure black phosphorus and a two-dimensional material-black phosphorus in a stacked heterojunction form;

[0017] The preparation of a field effect transistor containing black phosphorus specifically comprises the following steps:

[0018] 10-300nm SiO is grown on a P-type silicon wafer substrate. 2 Dielectric layer;

[0019] The prepared black phosphorus layer or two-dimensional material-black phosphorus stacked heterojunction layer is transferred to the SiO 2 The surface of the dielectric layer is provided to obtain an intermediate component, wherein the thickness of the black phosphorus layer is 0.5-5 nm, the thickness of the two-dimensional material-black phosphorus stacked heterojunction layer is 0.5-5 nm, and the two-dimensional material is one of graphene, BN and InSe;

[0020] Annealing the intermediate piece, wherein the annealing is carried out in an inert gas, the annealing temperature is 250-300° C., the annealing time is 30-60 min, and the annealing heating and cooling rate is 5-10° C. / min;

[0021] The middle is processed using a mask plate to obtain a channel with a length of 5-50 μm and a width of 5-50 μm;

[0022] By magnetron sputtering or evaporation, electrodes are deposited at both ends of the channel as source and drain to prepare a field effect transistor containing black phosphorus.

[0023] Furthermore, by measuring the electrical characteristics of the first controllable environmental variable, a transmission model of the field effect transistor is provided, which specifically includes the following steps:

[0024] Determining a parameter and a parameter value range of a first controllable environmental variable;

[0025] Through the transfer characteristics and output characteristics tests, the electrical characteristics data under different controllable environmental variables are given;

[0026] Give the transfer model of the field effect transistor.

[0027] Further, the parameters of the first controllable environmental variable include a first environmental atmosphere, a voltage between a source and a drain, a gate voltage, and a test time, and the first environmental atmosphere includes humidity, oxygen concentration, and temperature;

[0028] The electrical characteristic data includes the average mobility of the field effect transistor.

[0029] Furthermore, the transmission model of the field effect transistor is specifically expressed as:

[0030]

[0031] Among them, μ lin is the average mobility in the linear state, μ sat is the average mobility under saturation conditions, I D，lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i SiO 2 Capacitance per unit area of ​​the dielectric layer, V GS is the gate voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D，sat is the source-drain current in saturation state.

[0032] Furthermore, the bias temperature instability data is obtained and the failure behavior is analyzed, which specifically includes the following steps:

[0033] Determining the parameters and parameter value ranges of the second controllable environmental variables;

[0034] The bias temperature instability test is carried out to provide the bias temperature instability data under different controllable environmental variables and analyze the failure behavior of the field effect transistor. The bias temperature instability test includes the positive bias temperature instability test and the negative bias temperature instability test.

[0035] Further, the parameters of the second controllable environmental variables include: the second environmental atmosphere, source-drain voltage, bottom gate bias, the bottom gate bias includes bottom gate positive bias and bottom gate negative bias, the second environmental atmosphere includes aging temperature and aging time;

[0036] The bias temperature instability data includes threshold voltage and subthreshold swing.

[0037] Further, a bias temperature instability test is performed, which specifically includes the following steps:

[0038] Setting the aging temperature, relaxation time and aging time, the relaxation time is the interval between the aging times of applying adjacent bottom gate biases, and the ratio of the aging time to the relaxation time is 1:(0.1-10);

[0039] Apply a preset equivalent bottom gate bias voltage, and after multiple aging times, give the threshold voltage and subthreshold swing under the bias voltage;

[0040] A preset arbitrarily increasing bias or an arbitrarily decreasing bias is applied, and after multiple aging times, the threshold voltage and subthreshold swing under the bias are given.

[0041] Furthermore, combining the characterization of channel defects and surface potential, the transfer model of the field effect transistor is optimized, which specifically includes the following steps:

[0042] The transfer characteristics and output characteristics of field effect transistors are tested using a scanning probe microscope, and the channel defects and channel surface potential are given;

[0043] Based on the channel defects, the equivalent channel size and ideal channel size of the field effect transistor are given, and the current in the center of the channel is analyzed in combination with the distribution of the channel surface potential, which is specifically expressed as:

[0044]

[0045] Among them, I D，C，0 is the current in the center of the channel under ideal channel size, W 0 is the width of the ideal channel, n C，0 is the carrier density under ideal channel size, μ C，0 is the mobility at the center of the channel under ideal channel size, q is the charge of the electron, and F D，0，x＝0 (y)dy is the longitudinal line surface potential when the channel is zero in the lateral direction under the ideal channel size, I D，C is the current in the center of the channel under equivalent channel size, W sc is the width of the equivalent channel, n C is the carrier density under equivalent channel size, μ C is the mobility at the center of the channel under equivalent channel size, F D，x＝0 (y)dy is the longitudinal line surface potential when the channel is zero in the lateral direction under the equivalent channel size;

[0046] Based on the analysis and comparison of the current in the center of the channel, the transmission adjustment coefficient is given and the transmission model of the field effect transistor is optimized, which is specifically expressed as:

[0047]

[0048] Where η is the transmission adjustment coefficient, μ lin′is the average mobility in the linear state after optimization, μ sat ′ is the average mobility in the saturated state after optimization, I D，lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i SiO 2 Capacitance per unit area of ​​the dielectric layer, V GS is the gate voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D，sat is the source-drain current in saturation state.

[0049] In a second aspect, the present invention further provides a performance evaluation device for a field effect transistor containing black phosphorus, using the above-mentioned performance evaluation method for a field effect transistor containing black phosphorus, specifically comprising:

[0050] An acquisition module, used to acquire electrical characteristic data of electrical characteristic measurement under a first controllable environmental variable, bias temperature instability data, channel defect and surface potential characterization data;

[0051] An analysis module is used to construct a transmission model of the field effect transistor based on the collected electrical characteristic data, analyze the failure behavior based on the collected bias temperature instability data, and optimize the transmission model and failure behavior of the field effect transistor in combination with the characterization data of channel defects and surface potential;

[0052] The evaluation module is used to combine the optimized transmission model and failure behavior analysis to achieve performance evaluation of field effect transistors containing black phosphorus.

[0053] The present invention provides a method and device for evaluating the performance of a field effect transistor containing black phosphorus, which has at least the following beneficial effects:

[0054] (1) The present invention integrates electrical property measurement, failure analysis of bias temperature instability data, and characterization of defects and surface potentials to provide an optimized transmission model and failure behavior analysis, which can more effectively guide the selection of heterojunction materials in field effect transistors containing black phosphorus, the design of field effect transistor device structures, and the optimization of preparation processes.

[0055] (2) Through the analysis of channel defects and surface potential, the mobility of field effect transistors containing black phosphorus is corrected and the transmission model of field effect transistors is optimized. The defects on the channel surface are characterized, the defects in the initial state of the field effect transistor device are compared, the influence of the failure mechanism on the defects is explored, and the law of charge capture on the channel surface under the influence of the failure mechanism is revealed, as well as the static electricity accumulation and potential change trend during the device failure process. This can verify the analyzed BTI failure behavior to a certain extent, thereby further improving the failure behavior mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 Schematic diagram of the structure of a pure black phosphorus field effect transistor and a stacked heterojunction transistor of a two-dimensional material-black phosphorus provided by the present invention, (a) is a pure black phosphorus field effect transistor, (b) is a stacked heterojunction transistor of a two-dimensional material-black phosphorus;

[0057] Figure 2 A schematic flow chart of a method for evaluating the performance of a field effect transistor containing black phosphorus provided by the present invention;

[0058] Figure 3 A schematic diagram of an equivalent channel and an ideal channel of a field effect transistor containing black phosphorus provided by the present invention;

[0059] Figure 4 A schematic diagram of a structure of using CAFM technology to characterize channel defects and surface potential in an embodiment provided by the present invention;

[0060] Figure 5 A schematic diagram of a structure of using KPFM technology to characterize channel defects and surface potential in an embodiment provided by the present invention;

[0061] Figure 6 This is an example diagram of a preset bottom gate bias voltage of a certain embodiment provided by the present invention, (a) is an example diagram of aging time and relaxation time, and (b) is an example diagram of equal value bias voltage, equidistant increasing bias voltage and equidistant decreasing bias voltage.

[0062] Description of reference numerals:

[0063] 11-P-type silicon wafer substrate; 12-SiO 2 Dielectric layer; 13-black phosphorus layer; 14-two-dimensional material layer. DETAILED DESCRIPTION

[0064] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0065] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings, and "multiple" generally includes at least two.

[0066] It should also be noted that the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the commodity or device including the elements.

[0067] The evolution of the preparation process of field effect transistors containing black phosphorus is mainly based on improving the stability and mobility of field effect transistors. First, the black phosphorus surface is modified by molecules and ions to passivate the lone pair electrons of the phosphorus atoms in black phosphorus, thereby improving the stability of the black phosphorus sheet. However, this strategy changes the intrinsic properties of the black phosphorus layer, the controllability of device modification is poor, and the interface modification has problems such as thermal stability and time degradation; second, the covering method, that is, the black phosphorus layer is covered with two-dimensional materials such as oxide film or boron nitride to improve its stability, thereby improving stability without significantly affecting the mobility of the device. The structure of the two-dimensional material (such as boron nitride)-black phosphorus heterojunction is currently the better technical strategy to improve the comprehensive performance of field effect transistors containing black phosphorus.

[0068] However, a lot of research is still needed on the basic data of the structure of the two-dimensional material-black phosphorus heterojunction, such as charge transfer and band gap change. At the same time, stacking a heterojunction on the structure of the original field-effect transistor as the channel of the field-effect transistor will produce a huge redistribution of electrostatic potential on the contact surface, greatly affecting the movement of carriers.

[0069] Therefore, it is necessary to conduct relevant research on the carrier transport properties and reliability evaluation of field effect transistors with stacked two-dimensional materials and black phosphorus heterojunctions. Regarding the performance evaluation of black phosphorus field effect transistors, it is necessary not only to start with the characterization of basic device characteristics (such as current switching ratio, mobility, etc.), but also to consider the overall reliability of the device and conduct reliability evaluation. In reliability evaluation, bias temperature instability (Bias Temperature Instabilities, BTI, the transistor characteristics are offset due to the charge trapping effect of the device) is one of the most important failure mechanisms in field effect transistors. It has also been proven to have an important influence on the characteristics of two-dimensional material field effect transistors and is an important direction for reliability research.

[0070] The present invention adopts conductive atomic force microscopy and Kelvin probe force microscopy technology to realize in situ research on the failure mechanism of two-dimensional material-black phosphorus heterojunction, constructs the physical mechanism of degradation of field effect transistor devices containing black phosphorus, and combines with other various electronic research methods to construct a comprehensive and complete reliability evaluation scheme based on the electrical characteristics, defects and bias temperature instability of FETs with two-dimensional material-black phosphorus heterojunctions.

[0071] like Figure 1 As shown, the field effect transistor containing black phosphorus uses a material containing black phosphorus as the channel of the field effect transistor, and the material containing black phosphorus includes pure black phosphorus and a two-dimensional material in the form of a stacked heterojunction - black phosphorus.

[0072] A pure black phosphorus field effect transistor is a field effect transistor that uses only black phosphorus as the channel layer material; a two-dimensional material-black phosphorus stacked heterojunction transistor is a field effect transistor that uses a stacked heterojunction formed by attaching black phosphorus to a two-dimensional material, and uses the stacked heterojunction as the channel layer material. The two-dimensional material in the two-dimensional material-black phosphorus stacked heterojunction transistor can be graphene, boron nitride (BN), or indium selenide (InSe).

[0073] Field effect transistors containing black phosphorus can be prepared using existing or the following transfer process. The device structure adopts a bottom gate electrode and a top source-drain electrode structure. Such an open channel structure greatly facilitates the use of scanning probe microscopy (SPM) to characterize device characteristics (for example, channel defects and surface potential). The following scheme uses a typical atomic force microscope (CAFM) and a Kelvin probe force microscope (KPFM) in SPM to characterize channel defects and surface potential.

[0074] Specifically, preparing a field effect transistor containing black phosphorus includes the following steps:

[0075] 10-300nm SiO is grown on a P-type silicon wafer substrate. 2 Dielectric layer;

[0076] The prepared black phosphorus layer or two-dimensional material-black phosphorus stacked heterojunction layer is transferred to the SiO 2 The surface of the dielectric layer is used to obtain an intermediate component, wherein the black phosphorus layer has a thickness of 0.5-5nm, the two-dimensional material-black phosphorus stacked heterojunction layer has a thickness of 0.5-5nm, and the two-dimensional material is one of graphene, BN and InSe; the preparation of the black phosphorus layer and the two-dimensional material-black phosphorus stacked heterojunction layer can adopt the existing method, and no further limitation is made here.

[0077] The intermediate piece is annealed, wherein the annealing is carried out in an inert gas, the annealing temperature is 250-300°C, the annealing time is 30-60min, and the annealing heating and cooling rate is 5-10°C / min; annealing the intermediate piece can reduce the oxidation of the black phosphorus surface and the generation of impurities, and the inert gas can be nitrogen or argon to avoid the black phosphorus being exposed to the air environment.

[0078] The middle is processed using a mask plate to obtain a channel with a length of 5-50 μm and a width of 5-50 μm;

[0079] Electrodes are deposited at both ends of the channel as source and drain by magnetron sputtering or evaporation to prepare a field effect transistor containing black phosphorus. The size of the source and drain is 50×50μm to 200×200μm.

[0080] like Figure 2 The present invention provides a performance evaluation method for a field effect transistor containing black phosphorus, which specifically comprises the following steps:

[0081] Preparation of field effect transistors containing black phosphorus;

[0082] By measuring the electrical characteristics in the first controllable environmental variable, a transmission model of the field effect transistor is provided;

[0083] Obtain bias temperature instability data and analyze failure behavior;

[0084] Combined with the characterization of channel defects and surface potential, optimization of field effect transistor transfer models and analysis of failure behavior;

[0085] Combined with the optimized transfer model and the analysis of failure behavior, the performance evaluation of field effect transistors containing black phosphorus is achieved.

[0086] Through a set of research methods such as electrical property measurement, characterization of channel defects and surface potential, and failure behavior analysis of bias temperature instability, the physical mechanism (transfer model) of different types of field-effect transistors containing black phosphorus is studied, the charge exchange is evaluated, the electrostatic shielding effect and its cause are given, the reliability performance evaluation is achieved, and the design of field-effect transistors containing black phosphorus is optimized.

[0087] By measuring the electrical characteristics of the first controllable environmental variable, a transmission model of the field effect transistor is given, which specifically includes the following steps:

[0088] Determining a parameter and a parameter value range of a first controllable environmental variable;

[0089] Through the transfer characteristics and output characteristics tests, the electrical characteristics data under different controllable environmental variables are given;

[0090] Give the transfer model of the field effect transistor.

[0091] The parameters of the first controllable environmental variable include a first environmental atmosphere, a voltage between a source and a drain, a gate voltage, and a test time, and the first environmental atmosphere includes humidity, oxygen concentration, and temperature;

[0092] The electrical characteristic data includes the average mobility of the field effect transistor.

[0093] The above electrical characteristic measurements of the field effect transistor containing black phosphorus can be performed by a semiconductor analyzer, with an auxiliary device for controlling environmental variables. The first environmental atmosphere can be a vacuum, nitrogen and atmospheric environment, and the parameters such as humidity, oxygen concentration and temperature in these three environments are given.

[0094] The parameter value ranges for the first controllable environmental variable can be set as follows: source-drain voltage (0-40V), gate voltage (0-80V), humidity (10-60%), oxygen concentration (0-90%) and temperature (25-180°C). The test time span can be extended to 1 year, and the test time points for electrical characteristic data can be set at 1, 2, 3, 7, 14, 30, 60, 90, 180, and 360 days. By calculating the average mobility of field effect transistors of different black phosphorus types at different time points, evaluating the performance and degradation time characteristics of field effect transistors, a transmission model of field effect transistors can be constructed, and the laws of device performance and stability can be given.

[0095] Specifically, the transfer model of the field effect transistor is expressed as:

[0096]

[0097] Among them, μ lin is the average mobility in the linear state, μ sat is the average mobility under saturation conditions, I D，lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i SiO 2 Capacitance per unit area of ​​the dielectric layer, V GS is the gate voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D，sat is the source-drain current in saturation state.

[0098] The average mobility of the field effect transistor needs to be analyzed in the linear state and the saturation state. The linear state (i.e., linear region) and the saturation state (i.e., saturation region) can be clearly seen in the output characteristic curve of the field effect transistor. Generally, the material containing black phosphorus presents an irregular shape, and the width and length of the channel are equivalent size values.

[0099] However, among the core performance indicators of field-effect transistors, average mobility is often overestimated. Possible reasons include errors introduced by contact resistance, channel bypass effect, edge field effect, etc. Among them, the edge field effect is particularly important in field-effect transistors based on materials such as metal oxides, polymers and two-dimensional materials.

[0100] like Figure 3 As shown in Figure 1, the actual channel layer material area (equivalent size) is significantly larger than the apparent channel area (the ideal rectangular area between the source and drain electrodes), which results in a considerable edge current when the field effect transistor device is working, which is reflected in the transfer and output characteristics of the device, and ultimately leads to an overestimation of the mobility. The above analysis of channel defects and surface potential is used to correct the mobility of field effect transistors containing black phosphorus.

[0101] For the optimization of the transport model, specifically, the transport model is optimized by characterizing the channel defects and the surface potential, which specifically includes the following steps:

[0102] The transfer characteristics and output characteristics of field effect transistors are tested using a scanning probe microscope, and the channel defects and channel surface potential are given;

[0103] Based on the channel defects, the equivalent channel size and ideal channel size of the field effect transistor are given, and the current in the center of the channel is analyzed in combination with the distribution of the channel surface potential, which is specifically expressed as:

[0104]

[0105] Among them, I D，C，0 is the current in the center of the channel under ideal channel size, W 0 is the width of the ideal channel, n C，0 is the carrier density under ideal channel size, μ C，0 is the mobility at the center of the channel under ideal channel size, q is the charge of the electron, and F D，0，x＝0 (y)dy is the longitudinal line surface potential when the channel is zero in the lateral direction under the ideal channel size, I D，C is the current in the center of the channel under equivalent channel size, W sc is the width of the equivalent channel, n C is the carrier density under equivalent channel size, μ Cis the mobility at the center of the channel under equivalent channel size, F D，x＝0 (y)dy is the longitudinal line surface potential when the channel is zero in the lateral direction under the equivalent channel size;

[0106] Based on the analysis and comparison of the current in the center of the channel, the transmission adjustment coefficient is given and the transmission model of the field effect transistor is optimized, which is specifically expressed as:

[0107]

[0108] Where η is the transmission adjustment coefficient, μ lin ′ is the average mobility in the linear state after optimization, μ sat ′ is the average mobility in the saturated state after optimization, I D，lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i SiO 2 Capacitance per unit area of ​​the dielectric layer, V GS is the gate voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D，sat is the source-drain current in saturation state.

[0109] The channel defects are determined by combining scanning probe microscopy, and the equivalent channel size is determined. Then, the carrier density, mobility and surface potential of the channel center are obtained under the equivalent channel size and the ideal channel size. Among them, the surface potential obtained by the scanning probe microscope will be different due to the size difference between the equivalent channel size and the ideal channel size, and the potential data format given by different types of scanning probe microscopes is also different. Here, the specific data and expression form of the surface potential are not limited.

[0110] The current in the center of the channel is determined by the carrier density, mobility and surface potential. By comparing the current conditions in the two cases, the transmission adjustment coefficient can be obtained, thereby optimizing the transmission model of the field effect transistor.

[0111] To study the reliability of various types of field-effect transistors containing black phosphorus, the failure behavior can be analyzed by obtaining bias temperature instability data, which includes the following steps:

[0112] Determining the parameters and parameter value ranges of the second controllable environmental variables;

[0113] The bias temperature instability test is carried out to provide the bias temperature instability data under different controllable environmental variables and analyze the failure behavior of the field effect transistor. The bias temperature instability test includes the positive bias temperature instability test and the negative bias temperature instability test.

[0114] The parameters of the second controllable environmental variables include: the second environmental atmosphere, the source-drain voltage, the bottom gate bias, the bottom gate bias including the bottom gate positive bias and the bottom gate negative bias, and the second environmental atmosphere including the aging temperature and the aging time;

[0115] The bias temperature instability data includes threshold voltage and subthreshold swing.

[0116] Bias temperature instability (BTI) refers to the phenomenon of performance degradation of field effect transistors under bias and high temperature conditions. The degradation is manifested by the decrease of parameters such as operating voltage and transconductance, the increase of parameters such as leakage current, and the most critical threshold voltage shift. Therefore, threshold voltage and subthreshold swing are used as the core indicators for quantitative analysis of failure behavior.

[0117] Bias temperature instability is divided into positive bias temperature instability (Positive Bias Temperature Instability, PBTI) and negative bias temperature instability (Negative Bias Temperature Instability, NBTI).

[0118] The above BTI test can be combined with CAFM and KPFM technology, semiconductor analyzer, etc., to assist in controlling the auxiliary device of the environmental variable. Among them, the parameter value of the second controllable environmental variable can be set as follows:

[0119] Apply bottom gate bias (PBTI: 0 to 80 V range; NBTI: 0 to -80 V range), source-drain voltage (0–40 V); heat to aging temperature (50–180°C), aging time (0-3600 s).

[0120] Conduct a bias temperature instability test, specifically including the following steps:

[0121] Setting the aging temperature, relaxation time and aging time, the relaxation time is the interval between the aging times of applying adjacent bottom gate biases, and the ratio of the aging time to the relaxation time is 1:(0.1-10);

[0122] Apply a preset equivalent bottom gate bias voltage, and after multiple aging times, give the threshold voltage and subthreshold swing under the bias voltage;

[0123] A preset arbitrarily increasing bias or an arbitrarily decreasing bias is applied, and after multiple aging times, the threshold voltage and subthreshold swing under the bias are given.

[0124] By measuring data multiple times, we draw curves showing how threshold voltage and subthreshold swing change with aging time, temperature, and bottom gate bias. We use physical models (such as power law model, exponential model, etc.) to fit the experimental data and analyze the mechanism of the BTI effect. In this way, we determine the parameters of the physical model (such as acceleration factor, activation energy, etc.) and predict the long-term stability of the device under actual working conditions.

[0125] like Figure 6 As shown in the figure, in the multiple aging and measurement cycles in the BTI test, a specific BTI aging time and relaxation time t(base) are configured, and the bias temperature instability data of the device is measured at the time point when aging ends and relaxation begins. Three different bias (VG) loading modes are set, namely, equal bias: the aging bias is the same each time; arithmetic increasing bias: the aging bias gradually increases; arithmetic decreasing bias: the aging bias gradually decreases. By adjusting the BTI aging time, relaxation time and maximum bias (VG,max), the degree of slowing down or accelerating the failure of the field effect transistor device is evaluated, and its main mechanism is analyzed in combination with the failure mechanism model, thereby guiding the optimization of the field effect transistor containing black phosphorus.

[0126] The failure behavior of the above field effect transistors can also be optimized through in situ characterization of channel defects and surface potential.

[0127] like Figure 4 As shown, CAFM is used to perform channel defect analysis. Various types of black phosphorus field effect transistor devices are placed on the atomic force microscope sample stage. The probe scans the transistor channel in contact mode or tapping mode and applies a DC voltage at the same time, thereby obtaining the current signal at the contact point position, which is collected by the CAFM system after amplification. While the probe is scanning, the field effect transistor can be in a working or non-working state. The working state is when a voltage is applied between the source and the drain.

[0128] The following technical solutions can be used to analyze channel defects: First, perform CAFM scanning on the area between the source and drain electrodes of the field effect transistor device containing black phosphorus, covering the area inside the channel and the area near the source and drain electrodes, and obtain the conductivity and current map of the area, the surface potential, and the density and distribution of defects.

[0129] The probe used is made of platinum Pt or iridium Ir, in contact mode, with a scanning area of ​​2×2 to 20×20μm 2The scanning speed is 0.1-10s / line, the voltage applied between the source and drain is in the range of 0-10V, the bottom gate voltage is in the range of 0-10V, and the CAFM probe voltage is in the range of 0-10V. Subsequently, the output characteristic curve and transfer characteristic curve test of the field effect transistor device are carried out, including the introduction of controlled humidity (10-60% range), oxygen concentration (0-90% range) and temperature (25-180℃ range) environmental variables to measure the electrical characteristics of the device as a simulation of the actual working conditions of the field effect transistor.

[0130] Subsequently, the area between the source and drain electrodes after each test was scanned by CAFM, and compared with the scan results in the prepared state, to obtain the changes in defects after the device simulated working conditions, so as to study the influence of the changes in charged impurities generated by different stacked heterojunctions on the channel defects of field effect transistors, and thus reflect the defect stability of the device under different conditions. In addition, the channel defect state of the field effect transistor device during the aging process was characterized: without introducing other external factors, the transistor was placed in nitrogen and atmospheric environments for a long time, with a time span of about 1 year, and the area between the source and drain electrodes of the field effect transistor containing black phosphorus was scanned by CAFM on the 1st, 2nd, 3rd, 7th, 14th, 30th, 60th, 90th, 180th, and 360th days, respectively, and the scan results in the prepared state were compared to analyze and study the changes in defects during the degradation of the field effect transistor. Given the large time span of the experiment, the field effect transistor devices prepared in the same batch can be used to carry out the electrical characteristics measurement test of the field effect transistor containing black phosphorus in parallel.

[0131] In addition, if Figure 5 As shown, KPFM is used to analyze the channel surface potential. The device is placed on the atomic force microscope sample stage and a conductive probe made of platinum Pt or iridium Ir is used to scan the transistor channel in a constant distance mode and non-contact mode. The scanning area is between 2×2 and 20×20μm. 2 The output characteristic curve and transfer characteristic curve test of the field effect transistor device containing black phosphorus were carried out, including measuring the electrical characteristics of the device under the conditions of introducing controllable humidity (10-60% range), oxygen concentration (0-90% range) and temperature (25-180℃ range) environmental variables; the voltage between the source and drain was controlled at 0-40V, and the gate voltage was controlled at 0-80V; and the KPFM scan of the channel area was performed at the same time.

[0132] In addition, the changes in defects during the degradation of field effect transistors can also be studied, and the electrical characteristics measurement test of field effect transistors containing black phosphorus can be carried out simultaneously.

[0133] In addition, after several sets of tests with specific bias voltage and temperature, CAFM was used to characterize defects on the channel surface, compare defects in the initial state of the device, explore the impact of the failure mechanism on defects, reveal the law of charge capture on the channel surface under the influence of the failure mechanism, as well as the static electricity accumulation and potential change trend during the device failure process, which can verify the analyzed BTI failure behavior to a certain extent, thereby further improving the failure behavior mechanism. Based on the above failure behavior analysis, by adjusting the bias voltage, aging time in the BTI test and the interval time in the cycle test, the possibility of slowing down and accelerating the failure of the device is explored, and the effectiveness of the failure behavior mechanism is verified.

[0134] In addition, the present invention also provides a performance evaluation device for a field effect transistor containing black phosphorus, which uses the above-mentioned performance evaluation method for a field effect transistor containing black phosphorus, specifically comprising:

[0135] An acquisition module, used to acquire electrical characteristic data of electrical characteristic measurement under a first controllable environmental variable, bias temperature instability data, channel defect and surface potential characterization data;

[0136] An analysis module is used to construct a transmission model of the field effect transistor based on the collected electrical characteristic data, analyze the failure behavior based on the collected bias temperature instability data, and optimize the transmission model and failure behavior of the field effect transistor in combination with the characterization data of channel defects and surface potential;

[0137] The evaluation module is used to combine the optimized transmission model and failure behavior analysis to achieve performance evaluation of field effect transistors containing black phosphorus.

[0138] The present invention provides a method and device for evaluating the performance of a field effect transistor containing black phosphorus, which has at least the following beneficial effects:

[0139] (1) The present invention integrates electrical property measurement, failure analysis of bias temperature instability data, and characterization of defects and surface potentials to provide an optimized transmission model and failure behavior analysis, which can more effectively guide the selection of heterojunction materials in field effect transistors containing black phosphorus, the design of field effect transistor device structures, and the optimization of preparation processes.

[0140] (2) Through the analysis of channel defects and surface potential, the mobility of field effect transistors containing black phosphorus is corrected and the transmission model of field effect transistors is optimized. The defects on the channel surface are characterized, the defects in the initial state of the field effect transistor device are compared, the influence of the failure mechanism on the defects is explored, and the law of charge capture on the channel surface under the influence of the failure mechanism is revealed, as well as the static electricity accumulation and potential change trend during the device failure process. This can verify the analyzed BTI failure behavior to a certain extent, thereby further improving the failure behavior mechanism.

[0141] Although preferred embodiments of the present invention have been described, additional changes and modifications may be made to these embodiments by those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for evaluating the performance of a field effect transistor containing black phosphorus, characterized in that: The specific steps include: Preparation of field effect transistors containing black phosphorus; By measuring the electrical characteristics in the first controllable environmental variable, a transmission model of the field effect transistor is provided; Obtain bias temperature instability data and analyze failure behavior; Combined with the characterization of channel defects and surface potential, optimization of field effect transistor transfer models and analysis of failure behavior; Combined with the optimized transfer model and the analysis of failure behavior, the performance evaluation of field effect transistors containing black phosphorus is achieved.

2. The performance evaluation method for a field effect transistor containing black phosphorus according to claim 1, characterized in that: The field effect transistor containing black phosphorus uses a material containing black phosphorus as a channel of the field effect transistor, and the material containing black phosphorus includes pure black phosphorus and a two-dimensional material-black phosphorus in the form of a stacked heterojunction; The preparation of a field effect transistor containing black phosphorus specifically comprises the following steps: A 10-300nm SiO2 dielectric layer is grown on a P-type silicon wafer substrate; The prepared black phosphorus layer or the two-dimensional material-black phosphorus stacked heterojunction layer is transferred to the surface of the SiO2 dielectric layer to obtain an intermediate component, wherein the black phosphorus layer has a thickness of 0.5-5nm, the two-dimensional material-black phosphorus stacked heterojunction layer has a thickness of 0.5-5nm, and the two-dimensional material is one of graphene, BN and InSe; Annealing the intermediate piece, wherein the annealing is performed in an inert gas, the annealing temperature is 250-300° C., the annealing time is 30-60 min, and the annealing heating and cooling rate is 5-10° C. / min; The middle is processed using a mask plate to obtain a channel with a length of 5-50 μm and a width of 5-50 μm; By magnetron sputtering or evaporation, electrodes are deposited at both ends of the channel as source and drain to prepare a field effect transistor containing black phosphorus.

3. The performance evaluation method for a field effect transistor containing black phosphorus according to claim 2, characterized in that: By measuring the electrical characteristics of the first controllable environmental variable, a transmission model of the field effect transistor is given, which specifically includes the following steps: Determining a parameter and a parameter value range of a first controllable environmental variable; Through the transfer characteristics and output characteristics tests, the electrical characteristics data under different controllable environmental variables are given; Give the transfer model of the field effect transistor.

4. The performance evaluation method for a field effect transistor containing black phosphorus according to claim 3, characterized in that: The parameters of the first controllable environmental variable include a first environmental atmosphere, a voltage between a source and a drain, a gate voltage, and a test time, and the first environmental atmosphere includes humidity, oxygen concentration, and temperature; The electrical characteristic data includes the average mobility of the field effect transistor.

5. The performance evaluation method for a field effect transistor containing black phosphorus according to claim 4, characterized in that: The transfer model of the field effect transistor is specifically expressed as: Among them, μ lin is the average mobility in the linear state, μ sat is the average mobility under saturation condition, I D,lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i is the capacitance per unit area of ​​the SiO2 dielectric layer, V GS is the gate voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D,sat is the source-drain current in saturation state.

6. The performance evaluation method for a field effect transistor containing black phosphorus according to claim 1, characterized in that: Obtain bias temperature instability data and analyze failure behavior, including the following steps: Determining the parameters and parameter value ranges of the second controllable environmental variables; The bias temperature instability test is carried out to provide the bias temperature instability data under different controllable environmental variables and analyze the failure behavior of the field effect transistor. The bias temperature instability test includes the positive bias temperature instability test and the negative bias temperature instability test.

7. The performance evaluation method for a field effect transistor containing black phosphorus according to claim 6, characterized in that: The parameters of the second controllable environmental variables include: the second environmental atmosphere, the source-drain voltage, the bottom gate bias, the bottom gate bias including the bottom gate positive bias and the bottom gate negative bias, and the second environmental atmosphere including the aging temperature and the aging time; The bias temperature instability data includes threshold voltage and subthreshold swing.

8. The performance evaluation method for a field effect transistor containing black phosphorus according to claim 7, characterized in that: Conduct a bias temperature instability test, specifically including the following steps: Setting the aging temperature, relaxation time and aging time, the relaxation time is the interval between the aging times of applying adjacent bottom gate biases, and the ratio of the aging time to the relaxation time is 1:(0.1-10); Apply a preset equivalent bottom gate bias voltage, and after multiple aging times, give the threshold voltage and subthreshold swing under the bias voltage; A preset arbitrarily increasing bias or an arbitrarily decreasing bias is applied, and after multiple aging times, the threshold voltage and subthreshold swing under the bias are given.

9. The method for evaluating the performance of a field effect transistor containing black phosphorus according to claim 4, characterized in that: Combined with the characterization of channel defects and surface potential, the transfer model of the field effect transistor is optimized, which includes the following steps: The transfer characteristics and output characteristics of field effect transistors are tested using a scanning probe microscope, and the channel defects and channel surface potential are given; Based on the channel defects, the equivalent channel size and ideal channel size of the field effect transistor are given, and the current in the center of the channel is analyzed in combination with the distribution of the channel surface potential, which is specifically expressed as: Among them, I D,C,0 is the current in the center of the channel under the ideal channel size, W0 is the width of the ideal channel, n C,0 is the carrier density under ideal channel size, μ C,0 is the mobility at the center of the channel under ideal channel size, q is the charge of the electron, and F D,0,x＝0 (y)dy is the longitudinal line surface potential when the channel is zero in the lateral direction under the ideal channel size, I D,C is the current in the center of the channel under equivalent channel size, W sc is the width of the equivalent channel, n C is the carrier density under equivalent channel size, μ C is the mobility at the center of the channel under equivalent channel size, F D,x＝0 (y)dy is the longitudinal line surface potential when the channel is zero in the lateral direction under the equivalent channel size; Based on the analysis and comparison of the current in the center of the channel, the transmission adjustment coefficient is given and the transmission model of the field effect transistor is optimized, which is specifically expressed as: Where η is the transmission adjustment coefficient, μ lin ' is the average mobility in the linear state after optimization, μ sat ' is the average mobility in the saturated state after optimization, I D,lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i is the capacitance per unit area of ​​the SiO2 dielectric layer, V GS is the gate voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D,sat is the source-drain current in saturation state.

10. A performance evaluation device for a field effect transistor containing black phosphorus, characterized in that: The performance evaluation method for a field effect transistor containing black phosphorus as claimed in any one of claims 1 to 9 specifically comprises: An acquisition module, used to acquire electrical characteristic data of electrical characteristic measurement under a first controllable environmental variable, bias temperature instability data, channel defect and surface potential characterization data; An analysis module is used to construct a transmission model of the field effect transistor based on the collected electrical characteristic data, analyze the failure behavior based on the collected bias temperature instability data, and optimize the transmission model and failure behavior of the field effect transistor in combination with the characterization data of channel defects and surface potential; The evaluation module is used to combine the optimized transmission model and failure behavior analysis to achieve performance evaluation of field effect transistors containing black phosphorus.

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