Semiconductor packaging structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises a plurality of semiconductor chips which are arranged in a stacked mode. The at least one semiconductor chip comprises a plurality of stress detection structures arranged along a plurality of different directions; the stress detection structure is located in an interconnection structure of the semiconductor chip; the plurality of semiconductor chips comprise a lead-out structure which passes through at least one semiconductor chip and is connected with the stress detection structure; the lead-out structure leads out the stress detection structure to the top or the bottom of the plurality of semiconductor chips.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor packaging structure and a method for manufacturing the same. Background Art

[0002] Three-dimensional chip stacking interconnection technology can both increase the bandwidth between chips and improve computing performance. Chip stacking poses great challenges to heat dissipation and stress reliability. Three-dimensional chip stacking is heterogeneous and has large differences in thermal expansion coefficients of different materials. It is easy to generate stress during high and low temperature cycles, which affects the performance of the chip. It is necessary to obtain the stress conditions of the specific internal positions of the chips in the three-dimensional chip stack. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a semiconductor packaging structure and a manufacturing method thereof.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor packaging structure, which includes a plurality of semiconductor chips stacked together; at least one semiconductor chip includes a plurality of stress detection structures arranged along a plurality of different directions; the stress detection structure is located in an interconnection structure of the semiconductor chip; the plurality of semiconductor chips include a lead-out structure passing through at least one semiconductor chip and connected to the stress detection structure; the lead-out structure leads the stress detection structure to the top or bottom of the plurality of semiconductor chips.

[0005] In some embodiments, multiple stress detection structures include a corresponding multiple zigzag wires; the multiple zigzag wires include a first zigzag wire extending along a first direction and a second zigzag wire extending along a second direction; the first direction and the second direction extend and intersect in an interconnection layer of the interconnection structure; the first end of the first zigzag wire and the first end of the second zigzag wire are connected to a common end, and the common end, the second end of the first zigzag wire and the second end of the second zigzag wire are connected to a common pad, a first pad and a second pad of the lead-out structure.

[0006] In some embodiments, the plurality of zigzag conductors further include a third zigzag conductor extending along a first direction and a fourth zigzag conductor extending along a second direction; the first zigzag conductor to the fourth zigzag conductor are arranged circumferentially along a common end in an interconnection layer of an interconnection structure; the first end of the third zigzag conductor and the first end of the fourth zigzag conductor are connected to the common end, and the second end of the third zigzag conductor and the second end of the fourth zigzag conductor are connected to a third pad and a fourth pad of the lead-out structure.

[0007] In some embodiments, the multiple zigzag wires also include a fifth zigzag wire and a seventh zigzag wire extending along a third direction, and a sixth zigzag wire and an eighth zigzag wire extending along a fourth direction; the first zigzag wire to the eighth zigzag wire are arranged circumferentially along a common end in an interconnection layer of the interconnection structure; the first ends of the fifth to the eighth zigzag wires are connected to the common end, the common end is connected to the common pad of the lead-out structure, and the second ends of the fifth to the eighth zigzag wires are respectively connected to the fifth pad to the eighth pad of the lead-out structure.

[0008] In some embodiments, the outer contour of the zigzag wire is a quadrilateral or a triangle.

[0009] In some embodiments, the stress detection structure is located in a first interconnection layer of the interconnection structure; the first interconnection layer is located at a side of the substrate close to the semiconductor chip in the interconnection structure.

[0010] In some embodiments, the lead-out structure includes a dummy through silicon via, a dummy conductive via and a lead-out pad; wherein the dummy through silicon via passes through at least one semiconductor chip; the dummy conductive via is located in the interconnect structure of the semiconductor chip, connected between the dummy through silicon via and the lead-out pad, and connected between the dummy through silicon via and the stress detection structure; the lead-out pad is located at the top or bottom of the plurality of semiconductor chips, and is used to receive or output a stress test signal, and the stress test signal is applied to the lead-out pad from the outside of the plurality of semiconductor chips, or is output from the lead-out pad to the outside of the plurality of semiconductor chips.

[0011] In some embodiments, the semiconductor packaging structure also includes a bonding structure located between two adjacent semiconductor chips; the lead-out structure includes dummy bonding vias and dummy bonding pads located in the bonding structure and connected to each other and penetrating the bonding structure; the dummy bonding vias and dummy bonding pads are connected between the dummy through silicon via and the dummy via.

[0012] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor packaging structure, the manufacturing method comprising: forming a first semiconductor chip; the first semiconductor chip comprises a plurality of stress detection structures and a corresponding plurality of first lead-out structures arranged along a plurality of different directions; the first lead-out structure is located on the stress detection structure and connected to the stress detection structure; the stress detection structure is located in an interconnection structure of the first semiconductor chip; the interconnection structure of the first semiconductor chip is located on a substrate of the first semiconductor chip; a second semiconductor chip is formed on the first semiconductor chip; the second semiconductor chip comprises a second lead-out structure that passes through the substrate of the second semiconductor chip and is connected to the corresponding first lead-out structure; the first lead-out structure and the second lead-out structure lead the stress detection structure to the top of the plurality of semiconductor chips; or, forming a first semiconductor chip; the first semiconductor chip The conductor chip includes a plurality of first lead-out structures; the first lead-out structures pass through the substrate of the first semiconductor chip and the interconnection structure of the first semiconductor chip; the interconnection structure of the first semiconductor chip is located on the substrate of the first semiconductor chip; a second semiconductor chip is formed on the first semiconductor chip; the second semiconductor chip includes a plurality of stress detection structures arranged along a plurality of different directions and a corresponding plurality of second lead-out structures; the second lead-out structure is located under the stress detection structure and is connected to the stress detection structure; the second lead-out structure passes through the substrate of the second semiconductor chip and is connected to the corresponding first lead-out structure; the stress detection structure is located in the interconnection structure of the second semiconductor chip; the interconnection structure of the second semiconductor chip is located on the substrate of the second semiconductor chip; the first lead-out structure and the second lead-out structure lead the stress detection structure to the bottom of the plurality of semiconductor chips.

[0013] In some embodiments, a first semiconductor chip including a plurality of stress detection structures arranged along a plurality of different directions and a corresponding plurality of first lead-out structures is formed, comprising: a first interconnection layer of an interconnection structure of the first semiconductor chip is formed on a substrate of the first semiconductor chip; the first interconnection layer comprises a first metal interconnection layer and a stress detection structure of the first semiconductor chip; or, a second semiconductor chip including a plurality of stress detection structures arranged along a plurality of different directions and a corresponding plurality of second lead-out structures is formed, comprising: a first interconnection layer of an interconnection structure of the second semiconductor chip is formed on a substrate of the second semiconductor chip; the first interconnection layer comprises a first metal interconnection layer and a stress detection structure of the second semiconductor chip.

[0014] In some embodiments, forming a second semiconductor chip on a first semiconductor chip includes: using a bonding process to bond the first semiconductor chip to the second semiconductor chip.

[0015] In each embodiment of the present application, at least one semiconductor chip among the multiple semiconductor chips that are stacked is provided with multiple stress detection structures arranged along multiple different directions. The stress detection structure is located in the interconnection structure of the semiconductor chip and is led out to the top or bottom of the multiple semiconductor chips through a lead-out structure that passes through at least one semiconductor chip and is connected to the stress detection structure. The stress conditions at the locations of the multiple stress detection structures in the interconnection structure are tested to detect the stress distribution in the multiple semiconductor chips that are stacked. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 One of the cross-sectional schematic diagrams of the semiconductor package structure provided in the embodiment of the present application;

[0017] Figure 2 A second cross-sectional schematic diagram of a semiconductor package structure provided in an embodiment of the present application;

[0018] Figure 3 One of the planar schematic diagrams of the zigzag wire provided in the embodiment of the present application as a stress detection structure;

[0019] Figure 4 The second plan view of the zigzag wire provided in the embodiment of the present application as a stress detection structure;

[0020] Figure 5 One of the plan schematic diagrams of a stress detection structure provided in an embodiment of the present application with multiple zigzag wires extending in different directions;

[0021] Figure 6 A second plan view of a stress detection structure provided by an embodiment of the present application, wherein a plurality of zigzag wires extending in different directions are provided;

[0022] Fig. 7A One of the plan schematic diagrams of the stress detection structure provided in the embodiment of the present application, which has two quadrilateral zigzag wires extending in each different direction;

[0023] Figure 7B A second schematic plan view of a stress detection structure having two quadrilateral folded-line conductive wires extending in different directions provided in an embodiment of the present application;

[0024] Fig. 8A One of the plan schematic diagrams of the stress detection structure provided in the embodiment of the present application, which has two triangular zigzag wires extending in each different direction;

[0025] Figure 8B A second schematic plan view of a stress detection structure having two triangular zigzag wires extending in different directions provided in an embodiment of the present application;

[0026] Fig. 9AA third plan view of a stress detection structure having two triangular zigzag wires extending in different directions provided in an embodiment of the present application;

[0027] Fig. 9B A fourth schematic plan view of a stress detection structure having two triangular zigzag wires extending in different directions provided in an embodiment of the present application;

[0028] Fig.10 One of the flow charts of the method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application;

[0029] FIG. 11A to FIG. 11C for Fig.10 A schematic cross-sectional view of the manufacturing method shown;

[0030] Fig.12 A second flow chart of a method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application;

[0031] FIG. 13A to FIG. 13C for Fig.12 A schematic cross-sectional view of the manufacturing method is shown. DETAILED DESCRIPTION

[0032] The following will combine the implementation methods and drawings of this application to clearly and completely describe the technical solutions in the implementation methods of this application. The described implementation methods are only part of the implementation methods of this application, not all of the implementation methods. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] In the related art, the surface stress distribution of the wafer can be obtained by finite element simulation method or theoretical formula. For example, a strain gauge is buried at the junction of the passivation layer and the electrical insulation layer of the chip package or between multiple redistribution layers, and an electrical connection is achieved with the chip package through solder balls to obtain the stress conditions at specific internal locations. However, stress measurement inside the wafer is very difficult. The package-level strain gauge is limited to measuring the internal stress of the chip package because of its millimeter size, and its testing technology cannot be applied to the inside of the chip in a three-dimensional chip stack (for example, High Bandwidth Memory (HBM)).

[0036] In view of this, an embodiment of the present application provides a semiconductor packaging structure and a manufacturing method thereof.

[0037] Figure 1 This is one of the cross-sectional schematic diagrams of the semiconductor packaging structure provided in an embodiment of the present application. Figure 2 The second cross-sectional schematic diagram of the semiconductor packaging structure provided in the embodiment of the present application.

[0038] In a first aspect, the present invention provides a semiconductor packaging structure, referring to Figure 1 and Figure 2 The semiconductor packaging structure 300 includes a plurality of semiconductor chips (for example, a first semiconductor chip 100 and a second semiconductor chip 200) arranged in a stacked manner; at least one semiconductor chip (for example, the first semiconductor chip 100 or the second semiconductor chip 200) includes a plurality of stress detection structures SS12 arranged along a plurality of different directions; the stress detection structure SS12 is located in the interconnection structure of the semiconductor chip; the plurality of semiconductor chips include a lead-out structure SS10 that passes through at least one semiconductor chip and is connected to the stress detection structure; the lead-out structure SS10 leads the stress detection structure SS12 to the top (also referred to as the top surface) SUR2 or the bottom (also referred to as the bottom surface) SUR1 of the plurality of semiconductor chips.

[0039] For the convenience of describing the embodiments of the present application, the first direction and the second direction are represented as two intersecting directions parallel to the top / bottom surface of the semiconductor chip, for example, the first direction and the second direction are orthogonal; the fifth direction is a direction perpendicular to the top / bottom surface of the semiconductor chip or the fifth direction is a stacking direction of multiple semiconductor chips. For example, the first direction can be represented as the X direction in the drawings; the second direction can be represented as the Y direction in the drawings; and the fifth direction can be represented as the Z direction in the drawings.

[0040] It should be noted that Figure 1 The lead-out structure SS10 of the semiconductor package structure 300 leads the stress detection structure SS12 to the top SUR2 of the plurality of semiconductor chips. Figure 2The lead-out structure SS10 of the semiconductor package structure 300 leads the stress detection structure SS12 to the bottom SUR1 of the plurality of semiconductor chips; wherein the top SUR2 and the bottom SUR1 are two opposite ends of the plurality of semiconductor chips along the stacking direction.

[0041] It should be noted that the materials of the stress detection structure SS12 and the lead-out structure SS10 include but are not limited to tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride or any combination thereof. For example, the materials of the stress detection structure SS12 and the lead-out structure SS10 may include copper and copper alloys.

[0042] It should be noted that the term "dummy" in this article is used to represent a component that is different from the functional circuit of the semiconductor chip. For example, the "dummy silicon via" is not used to implement the function of the semiconductor chip, such as to implement the lead-out of the stress detection structure SS12. In contrast, the term "silicon via" ( Figure 1 and Figure 2 The electrical connections (not shown) can be understood as electrical connections for constituting functional circuits of a semiconductor chip, and can be used to implement various functions of the semiconductor chip.

[0043] refer to Figure 1 and Figure 2 , substrate ( Figure 1 and Figure 2 A semiconductor chip (not shown) is used as a substrate for the semiconductor packaging structure, which may be a printed circuit board (PCB), a glass substrate, a ceramic substrate, or a board with wiring. The semiconductor chip may be a memory chip or a logic chip. The logic chip may be, for example, a central processing unit (CPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a microcontroller unit (MCU), or an application specific integrated circuit (ASIC). The memory chip may be a volatile memory chip, such as a dynamic random access memory (DRAM) chip and a static random access memory (SRAM) chip, or may be a non-volatile memory chip, such as a resistive random access memory (RRAM) chip.

[0044] In some embodiments, the semiconductor package structure 300 includes a plurality of semiconductor chips stacked on a substrate, the plurality of semiconductor chips including a first semiconductor chip 100 and a second semiconductor chip 200 stacked in sequence. The first semiconductor chip 100 includes a logic chip, and the second semiconductor chip 200 includes a memory chip. The first semiconductor chip 100 and at least one second semiconductor chip 200 on the first semiconductor chip 100 may constitute an HBM DRAM. Although a semiconductor package structure 300 of one first semiconductor chip 100 and one second semiconductor chip 200 stacked in sequence on a substrate is shown in this example embodiment, the number of second semiconductor chips 200 that can be stacked on the first semiconductor chip 100 is not limited thereto. For example, two, three, or more than three second semiconductor chips 200 (e.g., 4 chips) may be stacked on the first semiconductor chip 100.

[0045] In some embodiments, the circuit of the first semiconductor chip 100 and / or the circuit of the second semiconductor chip 200 is connected to the functional circuit ( Figure 1 and Figure 2 (not shown). The functional circuit may include a variety of active and passive devices (e.g., capacitors, resistors, inductors, and the like) that meet the desired structural and functional requirements of the design. The functional circuit may include an NMOS device or a PMOS device. The material of the insulating layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The material of the interconnect layer includes, but is not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof.

[0046] For example, the material of the substrate of the first semiconductor chip 100 may include silicon (Si), germanium (Ge), silicon germanium (SiGe) substrate, etc.; the substrate may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). Functional circuits and interconnect structures of the functional circuits on the substrate for lead-out may be formed in the substrate of the first semiconductor chip 100 by one or more patterning processes. The interconnection layer in the interconnection structure of the first semiconductor chip 100 includes a dielectric layer ( Figure 1 and Figure 2 not shown) and a conductive member ( Figure 1 and Figure 2(not shown). The dielectric layer is an inter-metal dielectric (IMD) or an inter-layer dielectric (ILD), which may be formed of a dielectric material. The material of the dielectric layer may include a dielectric material having a dielectric constant (k value) lower than 3.8. The material of the conductive component may include a metal such as copper or tungsten.

[0047] In some embodiments, at least two of the plurality of semiconductor chips include a plurality of stress detection structures SS12 ( Figure 1 and Figure 2 (not shown). For example, each semiconductor chip includes a plurality of stress detection structures arranged in a plurality of different directions, and the plurality of stress detection structures are all led out toward the top SUR2, or are all led out toward the bottom SUR1. In some embodiments, at least two interconnection layers of the semiconductor chip include a plurality of stress detection structures SS12 arranged in a plurality of different directions (in this case Figure 1 and Figure 2 For example, the first interconnection layer M1, the second interconnection layer M2 and the third interconnection layer M3 of the first semiconductor chip 100 are respectively provided with a plurality of stress detection structures SS12 arranged in a plurality of different directions (in this case Figure 1 and Figure 2 not shown).

[0048] In the following description, Figure 1 The semiconductor package structure 300 shown is described in detail, and this exemplary description is not intended to limit the embodiments of the present application.

[0049] In some embodiments, the stress detection structure may be located in the substrate of the semiconductor chip or in the interconnect structure of the semiconductor chip. For example, the stress detection structure is located in an interconnect layer in the interconnect structure. In some embodiments, the stress detection structure is located in the first interconnect layer M1 of the interconnect structure; the first interconnect layer M1 is located on one side of the substrate close to the semiconductor chip in the interconnect structure.

[0050] In some embodiments, the stress detection structure may be a resistor or a capacitor. For example, the stress detection structure may be a linear resistor. Exemplarily, the stress detection structure may be a zigzag wire composed of a P-type semiconductor material or an N-type semiconductor material located in the substrate, or the stress detection structure may be a zigzag wire composed of a conductive component located in an interconnect layer.

[0051] Figure 3 One of the plan schematic diagrams of the zigzag wire provided in the embodiment of the present application as a stress detection structure. Figure 4The second plan view of the zigzag wire provided in the embodiment of the present application as a stress detection structure.

[0052] like Figure 3 and Figure 4 As shown, a semiconductor manufacturing process technology can be used to make a zigzag wire in at least one interconnection layer in the interconnection structure of a semiconductor chip as a stress detection structure SS12. When the wafer (which can be understood as a semiconductor packaging structure in the process) is warped, stress is generated at the location of the stress detection structure SS12, and the stress on the zigzag wire causes its resistance to change. According to the resistance law R=ρL / S (hereinafter referred to as Formula 1), the resistance R of the zigzag wire is proportional to its length L and resistivity ρ, and inversely proportional to its cross-sectional area S, where ρ is the resistivity of the material used to make the zigzag wire, L is the length of the zigzag wire, S is the cross-sectional area of ​​the zigzag wire, and R is the resistance value of the zigzag wire. It can be seen from the resistance R=ρL / S of the zigzag wire that the length L can be calculated by the cross-sectional area S and the Poisson's ratio of the material of the zigzag wire. There is a linear relationship between the length L and the stress. Therefore, the length change ΔL of the zigzag wire before and after the stress can be characterized by the measurable resistance change ΔR of the zigzag wire before and after the stress. The resistance change ΔR can be expressed as a linear function of the circumferential stress of the zigzag wire. That is to say, by measuring the resistance change ΔR of the zigzag wire before and after the stress, the stress at the location of the zigzag wire can be characterized.

[0053] According to the formula Ks*ε=ΔR / R (hereinafter referred to as Formula 2), the stress at the position can be calculated, and the positive or negative value of the stress can be used to determine whether the position is stretched or compressed; wherein, Ks is the sensitivity coefficient of the stress detection structure, ε is the stress at the position where the stress detection structure is located, ΔR is the resistance change of the stress detection structure before and after the stress is applied, and R is the initial resistance of the stress detection structure before the stress is applied. The stress ε generated at the position where the zigzag wire is located, the resistance change ΔR of the zigzag wire, the initial resistance R and the sensitivity coefficient Ks have a linear relationship as shown in Formula 2 above. By measuring the initial resistance R of the stress detection structure before the stress is applied, and measuring the final resistance R' of the stress detection structure after the stress is applied, the resistance change ΔR=(R'-R) can be obtained. According to Formula 2, the stress at the position can be calculated, and the positive or negative value of the stress can be used to determine whether the position is stretched or compressed.

[0054] refer to Figure 3 and Figure 4Before the stress detection structure is subjected to stress, an initial resistance R can be obtained by applying a test voltage to the first end and the second end of the stress detection structure SS12, and after the stress detection structure is subjected to stress, a final resistance R' can be obtained by applying a test voltage to the first end and the second end of the stress detection structure SS12. The first end and the second end of the stress detection structure SS12 can be respectively led out through a lead pad and another lead pad, and the lead pad and the other lead pad receive the test voltage.

[0055] refer to Figure 3 and Figure 4 In some embodiments, the outer contour of the zigzag wire is a quadrilateral or a triangle.

[0056] Figure 5 One of the plan schematic diagrams of a stress detection structure provided in an embodiment of the present application is a plurality of zigzag wires extending in different directions. Figure 6 The second plan view of a stress detection structure provided in an embodiment of the present application, wherein a plurality of zigzag conductive lines extending in different directions are provided.

[0057] In some embodiments, by extending and arranging multiple stress detection structures in different directions, the stress distribution magnitudes in different stress detection directions can be obtained. Different stress detection directions can be any different directions within a plane within a range of 0 degrees to 180 degrees, and different stress detection direction settings can be adaptively set according to actual process requirements. For example, refer to Figure 5 By arranging multiple stress detection structures along the X direction (illustrated as 0 degrees) and the Y direction (illustrated as 90 degrees), the stress distribution magnitude in the 0 degree and 90 degree directions can be obtained. Figure 6 By arranging a plurality of stress detection structures along the fourth direction D4 (illustrated as 45 degrees) and the Y direction (illustrated as 90 degrees), the stress distribution magnitudes in the directions of 45 degrees and 90 degrees can be obtained.

[0058] In some embodiments, by extending and arranging multiple stress detection structures in different directions, they can be closely arranged in the same direction to obtain the smallest occupied area. Figure 5 , two stress detection structures with a quadrilateral outer contour of the zigzag wire can be arranged adjacent to each other in the X direction, and the two stress detection structures of the quadrilateral are squares extending in the X direction and the Y direction respectively, and the two stress detection structures of the quadrilateral are taken as a whole, and the whole is still an extended square in the X direction and the Y direction, so that the minimum occupied area can be obtained in the X direction and the Y direction. For another example, referring to Figure 6The two stress detection structures whose outer contours are triangles of the zigzag wire can be arranged adjacent to each other in the X direction. Although one of the two triangular stress detection structures extends in a direction that intersects both the X direction and the Y direction, the two triangular stress detection structures as a whole are still a square extending in the X direction and the Y direction, and the minimum occupied area can be obtained in the X direction and the Y direction.

[0059] Fig. 7A The embodiment of the present application provides a plan view of a stress detection structure having two quadrilateral zigzag wires extending in different directions. Figure 7B The second plan view schematic diagram of a stress detection structure provided in an embodiment of the present application has two quadrilateral zigzag wires extending in different directions.

[0060] refer to Fig. 7A In some embodiments, the plurality of stress detection structures include a corresponding plurality of zigzag wires; the plurality of zigzag wires include a first zigzag wire extending along a first direction and a second zigzag wire extending along a second direction; the first direction and the second direction extend and intersect in an interconnection layer of the interconnection structure; the first end of the first zigzag wire and the first end of the second zigzag wire are connected to a common end, and the common end, the second end of the first zigzag wire and the second end of the second zigzag wire are connected to a common pad P0, a first pad P1 and a second pad P2 of the lead-out structure. In some embodiments, the plurality of zigzag wires also include a third zigzag wire extending along the first direction and a fourth zigzag wire extending along the second direction; the first zigzag wire to the fourth zigzag wire are arranged circumferentially along the common end in an interconnection layer of the interconnection structure; the first end of the third zigzag wire and the first end of the fourth zigzag wire are connected to the common end, and the second end of the third zigzag wire and the second end of the fourth zigzag wire are connected to a third pad P3 and a fourth pad P4 of the lead-out structure.

[0061] The first zigzag conductor to the fourth zigzag conductor are arranged circumferentially along the common end, that is, the zigzag conductor extending along the first direction (the first zigzag conductor or the third zigzag conductor) and the zigzag conductor extending along the second direction (the second zigzag conductor or the fourth zigzag conductor) are arranged alternately in the circumferential direction, and the four zigzag conductors symmetrically arranged circumferentially as a whole can occupy a smaller area, and the environment in which each zigzag conductor is located is symmetrical; at the same time, two zigzag conductors that are symmetrical about the common end environment are arranged in each direction, which can avoid large measurement fluctuations caused by only setting one zigzag conductor in each direction.

[0062] refer to Figure 7BIn some embodiments, the plurality of zigzag conductors further include a fifth zigzag conductor and a seventh zigzag conductor extending along a third direction, and a sixth zigzag conductor and an eighth zigzag conductor extending along a fourth direction; the first zigzag conductor to the eighth zigzag conductor are arranged circumferentially along a common end in an interconnection layer of the interconnection structure; the first ends of the fifth zigzag conductor to the eighth zigzag conductor are connected to the common end, the common end is connected to the common pad P10 of the lead-out structure, and the second ends of the fifth zigzag conductor to the eighth zigzag conductor are respectively connected to the fifth pad P5 to the eighth pad P8 of the lead-out structure.

[0063] Combination Fig. 7A and Figure 7B , a total of 10 pads, including the common pad P0, the common pad P10, and the first pad P1 to the eighth pad P8, are used to lead out 8 zigzag wires, and the stress distribution in 4 different directions (X direction (shown as 0 degrees), the fourth direction D4 (shown as 45 degrees), the Y direction (shown as 90 degrees), and the third direction D3 (shown as 135 degrees)) can be obtained. In this way, the stress distribution in more directions can be detected while the zigzag wires occupy a smaller area as a whole.

[0064] Fig. 8A The embodiment of the present application provides two triangular zigzag wires extending in different directions as one of the plan schematic diagrams of the stress detection structure. Figure 8B The second plan view schematic diagram of a stress detection structure provided in an embodiment of the present application has two triangular zigzag wires extending in different directions. Fig. 9A The third plan view schematic diagram of a stress detection structure provided in an embodiment of the present application, wherein two triangular zigzag wires extending in different directions are provided. Fig. 9B The fourth plan view of the stress detection structure provided in the embodiment of the present application has two triangular zigzag wires extending in different directions.

[0065] The four zigzag wires are taken as a whole. When the overall shape (square) remains unchanged and the extension direction of the zigzag wires remains unchanged, the Fig. 7A , Fig. 8A The zigzag wire shown changes to a triangle.

[0066] The four zigzag wires are taken as a whole. When the overall shape (diamond shape) remains unchanged and the extension direction of the zigzag wires remains unchanged, the Figure 7B , Figure 8B The zigzag wire shown changes to a triangle.

[0067] The four zigzag wires are taken as a whole. When the overall shape (square) and the individual shapes (triangle) in the whole remain unchanged, the Fig. 8A , Fig. 9A The extending direction of the zigzag wire shown is changed to a third direction D3 and a fourth direction D4.

[0068] The four zigzag wires are taken as a whole. When the overall shape (diamond) and the individual shapes (triangle) in the whole remain unchanged, the Figure 8B , Fig. 9B The extending direction of the zigzag wire shown is changed into a first direction X and a second direction Y.

[0069] In some embodiments, in combination Fig. 7A and Fig. 9A , or, combining 8A and Fig. 9A , a total of 10 pads, including the common pad P0, the common pad P10, and the first pad P1 to the eighth pad P8, are used to lead out 8 zigzag wires, and the stress distribution in 4 different directions (X direction (illustrated as 0 degrees), the fourth direction D4 (illustrated as 45 degrees), the Y direction (illustrated as 90 degrees), and the third direction D3 (illustrated as 135 degrees)) can be obtained; and the two groups of four zigzag wires extend along the first direction and the second direction as a whole, and the two groups of four zigzag wires are combined into eight zigzag wires, and the eight zigzag wires as a whole still extend along the first direction and the second direction, with a compact structure. In this way, the stress distribution in more directions can be detected while the multiple zigzag wires occupy a smaller area as a whole.

[0070] Similarly, in some embodiments, in combination Figure 7B and Fig. 9B , or, combined with Figure 8B and Fig. 9B , eight zigzag wires extending along the third direction and the fourth direction can be obtained.

[0071] In order to clearly show the relative position relationship between the two ends (the first end and the second end) of the zigzag wire and the lead pad, Figures 5 to 9B There are a total of 10 pads, including the common pad P0, the common pad P10, and the first pad P1 to the eighth pad P8 shown in the figure. Some of the 10 pads are schematically projected within the plane where the corresponding multiple zigzag wires are located. The shapes and sizes of the 10 pads are not used to limit the shape and size of the actual lead-out pads.

[0072] refer to Figure 1 and Figure 2 In some embodiments, the lead-out structure SS10 includes a dummy silicon through via SS16, a dummy via ( Figure 1 and Figure 2wherein, the dummy through silicon via SS16 passes through at least one semiconductor chip; the dummy via is located in the interconnect structure of the semiconductor chip, connected between the dummy through silicon via SS16 and the lead-out pad SS18, and connected between the dummy through silicon via SS16 and the stress detection structure SS12; the lead-out pad SS18 is located at the top or bottom of the plurality of semiconductor chips, and is used to receive or output a stress test signal, the stress test signal is applied to the lead-out pad from the outside of the plurality of semiconductor chips, or is output from the lead-out pad to the outside of the plurality of semiconductor chips.

[0073] It should be noted that the dummy vias may be located between interconnection layers in the interconnection structure to achieve connection between interconnection layers. For example, the two ends of the stress detection structure SS12 may be connected to the corresponding dummy silicon through vias SS16 through the dummy vias connected between the interconnection layers.

[0074] In some embodiments, the first end (or second end) of the stress detection structure, the corresponding dummy silicon through via and the corresponding dummy via at least partially overlap with the lead-out pad in the plane where the lead-out pad is located. In this way, the lead-out structure SS10 extends in the stacking direction of the plurality of semiconductor chips, avoiding the introduction of measurement errors due to the extension in the plane where the first direction and the second direction are located. For example, the stress detection structure SS12 is a component for sensing stress changes, and the extension direction of the stress is within the plane where the first direction and the second direction are located, and other non-sensing parts (lead-out structure SS10) should be avoided from being affected by stress in the plane where the first direction and the second direction are located; or, compared with the sensing part (stress detection structure SS12) being affected by stress in the plane where the first direction and the second direction are located, the non-sensing part (lead-out structure SS10) being affected by stress in the plane where the first direction and the second direction are located can be ignored. In other words, the lead-out structure SS10 extends in the stacking direction and avoids extending in the plane where the first direction and the second direction are located, which can reduce or avoid the introduction of measurement errors.

[0075] In some embodiments, the semiconductor packaging structure also includes a bonding structure located between two adjacent semiconductor chips; the lead-out structure includes dummy bonding vias and dummy bonding pads SS14 located in the bonding structure and connected to each other and penetrating the bonding structure; the dummy bonding vias and dummy bonding pads SS14 are connected between the dummy through silicon via SS16 and the dummy via.

[0076] The bonding structure includes a first bonding structure 106 located on the first semiconductor chip 100 and a second bonding structure 206 located on the second semiconductor chip 200. The second semiconductor chip 200 can be disposed on the first semiconductor chip 100 by a bonding process, such as a hybrid bonding process, to connect the dummy silicon through via SS16 and the stress detection structure SS12 to realize the lead-out of the stress detection structure SS12.

[0077] In each embodiment of the present application, at least one semiconductor chip among the multiple semiconductor chips in a stacked arrangement is provided with multiple stress detection structures arranged along multiple different directions. The stress detection structure is located in the interconnection structure of the semiconductor chip and is led out to the top or bottom of the multiple semiconductor chips through a lead-out structure that passes through at least one semiconductor chip and is connected to the stress detection structure. The stress conditions at the locations of the multiple stress detection structures in the interconnection structure of the middle layer of the semiconductor chip are used to test the stress distribution in the multiple semiconductor chips in the stacked arrangement.

[0078] Fig.10 This is one of the flow charts of the method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application. FIG. 11A to FIG. 11C for Fig.10 A schematic cross-sectional view of the manufacturing method is shown. Fig.12 The second schematic flow chart of the method for manufacturing a semiconductor packaging structure provided in an embodiment of the present application. FIG. 13A to FIG. 13C for Fig.12 A schematic cross-sectional view of the manufacturing method is shown.

[0079] In a second aspect, the present invention provides a method for manufacturing a semiconductor packaging structure. Fig.10 The manufacturing method includes the following steps: S101, forming a first semiconductor chip; the first semiconductor chip includes a plurality of stress detection structures and a corresponding plurality of first lead-out structures arranged along a plurality of different directions; the first lead-out structure is located on the stress detection structure and is connected to the stress detection structure; the stress detection structure is located in an interconnection structure of the first semiconductor chip; the interconnection structure of the first semiconductor chip is located on a substrate of the first semiconductor chip; S102, forming a second semiconductor chip on the first semiconductor chip; the second semiconductor chip includes a second lead-out structure that passes through the substrate of the second semiconductor chip and is connected to the corresponding first lead-out structure; the first lead-out structure and the second lead-out structure lead the stress detection structure to the top of the plurality of semiconductor chips.

[0080] In some embodiments, a first semiconductor chip is formed including a plurality of stress detection structures arranged along a plurality of different directions and a corresponding plurality of first lead-out structures, including: a first interconnection layer of an interconnection structure of the first semiconductor chip is formed on a substrate of the first semiconductor chip; the first interconnection layer includes a first metal interconnection layer and a stress detection structure of the first semiconductor chip.

[0081] refer to Fig.11A , a functional circuit is formed in the substrate 102 of the first semiconductor chip 100 ( Fig.11A (not shown). An insulating layer is formed on the substrate 102 of the first semiconductor chip 100, and an interconnection structure 104 of a functional circuit is formed in the insulating layer. In some embodiments, a first interconnection layer M1, a second interconnection layer M2, and a third interconnection layer M3 of the interconnection structure 104 are formed in sequence, and a stress detection structure SS12 can be formed in the photolithography etching process of forming the first interconnection layer M1. An insulating layer is formed on the interconnection structure 104, and a first bonding structure 106 connected to the interconnection structure 104 is formed in the insulating layer. The first bonding structure 106 includes a first dummy bonding pad SS13. For example, the first dummy bonding pad SS13 can be a through-hole dummy via ( Fig.11A For example, two ends of the stress detection structure SS12 may be led out to the corresponding first dummy bonding pads SS13 through dummy vias connected between the interconnection layers.

[0082] In some embodiments, the stress detection structure SS12 can be measured when it is manufactured (located on the surface of the semiconductor chip at this time), and then its sensitivity coefficient Ks can be calibrated. In some embodiments, when the stress detection structure SS12 is manufactured, the test voltage can be received by two first dummy bonding pads SS13 connected to both ends of the stress detection structure SS12, and the first resistance R1 of the stress detection structure SS12 and the first lead-out structure can be obtained by testing.

[0083] refer to Fig. 11B , a functional circuit is formed in the substrate 202 of the second semiconductor chip 200 ( Fig. 11B (not shown). An insulating layer is formed on the substrate 202 of the second semiconductor chip 200, and an interconnection structure 204 of a functional circuit led out is formed in the insulating layer, and a dummy silicon through-hole SS16 is formed through the substrate 202. An insulating layer is formed on the interconnection structure 204, and a lead-out structure 208 connected to the interconnection structure 204 is formed in the insulating layer, and the lead-out structure 208 includes a lead-out pad SS18. A second bonding structure 206 is formed under the substrate 202 of the second semiconductor chip 200, and the second bonding structure 206 includes a second dummy bonding pad SS15. For example, the second dummy bonding pad SS15 can be a through-hole dummy via ( Fig. 11B The dummy through silicon via SS16 is connected to one end of the corresponding dummy through silicon via SS16, and the other end of the dummy through silicon via SS16 is connected to the corresponding dummy through silicon via SS16 through the dummy conductive hole ( Fig. 11B The lead pads (not shown) are connected to corresponding lead pads SS18.

[0084] In some embodiments, the test voltage can be received by two pairs of pads connected to both ends of the stress detection structure SS12 (wherein one pair of pads corresponds to a second dummy bonding pad SS15 and a lead pad SS18) to test and obtain the second resistance R2 of the second lead structure.

[0085] refer to Fig. 11C The first semiconductor chip and the second semiconductor chip are bonded and connected by a bonding process such as a hybrid bonding process, and the lead-out structure SS10 of the semiconductor package structure 300 leads the stress detection structure SS12 to the top SUR2 of the plurality of semiconductor chips. The first bonding structure 106 and the second bonding structure 206 constitute a bonding structure 302, and the first dummy bonding pad SS13 and the second dummy bonding pad SS15 constitute a dummy bonding pad SS14. For example, one end of the dummy bonding pad SS14 can be connected to a dummy via hole ( Fig. 11C The dummy bonding pad SS14 may be connected to one end of the corresponding dummy silicon through via SS16 (not shown), and the other end of the dummy bonding pad SS14 may be connected to the corresponding dummy silicon through via SS16. Fig. 11C not shown) are connected to the corresponding stress sensing structure SS12.

[0086] In some embodiments, the test voltage can be received by two lead pads SS18 connected to both ends of the stress detection structure SS12, and the final resistance R' of the lead structure can be obtained by testing. As described above, compared with the sensing part (stress detection structure SS12) being affected by stress in the plane where the first direction and the second direction are located, the non-sensing part (lead structure SS10) being affected by stress in the plane where the first direction and the second direction are located can be ignored, and the resistance of the first lead structure (included in the first resistor R1) and the second resistor R2 of the second lead structure before and after bonding (which can be interpreted as before and after being stressed) can be ignored, that is, the resistance of the first lead structure and the second resistor R2 of the second lead structure remain unchanged before and after bonding; it can be obtained that the resistance change ΔR of the stress detection structure before and after being stressed is = (R'-(R1+R2)) (hereinafter referred to as Formula 3). According to Formula 3, the stress at the position can be calculated, and the positive and negative stress can be used to determine whether the position is stretched / compressed.

[0087] The present application provides another method for manufacturing a semiconductor packaging structure. Fig.12The manufacturing method includes the following steps: S201, forming a first semiconductor chip; the first semiconductor chip includes a plurality of first lead-out structures; the first lead-out structures pass through the substrate of the first semiconductor chip and the interconnection structure of the first semiconductor chip; the interconnection structure of the first semiconductor chip is located on the substrate of the first semiconductor chip; S202, forming a second semiconductor chip on the first semiconductor chip; the second semiconductor chip includes a plurality of stress detection structures arranged along a plurality of different directions and a corresponding plurality of second lead-out structures; the second lead-out structure is located under the stress detection structure and connected to the stress detection structure; the second lead-out structure passes through the substrate of the second semiconductor chip and is connected to the corresponding first lead-out structure; the stress detection structure is located in the interconnection structure of the second semiconductor chip; the interconnection structure of the second semiconductor chip is located on the substrate of the second semiconductor chip; the first lead-out structure and the second lead-out structure lead the stress detection structure to the bottom of the plurality of semiconductor chips.

[0088] In some embodiments, a second semiconductor chip is formed including a plurality of stress detection structures arranged along a plurality of different directions and a corresponding plurality of second lead-out structures, including: a first interconnection layer of an interconnection structure of the second semiconductor chip is formed on a substrate of the second semiconductor chip; the first interconnection layer includes a first metal interconnection layer and a stress detection structure of the second semiconductor chip.

[0089] refer to Fig.13A , a functional circuit is formed in the substrate 102 of the first semiconductor chip 100 ( Fig.13A (not shown). An insulating layer is formed on the substrate 102 of the first semiconductor chip 100, and an interconnection structure 104 of a functional circuit led out is formed in the insulating layer. An insulating layer is formed on the interconnection structure 104, and a first bonding structure 106 connected to the interconnection structure 104 is formed in the insulating layer, and the first bonding structure 106 includes a first dummy bonding pad SS13. A dummy silicon through via SS17 is formed under the substrate 102 of the first semiconductor chip 100, penetrating the substrate 102, and a lead-out structure 108 is formed under the substrate 102 of the first semiconductor chip 100 and connected to the dummy silicon through via SS17, and the lead-out structure 108 includes a lead-out pad SS18. For example, the first dummy bonding pad SS13 can be a through-hole dummy via ( Fig.13A The dummy through silicon via SS17 is connected to one end of the corresponding dummy through silicon via SS17, and the other end of the dummy through silicon via SS17 is connected to the corresponding dummy through silicon via SS17 through the dummy conductive hole ( Fig.13A The lead pads (not shown) are connected to corresponding lead pads SS18.

[0090] In some embodiments, the test voltage can be received by two pairs of pads corresponding to both ends of the stress detection structure SS12 (one pair of pads corresponds to a first dummy bonding pad SS13 and a lead pad SS18), and the second resistance R2 of the first lead structure can be obtained by testing.

[0091] refer to Fig. 13B , a functional circuit is formed in the substrate 202 of the second semiconductor chip 200 ( Fig. 13B (not shown). An insulating layer is formed on the substrate 202 of the second semiconductor chip 200, and an interconnection structure 204 of a functional circuit led out is formed in the insulating layer. In some embodiments, a first interconnection layer M1, a second interconnection layer M2, and a third interconnection layer M3 of the interconnection structure 104 are formed in sequence, and a stress detection structure SS12 can be formed in the photolithography etching process of forming the first interconnection layer M1. A dummy silicon through via SS16 is formed under the substrate 202 of the second semiconductor chip 200 to penetrate the substrate 202, and a second bonding structure 206 is formed under the substrate 202 of the second semiconductor chip 200 and connected to the dummy silicon through via SS16, and the second bonding structure 206 includes a second dummy bonding pad SS15. For example, one end of the dummy silicon through via SS16 can be connected to the corresponding stress detection structure SS12, and the other end of the dummy silicon through via SS16 can be connected to the dummy through hole ( Fig. 13B Not shown) is connected to the corresponding second dummy bonding pad SS15.

[0092] In some embodiments, the stress detection structure SS12 can be measured when it is manufactured (located on the surface of the semiconductor chip at this time), and then its sensitivity coefficient Ks can be calibrated. In some embodiments, when the stress detection structure SS12 is manufactured, the test voltage can be received by two second dummy bonding pads SS15 connected to both ends of the stress detection structure SS12, and the first resistance R1 of the stress detection structure SS12 and the second lead-out structure can be obtained by testing.

[0093] refer to Fig. 13C The first semiconductor chip and the second semiconductor chip are bonded and connected by a bonding process such as a hybrid bonding process. The lead-out structure SS10 of the semiconductor package structure 300 leads the stress detection structure SS12 to the bottom SUR1 of the plurality of semiconductor chips. The first bonding structure 106 and the second bonding structure 206 constitute a bonding structure 302, and the first dummy bonding pad SS13 and the second dummy bonding pad SS15 constitute a dummy bonding pad SS14. For example, one end of the dummy bonding pad SS14 can be a through hole dummy conductive hole ( Fig. 13C The dummy bonding pad SS14 may be connected to one end of the corresponding dummy silicon through via SS16 (not shown), and the other end of the dummy bonding pad SS14 may be connected to the corresponding dummy silicon through via SS16. Fig. 13C The dummy through silicon via SS17 is connected to one end of the corresponding dummy through silicon via SS17, and the other end of the dummy through silicon via SS17 is connected to the dummy through hole ( Fig. 13C The first and second electrodes (not shown) are connected to corresponding lead pads SS18.

[0094] In some embodiments, the test voltage can be received by two lead pads SS18 connected to both ends of the stress detection structure SS12, and the final resistance R' of the lead structure can be obtained by testing. As described above, the resistance change ΔR of the stress detection structure before and after the stress is applied can be obtained, and the stress at the position can be calculated according to Formula 3. The positive or negative value of the stress can be used to determine whether the position is stretched / compressed.

[0095] The semiconductor packaging structure obtained by the manufacturing method of the semiconductor packaging structure provided in the second aspect of the embodiment of the present application is similar to the semiconductor packaging structure provided in the first aspect above. For the technical features not fully disclosed in the embodiment of the present application, please refer to the semiconductor packaging structure in the above embodiment for understanding, and no further details will be given here.

[0096] The above description is only a preferred implementation mode of the present application, and does not limit the protection scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the protection scope of the present application.

Claims

1. A semiconductor packaging structure, characterized in that: comprising a plurality of semiconductor chips arranged in a stack; At least one of the semiconductor chips comprises a plurality of stress detection structures arranged along a plurality of different directions; the stress detection structures are located in an interconnect structure of the semiconductor chip; The plurality of semiconductor chips include a lead-out structure that passes through at least one of the semiconductor chips and is connected to the stress detection structure; the lead-out structure leads the stress detection structure out to the top or bottom of the plurality of semiconductor chips.

2. The semiconductor package structure according to claim 1, wherein: The plurality of stress detection structures include a corresponding plurality of zigzag wires; the plurality of zigzag wires include a first zigzag wire extending along a first direction and a second zigzag wire extending along a second direction; the first direction and the second direction extend and intersect in an interconnect layer of the interconnect structure; The first end of the first zigzag wire and the first end of the second zigzag wire are connected to a common end, and the common end, the second end of the first zigzag wire and the second end of the second zigzag wire are connected to a common pad, a first pad and a second pad of the lead-out structure.

3. The semiconductor package structure according to claim 2, characterized in that: The plurality of zigzag wires further include a third zigzag wire extending along the first direction and a fourth zigzag wire extending along the second direction; the first zigzag wire to the fourth zigzag wire are arranged circumferentially along the common end in an interconnection layer of the interconnection structure; The first end of the third zigzag wire and the first end of the fourth zigzag wire are connected to the common end, and the second end of the third zigzag wire and the second end of the fourth zigzag wire are connected to the third pad and the fourth pad of the lead-out structure.

4. The semiconductor package structure according to claim 3, characterized in that: The plurality of zigzag wires further include a fifth zigzag wire and a seventh zigzag wire extending along the third direction, and a sixth zigzag wire and an eighth zigzag wire extending along the fourth direction; The first to eighth zigzag wires are arranged circumferentially along the common end in an interconnect layer of the interconnect structure; The first ends of the fifth to eighth zigzag wires are connected to the common end, the common end is connected to the common pad of the lead-out structure, and the second ends of the fifth to eighth zigzag wires are respectively connected to the fifth to eighth pads of the lead-out structure.

5. The semiconductor package structure according to claim 2, wherein: The outer contour of the zigzag wire is a quadrilateral or a triangle.

6. The semiconductor package structure according to claim 1, wherein: The stress detection structure is located in a first interconnection layer of the interconnection structure; the first interconnection layer is located at a side of the substrate close to the semiconductor chip in the interconnection structure.

7. The semiconductor package structure according to claim 1, wherein: The lead-out structure includes a dummy silicon through-hole, a dummy conductive hole and a lead-out pad; wherein, The dummy through silicon via passes through at least one of the semiconductor chips; The dummy via is located in the interconnect structure of the semiconductor chip, connected between the dummy through silicon via and the lead pad, and connected between the dummy through silicon via and the stress detection structure; The lead pad is located at the top or bottom of the multiple semiconductor chips, and is used to receive or output a stress test signal. The stress test signal is applied to the lead pad from the outside of the multiple semiconductor chips, or is output from the lead pad to the outside of the multiple semiconductor chips.

8. The semiconductor package structure according to claim 7, characterized in that: The semiconductor packaging structure further includes a bonding structure located between two adjacent semiconductor chips; The lead-out structure includes dummy bonding vias and dummy bonding pads that are interconnected and penetrate the bonding structure. The dummy bonding via and the dummy bonding pad are connected between the dummy through silicon via and the dummy via.

9. A method for manufacturing a semiconductor packaging structure, characterized in that: include: forming a first semiconductor chip; The first semiconductor chip includes a plurality of stress detection structures and corresponding plurality of first lead-out structures arranged along a plurality of different directions; The first lead-out structure is located on the stress detection structure and connected to the stress detection structure; The stress detection structure is located in the interconnect structure of the first semiconductor chip; The interconnect structure of the first semiconductor chip is located on the substrate of the first semiconductor chip; A second semiconductor chip is formed on the first semiconductor chip; the second semiconductor chip includes a second lead-out structure that passes through the substrate of the second semiconductor chip and is connected to the corresponding first lead-out structure; the first lead-out structure and the second lead-out structure lead the stress detection structure to the top of the plurality of semiconductor chips; or, forming a first semiconductor chip; the first semiconductor chip comprises a plurality of first lead-out structures; the first lead-out structures pass through a substrate of the first semiconductor chip and an interconnection structure of the first semiconductor chip; the interconnection structure of the first semiconductor chip is located on the substrate of the first semiconductor chip; A second semiconductor chip is formed on the first semiconductor chip; the second semiconductor chip comprises a plurality of stress detection structures and a corresponding plurality of second lead-out structures arranged in a plurality of different directions; the second lead-out structures are located under the stress detection structures and connected to the stress detection structures; the second lead-out structures pass through the substrate of the second semiconductor chip and are connected to the corresponding first lead-out structures; The stress detection structure is located in the interconnect structure of the second semiconductor chip; The interconnection structure of the second semiconductor chip is located on the substrate of the second semiconductor chip; the first lead-out structure and the second lead-out structure lead the stress detection structure to the bottom of the plurality of semiconductor chips.

10. The manufacturing method according to claim 9, characterized in that: Forming the first semiconductor chip including a plurality of stress detection structures and corresponding first lead-out structures arranged in a plurality of different directions, comprising: forming a first interconnection layer of the interconnection structure of the first semiconductor chip on a substrate of the first semiconductor chip; the first interconnection layer including a first metal interconnection layer of the first semiconductor chip and the stress detection structure; or, The second semiconductor chip is formed to include a plurality of stress detection structures arranged along a plurality of different directions and a corresponding plurality of second lead-out structures, including: a first interconnection layer of the interconnection structure of the second semiconductor chip is formed on a substrate of the second semiconductor chip; the first interconnection layer includes a first metal interconnection layer of the second semiconductor chip and the stress detection structure.

11. The manufacturing method according to claim 9, characterized in that: The second semiconductor chip is formed on the first semiconductor chip, including: using a bonding process to bond the first semiconductor chip to the second semiconductor chip.

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