Buck switching converter set and converter chip in fixed on-time mode

Abstract

The application relates to the technical field of electronic circuits, and discloses a fixed conduction time mode step-down switching converter group and a converter chip. The converter group comprises N parallel step-down switching converters, and each converter comprises a main circuit, a flip-flop, a first phase-shifting circuit and a second phase-shifting circuit, a pulse modulation control circuit and a timing circuit. The output end of the flip-flop is connected with the gate of the upper and lower power tubes of the main circuit. The clock input ends of the first and second phase-shifting circuits are connected with the S and R ends of the flip-flop respectively, and the phase shift angle of the phase-shifting circuit is adjusted to 360 DEG / N. The first converter further comprises the pulse modulation control circuit, the first and second input ends of which are connected with the output end and the feedback point of the main circuit respectively, and the output end is connected with the S end. The input and output ends of the timing circuit are connected with the output end and the R end of the flip-flop respectively, and the timing circuit is used for controlling the fixed conduction time of the upper power tube. The application carries out multi-phase operation through multiple phases, can provide sufficient load current required by engineering application, and can offset the inductance current ripple, so that the output voltage ripple is smaller.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a buck converter group and converter chip with a fixed on-time mode. Background Technology

[0002] Since the advent of electronic products, buck converters have been widely used in battery-powered applications such as various communication devices, portable electronic devices, microprocessors, and automotive electronics. This has led to newer and more diverse design requirements for buck converters, one of which is the power supply for autonomous vehicles. The processors inside autonomous vehicles need to perform a large amount of computation and processing on driving environment information in a short period of time to ensure safe driving. This requires the power supply system to provide a large current and respond quickly to changes in load current.

[0003] However, in existing buck switching converter chips, in-phase operation with a single phase can lead to insufficient load current supply. Summary of the Invention

[0004] The purpose of this invention is to provide a buck converter group and converter chip with a fixed on-time mode, which can perform multi-phase operation in multiple phases, provide sufficient load current required for engineering applications, and cancel out inductor current ripple, resulting in smaller output voltage ripple.

[0005] To achieve the above objectives, the present invention provides a buck converter group under a fixed on-time mode. The buck converter group includes N buck converters connected in parallel, where N is an integer greater than 1. Each buck converter includes: a main circuit; a first flip-flop, the output of which is connected to the gates of the upper and lower power transistors of the main circuit; a first phase-shifting circuit, the clock input of which is connected to the S input of the first flip-flop; and a second phase-shifting circuit, the clock input of which is connected to the R input of the first flip-flop. The phase shift angle between the first and second phase-shifting circuits is adjusted to 360° / N. In any two adjacent buck converters, the first phase shift angle of the first phase-shifting circuit is... The clock output terminal of the phase circuit is connected to the clock input terminal of the first phase shift circuit in the second circuit, and the clock output terminal of the second phase shift circuit in the first circuit is connected to the clock input terminal of the second phase shift circuit in the second circuit. The first buck switching converter further includes: a pulse modulation control circuit, the first input terminal of which is connected to the output terminal of the main circuit, and the second input terminal of which is connected to a voltage feedback point external to the output terminal of the main circuit; the output terminal of which is connected to the S input terminal of the first flip-flop; and a timing circuit, the input terminal of which is connected to the output terminal of the first flip-flop, and the output terminal of which is connected to the R input terminal of the first flip-flop, for controlling the fixed on-time of the upper power transistor.

[0006] Preferably, the first phase-shifting circuit and the second phase-shifting circuit include: an adjustable resistor; a first switching module, which, in response to a first reference voltage, turns on the circuit containing the adjustable resistor to generate current in the circuit; a current mirror; a second flip-flop, the R input terminal of the second flip-flop serving as a clock input terminal; the second switching module includes: a first switching unit, a second switching unit, and an inverter, wherein the output terminal of the second flip-flop is connected to the control terminal of the second switching unit, and the output terminal of the second flip-flop is connected to the control terminal of the first switching unit via the inverter; a first capacitor, the first capacitor being connected in series with the first switching unit and in parallel with the second switching unit; and a first comparator, the output terminal of the first comparator serving as a clock output terminal, the positive input terminal of the first comparator being connected to one end of the first capacitor, and the negative input terminal of the first comparator being connected to the second reference voltage, wherein, in response to a high level clock signal, the first switching unit closes and the second switching unit opens, and the current charges the first capacitor via the current mirror; in response to a low level clock signal and the voltage of the first capacitor being greater than the second reference voltage, the first switching unit opens and the second switching unit closes, and the first capacitor discharges.

[0007] Preferably, the first switching module includes an operational amplifier and a PMOS transistor. The positive input terminal of the operational amplifier is connected to the first reference voltage, the negative input terminal of the operational amplifier is connected to the source of the PMOS transistor and one end of the adjustable resistor, and the output of the operational amplifier is connected to the gate of the PMOS transistor.

[0008] Preferably, the current mirror includes a first NMOS transistor and a second NMOS transistor with their gates connected. The drain and gate of the first NMOS transistor are connected to the drain of the PMOS transistor, and the drain of the second NMOS transistor is connected to the first capacitor via the first switching unit.

[0009] Preferably, the N parallel-connected buck switching converters have the same structure. Each buck switching converter further includes a third switching module, comprising a third switching unit, a fourth switching unit, and a switching control circuit. The output of the pulse modulation control circuit is connected to the S input of the first flip-flop via the third switching unit, and the output of the timing circuit is connected to the R input of the first flip-flop via the fourth switching unit. The switching control circuit in the first buck switching converter controls the corresponding third and fourth switching units to close; the switching control circuits in other buck switching converters control the corresponding third and fourth switching units to open.

[0010] Preferably, the switch control circuit includes: a second comparator, the positive input terminal of the second comparator being connected to a selection signal, the negative input terminal of the second comparator being connected to a third reference voltage, and the output terminal of the second comparator being connected to the control terminals of the third switch unit and the fourth switch unit.

[0011] Preferably, the main circuit includes: the upper power transistor; the lower power transistor; a CCVS located between the upper power transistor and the lower power transistor; an inductor; and an output capacitor, wherein the inductor is connected in series with the output capacitor and in parallel with the lower power transistor.

[0012] Preferably, the pulse modulation control circuit includes: a VCVS, one input terminal of which is connected to the output terminal of the main circuit, and the other input terminal of which is connected to the output terminal of the CCVS; an OTA, the negative input terminal of which is connected to the voltage feedback point, and the positive input terminal of which is connected to the target feedback voltage; and a PWM comparator, the positive input terminal of which is connected to the output terminal of the OTA, and the negative input terminal of which is connected to the output terminal of the VCVS, and the output terminal of which is connected to the S input terminal of the first flip-flop.

[0013] Preferably, the pulse modulation control circuit further includes a compensation circuit, comprising a second capacitor and a third resistor, one end of the second capacitor being connected to the positive input terminal of the PWM comparator, the other end of the second capacitor being connected to one end of the third resistor, and the other end of the third resistor being grounded.

[0014] Through the above technical solution, the present invention creatively introduces a phase-shifting circuit with adjustable phase shift angle into a buck switching converter. A pulse modulation control circuit and a timing circuit are set in the first buck switching converter to generate its own clock signal, thereby controlling the fixed on-time of the power transistor. Furthermore, by connecting multiple buck switching converters in parallel, the present invention can perform multi-phase operation, provide sufficient load current required for engineering applications, and cancel out inductor current ripple, resulting in smaller output voltage ripple.

[0015] A second aspect of the present invention provides a converter chip, the converter chip comprising: a buck switching converter group in a fixed on-time mode; and a selection switch for selecting the 1st to the 1st buck switching converter from N parallel-connected buck switching converters in the buck switching converter group, wherein 1 <i≤N。

[0016] Through the above technical solution, the present invention creatively uses a phase-shifting circuit to form multiple phase-shifting options when multiple chips are connected in parallel, so that the inductor current ripple can be canceled when multiple chips are connected in parallel, the output voltage ripple is smaller, and sufficient load current can be provided for engineering applications.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0019] Figure 1A This is a schematic diagram of a buck switching converter in COT mode provided in an embodiment of the present invention;

[0020] Figure 1B This is a schematic diagram of a buck switching converter in COT mode provided by an embodiment of the present invention;

[0021] Figure 1C This is a schematic diagram of a buck switching converter in COT mode provided in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the phase-shifting circuit provided in an embodiment of the present invention;

[0023] Figure 3 This is an inductor current waveform diagram provided in an embodiment of the present invention;

[0024] Figure 4 This is a connection diagram of two cascaded step-down switching converters provided in an embodiment of the present invention. Detailed Implementation

[0025] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0026] One embodiment of the present invention provides a buck converter group in a fixed on-time (COT) mode, wherein the buck converter group may include N buck converters 100 connected in parallel, such as... Figures 1A to 1C As shown, N is an integer greater than 1. For example, the buck switching converter group includes two buck switching converters 100 connected in parallel, such as... Figure 4 As shown.

[0027] like Figure 1AAs shown, the buck converter 100 includes: a main circuit 10; a first flip-flop 20, the output of which is connected to the gates of the upper power transistor M1 and the lower power transistor M2 of the main circuit 10; a first phase shift circuit 30, the clock input S_IN of which is connected to the S input of the first flip-flop 20; and a second phase shift circuit 40, the clock input R_IN of which is connected to the R input of the first flip-flop 20. The phase shift angle between the first phase shift circuit 30 and the second phase shift circuit 40 is adjusted to 360° / N. Figure 4 As shown, two buck converters 100 connected in parallel have their phase shift angles adjusted to 180°. The final inductor current waveform is shown in the figure. Figure 3 As shown.

[0028] In any two adjacent buck-type switching converters, the clock output terminal of the first phase-shifting circuit in the first converter is connected to the clock input terminal of the first phase-shifting circuit in the second converter, and the clock output terminal of the second phase-shifting circuit in the first converter is connected to the clock input terminal of the second phase-shifting circuit in the second converter.

[0029] like Figure 4 As shown, for two parallel buck converters, the clock output terminal S_OUT of the first phase shift circuit in the first buck converter is connected to the clock input terminal S_IN of the first phase shift circuit in the second buck converter, and the clock output terminal R_OUT of the second phase shift circuit in the first buck converter is connected to the clock input terminal R_IN of the second phase shift circuit in the second buck converter.

[0030] like Figure 1B As shown, the first buck switching converter may further include: a pulse modulation control circuit 50, the first input terminal of which is connected to the output terminal (output voltage VOUT) of the main circuit 10, and the second input terminal of which is connected to the voltage feedback point FB external to the output terminal of the main circuit, and the output terminal of which is connected to the S input terminal of the first flip-flop 20; and a timing circuit 60, the input terminal of which is connected to the output terminal Q of the first flip-flop 20, and the output terminal of which is connected to the R input terminal of the first flip-flop, for controlling the fixed on-time of the upper power transistor.

[0031] Specifically, each buck converter includes: a main circuit 10; a first trigger 20; a first phase-shifting circuit 30; and a second phase-shifting circuit 40. The main circuit 10 converts the high voltage supplied by the DC source into the low DC voltage required for the normal operation of the electrical equipment. In addition, as... Figure 1B As shown, the first buck switching converter also includes a pulse modulation control circuit 50 and a timing circuit 60 (e.g., a Ton module). The pulse modulation control circuit 50 employs voltage and current feedback closed-loop control, adjusting the duty cycle based on the output feedback voltage of the buck switching converter to maintain a stable output voltage. The first trigger 20 outputs a control signal based on the clock signal (S signal) generated by the pulse modulation control circuit 50 and the clock signal (R signal) generated by the timing circuit, triggering the on / off of the upper and lower power transistors. In COT mode, the S and R signals in the first trigger jointly determine the on and off times of the upper and lower power transistors.

[0032] The timing circuit 60 (e.g., the Ton module) acquires the signal generated by the state of M1 (as shown in C_2) to control the turning on of the lower power transistor M2. The difference between the output feedback voltage FB and the 0.6V reference voltage is amplified by a transconductance amplifier and used as the positive terminal of the PWM comparator. The difference between the feedback current sample Vsense and the output voltage Vout is amplified by a voltage-controlled voltage source (VCVS) and used as the negative terminal of the PWM comparator. The PWM output is the S-terminal input of the first flip-flop, controlling the turning on of the upper power transistor M1.

[0033] As one specific solution in the embodiment, such as Figure 4 As shown, for example, when two chips are connected in parallel, R_IN is connected to the output signal R_OUT generated by the previous chip, and S_IN is connected to the output signal S_OUT generated by the previous chip. After passing through a phase-shifting circuit, the outputs R_OUT and S_OUT are connected to R_IN and S_IN of the next chip, thereby achieving phase shifting of the inductor current. When two chips are connected in parallel, the chip input voltage range is 4-20V, the frequency range is 800kHz-4MHz, the output voltage is a stable 1.5V, the operating frequency is 1MHz, the single-chip output current is 5A, and the output current after two chips are connected in parallel is 10A.

[0034] like Figure 1AAs shown, the main circuit 10 includes: an upper power transistor M1; a lower power transistor M2; a CCVS located between the upper power transistor M1 and the lower power transistor M2; an inductor L; and an output capacitor Cout, wherein the inductor L is connected in series with the output capacitor Cout and in parallel with the lower power transistor M2. A first voltage divider resistor R1 and a second voltage divider resistor R2, connected in series through the voltage feedback point FB, are connected in parallel with the output capacitor Cout, wherein the first voltage divider resistor R1 and the second voltage divider resistor R2 are either output terminals of the main circuit or external voltage divider resistors connected to the converter.

[0035] like Figure 1A As shown, the pulse modulation control circuit 50 includes: a VCVS, one input terminal of which is connected to the output terminal of the main circuit (e.g., VOUT), and the other input terminal of which is connected to the output terminal of the CCVS (e.g., Vsense); an OTA, the negative input terminal of which is connected to the output terminal of the main circuit or the voltage feedback point FB of the first voltage divider resistor R1 and the second voltage divider resistor R2 connected externally to the converter, and the positive input terminal of which is connected to the target feedback voltage (e.g., 0.6V); and a PWM comparator, the positive input terminal of which is connected to the output terminal of the OTA, and the negative input terminal of which is connected to the output terminal of the VCVS, and the output terminal of which is connected to the S input terminal of the first flip-flop.

[0036] This embodiment uses a current-controlled voltage source to output current disturbance information (Vsense). The current of the upper power transistor is fed back into the loop through a certain proportion of gain, replacing the ramp generator in the voltage mode and peak current mode. The modulation information does not need to pass through the large capacitor integrator of the error amplifier, thus having a great advantage in transient response.

[0037] The clock signal generated by the pulse modulation control circuit 50 is phase-shifted by the first phase-shifting circuit 30 to output a phase-shifted clock signal S_OUT. This clock signal S_OUT serves as the input signal S_IN of the first phase-shifting circuit of the next buck-type switching converter. Similarly, the clock signal generated by the timing circuit 60 is phase-shifted by the second phase-shifting circuit 40 to output a phase-shifted clock signal R_OUT. This clock signal R_OUT serves as the input signal R_IN of the second phase-shifting circuit of the next buck-type switching converter. Likewise, multiple buck-type switching converters can generate multi-phase output signals. The buck-type switching converter provided by this invention introduces a clock phase-shifting circuit and uses a multi-phase output interleaving method to reduce ripple. This load current sharing technology can solve the problem of local overheating or insufficient output power caused by uneven output current, and quickly achieve loop stability.

[0038] When the system starts working, its operation is as follows: During the off-time period, M1 is off, M2 is on, the energy storage inductor L discharges, and the inductor current gradually decreases. The inductor current information is also connected to one input of the pulse modulation control circuit 50 (e.g., voltage-controlled voltage source VCVS) through the current-controlled voltage source CCVS (which acts as a current sampling module). The output voltage VOUT is connected to the other input of VCVS. The difference between Vsense and VOUT is connected to the negative terminal of the PWM comparator through the gain of VCVS. The output voltage VOUT (e.g., 1.5V) is connected to the feedback voltage of the voltage feedback point FB through voltage divider resistors R1 and R2. The feedback voltage and the target voltage 0.6V are connected to the positive input of the PWM comparator through the gain of the transconductance amplifier (OTA). When the sampled current touches the valley current, the PWM comparator outputs a narrow pulse to flip the drive control signal (i.e., the output signal of the first flip-flop 20) high, turning off M2 and turning on M1. The off-time ends and the conduction timer begins. At this time, the conduction timer (Ton) module collects the state of M1 and starts timing, and the inductor current rises. After a fixed time has elapsed, the timer outputs a narrow pulse, which brings the control signal low, causing the system to enter a shutdown cycle. At the same time, the Ton timer is cleared, completing a full control cycle.

[0039] Multiple buck switching converters can generate multi-phase output signals. The buck switching converter provided by this invention introduces a clock phase shift circuit and adopts a multi-phase output interleaving method to reduce ripple. This load current sharing technology can solve the problem of local overheating or insufficient output power caused by uneven output current and quickly achieve loop stability.

[0040] like Figure 1A As shown, the pulse modulation control circuit further includes a compensation circuit, comprising a second capacitor and a third resistor. One end of the second capacitor is connected to the positive input terminal of the PWM comparator, and the other end of the second capacitor is connected to one end of the third resistor, with the other end of the third resistor grounded.

[0041] Compared to peak current mode, COT mode eliminates the need for a slope compensation module. The compensation value only needs to be designed at OTA. In COT mode, the disturbance of inductor current only affects the current cycle. Subsequent cycles are no different from the steady-state waveform except for shifting on the time axis. There will be no situation where the disturbance of peak current mode increases cycle by cycle. It is more stable and the compensation value is easier to adjust.

[0042] As analyzed above, each phase has a phase shift of 360° / N, where N represents the number of phases or the number of parallel converters. For example... Figure 4As shown, the CLKOUT (e.g., S_OUT and R_OUT) generated by the first converter should be consistent with the switching frequency generated by the converter itself, with a 180° phase shift, and input to the CLKIN (e.g., S_IN and R_IN) pins of the second converter. Therefore, the Rext pins at the PHMODE1 and PHMODE2 pins of the first chip are both connected to 500kΩ. The resistors at the PHMODE1 and PHMODE2 pins of the second chip are connected to any value. The SELECT pin of the first chip is connected to the input voltage VIN to select its own clock signal, and the SELECT pin of the second chip is grounded to select the clock signal provided by the first chip.

[0043] This example uses a multi-master control current sharing method, such as... Figure 4 As shown, when the two chips are connected in parallel, the FB, SW, Vsense, and Vout pins are all connected.

[0044] In one embodiment, since it is not yet clear which one will be the first converter in the converter group when the buck switching converter is fabricated, the structures of each converter can be designed to be the same, and the pulse modulation control circuit and the timing circuit can be turned on or off by configuring certain switching modules.

[0045] Specifically, the N parallel-connected buck switching converters have the same structure. For example... Figure 1C As shown, the step-down switching converter 100 may further include: a third switching module, including a third switching unit S2, a fourth switching unit S1 and a switching control circuit, wherein the output terminal of the pulse modulation control circuit 50 is connected to the S input terminal of the first trigger 20 via the third switching unit S2, and the output terminal of the timing circuit 60 is connected to the R input terminal of the first trigger 20 via the fourth switching unit S1.

[0046] Accordingly, the switch control circuit in the first buck converter controls the corresponding third switch unit S2 and fourth switch unit S1 to close; the switch control circuit in other buck converters controls the corresponding third switch unit S2 and fourth switch unit S1 to open.

[0047] In other words, for the first buck switching converter in the converter group, the pulse modulation control circuit 50 and the timing circuit 60 are turned on by controlling S2 and S1 to close; while for other buck switching converters, the pulse modulation control circuit 50 and the timing circuit 60 are turned off by controlling S2 and S1 to open.

[0048] like Figure 1CAs shown, the switch control circuit includes: a second comparator 70, the positive input terminal of the second comparator 70 is connected to the selection signal SELECT, the negative input terminal of the second comparator 70 is connected to a third reference voltage (e.g., 4V), and the output terminal of the second comparator 70 is connected to the control terminals of the third switch unit S2 and the fourth switch unit S1.

[0049] like Figure 1C As shown, SELECT is a direct user input. When the input is high (e.g., above 4V), the comparator connected to the SELECT pin outputs a high level (e.g., signal C_1). The C_1 signal directly controls the switching states of S1 and S2. In this state, S1 and S2 are closed, using their own S and R signals as inputs. When SELECT is grounded, the comparator outputs a low level, S1 and S2 are open, and external S and R signals are used as inputs. In other words, SELECT is a direct user input used to determine whether the converter selects the clock output signal generated by the previous converter.

[0050] Specifically, such as Figure 1C As shown, the external input voltage provides the internal power supply VIN to the chip. The VIN pin is connected to the drain of the upper power transistor M1. The source of M1 is connected to one end of the current-controlled voltage source, and the other end of the current-controlled voltage source is connected to the drain of the lower power transistor M2, outputting the SW signal. One end of the inductor L is connected to the current-controlled voltage source, and the other end is connected to the feedback voltage divider resistors R1 and R2, the output capacitor Cout, and the load Rload, respectively. The lower end of R1 and the upper end of R2 output a feedback voltage FB, which is connected to one end of the transconductance amplifier OTA. The other end of OTA is connected to a 0.6V reference voltage, and the difference between the two is connected to the positive terminal of the PWM comparator after passing through OTA. One end of R4 is connected to ground, and the other end is connected to one end of C1. The other end of C1 is connected to the output of OTA. Vsense and the output voltage sample VOUT are connected to the two input terminals of the voltage-controlled voltage source, respectively. The output of the voltage-controlled voltage source is connected to the negative terminal of the PWM comparator. The output of the PWM comparator is connected to the S input terminal of the first flip-flop. The input of the timing circuit (e.g., the Ton module) acquires the on-state of M1, and its output is connected to the S input of the first flip-flop. The output Q of the first flip-flop is connected to the input of the drive circuit, and the output of the drive circuit is connected to the gates of M1 and M2.

[0051] Therefore, the COT architecture simplifies converter design, reduces the number of components, makes compensation values ​​easier to adjust, and requires less output capacitance to meet the transient response of a given load.

[0052] The specific structure of the phase-shifting circuit in the above embodiments will be described below.

[0053] In one embodiment, such as Figure 2 As shown, the first phase-shifting circuit and the second phase-shifting circuit include: an adjustable resistor Rext; a first switching module 1, which conducts the circuit containing the adjustable resistor Rext in response to a first reference voltage to generate current in the circuit; a current mirror 2; a second flip-flop 3, the R input terminal of the second flip-flop 3 serving as a clock input terminal; a second switching module, including: a first switching unit S3, a second switching unit S4, and an inverter 4, wherein the output terminal of the second flip-flop 3 is connected to the control terminal of the second switching unit S4, and the output terminal of the second flip-flop 3 is connected to the control terminal of the first switching unit S3 via the inverter 4; a first capacitor C2, the first capacitor C2 being connected in series with the first switching unit S3 and in parallel with the second switching unit S4; and a first comparator 5, the output terminal of the first comparator 5 serving as a clock output terminal, the positive input terminal of the first comparator 5 being connected to one end of the first capacitor C2, and the negative input terminal of the first comparator 5 being connected to the second reference voltage.

[0054] In response to a high clock signal, the first switch unit S3 is closed and the second switch unit S4 is open, and the current charges the first capacitor C2 through the current mirror 2; in response to a low clock signal and the voltage of the first capacitor C2 being greater than the second reference voltage, the first switch unit S3 is open and the second switch unit S4 is closed, and the first capacitor C2 discharges.

[0055] like Figure 2 As shown, Vref1 is the reference voltage, connected to the input of the first switching module 1, so as to control the circuit containing the adjustable resistor to be turned on or off. The source of the current mirror 2 is connected to VIN, the drain of the current mirror 2 is connected to the upper end of the voltage-controlled switch S1, the other end of S1 is connected to the upper end of C2, and the other end of C2 is grounded. At the same time, a lead is drawn from the lower end of S1 and the upper end of C2 to the positive input of the first comparator 5, and the negative input of the first comparator 5 is connected to the reference voltage Vref2. The output of the first comparator 5 is connected to the pin CLKOUT (which corresponds to R_OUT or S_OUT), and is also connected to the S input of the second flip-flop 3. The R input is connected to CLKIN (which corresponds to R_IN or S_IN). The output Q of the second flip-flop 3 is connected to the control terminal of the voltage-controlled switch S2, and is also connected to the input of the inverter 4. The two ends of S2 are respectively connected to the two ends of C2 to complete the control of the charging and discharging of the capacitor.

[0056] like Figure 2As shown, CLKIN is the system input clock (corresponding to R_IN or S_IN). When Rext of the phase-shifting circuit is determined, the reference voltage Vref1 turns on the first switch module 1. The current value I1 of the circuit where Rext is located is obtained by Vref1 / Rext, and I1 charges capacitor C through the current mirror. When the voltage across the first capacitor C2 exceeds the reference voltage Vref2, the first comparator 5 outputs a high level, which sets the S terminal of the second flip-flop 3 to 1. At this time, the R terminal is 0, and the output Q of the second flip-flop 3 is 1, which closes the voltage-controlled switch S2 connected across the capacitor. At the same time, the control signal opens S1 through the inverter 4, and the first capacitor C2 begins to discharge. When the signal at the R terminal (i.e., the system input clock arrives) is 1, Q is cleared to zero, S2 is opened, S1 is closed, and I1 continues to charge the first capacitor C2 until the first comparator 5 outputs a high level. At this time, the signal is simultaneously output to the S terminal and CLKOUT of the second flip-flop 3. The signal at the S terminal or CLKOUT is the phase-shifted clock signal, and the phase-shifting time is the capacitor charging time.

[0057] Specifically, the first switching module 1 includes an operational amplifier 11 and a PMOS transistor M3. The positive input terminal of the operational amplifier 11 is connected to the first reference voltage, the negative input terminal of the operational amplifier 11 is connected to the source of the PMOS transistor M3 and one end of the adjustable resistor Rext, and the output of the operational amplifier 11 is connected to the gate of the PMOS transistor M3.

[0058] like Figure 2 As shown, the current mirror 2 includes a first NMOS transistor M4 and a second NMOS transistor M5 with their gates connected. The drain and gate of the first NMOS transistor M4 are connected to the drain of the PMOS transistor M3, and the drain of the second NMOS transistor M5 is connected to the first capacitor C2 via the first switching unit S3.

[0059] like Figure 2As shown, Vref1 is the reference voltage, connected to the positive terminal of the operational amplifier. The output of the operational amplifier is connected to the gate of M3, and the source of M3 is connected to the negative terminal of the operational amplifier. The source of M3 is also connected to the upper end of Rext. A PHMODE pin is led out between the source of M3 and Rext, and the other end of Rext is grounded. The drain of M3 is connected to the drain of M4, and the source of M4 is connected to VIN. The gate of M4 is connected to the gate of M5, and the gate and drain of M4 are connected, forming a diode connection. The source of M5 is also connected to VIN, and its drain is connected to the upper end of the voltage-controlled switch S1. The other end of S1 is connected to the upper end of C2, and the other end of C2 is grounded. A line is led out between the lower end of S1 and the upper end of C2 and connected to the positive input of the comparator. The negative input of the comparator is connected to the reference voltage Vref2. The comparator output is sent to the CLKOUT pin and connected to the S input of the second flip-flop. The R input is connected to CLKIN. The S / R output Q is connected to the control terminal of the voltage-controlled switch S2 and also to the input of the inverter. The two ends of S2 are connected to the two ends of C2 respectively to control the charging and discharging of the capacitor.

[0060] like Figure 2 As shown, CLKIN is the system input clock (which corresponds to R_IN or S_IN). When the Rext of the phase shift circuit is determined, the reference voltage Vref1 is output to the gate of M3 after passing through the operational amplifier, so that M3 is turned on. At the same time, the operational amplifier, M3 and Rext form a negative feedback loop to ensure that the Vgs of M3 is constant. The current value I1 of M3 is obtained by Vref1 / Rext. Meanwhile, M4 and M5 form a current mirror, and I1 charges capacitor C through the current mirror. When the voltage across the capacitor exceeds the reference voltage Vref2, the comparator outputs a high level, which sets the S terminal of the flip-flop to 1. At this time, the R terminal is 0, and the flip-flop outputs Q to 1, which closes the voltage-controlled switch S2 connected across the capacitor. At the same time, the control signal passes through the inverter to open S1, and capacitor C begins to discharge. When the signal at the R terminal (i.e., the system input clock arrives) is 1, Q is cleared to zero, S2 is opened, S1 is closed, and I1 continues to charge C until the comparator outputs a high level. At this time, the signal is simultaneously output to the S terminal of the flip-flop and CLKOUT. The signal at the S terminal or CLKOUT is the phase-shifted clock signal, and the phase-shifting time is the capacitor charging time.

[0061] When multiple chips are connected in parallel, the S and R signals of the first chip enter the corresponding phase-shifting circuit. The user selects the desired phase shift angle directly through the external Rext pin via the phase selection input PHMODE. The phase-shifted clock signal is then connected to the S_IN and R_IN pins of the next chip via S_OUT and R_OUT. This process is repeated to achieve phase shifting of the two signals. The Rext pin of the last chip can have any resistance value. When multiple chips are connected in parallel, the phase-shifting circuit provides various phase shift options, allowing the inductor current ripple to be canceled out and resulting in a smaller output voltage ripple.

[0062] The phase shift angle achieved by the phase shift circuit is directly determined by Rext. The specific relationship between the phase shift time t and Rext is: t = CRext, where C is the capacitance value in the phase shift circuit, for example, C = 1pF. For example, in a three-phase cascaded circuit with a frequency of 1MHz, the inductor current phase shifts by 120°, then t = 330ns, and the corresponding Rext = 330kΩ. The phase shift angle can be selected from any angle from 1° to 180°, with a wide range of variation, and can adapt to various parallel connection methods from 2 to 12 phases. The phase shift circuit pins include clock input CLK_IN, phase selection input PHMODE, and phase-shifted output clock CLK_OUT.

[0063] The phase-shifting circuit is suitable for an adjustable frequency system clock. In the buck switching converter in the COT mode, the system frequency is from 800kHz to 4MHz. The phase-shifting circuit can work normally when multiple chips are connected in parallel.

[0064] This embodiment incorporates a phase-shifting circuit to control the output clock phase into the buck switching converter chip. This phase-shifting circuit is simple and easy to control, allowing for a reduction in the size of the chip's input and input capacitors, which helps improve loop response and results in faster load response. When connected in parallel, the inductor current ripple is canceled out, leading to lower output voltage ripple.

[0065] This invention designs a programmable phase-shifting circuit for parallel applications of COT mode buck converters. It can effectively shift the phase of the clock signal, and the parallel power supply system can share current stress and achieve N+1 redundancy. Furthermore, the multi-phase interleaved parallel connection can cancel inductor current ripple, resulting in lower output voltage ripple. Multi-phase interleaved parallel technology is divided into in-phase and out-of-phase operation. In-phase operation refers to the same frequency and phase, where the increment of the inductor current iL in one cycle Tsw is equivalent to the superposition of multiple inductor currents. Out-of-phase operation refers to the same frequency but different phases, where the increment of the inductor current of multiple converters in one cycle Tsw is partially or completely canceled out by the inductor currents output by multiple chips with different phases. The phase shifting referred to in various embodiments of this invention is all out-of-phase operation.

[0066] In summary, this invention creatively introduces a phase-shifting circuit with adjustable phase shift angle into a buck switching converter. A pulse modulation control circuit and a timing circuit are set in the first buck switching converter to generate its own clock signal, thereby controlling the fixed on-time of the power transistor. Furthermore, by connecting multiple buck switching converters in parallel, this invention enables multi-phase operation, providing sufficient load current for engineering applications, and canceling out inductor current ripple, resulting in lower output voltage ripple.

[0067] An embodiment of the present invention provides a converter chip, the converter chip comprising: a buck switching converter group according to the fixed on-time mode; and a selection switch for selecting the 1st to the 1st buck switching converter from N parallel-connected buck switching converters in the buck switching converter group, wherein 1 <i≤N。

[0068] Specifically, based on actual needs, the first i buck converters can be selected from N parallel-connected buck converters using a selector switch to form the i-phase output signal. Here, i is an integer. When i = 2, the phase shift angle of the phase-shifting circuit is adjusted to 180°.

[0069] In summary, this invention creatively applies a phase-shifting circuit to multiple parallel circuits, creating various phase-shifting options. This allows the inductor current ripple to be canceled out when multiple circuits are connected in parallel, resulting in smaller output voltage ripple and providing sufficient load current for engineering applications.

[0070] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0071] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0072] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a microcontroller, chip, or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0073] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0074] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0075] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A step-down switching converter bank with a fixed on-time mode, characterized in that, The buck switching converter group comprises: N buck switching converters connected in parallel, where N is an integer greater than 1. The buck converter includes: a main circuit; a first flip-flop, the output of which is connected to the gates of the upper and lower power transistors of the main circuit; a first phase-shifting circuit, the clock input of which is connected to the S input of the first flip-flop; and a second phase-shifting circuit, the clock input of which is connected to the R input of the first flip-flop, wherein the phase shift angle between the first and second phase-shifting circuits is adjusted to 360° / N. In any two adjacent buck switching converters, the clock output of the first phase-shifting circuit in the first converter is connected to the clock input of the first phase-shifting circuit in the second converter, and the clock output of the second phase-shifting circuit in the first converter is connected to the clock input of the second phase-shifting circuit in the second converter. The first step-down switching converter further includes: a pulse modulation control circuit, the first input terminal of which is connected to the output terminal of the main circuit, and the second input terminal of which is connected to an external voltage feedback point of the output terminal of the main circuit; the output terminal of which is connected to the S input terminal of the first flip-flop; and a timing circuit, the input terminal of which is connected to the output terminal of the first flip-flop, and the output terminal of which is connected to the R input terminal of the first flip-flop, for controlling the fixed on-time of the upper power transistor. The first and second phase-shifting circuits each include: an adjustable resistor; a first switching module, which, in response to a first reference voltage, turns on the circuit containing the adjustable resistor to generate current in that circuit; a current mirror; a second flip-flop, the R input terminal of which serves as a clock input terminal; and a second switching module, including: a first switching unit, a second switching unit, and an inverter, wherein the output terminal of the second flip-flop is connected to the control terminal of the second switching unit, and the output terminal of the second flip-flop is connected to the control terminal of the first switching unit via the inverter; a first capacitor, which is connected in series with the first switching unit and in parallel with the second switching unit; and a first comparator, the output terminal of which serves as a clock output terminal, the positive input terminal of which is connected to one end of the first capacitor, and the negative input terminal of which is connected to the second reference voltage. Specifically, in response to a high-level clock signal, the first switching unit closes and the second switching unit opens, allowing the current to charge the first capacitor via the current mirror; in response to a low-level clock signal and a voltage of the first capacitor greater than the second reference voltage, the first switching unit opens and the second switching unit closes, allowing the first capacitor to discharge. The main circuit includes: the upper power transistor; the lower power transistor; a CCVS located between the upper power transistor and the lower power transistor; an inductor; and an output capacitor, wherein the inductor is connected in series with the output capacitor and in parallel with the lower power transistor.

2. The step-down switching converter group according to claim 1, characterized in that, The first switching module includes an operational amplifier and a PMOS transistor. The positive input terminal of the operational amplifier is connected to the first reference voltage, the negative input terminal of the operational amplifier is connected to the source of the PMOS transistor and one end of the adjustable resistor, and the output of the operational amplifier is connected to the gate of the PMOS transistor.

3. The step-down switching converter group according to claim 2, characterized in that, The current mirror includes a first NMOS transistor and a second NMOS transistor with their gates connected. The drain and gate of the first NMOS transistor are connected to the drain of the PMOS transistor, and the drain of the second NMOS transistor is connected to the first capacitor via the first switching unit.

4. The step-down switching converter group according to claim 1, characterized in that, The N parallel-connected buck switching converters have the same structure, and the buck switching converter further includes: The third switching module includes a third switching unit, a fourth switching unit, and a switching control circuit. The output of the pulse modulation control circuit is connected to the S input of the first flip-flop via the third switching unit, and the output of the timing circuit is connected to the R input of the first flip-flop via the fourth switching unit. The corresponding third and fourth switching units are closed by the switch control circuit in the first buck switching converter; the corresponding third and fourth switching units are opened by the switch control circuit in other buck switching converters.

5. The step-down switching converter group according to claim 4, characterized in that, The switch control circuit includes: a second comparator, the positive input terminal of the second comparator being connected to a selection signal, the negative input terminal of the second comparator being connected to a third reference voltage, and the output terminal of the second comparator being connected to the control terminals of the third switch unit and the fourth switch unit.

6. The step-down switching converter group according to claim 1, characterized in that, The pulse modulation control circuit includes: a VCVS, one input terminal of which is connected to the output terminal of the main circuit, and the other input terminal of which is connected to the output terminal of the CCVS; an OTA, the negative input terminal of which is connected to the voltage feedback point, and the positive input terminal of which is connected to the target feedback voltage; and a PWM comparator, the positive input terminal of which is connected to the output terminal of the OTA, and the negative input terminal of which is connected to the output terminal of the VCVS, and the output terminal of which is connected to the S input terminal of the first flip-flop.

7. The step-down switching converter group according to claim 6, characterized in that, The pulse modulation control circuit further includes a compensation circuit, comprising a second capacitor and a third resistor. One end of the second capacitor is connected to the positive input terminal of the PWM comparator, and the other end of the second capacitor is connected to one end of the third resistor, with the other end of the third resistor grounded.

8. A converter chip, characterized in that, The converter chip includes: A buck switching converter group in fixed on-time mode according to any one of claims 1-7; and A selection switch is used to select the 1st to the 1st buck switch converter from the N parallel-connected buck switch converters in the buck switch converter group, wherein 1 <i≤N。

Images