Control circuit with the function of memorizing the polarity of the initial induction magnetic field

Abstract

The present invention discloses a control circuit with the function of memorizing the polarity of the initial induction magnetic field, including a full-pole to south-pole single-pole control circuit. The input end of the full-pole to south-pole single-pole control circuit is connected to a south-pole induction synchronization control circuit. The output end of the full-pole to south-pole single-pole control circuit is connected to a north-pole induction synchronization control circuit. The output end of the north-pole induction synchronization control circuit is respectively connected to a full-pole to north-pole single-pole control circuit and a judgment circuit. The output end of the south-pole induction synchronization control circuit is connected to the judgment circuit. The south-pole induction synchronization control circuit and the input end of the north-pole induction synchronization control circuit are jointly connected to a synchronization control logic signal. The input end of the south-pole induction synchronization control circuit is connected to a south-pole induction signal, and the input end of the north-pole induction synchronization control circuit is connected to a north-pole induction signal; it solves the problem in the prior art that the magnet polarity needs to be measured first during magnet assembly, which affects the packaging efficiency.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a control circuit with the function of memorizing the polarity of the initial induced magnetic field. Background Art

[0002] With the development of technology and the continuous innovation in the electronics industry, the functional requirements for chips are becoming increasingly strict. As one of the many types of chips, Hall chips have a wide range of applications. The existing Hall chips on the market are divided into unipolar switch Hall, unipolar linear Hall, bipolar latch switch Hall, bipolar linear Hall, and omnipolar switch Hall. However, when customers use them in some specific occasions, they can only use unipolar switch Hall or unipolar linear Hall. However, unipolar Hall chips have strict requirements for the assembly of the matching magnet, and the polarity of the magnet must be consistent with the induction polarity of the Hall chip. Therefore, in the production process, it is necessary to add a process to identify the polarity of the magnet, which reduces the efficiency, increases the production cost, and brings inconvenience. Summary of the Invention

[0003] The purpose of the present invention is to provide a control circuit with the function of memorizing the polarity of the initial induced magnetic field, which solves the problem in the prior art that the polarity of the magnet needs to be measured first during magnet assembly, affecting the packaging efficiency.

[0004] The first technical solution adopted by the present invention is a control circuit with the function of memorizing the polarity of the initial induced magnetic field, including an omnipolar to south-pole unipolar control circuit. The input end of the omnipolar to south-pole unipolar control circuit is connected to a south-pole induction synchronization control circuit, the output end of the omnipolar to south-pole unipolar control circuit is connected to a north-pole induction synchronization control circuit. The output end of the north-pole induction synchronization control circuit is respectively connected to an omnipolar to north-pole unipolar control circuit and a judgment circuit. The output end of the south-pole induction synchronization control circuit is connected to the judgment circuit. A synchronization control logic signal is commonly connected to the input ends of the south-pole induction synchronization control circuit and the north-pole induction synchronization control circuit. The input end of the south-pole induction synchronization control circuit is connected to a south-pole induction signal, and the input end of the north-pole induction synchronization control circuit is connected to a north-pole induction signal.

[0005] The features of the technical solution of the present invention also lie in:

[0006] The south-pole induction synchronization control circuit is a first flip-flop. The first flip-flop includes a first data input pin D1, a first clock input pin CLK1, a first reset pin RN1, and a first output pin Q1. The first data input pin D1 is connected to the south-pole induction signal, the first clock input pin CLK1 is connected to the synchronization control logic signal, and the first reset pin RN1 is connected to a power-on reset signal.

[0007] The north pole induction synchronization control circuit is the third flip-flop. The third flip-flop includes a third data input pin D3, a third clock input pin CLK3, a third reset pin RN3, and a third output pin Q3. The third data input pin D3 is connected to the north pole induction signal, the third clock input pin CLK3 is connected to the synchronization control logic signal, and the first reset pin RN1 is connected to the power-on reset signal.

[0008] The full-pole to south-pole single-pole control circuit includes a second flip-flop. The second flip-flop includes a second data input pin D2, a second clock input pin CLK2, a second reset pin RN2, a second output pin Q2, and a first inverted output QN1. The second data input pin D2 is grounded, the second clock input pin CLK2 is connected to the first output pin Q1. The first output pin Q1 is connected to an input terminal of a first NAND gate. The first NAND gate is a two-input NAND gate. The second reset pin RN2 is connected to an output terminal of a first NOR gate. The first NOR gate is a two-input NOR gate. One input terminal of the first NOR gate is connected to an output terminal of a first inverter. The input terminal of the first inverter is connected to the power-on reset signal. The output terminal of the first NAND gate is connected to an input terminal of a third inverter.

[0009] The full-pole to north-pole single-pole control circuit includes a fourth flip-flop. The fourth flip-flop includes a fourth data input pin D4, a fourth clock input pin CLK4, a fourth reset pin RN4, a fourth output pin Q4, and a second inverted output QN2. The input terminal of the fourth reset pin RN4 is connected to an output terminal of a second NOR gate. The second NOR gate is a two-input NOR gate. One input terminal of the second NOR gate is connected to an output terminal of a second inverter. The input terminal of the second inverter is connected to the power-on reset signal. The other input terminal of the second NOR gate is connected to the second output pin Q2. The fourth clock input pin CLK4 is connected to the third output pin Q3. The third output pin Q3 is connected to an input terminal of a second NAND gate. The second NAND gate is a two-input NAND gate. The other input terminal of the second NAND gate is connected to the first inverted output QN1. The output terminal of the second NAND gate is connected to an input terminal of a fourth inverter. The fourth data input pin D4 is grounded. The second inverted output QN2 is connected to the input terminal of the first NAND gate.

[0010] The judgment circuit is a two-input OR gate.

[0011] The input terminals of the two-input OR gate are respectively connected to the output terminal of the third inverter and the output terminal of the fourth inverter.

[0012] The first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are all D flip-flops.

[0013] The beneficial effects of the present invention are as follows: The south pole induction synchronization control circuit and the north pole induction synchronization control circuit of the present invention receive the induction results of the magnetic field. After power-on, the polarity (south pole or north pole) first sensed will be used as the polarity for subsequent sensing, and the other polarity (north pole or south pole) will not be sensed. This reduces the steps of manual polarity detection during magnet assembly and improves the assembly efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a control circuit diagram with the function of memorizing the polarity of the initially sensed magnetic field;

[0015] Figure 2 is a component connection diagram of the control circuit with the function of memorizing the polarity of the initially sensed magnetic field. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The present invention will be described in detail below in conjunction with the drawings and specific embodiments.

[0017] The control circuit of the present invention with the function of memorizing the polarity of the initially sensed magnetic field, as Figure 1 shown, includes a full-pole to single south-pole control circuit. The input end of the full-pole to single south-pole control circuit is connected to a south pole induction synchronization control circuit, the output end of the full-pole to single south-pole control circuit is connected to a north pole induction synchronization control circuit, the output end of the north pole induction synchronization control circuit is respectively connected to a full-pole to single north-pole control circuit and a judgment circuit, the output end of the south pole induction synchronization control circuit is connected to the judgment circuit, the input ends of the south pole induction synchronization control circuit and the north pole induction synchronization control circuit are jointly connected to a synchronization control logic signal, the input end of the south pole induction synchronization control circuit is connected to a south pole induction signal, and the input end of the north pole induction synchronization control circuit is connected to a north pole induction signal.

[0018] The south pole induction synchronization control circuit is a first flip-flop. The first flip-flop includes a first data input pin D1, a first clock input pin CLK1, a first reset pin RN1, and a first output pin Q1. The first data input pin D1 is connected to the south pole induction signal, the first clock input pin CLK1 is connected to the synchronization control logic signal, and the first reset pin RN1 is connected to a power-on reset signal.

[0019] The north pole induction synchronization control circuit is a third flip-flop. The third flip-flop includes a third data input pin D3, a third clock input pin CLK3, a third reset pin RN3, and a third output pin Q3. The third data input pin D3 is connected to the north pole induction signal, the third clock input pin CLK3 is connected to the synchronization control logic signal, and the first reset pin RN1 is connected to the power-on reset signal.

[0020] The full-pole to south-pole single-pole control circuit includes a second flip-flop. The second flip-flop includes a second data input pin D2, a second clock input pin CLK2, a second reset pin RN2, a second output pin Q2, and a first inverted output QN1. The second data input pin D2 is grounded. The second clock input pin CLK2 is connected to the first output pin Q1. The first output pin Q1 is connected to an input terminal of a first NAND gate. The first NAND gate is a two-input NAND gate. The second reset pin RN2 is connected to an output terminal of a first NOR gate. The first NOR gate is a two-input NOR gate. One input terminal of the first NOR gate is connected to an output terminal of a first inverter. The input terminal of the first inverter is connected to the power-on reset signal. The output terminal of the first NAND gate is connected to an input terminal of a third inverter.

[0021] The full-pole to north-pole single-pole control circuit includes a fourth flip-flop. The fourth flip-flop includes a fourth data input pin D4, a fourth clock input pin CLK4, a fourth reset pin RN4, a fourth output pin Q4, and a second inverted output QN2. The input terminal of the fourth reset pin RN4 is connected to an output terminal of a second NOR gate. The second NOR gate is a two-input NOR gate. One input terminal of the second NOR gate is connected to an output terminal of a second inverter. The input terminal of the second inverter is connected to the power-on reset signal. The other input terminal of the second NOR gate is connected to the second output pin Q2. The fourth clock input pin CLK4 is connected to the third output pin Q3. The third output pin Q3 is connected to an input terminal of a second NAND gate. The second NAND gate is a two-input NAND gate. The other input terminal of the second NAND gate is connected to the first inverted output QN1. The output terminal of the second NAND gate is connected to an input terminal of a fourth inverter. The fourth data input pin D4 is grounded. The second inverted output QN2 is connected to an input terminal of the first NAND gate, as Figure 2 shown.

[0022] The judgment circuit is a two-input OR gate.

[0023] The input terminals of the two-input OR gate are respectively connected to the output terminal of the third inverter and the output terminal of the fourth inverter.

[0024] The first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are all D flip-flops.

[0025] After power-on, the magnetic field polarity sensed for the first time is the induction signal. If the sensed magnetic field polarity is south pole, the induction signal is the south pole induction signal. If the sensed magnetic field polarity is north pole, the induction signal is the north pole induction signal.

[0026] In the control circuit with the function of memorizing the initial sensed magnetic field polarity, power on the circuit. When the circuit first senses the north pole induction signal, it works when the north pole approaches under the condition of power on and does not work when it moves away. When the south pole approaches, it does not work.

[0027] After power-off, when the circuit is powered on again, if the circuit first senses the south pole induction signal, it works when the south pole approaches and stops working when it moves away. It doesn't work when the north pole approaches.

[0028] Each time after power-off and then power-on again, it will re-collect the induction signal of the first magnetic field polarity sensed, and work after judgment.

[0029] SI represents the north pole induction signal, NI represents the south pole induction signal, SYN_CTRL represents the synchronous control logic signal. If the north pole induction signal is sensed, the logic of the north pole induction signal is "1". If the south pole induction signal is sensed, the logic of the south pole induction signal is "1". When the rising edge or falling edge of SYN_CTRL arrives, the output logic of the south pole induction synchronous control circuit is the same as the logic of the south pole induction signal, and the output logic of the north pole induction synchronous control circuit is the same as the logic of the south pole induction signal; the output logic of the north pole induction synchronous control circuit and the output logic of the south pole induction synchronous control circuit are subjected to a logical "OR" operation to obtain the final output result.

[0030] After the circuit is powered on, when the rising edge or falling edge of SYN_CTRL arrives, if SI first changes from logic "0" to logic "1" and NI still remains at logic "0", then the logic of the south pole induction signal sensed by the all-pole to south pole single-pole control circuit is "1", the input logic of the all-pole to north pole single-pole control circuit is "0", and the output logic of the all-pole to south pole single-pole control circuit is "1", making the output logic of the north pole induction synchronous logic control circuit "0". The final output result of the circuit is only determined by the logic of the south pole induction signal and has nothing to do with the north pole induction signal. For the control circuit with the function of memorizing the initial induction magnetic field polarity, its output form changes from the all-pole magnetic field magnetism at power-on to a single-pole that can only sense the south pole.

[0031] After the circuit is powered on, when the rising edge or falling edge of SYN_CTRL arrives, if NI first changes from logic "0" to logic "1" and SI still remains at logic "0", then the input logic of the all-pole to north pole single-pole control circuit is "1", the logic of the south pole induction signal sensed by the all-pole to south pole single-pole control circuit is "0", and the output logic of the all-pole to north pole single-pole control circuit is "1", making the output logic of the south pole induction synchronous logic control circuit "0". The final output result of the circuit is only determined by the logic of the north pole induction signal and has nothing to do with the south pole induction signal. For the control circuit with the function of memorizing the initial induction magnetic field polarity, its output form changes from the all-pole magnetic field magnetism at power-on to a single-pole that can only sense the north pole.

[0032] If the control circuit with the function of memorizing the polarity of the initially induced magnetic field first senses a south pole signal after power-on, it works when the south pole approaches the circuit and does not work when the south pole moves away from the circuit, and does not work when the north pole approaches the circuit; if the control circuit with the function of memorizing the polarity of the initially induced magnetic field first senses a north pole signal after power-on, it works when the north pole approaches the circuit and does not work when the north pole moves away from the circuit, and does not work when the south pole approaches the circuit.

[0033] Embodiment 1

[0034] The control circuit of the present invention with the function of memorizing the polarity of the initially induced magnetic field includes a full-pole to south-pole single-pole control circuit. The input end of the full-pole to south-pole single-pole control circuit is connected with a south-pole induction synchronization control circuit. The output end of the full-pole to south-pole single-pole control circuit is connected with a north-pole induction synchronization control circuit. The output end of the north-pole induction synchronization control circuit is respectively connected with a full-pole to north-pole single-pole control circuit and a judgment circuit. The output end of the south-pole induction synchronization control circuit is connected with the judgment circuit. The south-pole induction synchronization control circuit and the input end of the north-pole induction synchronization control circuit are jointly connected with a synchronization control logic signal. The input end of the south-pole induction synchronization control circuit is connected with a south-pole induction signal. The input end of the north-pole induction synchronization control circuit is connected with a north-pole induction signal.

[0035] Embodiment 2

[0036] The control circuit of the present invention with the function of memorizing the polarity of the initially induced magnetic field includes a full-pole to south-pole single-pole control circuit. The input end of the full-pole to south-pole single-pole control circuit is connected with a south-pole induction synchronization control circuit. The output end of the full-pole to south-pole single-pole control circuit is connected with a north-pole induction synchronization control circuit. The output end of the north-pole induction synchronization control circuit is respectively connected with a full-pole to north-pole single-pole control circuit and a judgment circuit. The output end of the south-pole induction synchronization control circuit is connected with the judgment circuit. The south-pole induction synchronization control circuit and the input end of the north-pole induction synchronization control circuit are jointly connected with a synchronization control logic signal. The input end of the south-pole induction synchronization control circuit is connected with a south-pole induction signal. The input end of the north-pole induction synchronization control circuit is connected with a north-pole induction signal.

[0037] The south-pole induction synchronization control circuit is a first flip-flop. The first flip-flop includes a first data input pin D1, a first clock input pin CLK1, a first reset pin RN1, and a first output pin Q1. The first data input pin D1 is connected with the south-pole induction signal. The first clock input pin CLK1 is connected with the synchronization control logic signal. The first reset pin RN1 is connected with a power-on reset signal.

[0038] Embodiment 3

[0039] The control circuit with the function of memorizing the polarity of the initial induction magnetic field of the present invention includes a full-pole to south-pole single-pole control circuit. The input end of the full-pole to south-pole single-pole control circuit is connected to a south-pole induction synchronization control circuit. The output end of the full-pole to south-pole single-pole control circuit is connected to a north-pole induction synchronization control circuit. The output end of the north-pole induction synchronization control circuit is respectively connected to a full-pole to north-pole single-pole control circuit and a judgment circuit. The output end of the south-pole induction synchronization control circuit is connected to the judgment circuit. The south-pole induction synchronization control circuit and the input end of the north-pole induction synchronization control circuit are jointly connected to a synchronization control logic signal. The input end of the south-pole induction synchronization control circuit is connected to a south-pole induction signal. The input end of the north-pole induction synchronization control circuit is connected to a north-pole induction signal.

[0040] The south-pole induction synchronization control circuit is a first flip-flop. The first flip-flop includes a first data input pin D1, a first clock input pin CLK1, a first reset pin RN1, and a first output pin Q1. The first data input pin D1 is connected to the south-pole induction signal. The first clock input pin CLK1 is connected to the synchronization control logic signal. The first reset pin RN1 is connected to a power-on reset signal.

[0041] The north-pole induction synchronization control circuit is a third flip-flop. The third flip-flop includes a third data input pin D3, a third clock input pin CLK3, a third reset pin RN3, and a third output pin Q3. The third data input pin D3 is connected to the north-pole induction signal. The third clock input pin CLK3 is connected to the synchronization control logic signal. The first reset pin RN1 is connected to the power-on reset signal.

[0042] Embodiment 4

[0043] The control circuit with the function of memorizing the polarity of the initial induction magnetic field of the present invention includes a full-pole to south-pole single-pole control circuit. The input end of the full-pole to south-pole single-pole control circuit is connected to a south-pole induction synchronization control circuit. The output end of the full-pole to south-pole single-pole control circuit is connected to a north-pole induction synchronization control circuit. The output end of the north-pole induction synchronization control circuit is respectively connected to a full-pole to north-pole single-pole control circuit and a judgment circuit. The output end of the south-pole induction synchronization control circuit is connected to the judgment circuit. The south-pole induction synchronization control circuit and the input end of the north-pole induction synchronization control circuit are jointly connected to a synchronization control logic signal. The input end of the south-pole induction synchronization control circuit is connected to a south-pole induction signal. The input end of the north-pole induction synchronization control circuit is connected to a north-pole induction signal.

[0044] The south-pole induction synchronization control circuit is a first flip-flop. The first flip-flop includes a first data input pin D1, a first clock input pin CLK1, a first reset pin RN1, and a first output pin Q1. The first data input pin D1 is connected to the south-pole induction signal. The first clock input pin CLK1 is connected to the synchronization control logic signal. The first reset pin RN1 is connected to a power-on reset signal.

[0045] The north pole induction synchronous control circuit is the third flip-flop. The third flip-flop includes a third data input pin D3, a third clock input pin CLK3, a third reset pin RN3, and a third output pin Q3. The third data input pin D3 is connected to the north pole induction signal, the third clock input pin CLK3 is connected to the synchronous control logic signal, and the first reset pin RN1 is connected to the power-on reset signal.

[0046] The all-pole to south-pole single-pole control circuit includes a second flip-flop. The second flip-flop includes a second data input pin D2, a second clock input pin CLK2, a second reset pin RN2, a second output pin Q2, and a first inverted output QN1. The second data input pin D2 is grounded, the second clock input pin CLK2 is connected to the first output pin Q1. The first output pin Q1 is connected to an input terminal of a first NAND gate. The first NAND gate is a two-input NAND gate. The second reset pin RN2 is connected to an output terminal of a first NOR gate. The first NOR gate is a two-input NOR gate. One input terminal of the first NOR gate is connected to an output terminal of a first inverter. The input terminal of the first inverter is connected to the power-on reset signal. The output terminal of the first NAND gate is connected to an input terminal of a third inverter.

[0047] Embodiment 5

[0048] The control circuit with the function of memorizing the polarity of the initial induction magnetic field according to the present invention includes an all-pole to south-pole single-pole control circuit. The input terminal of the all-pole to south-pole single-pole control circuit is connected to a south pole induction synchronous control circuit. The output terminal of the all-pole to south-pole single-pole control circuit is connected to a north pole induction synchronous control circuit. The output terminal of the north pole induction synchronous control circuit is respectively connected to an all-pole to north-pole single-pole control circuit and a judgment circuit. The output terminal of the south pole induction synchronous control circuit is connected to the judgment circuit. The south pole induction synchronous control circuit and the input terminal of the north pole induction synchronous control circuit are jointly connected to a synchronous control logic signal. The input terminal of the south pole induction synchronous control circuit is connected to a south pole induction signal. The input terminal of the north pole induction synchronous control circuit is connected to a north pole induction signal.

[0049] The south pole induction synchronous control circuit is the first flip-flop. The first flip-flop includes a first data input pin D1, a first clock input pin CLK1, a first reset pin RN1, and a first output pin Q1. The first data input pin D1 is connected to the south pole induction signal, the first clock input pin CLK1 is connected to the synchronous control logic signal, and the first reset pin RN1 is connected to the power-on reset signal.

[0050] The Arctic induction synchronous control circuit is the third flip-flop. The third flip-flop includes a third data input pin D3, a third clock input pin CLK3, a third reset pin RN3, and a third output pin Q3. The third data input pin D3 is connected to the Arctic induction signal, the third clock input pin CLK3 is connected to the synchronous control logic signal, and the first reset pin RN1 is connected to the power-on reset signal.

[0051] The full-pole to south-pole single-pole control circuit includes a second flip-flop. The second flip-flop includes a second data input pin D2, a second clock input pin CLK2, a second reset pin RN2, a second output pin Q2, and a first inverted output terminal QN1. The second data input pin D2 is grounded, the second clock input pin CLK2 is connected to the first output pin Q1, the first output pin Q1 is connected to an input terminal of a first NAND gate. The first NAND gate is a two-input NAND gate. The second reset pin RN2 is connected to an output terminal of a first NOR gate. The first NOR gate is a two-input NOR gate. One input terminal of the first NOR gate is connected to an output terminal of a first inverter. The input terminal of the first inverter is connected to the power-on reset signal. The output terminal of the first NAND gate is connected to an input terminal of a third inverter.

[0052] The full-pole to north-pole single-pole control circuit includes a fourth flip-flop. The fourth flip-flop includes a fourth data input pin D4, a fourth clock input pin CLK4, a fourth reset pin RN4, a fourth output pin Q4, and a second inverted output terminal QN2. The input terminal of the fourth reset pin RN4 is connected to an output terminal of a second NOR gate. The second NOR gate is a two-input NOR gate. One input terminal of the second NOR gate is connected to an output terminal of a second inverter. The input terminal of the second inverter is connected to the power-on reset signal. The other input terminal of the second NOR gate is connected to the second output pin Q2. The fourth clock input pin CLK4 is connected to the third output pin Q3. The third output pin Q3 is connected to an input terminal of a second NAND gate. The second NAND gate is a two-input NAND gate. The other input terminal of the second NAND gate is connected to the first inverted output terminal QN1. The output terminal of the second NAND gate is connected to an input terminal of a fourth inverter. The fourth data input pin D4 is grounded. The second inverted output terminal QN2 is connected to the input terminal of the first NAND gate.

[0053] Embodiment 6

[0054] The control circuit with the function of memorizing the polarity of the initial induction magnetic field of the present invention includes a full-pole to south-pole single-pole control circuit. The input end of the full-pole to south-pole single-pole control circuit is connected with a south-pole induction synchronization control circuit. The output end of the full-pole to south-pole single-pole control circuit is connected with a north-pole induction synchronization control circuit. The output end of the north-pole induction synchronization control circuit is respectively connected with a full-pole to north-pole single-pole control circuit and a judgment circuit. The output end of the south-pole induction synchronization control circuit is connected with the judgment circuit. The south-pole induction synchronization control circuit and the input end of the north-pole induction synchronization control circuit are jointly connected with a synchronization control logic signal. The input end of the south-pole induction synchronization control circuit is connected with a south-pole induction signal. The input end of the north-pole induction synchronization control circuit is connected with a north-pole induction signal.

[0055] The south-pole induction synchronization control circuit is a first flip-flop. The first flip-flop includes a first data input pin D1, a first clock input pin CLK1, a first reset pin RN1 and a first output pin Q1. The first data input pin D1 is connected with the south-pole induction signal. The first clock input pin CLK1 is connected with the synchronization control logic signal. The first reset pin RN1 is connected with a power-on reset signal.

[0056] The north-pole induction synchronization control circuit is a third flip-flop. The third flip-flop includes a third data input pin D3, a third clock input pin CLK3, a third reset pin RN3 and a third output pin Q3. The third data input pin D3 is connected with the north-pole induction signal. The third clock input pin CLK3 is connected with the synchronization control logic signal. The first reset pin RN1 is connected with the power-on reset signal.

[0057] The full-pole to south-pole single-pole control circuit includes a second flip-flop. The second flip-flop includes a second data input pin D2, a second clock input pin CLK2, a second reset pin RN2, a second output pin Q2 and a first inverted output end QN1. The second data input pin D2 is grounded. The second clock input pin CLK2 is connected with the first output pin Q1. The first output pin Q1 is connected with the input end of a first NAND gate. The first NAND gate is a two-input NAND gate. The second reset pin RN2 is connected with the output end of a first NOR gate. The first NOR gate is a two-input NOR gate. One input end of the first NOR gate is connected with the output end of a first inverter. The input end of the first inverter is connected with the power-on reset signal. The output end of the first NAND gate is connected with the input end of a third inverter.

[0058] The all-pole to north single-pole control circuit includes a fourth flip-flop. The fourth flip-flop includes a fourth data input pin D4, a fourth clock input pin CLK4, a fourth reset pin RN4, a fourth output pin Q4, and a second inverted output QN2. The input end of the fourth reset pin RN4 is connected to the output end of a second NOR gate. The second NOR gate is a two-input NOR gate. One input end of the second NOR gate is connected to the output end of a second inverter. The input end of the second inverter is connected to the power-on reset signal. The other input end of the second NOR gate is connected to the second output pin Q2. The fourth clock input pin CLK4 is connected to the third output pin Q3. The third output pin Q3 is connected to the input end of a second NAND gate. The second NAND gate is a two-input NAND gate. The other input end of the second NAND gate is connected to the first inverted output QN1. The output end of the second NAND gate is connected to the input end of a fourth inverter. The fourth data input pin D4 is grounded. The second inverted output QN2 is connected to the input end of a first NAND gate.

[0059] The judgment circuit is a two-input OR gate. The input ends of the two-input OR gate are respectively connected to the output ends of a third inverter and a fourth inverter.

[0060] The first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are all D flip-flops.

Claims

1. A control circuit with the function of memorizing the polarity of the initially induced magnetic field, characterized in that, It includes a full-pole to south-pole single-pole control circuit. The input end of the full-pole to south-pole single-pole control circuit is connected to a south-pole induction synchronization control circuit. The output end of the full-pole to south-pole single-pole control circuit is connected to a north-pole induction synchronization control circuit. The output end of the north-pole induction synchronization control circuit is respectively connected to a full-pole to north-pole single-pole control circuit and a judgment circuit. The output end of the south-pole induction synchronization control circuit is connected to the judgment circuit. The south-pole induction synchronization control circuit and the input end of the north-pole induction synchronization control circuit are jointly connected to a synchronization control logic signal. The input end of the south-pole induction synchronization control circuit is connected to a south-pole induction signal. The input end of the north-pole induction synchronization control circuit is connected to a north-pole induction signal; The south-pole induction synchronization control circuit is a first flip-flop. The first flip-flop includes a first data input pin D1, a first clock input pin CLK1, a first reset pin RN1, and a first output pin Q1. The first data input pin D1 is connected to the south-pole induction signal. The first clock input pin CLK1 is connected to the synchronization control logic signal. The first reset pin RN1 is connected to a power-on reset signal; The north-pole induction synchronization control circuit is a third flip-flop. The third flip-flop includes a third data input pin D3, a third clock input pin CLK3, a third reset pin RN3, and a third output pin Q3. The third data input pin D3 is connected to the north-pole induction signal. The third clock input pin CLK3 is connected to the synchronization control logic signal. The first reset pin RN1 is connected to the power-on reset signal; The full-pole to south-pole single-pole control circuit includes a second flip-flop. The second flip-flop includes a second data input pin D2, a second clock input pin CLK2, a second reset pin RN2, a second output pin Q2, and a first inverted output terminal QN1. The second data input pin D2 is grounded. The second clock input pin CLK2 is connected to the first output pin Q1. The first output pin Q1 is connected to the input end of a first NAND gate. The first NAND gate is a two-input NAND gate. The second reset pin RN2 is connected to the output end of a first NOR gate. The first NOR gate is a two-input NOR gate. One input end of the first NOR gate is connected to the output end of a first inverter. The input end of the first inverter is connected to the power-on reset signal. The output end of the first NAND gate is connected to the input end of a third inverter; The all-pole to north-pole single-pole control circuit includes a fourth flip-flop. The fourth flip-flop includes a fourth data input pin D4, a fourth clock input pin CLK4, a fourth reset pin RN4, a fourth output pin Q4, and a second inverted output QN2. The input end of the fourth reset pin RN4 is connected to the output end of a second NOR gate. The second NOR gate is a two-input NOR gate. One input end of the second NOR gate is connected to the output end of a second inverter. The input end of the second inverter is connected to the power-on reset signal. The other input end of the second NOR gate is connected to the second output pin Q2. The fourth clock input pin CLK4 is connected to the third output pin Q3. The third output pin Q3 is connected to an input end of a second NAND gate. The second NAND gate is a two-input NAND gate. The other input end of the second NAND gate is connected to the first inverted output QN1. The output end of the second NAND gate is connected to an input end of a fourth inverter. The fourth data input pin D4 is grounded. The second inverted output QN2 is connected to an input end of a first NAND gate; The judgment circuit is a two-input OR gate.

2. The control circuit with the function of memorizing the polarity of the initially induced magnetic field according to claim 1, characterized in that, The input ends of the two-input OR gate are respectively connected to the output end of a third inverter and the output end of a fourth inverter.

3. The control circuit with the function of memorizing the polarity of the initial induction magnetic field according to claim 2, characterized in that, The first flip-flop, the second flip-flop, the third flip-flop, and the fourth flip-flop are all D flip-flops.

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