High common mode transient suppression OOK modulation circuit based on output substrate modulation

Abstract

The invention discloses a high common-mode transient suppression OOK modulation circuit based on output substrate modulation, which is characterized in that a reset control circuit and a common-mode substrate modulation circuit are added on the basis of a traditional OOK modulation circuit, and the substrate potential of an NMOS (N-channel Metal Oxide Semiconductor) tube in a traditional OOK signal output driving phase inverter is changed from fixed grounding to OOK output common-mode voltage modulation. When common-mode coupling interference occurs on a differential OOK signal, the pull-down capability of the phase inverter NMOS tube is adjusted by adjusting the substrate voltage of the phase inverter NMOS tube, so that the overturning threshold voltage of the phase inverter can be kept unchanged, and the influence of common-mode transient coupling interference is counteracted and suppressed. The method can be widely applied to isolation system chips such as various digital isolators and isolation type driving chips.

Description

Technical Field

[0001] The invention relates to a high common mode transient suppression OOK modulation circuit based on output substrate modulation, belonging to the technical field of integrated circuits. Background Art

[0002] Driven by emerging industries such as smart grids, mobile communications, and new energy vehicles, power electronics application systems require further improvement in system efficiency, miniaturization, and increased functionality, such as server power management, battery chargers, and micro-inverters for solar farms. All of the above systems require the use of various digital isolators.

[0003] Figure 1 A schematic diagram of the circuit architecture of a capacitive isolation digital isolator in the prior art is given, including a TX receiving circuit, an OSC generating circuit, an OOK modulation circuit, a first driver, a second driver, an OOK demodulation circuit, and high-voltage capacitors CC1, CC2, CC3, and CC4. The dotted box on the left is the transmitting circuit TX, and the dotted box on the right is the receiving circuit RX. The input DI controls the transmitting circuit to generate a set of differential signals. The OOK modulation circuit in the transmitting circuit generates modulation signals D3 and D3N, which enter the first driver and the second driver respectively to generate OOK modulated transmission signals. The differential signals from the transmitting end are coupled to the receiving circuit through four high-voltage capacitors, and the output signal DO is obtained through signal demodulation. The transmitting circuit (TX) and the receiving circuit (RX) are each connected to a ground voltage V GND and V GND2 DI is the input of the capacitive isolator circuit and DO is its output.

[0004] Since the two ground voltages V GND and V GND2 There is usually a certain degree of common-mode transient noise between the two, which will cause errors in the signal during transmission. Figure 1 The interference waveform diagram of common mode transient noise is also given. GND2 It can quickly increase from 0V to 3KV, and then quickly decrease from 3KV to 0V. Under the interference of this common-mode transient noise, TCM will produce a 3V fluctuation. The peak error of TCM voltage will inevitably cause data errors in the receiving circuit. To this end, an OOK modulation circuit with high common-mode transient suppression characteristics is provided, which has important application value for improving digital isolator chips. Summary of the invention

[0005] The purpose of the present invention is to provide a high common-mode transient suppression OOK modulation circuit based on output substrate modulation to address the inevitable common-mode transient interference noise problem in the system application of digital isolator chips.

[0006] The high common-mode transient suppression OOK modulation circuit based on output substrate modulation provided by the present invention comprises a PMOS tube M1, an NMOS tube M2, a positive terminal transmission capacitor CC1, a PMOS tube M4, an NMOS tube M5, and a negative terminal transmission capacitor CC2, wherein a first inverter formed by the PMOS tube M1 and the NMOS tube M2 and a second inverter formed by the PMOS tube M4 and the NMOS tube M5 are inverters of the same size; and further comprises a reset control circuit and a common-mode substrate modulation circuit;

[0007] The input end of the reset control circuit is connected to the control signal input from the outside, including control signals C1, C2, C3, C4 and protection control signals S1, S2. The first output end of the reset control circuit outputs the reset control signal CT1, and the second output end of the reset control circuit outputs the reset control signal CT2. The control signal C1 is also connected to the second input end of the NAND gate NA1, the gate of the NMOS tube M3, and the gate of the NMOS tube M6. The first input end of the NAND gate NA1 is connected to the data signal D2. The output of the NAND gate NA1 is connected to the first input end of the NAND gate NA2, the second input end of the NAND gate NA2 is connected to the control signal C2, the output end of the NAND gate NA2 is connected to the first input end of the NAND gate NA3, the second input end of the NAND gate NA3 is connected to the reset control signal CT2, the output end of the NAND gate NA3 is connected to the input end of the inverter INV1, and the output end of the inverter INV1 is respectively connected to the first input end of the NAND gate NA4 and the first input end of the NAND gate NA5.

[0008] The OSC signal output by the OSC generating circuit is connected to the input end of the inverter INV3, and the output end of the inverter INV3 is respectively connected to the input end of the inverter INV4 and the input end of the inverter INV6; the output end of the inverter INV4 is connected to the second input end of the NAND gate NA4 through the inverter INV5; the output end of the inverter INV6 is connected to the second input end of the NAND gate NA5 through the inverter INV7 and the inverter INV8 in sequence;

[0009] The output end of the NAND gate NA4 is connected to the input end of the inverter INV2, and the output end of the inverter INV2 is connected to the gate of the PMOS tube M1 and the gate of the NMOS tube M2;

[0010] The output end of the NAND gate NA5 is connected to the input end of the inverter INV9, and the output end of the inverter INV9 is connected to the gate of the PMOS tube M4 and the gate of the NMOS tube M5;

[0011] The source of the PMOS tube M1 is connected to the substrate of the PMOS tube M1 and is also connected to the power supply voltage VCCL; the source of the PMOS tube M4 is connected to the substrate of the PMOS tube M4 and is also connected to the power supply voltage VCCL;

[0012] The drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2, and the output positive phase signal DP is connected to the left end of the positive end sending capacitor CC1 and an input end of the common mode substrate modulation circuit; the right end of the positive end sending capacitor CC1 outputs the output positive phase signal OP of the sending end circuit; the source of the NMOS tube M2 is connected to the drain of the NMOS tube M3, the substrate of the NMOS tube M2 is connected to the substrate of the NMOS tube M3, and is connected to the positive phase substrate modulation signal BP output by the common mode substrate modulation circuit;

[0013] The drain of the PMOS tube M4 is connected to the drain of the NMOS tube M5, and the output inverted signal DN is connected to the left end of the negative terminal sending capacitor CC2 and the other input end of the common mode substrate modulation circuit; the right end of the negative terminal sending capacitor CC2 outputs the output inverted signal ON of the sending end circuit; the source of the NMOS tube M5 is connected to the drain of the NMOS tube M6; the substrate of the NMOS tube M5 is connected to the substrate of the NMOS tube M6, and is connected to the inverted substrate modulation signal BN output by the common mode substrate modulation circuit;

[0014] The source of the NMOS tube M3 and the source of the NMOS tube M6 are connected to the ground signal GND.

[0015] When rising edge common mode transient coupling interference appears on the DP and DN signals as differential OOK signals, the common mode voltage of the DP and DN signals will increase, which is equivalent to enhancing the pull-up capability of the PMOS tube M1 and the PMOS tube M4, thereby increasing the flip threshold voltage of the first and second inverters; at this time, the positive substrate modulation signal BP and the negative substrate modulation signal BN output by the common mode substrate modulation circuit simultaneously generate a positive increasing voltage signal, reducing the turn-on voltage of the NMOS tube M2, the NMOS tube M3, the NMOS tube M5 and the NMOS tube M6, thereby enhancing the pull-down capability of the NMOS tube M2, the NMOS tube M3, the NMOS tube M5 and the NMOS tube M6, and the flip threshold voltage of the first and second inverters can remain unchanged, that is, the influence of the rising edge common mode transient coupling interference is offset and suppressed;

[0016] When falling-edge common-mode transient coupling interference appears on the DP and DN signals as differential OOK signals, the common-mode voltages of the DP and DN signals will decrease, which is equivalent to enhancing the pull-down capabilities of the NMOS tubes M2, M3, M5 and M6, thereby reducing the flip threshold voltages of the first and second inverters. At this time, the positive-phase substrate modulation signal BP and the negative-phase substrate modulation signal BN output by the common-mode substrate modulation circuit simultaneously generate a negatively decreasing voltage signal, increasing the turn-on voltages of the NMOS tubes M2, M3, M5 and M6, thereby reducing the pull-down capabilities of the NMOS tubes M2, M3, M5 and M6, balancing the equivalently increased pull-down capabilities of the NMOS tubes, and the flip threshold voltages of the first and second inverters can remain unchanged, that is, the influence of the falling-edge common-mode transient coupling interference is offset and suppressed.

[0017] Specifically, the reset control circuit includes: a control signal C1 connected to the input end of the inverter IN1, a control signal C2 connected to the input end of the inverter IN8, a control signal C3 connected to the first input end of the NAND gate NB5, and a control signal C4 connected to the input end of the inverter IN11;

[0018] The output end of the inverter IN1 is connected to the input end of the inverter IN2, and the output end of the inverter IN2 is connected to the first input end of the NAND gate NB1; the second input end of the NAND gate NB1, the second input end of the NAND gate NB3, the second input end of the NAND gate NB5, and the second input end of the NAND gate NB7 are connected to the protection control signal S1; the output end of the NAND gate NB1 is connected to the first input end of the NAND gate NB2, and the second input end of the NAND gate NB2, the second input end of the NAND gate NB4, the second input end of the NAND gate NB6, and the second input end of the NAND gate NB8 are connected to the protection control signal S2; the output end of the NAND gate NB2 is connected to the gate of the PMOS tube M8 and the gate of the NMOS tube M9 through the inverter IN3 and the inverter IN4 in sequence;

[0019] The output end of the inverter IN8 is connected to the first input end of the NAND gate NB3, the output end of the NAND gate NB3 is connected to the first input end of the NAND gate NB4, and the output end of the NAND gate NB4 is connected to the gate of the NMOS tube M10 through the inverter IN9 and the inverter IN10 in sequence;

[0020] The output end of the NAND gate NB5 is connected to the first input end of the NAND gate NB6, and the output end of the NAND gate NB6 is connected to the gate of the NMOS tube M11 and the gate of the NMOS tube M12;

[0021] The source of the PMOS tube M8 is connected to the power supply voltage VCCL, the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M9 and the input terminal of the inverter IN5, and outputs a reset control signal CT1; the source of the NMOS tube M9 is connected to the drain of the NMOS tube M10, the source of the NMOS tube M10 is connected to the drain of the NMOS tube M11, the source of the NMOS tube M11 is connected to the drain of the NMOS tube M12, and the source of the NMOS tube M12 is connected to the ground signal GND;

[0022] The output end of the inverter IN5 is connected to the first input end of the NAND gate NB9 through the inverter IN6 and the inverter IN7 in sequence;

[0023] The output end of the inverter IN11 is connected to the first input end of the NAND gate NB7 through the inverter IN12, the output end of the NAND gate NB7 is connected to the first input end of the NAND gate NB8, and the output end of the NAND gate NB8 is connected to the second input end of the NAND gate NB9 through the inverter IN13 and the inverter IN14 in sequence;

[0024] The output terminal of the NAND gate NB9 outputs a reset control signal CT2.

[0025] Specifically, the common-mode substrate modulation circuit includes: a common-mode detection circuit, a first N-tube substrate modulation signal generating circuit, and a second N-tube substrate modulation signal generating circuit. The common-mode detection circuit receives a positive-phase signal DP, a negative-phase signal DN, and a reference voltage Vrn, and outputs a common-mode control signal D1 after common-mode detection processing; the input ends of the first N-tube substrate modulation signal generating circuit are respectively connected to the common-mode control signal D1, the reset control signal CT1, and the reset control signal CT2, and the first N-tube substrate modulation signal generating circuit outputs a positive-phase substrate modulation signal BP; the input ends of the second N-tube substrate modulation signal generating circuit are respectively connected to the common-mode control signal D1, the reset control signal CT1, and the reset control signal CT2, and the second N-tube substrate modulation signal generating circuit outputs a negative-phase substrate modulation signal BN;

[0026] The common-mode detection circuit detects the positive-phase signal DP and the negative-phase signal DN to obtain a real-time common-mode voltage Vcm, and compares the voltage with the internal reference voltage Vrn to determine whether the real-time common-mode voltage Vcm exceeds a normal threshold, and then generates a common-mode control signal D1; when the real-time common-mode voltage Vcm exceeds Vrn, the common-mode control signal D1 will be connected to the real-time common-mode voltage Vcm, the first N-transistor substrate modulation signal generating circuit and the second N-transistor substrate modulation signal generating circuit start substrate compensation, and the positive-phase substrate modulation signal BP and the negative-phase substrate modulation signal BN will output a compensation voltage related to the real-time common-mode voltage Vcm; when the real-time common-mode voltage Vcm does not exceed Vrn, the positive-phase substrate modulation signal BP and the negative-phase substrate modulation signal BN will output a fixed voltage.

[0027] Specifically, the common mode detection circuit includes: the upper end of the capacitor C51 is connected to the upper end of the resistor R51, and is connected to the input positive phase signal DP, the lower end of the capacitor C52 is connected to the lower end of the resistor R52, and is connected to the input negative phase signal DN; the lower end of the capacitor C51 is connected to the lower end of the resistor R51, the upper end of the capacitor C52, and the upper end of the resistor R52, to generate a real-time common mode voltage Vcm, which is connected to the gate of the PMOS tube M52, the source of the PMOS tube M58, and the source of the NMOS tube M59;

[0028] The source of the PMOS tube M52 is connected to the source of the PMOS tube M53 and the drain of the PMOS tube M51; the gate of the PMOS tube M51 is connected to the gate of the PMOS tube M56 and is connected to the first bias signal Vb1; the source of the PMOS tube M51 is connected to the source of the PMOS tube M56 and is connected to the power supply voltage VCCL; the gate of the PMOS tube M53 is connected to the reference voltage Vrn; the drain of the PMOS tube M52 is connected to the drain of the NMOS tube M54, the gate of the NMOS tube M54, and the gate of the NMOS tube M55; the drain of the PMOS tube M53 is connected to the drain of the NMOS tube M55 and the gate of the NMOS tube M57; the drain of the PMOS tube M56 is connected to the drain of the NMOS tube M57, the upper end of the resistor R53, the upper end of the capacitor C53, the gate of the PMOS tube M58, and the input end of the inverter INV51; the drain of the PMOS tube M58 is connected to the drain of the NMOS tube M59, and outputs the common mode control signal D1;

[0029] The source of the NMOS tube M54, the source of the NMOS tube M55, the source of the NMOS tube M57, the lower end of the resistor R53, and the lower end of the capacitor C53 are connected to the ground signal GND;

[0030] The circuit composed of capacitor C51, capacitor C52, resistor R51 and resistor R52 detects the positive phase signal DP and the negative phase signal DN to obtain the real-time common mode voltage Vcm; PMOS tube M51, PMOS tube M52, PMOS tube M53, NMOS tube M54, NMOS tube M55, PMOS tube M56 and NMOS tube M57 constitute a two-stage comparator, and the output signal SN of the two-stage comparator is delayed and filtered via resistor R53 and capacitor C53; PMOS tube M58 and NMOS tube M59 constitute a transmission gate, and the signal SN and the output of inverter INV51 are used as the transmission gate control signal to finally generate the common mode control signal D1.

[0031] The first N-tube substrate modulation signal generating circuit and the second N-tube substrate modulation signal generating circuit are implemented by using the same N-tube substrate modulation signal generating circuit, and the circuit structure includes:

[0032] The source of the PMOS tube M61, the source of the PMOS tube M65, and the source of the PMOS tube M67 are connected to the power supply voltage VCCL; the gate of the PMOS tube M61, the gate of the PMOS tube M62, the gate of the NMOS tube M63, the gate of the PMOS tube M65, and the gate of the PMOS tube M66 are connected to the reset control signal CT2; the drain of the PMOS tube M61 is connected to the source of the PMOS tube M62; the drain of the PMOS tube M62 is connected to the drain of the NMOS tube M63, the drain of the PMOS tube M66, the gate of the NMOS tube M64, and the gate of the NMOS tube M70; the source of the NMOS tube M63 is connected to the upper end of the resistor R61, the drain of the NMOS tube M64, the source of the NMOS tube M68, the upper end of the resistor R62, and the drain of the NMOS tube M71, and outputs the inverted substrate modulation signal BN;

[0033] The drain of the PMOS tube M65 is connected to the source of the PMOS tube M66, and the gate of the PMOS tube M67, the gate of the NMOS tube M68, and the gate of the NMOS tube M69 are commonly connected to the reset control signal CT1; the drain of the PMOS tube M67 is connected to the drain of the NMOS tube M68 and the gate of the NMOS tube M71, the lower end of the resistor R62 is connected to the drain of the NMOS tube M69, and the source of the NMOS tube M69 is connected to the drain of the NMOS tube M70 and the common-mode control signal D1; the lower end of the resistor R61, the source of the NMOS tube M64, the source of the NMOS tube M70, and the source of the NMOS tube M71 are commonly connected to the ground signal GND.

[0034] The advantages of the present invention are as follows: based on the traditional OOK modulation circuit, the present invention changes the substrate potential of the NMOS tube in the traditional OOK signal output driving inverter from fixed grounding to modulation by the OOK output common mode voltage. When common mode coupling interference appears on the differential OOK signals DP and DN, by adjusting the substrate voltage of the inverter NMOS tube, the pull-down capability thereof can be adjusted, and the flip threshold voltage of the inverter can remain unchanged, so that the influence of the common mode transient coupling interference is offset and suppressed. The present invention can be widely used in various types of high voltage insulation isolation gate driver chips and data isolators. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of a typical capacitive isolation digital isolator architecture.

[0036] Figure 2 This is a commonly used driver circuit implementation for OOK modulators.

[0037] Figure 3 The invention provides a high common-mode transient suppression OOK modulation circuit based on output substrate modulation.

[0038] Figure 4 This is an implementation method of the reset control circuit of the present invention.

[0039] Figure 5 This is an implementation of the common mode substrate modulation circuit of the present invention.

[0040] Figure 6 This is an implementation example of the common mode detection circuit of the present invention.

[0041] Figure 7 This is an implementation of the N-tube substrate modulation signal generating circuit of the present invention.

[0042] Figure 8 This is the application effect of the present invention in a digital isolator.

[0043] Fig. 9 This is the application effect of the present invention in the gate drive circuit. DETAILED DESCRIPTION

[0044] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0045] Figure 2 This is a common driver circuit implementation for OOK modulators. Figure 1 The first driver and the second driver are usually implemented by a driver circuit composed of the same cascade inverter. The inverter composed of the PMOS tube M1 and the NMOS tube M2, and the inverter composed of the PMOS tube M4 and the NMOS tube M5 are usually inverters of the same size, and the substrate of the PMOS tube is connected to the source power supply VCCL, and the substrate of the NMOS tube is connected to the source ground GND.

[0046] When the receiving circuit (RX) generates common-mode transient interference, it will be coupled to the differential OOK signal DP and DN signal through the positive terminal transmission capacitor CC1 and the negative terminal transmission capacitor CC2 to perform signal superposition, such as Figure 2 As shown in the waveform. When rising common-mode coupling interference appears on the differential OOK signals DP and DN, it is equivalent to increasing the pull-up capability of the PMOS tubes M1 and M4, which will increase the flip threshold voltage of the two inverters; when falling common-mode coupling interference appears on the differential OOK signals DP and DN, it is equivalent to increasing the pull-down capability of the NMOS tubes M2 and M5, which will reduce the flip threshold voltage of the two inverters; when the flip threshold voltage of the two inverters is reduced or increased to a certain level, the differential OOK signals DP and DN output by the two inverters will have waveform distortion and bit errors.

[0047] In order to suppress the influence of common-mode transient interference generated by a receiving end circuit (RX) on differential OOK signals DP and DN, the present invention provides a dynamic compensation measure. When rising-edge common-mode transient coupling interference appears on differential OOK signals DP and DN signals to increase the flip threshold voltage of two inverters, by enhancing the pull-down capability of NMOS tubes M2 and NMOS tubes M5, the flip threshold voltage of the two inverters can remain unchanged, so that the influence of rising-edge common-mode transient coupling interference is offset and suppressed. When falling-edge common-mode transient coupling interference appears on differential OOK signals DP and DN signals to reduce the flip threshold voltage of the two inverters, the substrate voltage of NMOS tubes M2 and NMOS tubes M5 is adjusted to reduce their pull-down capability, and the equivalently increased pull-down capability of NMOS tubes M2 and NMOS tubes M5 is balanced, and the flip threshold voltage of the two inverters can remain unchanged, so that the influence of falling-edge common-mode transient coupling interference is offset and suppressed.

[0048] The specific implementation of the high common mode transient suppression OOK modulation circuit based on output substrate modulation designed by the present invention is as follows: Figure 3 As shown, the circuit includes: NAND gate NA1, NAND gate NA2, NAND gate NA3, NAND gate NA4, NAND gate NA5, inverter INV1, inverter INV2, inverter INV3, inverter INV4, inverter INV5, inverter INV6, inverter INV7, inverter INV8, inverter INV9, PMOS tube M1, NMOS tube M2, NMOS tube M3, PMOS tube M4, NMOS tube M5, NMOS tube M6, positive terminal sending capacitor CC1, negative terminal sending capacitor CC2, reset control circuit 1 and common mode substrate modulation circuit 2.

[0049] The input end of the reset control circuit 1 is connected to an external input control signal, including control signals C1, C2, C3, C4 and protection control signals S1, S2. The first output end of the reset control circuit 1 outputs a reset control signal CT1, and the second output end of the reset control circuit 1 outputs a reset control signal CT2. The first input end of the NAND gate NA1 is connected to the data signal D2, the second input end of the NAND gate NA1, the gate of the NMOS tube M3, and the gate of the NMOS tube M6 are commonly connected to the control signal C1, the output of the NAND gate NA1 is connected to the first input end of the NAND gate NA2, the second input end of the NAND gate NA2 is connected to the control signal C2, the output end of the NAND gate NA2 is connected to the first input end of the NAND gate NA3, the second input end of the NAND gate NA3 is connected to the reset control signal CT2, the output end of the NAND gate NA3 is connected to the input end of the inverter INV1, the output of the inverter INV1 is connected to the first input end of the NAND gate NA4 and the first input end of the NAND gate NA5; the second input end of the NAND gate NA4 is connected to the output end of the inverter INV5; the output of the NAND gate NA4 is connected to the input end of the inverter INV2, and the output end of the inverter INV2 is connected to the gate of the PMOS tube M1 and the gate of the NMOS tube M2.

[0050] The input end of the inverter INV3 is connected to the OSC signal output by the OSC generating circuit, the output end of the inverter INV3 is connected to the input end of the inverter INV4 and the input end of the inverter INV6; the output end of the inverter INV4 is connected to the input end of the inverter INV5. The output end of the inverter INV6 is connected to the input end of the inverter INV7, the output end of the inverter INV7 is connected to the input end of the inverter INV8, the output end of the inverter INV8 is connected to the second input end of the NAND gate NA5, the output end of the NAND gate NA5 is connected to the input end of the inverter INV9, and the output end of the inverter INV9 is connected to the gate of the PMOS tube M4 and the gate of the NMOS tube M5.

[0051] The source of the PMOS tube M1 is connected to the substrate of the PMOS tube M1, the source of the PMOS tube M4, the substrate of the PMOS tube M4, and is connected to the power supply voltage VCCL signal. The drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2 and the left end of the positive end transmission capacitor CC1, and serves as the input positive phase signal DP of the common mode substrate modulation circuit 2; the right end of the positive end transmission capacitor CC1 generates the output positive phase signal OP of the TX circuit.

[0052] The source of the NMOS tube M2 is connected to the drain of the NMOS tube M3, the substrate of the NMOS tube M2 is connected to the substrate of the NMOS tube M3, and is connected to the positive phase substrate modulation signal BP output by the common mode substrate modulation circuit 2; the source of the NMOS tube M3 is connected to the source of the NMOS tube M6, and is connected to the ground signal GND.

[0053] The drain of the PMOS tube M4 is connected to the drain of the NMOS tube M5 and the left end of the negative terminal transmission capacitor CC2, and serves as the input inverted signal DN of the common mode substrate modulation circuit 2; the right end of the negative terminal transmission capacitor CC2 generates the output inverted signal ON of the TX circuit.

[0054] The source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M6 , the substrate of the NMOS transistor M5 is connected to the substrate of the NMOS transistor M6 , and is connected to the inverted substrate modulation signal BN output by the common mode substrate modulation circuit 2 .

[0055] Figure 3 Circuit in Figure 2 Based on the basic inverter given, a reset control circuit 1 and a common-mode substrate modulation circuit 2 are added. PMOS tube M1, NMOS tube M2, inverter INV2, PMOS tube M4, NMOS tube M5, and the third inverter INV9 are Figure 2 The basic inverter driving circuit shown. The first inverter formed by the PMOS tube M1 and the NMOS tube M2, and the second inverter formed by the PMOS tube M4 and the NMOS tube M5 are inverters of the same size. In the present invention, at the lower end of the inverter formed by the PMOS tube M1 and the NMOS tube M2, the source end of the NMOS tube M2 is added with an NMOS tube M3, and the substrate potentials of M2 and M3 are simultaneously connected to the output positive substrate modulation signal BP; at the lower end of the inverter formed by the PMOS tube M4 and the NMOS tube M5, the source end of the NMOS tube M5 is added with an NMOS tube M6, and the substrate potentials of M5 and M6 are simultaneously connected to the output negative substrate modulation signal BN.

[0056] When rising edge common mode transient coupling interference appears on the differential OOK signals DP and DN, the common mode voltage of the DP and DN signals will increase, which is equivalent to the enhancement of the pull-up capability of the PMOS tube M1 and the PMOS tube M4, thereby increasing the flip threshold voltage of the first and second inverters; if the common mode substrate modulation circuit 2 outputs the positive substrate modulation signal BP and the output reverse substrate modulation signal BN at this time and simultaneously generates a positive increasing voltage signal, the turn-on voltage of the NMOS tube M2, the NMOS tube M3, the NMOS tube M5 and the NMOS tube M6 can be reduced, thereby enhancing the pull-down capability of the NMOS tube M2, the NMOS tube M3, the NMOS tube M5 and the NMOS tube M6, and the flip threshold voltage of the two inverters can remain unchanged, so that the influence of the rising edge common mode transient coupling interference is offset and suppressed.

[0057] When falling-edge common-mode transient coupling interference appears on the differential OOK signals DP and DN, the common-mode voltage of the DP and DN signals will decrease, which is equivalent to enhancing the pull-down capabilities of the NMOS tubes M2, M3, M5 and M6, thereby reducing the flip threshold voltages of the first and second inverters. If the common-mode substrate modulation circuit 2 outputs the positive substrate modulation signal BP and the negative substrate modulation signal BN at this time and simultaneously generates a negative decreasing voltage signal, the turn-on voltages of the NMOS tubes M2, M3, M5 and M6 can be increased, thereby reducing the pull-down capabilities of the NMOS tubes M2, M3, M5 and M6, and balancing the equivalent increased pull-down capabilities of the NMOS tubes. The flip threshold voltages of the two inverters can remain unchanged, so that the influence of the falling-edge common-mode transient coupling interference is offset and suppressed.

[0058] In addition to the above functions, Figure 3 The circuit is added with a reset control circuit 1, which turns off the circuit when the circuit state is abnormal. The control signal C1, the control signal C2, the control signal C3, the control signal C4, the protection control signal S1, and the protection control signal S2 are all control signals input from the outside.

[0059] Figure 4 This is an implementation mode of the reset control circuit 1 of the present invention. The circuit includes: inverter IN1, inverter IN2, inverter IN3, inverter IN4, inverter IN5, inverter IN6, inverter IN7, inverter IN8, inverter IN9, inverter IN10, inverter IN11, inverter IN12, inverter IN13, inverter IN14, NAND gate NB1, NAND gate NB2, NAND gate NB3, NAND gate NB4, NAND gate NB5, NAND gate NB6, NAND gate NB7, NAND gate NB8, NAND gate NB9, PMOS tube M8, NMOS tube M9, NMOS tube M10, NMOS tube M11, NMOS tube M12.

[0060] The input end of the inverter IN1 is connected to the control signal C1; the output end of the inverter IN1 is connected to the input end of the inverter IN2; the output end of the inverter IN2 is connected to the first input end of the NAND gate NB1; the second input end of the NAND gate NB1, the second input end of the NAND gate NB3, the second input end of the NAND gate NB5, and the second input end of the NAND gate NB7 are commonly connected to the protection control signal S1.

[0061] The output of NAND gate NB1 is connected to the first input of NAND gate NB2; the second inputs of NAND gate NB2, NAND gate NB4, NAND gate NB6 and NAND gate NB8 are commonly connected to the protection control signal S2.

[0062] The output end of the NAND gate NB2 is connected to the input end of the inverter IN3, the output end of the inverter IN3 is connected to the input end of the inverter IN4, the output end of the inverter IN4 is connected to the gate of the PMOS tube M8 and the gate of the NMOS tube M9; the source of the PMOS tube M8 is connected to the internal power supply voltage VCCL of the TX chip; the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M9, generates a reset control signal CT1, and is connected to the input end of the inverter IN5, the output end of the inverter IN5 is connected to the input end of the inverter IN6, the output end of the inverter IN6 is connected to the input end of the inverter IN7, and the output end of the inverter IN7 is connected to the first input end of the NAND gate NB9.

[0063] The input end of the inverter IN8 is connected to the control signal C2; the output end of the inverter IN8 is connected to the first input end of the NAND gate NB3, the output end of the NAND gate NB3 is connected to the first input end of the NAND gate NB4, the output end of the NAND gate NB4 is connected to the input end of the inverter IN9, the output end of the inverter IN9 is connected to the input end of the inverter IN10, and the output end of the inverter IN10 is connected to the gate of the NMOS tube M10; the source of the NMOS tube M9 is connected to the drain of the NMOS tube M10; the source of the NMOS tube M10 is connected to the drain of the NMOS tube M11; the source of the NMOS tube M11 is connected to the drain of the NMOS tube M12, and the source of the NMOS tube M12 is connected to the ground signal GND.

[0064] A first input terminal of the NAND gate NB5 is connected to the control signal C3 , an output terminal of the NAND gate NB5 is connected to a first input terminal of the NAND gate NB6 , and an output terminal of the NAND gate NB6 is connected to the gates of the NMOS transistor M11 and the NMOS transistor M12 .

[0065] The input end of the inverter IN11 is connected to the control signal C4; the output end of the inverter IN11 is connected to the input end of the inverter IN12, the output end of the inverter IN12 is connected to the first input end of the NAND gate NB7, the output end of the NAND gate NB7 is connected to the first input end of the NAND gate NB8, the output end of the NAND gate NB8 is connected to the input end of the inverter IN13, the output end of the inverter IN13 is connected to the input end of the inverter IN14, and the output end of the inverter IN14 is connected to the second input end of the NAND gate NB9.

[0066] The output terminal of the NAND gate NB9 outputs a reset control signal CT2.

[0067] When the circuit is working normally, the protection control signals S1 and S2 are usually 1, and the control signals C1, C2, C3, and C4 are usually high level 1, so the output reset control signals CT1 and CT2 are low level 0. When the control signals C1, C2, C3, C4, the protection control signal S1, and the protection control signal S2 are all high level 1 at the same time, the reset control signals CT1 and CT2 are low level 0.

[0068] Figure 5 This is an implementation of the common-mode substrate modulation circuit 2 of the present invention. The circuit includes: a common-mode detection circuit 21, a first N-tube substrate modulation signal generation circuit 22, and a second N-tube substrate modulation signal generation circuit 23. The common-mode detection circuit 21 first receives a positive-phase signal DP, a negative-phase signal DN, and a reference voltage Vrn, and obtains a common-mode control signal D1 after common-mode detection processing. The common-mode control signal D1, the reset control signal CT1, and the reset control signal CT2 are input to the first N-tube substrate modulation signal generation circuit 22 to obtain a positive-phase substrate modulation signal BP. The common-mode control signal D1, the reset control signal CT1, and the reset control signal CT2 are input to the second N-tube substrate modulation signal generation circuit 23 to obtain a negative-phase substrate modulation signal BN.

[0069] Figure 5 In the circuit shown, the common mode detection circuit 21 first detects the positive phase signal DP and the negative phase signal DN to obtain the real-time common mode voltage Vcm, and compares the voltage with the internal reference voltage Vrn to determine whether the real-time common mode voltage Vcm exceeds the normal threshold, and then generates the common mode control signal D1; then the common mode control signal D1 and the output reset control signals CT1 and CT2 together control the first N-transistor substrate modulation signal generating circuit 22 and the second N-transistor substrate modulation signal generating circuit 23, respectively, to obtain the positive phase substrate modulation signal BP and the negative phase substrate modulation signal BN. When the real-time common mode voltage Vcm exceeds the normal threshold Vrn, the common mode control signal D1 will be connected to the real-time common mode voltage Vcm, the first N-transistor substrate modulation signal generating circuit 22 and the second N-transistor substrate modulation signal generating circuit 23 start substrate compensation, and the positive phase substrate modulation signal BP and the negative phase substrate modulation signal BN will output the compensation voltage related to the real-time common mode voltage Vcm; when the real-time common mode voltage Vcm does not exceed the normal threshold Vrn, the positive phase substrate modulation signal BP and the negative phase substrate modulation signal BN will output a fixed voltage.

[0070] Figure 6 for Figure 5Implementation of the common mode detection circuit 21. The circuit includes: capacitor C51, capacitor C52, capacitor C53, resistor R51, resistor R52, resistor R53, PMOS tube M51, PMOS tube M52, PMOS tube M53, NMOS tube M54, NMOS tube M55, PMOS tube M56, NMOS tube M57, PMOS tube M58, NMOS tube M59, and inverter INV51.

[0071] The upper end of the capacitor C51 is connected to the upper end of the resistor R51 and is connected to the input positive phase signal DP, and the lower end of the capacitor C52 is connected to the lower end of the resistor R52 and is connected to the input negative phase signal DN; the lower end of the capacitor C51 is connected to the lower end of the resistor R51, the upper end of the capacitor C52, and the upper end of the resistor R52 to generate a real-time common mode voltage Vcm, which is connected to the gate of the PMOS tube M52, the source of the PMOS tube M58, and the source of the NMOS tube M59.

[0072] The source of the PMOS tube M52 is connected to the source of the PMOS tube M53 and the drain of the PMOS tube M51; the gate of the PMOS tube M51 is connected to the gate of the PMOS tube M56 and is connected to the first bias signal Vb1; the source of the PMOS tube M51 is connected to the source of the PMOS tube M56 and is connected to the internal power supply voltage VCCL signal of the TX chip; the gate of the PMOS tube M53 is connected to the reference voltage signal Vrn; the drain of the PMOS tube M52 is connected to the drain of the NMOS tube M54, the gate of the NMOS tube M54, and the gate of the NMOS tube M55; the source of the NMOS tube M54, the NMOS tube M56, and the NMOS tube M55 are connected. The source of the OS transistor M55, the source of the NMOS transistor M57, the lower end of the resistor R53, and the lower end of the capacitor C53 are all connected to the ground signal GND of the TX chip; the drain of the PMOS transistor M53 is connected to the drain of the NMOS transistor M55 and the gate of the NMOS transistor M57; the drain of the PMOS transistor M56 is connected to the drain of the NMOS transistor M57, the upper end of the resistor R53, the upper end of the capacitor C53, the gate of the PMOS transistor M58, and the input end of the inverter INV51; the drain of the PMOS transistor M58 is connected to the drain of the NMOS transistor M59 and is connected to the common-mode control signal D1 output by the common-mode detection circuit 21.

[0073] Figure 6In the common-mode detection circuit 21 shown, capacitor C51, capacitor C52, capacitor C53, resistor R51, and resistor R52 are common-mode detection resistors and capacitors, which detect and sum the input positive-phase signal DP and the input negative-phase signal DN, and obtain a real-time common-mode voltage Vcm; PMOS tube M51, PMOS tube M52, PMOS tube M53, NMOS tube M54, NMOS tube M55, PMOS tube M56, and NMOS tube M57 constitute a two-stage comparator, and the output SN of the two-stage comparator is connected to resistor R53 and capacitor C53 for delay filtering; PMOS tube M58 and NMOS tube M59 constitute a transmission gate, and SN and the output of inverter INV51 are used as transmission gate control signals to finally generate a common-mode control signal D1.

[0074] Figure 5 The first N-tube substrate modulation signal generating circuit 22 and the second N-tube substrate modulation signal generating circuit 23 are both implemented by the same N-tube substrate modulation signal generating circuit. Figure 7 This is an implementation of the N-tube substrate modulation signal generating circuit of the present invention. The N-tube substrate modulation signal generating circuit includes: PMOS tube M61, PMOS tube M62, NMOS tube M63, NMOS tube M64, PMOS tube M65, PMOS tube M66, PMOS tube M67, NMOS tube M68, NMOS tube M69, NMOS tube M70, NMOS tube M71, resistor R61, and resistor R62.

[0075] The source of the PMOS tube M61 is connected to the source of the PMOS tube M65 and the source of the PMOS tube M67, and is connected to the internal power supply voltage VCCL signal of the TX chip; the gate of the PMOS tube M61 is connected to the gate of the PMOS tube M62, the gate of the NMOS tube M63, the gate of the PMOS tube M65, and the gate of the PMOS tube M66, and is connected to the reset control signal CT2; the drain of the PMOS tube M61 is connected to the source of the PMOS tube M62; the drain of the PMOS tube M62 is connected to the drain of the NMOS tube M63, the drain of the PMOS tube M66, the gate of the NMOS tube M64, and the gate of the NMOS tube M70; the source of the NMOS tube M63 is connected to the upper end of the resistor R61, the drain of the NMOS tube M64, the source of the NMOS tube M68, the upper end of the resistor R62, and the drain of the NMOS tube M71, and outputs the inverted substrate modulation signal BN.

[0076] The lower end of the resistor R61, the source of the NMOS tube M64, the source of the NMOS tube M70, and the source of the NMOS tube M71 are connected to the ground signal GND. The drain of the PMOS tube M65 is connected to the source of the PMOS tube M66; the gate of the PMOS tube M67 is connected to the gate of the NMOS tube M68, the gate of the NMOS tube M69, and is connected to the reset control signal CT1.

[0077] The drain of the PMOS tube M67 is connected to the drain of the NMOS tube M68 and the gate of the NMOS tube M71; the lower end of the resistor R62 is connected to the drain of the NMOS tube M69; the source of the NMOS tube M69 is connected to the drain of the NMOS tube M70 and is connected to the common mode control signal D1 output by the common mode detection circuit 21.

[0078] Figure 7 The circuit shown outputs the inverted substrate modulation signal BN under the control of the common mode control signal D1, the output reset control signals CT1 and CT2. As mentioned above, when the real-time common mode voltage Vcm exceeds the normal threshold value Vrn, the common mode control signal D1 will be connected to the real-time common mode voltage Vcm, at this time CT1 and CT2 are both 1, then the output inverted substrate modulation signal BN of the N-tube substrate modulation signal generating circuit will output a compensation voltage whose phase completely follows the real-time common mode voltage Vcm, but whose amplitude is amplified in the same phase; when the real-time common mode voltage Vcm does not exceed the normal threshold value Vrn, at this time CT1 and CT2 are both 0, then the output inverted substrate modulation signal BN will output a fixed voltage and be reset to 0 by the NMOS tube M71.

[0079] use Figure 7 After the circuit shown, when rising edge common mode transient coupling interference appears on the differential OOK signals DP and DN, the real-time common mode voltage Vcm increases, which is equivalent to the enhancement of the pull-up capability of the PMOS tubes M1 and M4. At this time, the positive substrate modulation signal BP and the negative substrate modulation signal BN of the common mode substrate modulation circuit 2 simultaneously output a voltage signal that increases positively compared with the real-time common mode voltage Vcm, thereby enhancing the pull-down capability of the NMOS tubes M2, M3, M5 and M6. Then, the flip threshold voltages of the two inverters can remain unchanged, so that the influence of the rising edge common mode transient coupling interference is offset and suppressed.

[0080] Figure 8 This is an implementation case of the application of the present invention in a digital isolator. The transmitter signal modulation module in this case can adopt the high common mode transient suppression OOK modulation circuit scheme of the present invention to transmit digital data through high voltage isolation capacitors. The transmitter sends a high frequency carrier through the isolation capacitor to represent a digital state, and does not send a signal to represent another digital state. The receiver demodulates the signal after signal conditioning and generates an output through a buffer stage.

[0081] Fig. 9 This is an application example of the present invention in a dual-channel gate isolation type driver. The high common-mode transient suppression OOK modulation circuit scheme described in the present invention is used to achieve Fig. 9The MOD (modulation and demodulation module circuit) in the device transmits digital data through high-voltage isolation capacitors. The isolated drive targets include various types of transistors including SiC MOSFET.

[0082] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A high common mode transient suppression OOK modulation circuit based on output substrate modulation includes a PMOS tube M1, an NMOS tube M2, a positive terminal transmission capacitor CC1, a PMOS tube M4, an NMOS tube M5, and a negative terminal transmission capacitor CC2, wherein: It also includes a reset control circuit (1) and a common mode substrate modulation circuit (2), The input end of the reset control circuit (1) is connected to an external input control signal, including control signals C1, C2, C3, C4 and protection control signals S1, S2; the first output end of the reset control circuit (1) outputs a reset control signal CT1, and the second output end of the reset control circuit (1) outputs a reset control signal CT2; the control signal C1 is also connected to the second input end of the NAND gate NA1, the gate of the NMOS tube M3, and the gate of the NMOS tube M6; the first input end of the NAND gate NA1 is connected to the data signal D2; the output of the NAND gate NA1 is connected to the first input end of the NAND gate NA2, the second input end of the NAND gate NA2 is connected to the control signal C2, the output end of the NAND gate NA2 is connected to the first input end of the NAND gate NA3, the second input end of the NAND gate NA3 is connected to the reset control signal CT2, the output end of the NAND gate NA3 is connected to the input end of the inverter INV1, and the output end of the inverter INV1 is respectively connected to the first input end of the NAND gate NA4 and the first input end of the NAND gate NA5; The OSC signal output by the OSC generating circuit is connected to the input end of the inverter INV3, and the output end of the inverter INV3 is respectively connected to the input end of the inverter INV4 and the input end of the inverter INV6; the output end of the inverter INV4 is connected to the second input end of the NAND gate NA4 through the inverter INV5; the output end of the inverter INV6 is connected to the second input end of the NAND gate NA5 through the inverter INV7 and the inverter INV8 in sequence; The output end of the NAND gate NA4 is connected to the input end of the inverter INV2, and the output end of the inverter INV2 is connected to the gate of the PMOS tube M1 and the gate of the NMOS tube M2; The output end of the NAND gate NA5 is connected to the input end of the inverter INV9, and the output end of the inverter INV9 is connected to the gate of the PMOS tube M4 and the gate of the NMOS tube M5; The source of the PMOS tube M1 is connected to the substrate of the PMOS tube M1 and is also connected to the power supply voltage VCCL; the source of the PMOS tube M4 is connected to the substrate of the PMOS tube M4 and is also connected to the power supply voltage VCCL; The drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2, and the output positive phase signal DP is connected to the left end of the positive end sending capacitor CC1 and an input end of the common mode substrate modulation circuit (2); the right end of the positive end sending capacitor CC1 outputs the output positive phase signal OP of the sending end circuit; the source of the NMOS tube M2 is connected to the drain of the NMOS tube M3, the substrate of the NMOS tube M2 is connected to the substrate of the NMOS tube M3, and is connected to the positive phase substrate modulation signal BP output by the common mode substrate modulation circuit (2); The drain of the PMOS tube M4 is connected to the drain of the NMOS tube M5, and the output inverted signal DN is connected to the left end of the negative end sending capacitor CC2 and the other input end of the common mode substrate modulation circuit (2); the right end of the negative end sending capacitor CC2 outputs the output inverted signal ON of the sending end circuit; the source of the NMOS tube M5 is connected to the drain of the NMOS tube M6; the substrate of the NMOS tube M5 is connected to the substrate of the NMOS tube M6, and is connected to the inverted substrate modulation signal BN output by the common mode substrate modulation circuit (2); The source of the NMOS tube M3 and the source of the NMOS tube M6 are connected to the ground signal GND.

2. The high common mode transient suppression OOK modulation circuit based on output substrate modulation according to claim 1 is characterized in that: The first inverter formed by the PMOS tube M1 and the NMOS tube M2, and the second inverter formed by the PMOS tube M4 and the NMOS tube M5 are inverters of the same size; When rising edge common mode transient coupling interference occurs on the DP and DN signals as differential OOK signals, the common mode voltage of the DP and DN signals will increase, which is equivalent to enhancing the pull-up capability of the PMOS tube M1 and the PMOS tube M4, thereby increasing the flip threshold voltage of the first and second inverters; at this time, the positive substrate modulation signal BP and the negative substrate modulation signal BN output by the common mode substrate modulation circuit (2) simultaneously generate a positive increasing voltage signal, reducing the turn-on voltage of the NMOS tube M2, the NMOS tube M3, the NMOS tube M5 and the NMOS tube M6, thereby enhancing the pull-down capability of the NMOS tube M2, the NMOS tube M3, the NMOS tube M5 and the NMOS tube M6, and the flip threshold voltage of the first and second inverters can remain unchanged, that is, the influence of the rising edge common mode transient coupling interference is offset and suppressed; When falling edge common mode transient coupling interference occurs on the DP and DN signals as differential OOK signals, the common mode voltage of the DP and DN signals will decrease, which is equivalent to enhancing the pull-down capability of the NMOS tubes M2, M3, M5 and M6, thereby reducing the flip threshold voltage of the first and second inverters; at this time, the positive substrate modulation signal BP and the negative substrate modulation signal BN output by the common mode substrate modulation circuit (2) simultaneously generate a negative decreasing voltage signal, increasing the turn-on voltage of the NMOS tubes M2, M3, M5 and M6, thereby reducing the pull-down capability of the NMOS tubes M2, M3, M5 and M6, balancing the equivalent increased pull-down capability of the NMOS tubes, and the flip threshold voltage of the first and second inverters can remain unchanged, that is, offsetting and suppressing the influence of the falling edge common mode transient coupling interference.

3. The high common mode transient suppression OOK modulation circuit based on output substrate modulation according to claim 1 is characterized in that: The reset control circuit (1) comprises: a control signal C1 connected to an input end of an inverter IN1, a control signal C2 connected to an input end of an inverter IN8, a control signal C3 connected to a first input end of a NAND gate NB5, and a control signal C4 connected to an input end of an inverter IN11; The output end of the inverter IN1 is connected to the input end of the inverter IN2, and the output end of the inverter IN2 is connected to the first input end of the NAND gate NB1; the second input end of the NAND gate NB1, the second input end of the NAND gate NB3, the second input end of the NAND gate NB5, and the second input end of the NAND gate NB7 are connected to the protection control signal S1; the output end of the NAND gate NB1 is connected to the first input end of the NAND gate NB2, and the second input end of the NAND gate NB2, the second input end of the NAND gate NB4, the second input end of the NAND gate NB6, and the second input end of the NAND gate NB8 are connected to the protection control signal S2; the output end of the NAND gate NB2 is connected to the gate of the PMOS tube M8 and the gate of the NMOS tube M9 through the inverter IN3 and the inverter IN4 in sequence; The output end of the inverter IN8 is connected to the first input end of the NAND gate NB3, the output end of the NAND gate NB3 is connected to the first input end of the NAND gate NB4, and the output end of the NAND gate NB4 is connected to the gate of the NMOS tube M10 through the inverter IN9 and the inverter IN10 in sequence; The output end of the NAND gate NB5 is connected to the first input end of the NAND gate NB6, and the output end of the NAND gate NB6 is connected to the gate of the NMOS tube M11 and the gate of the NMOS tube M12; The source of the PMOS tube M8 is connected to the power supply voltage VCCL, the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M9 and the input terminal of the inverter IN5, and outputs a reset control signal CT1; the source of the NMOS tube M9 is connected to the drain of the NMOS tube M10, the source of the NMOS tube M10 is connected to the drain of the NMOS tube M11, the source of the NMOS tube M11 is connected to the drain of the NMOS tube M12, and the source of the NMOS tube M12 is connected to the ground signal GND; The output end of the inverter IN5 is connected to the first input end of the NAND gate NB9 through the inverter IN6 and the inverter IN7 in sequence; The output end of the inverter IN11 is connected to the first input end of the NAND gate NB7 through the inverter IN12, the output end of the NAND gate NB7 is connected to the first input end of the NAND gate NB8, and the output end of the NAND gate NB8 is connected to the second input end of the NAND gate NB9 through the inverter IN13 and the inverter IN14 in sequence; The output terminal of the NAND gate NB9 outputs a reset control signal CT2.

4. The high common mode transient suppression OOK modulation circuit based on output substrate modulation according to claim 1 is characterized in that: The common-mode substrate modulation circuit (2) comprises: a common-mode detection circuit (21), a first N-transistor substrate modulation signal generating circuit (22), and a second N-transistor substrate modulation signal generating circuit (23); the common-mode detection circuit (21) receives a positive-phase signal DP, a negative-phase signal DN, and a reference voltage Vrn, and outputs a common-mode control signal D1 after common-mode detection processing; the input end of the first N-transistor substrate modulation signal generating circuit (22) is respectively connected to the common-mode control signal D1, the reset control signal CT1, and the reset control signal CT2, and the first N-transistor substrate modulation signal generating circuit (22) outputs a positive-phase substrate modulation signal BP; the input end of the second N-transistor substrate modulation signal generating circuit (23) is respectively connected to the common-mode control signal D1, the reset control signal CT1, and the reset control signal CT2, and the second N-transistor substrate modulation signal generating circuit (23) outputs a negative-phase substrate modulation signal BN; The common mode detection circuit (21) detects the positive phase signal DP and the negative phase signal DN to obtain a real-time common mode voltage Vcm, and compares the voltage with an internal reference voltage Vrn to determine whether the real-time common mode voltage Vcm exceeds a normal threshold, and then generates a common mode control signal D1; when the real-time common mode voltage Vcm exceeds Vrn, the common mode control signal D1 will be connected to the real-time common mode voltage Vcm, the first N-transistor substrate modulation signal generating circuit (22) and the second N-transistor substrate modulation signal generating circuit (23) will start substrate compensation, and the positive phase substrate modulation signal BP and the negative phase substrate modulation signal BN will output a compensation voltage related to the real-time common mode voltage Vcm; when the real-time common mode voltage Vcm does not exceed Vrn, the positive phase substrate modulation signal BP and the negative phase substrate modulation signal BN will output a fixed voltage.

5. The high common mode transient suppression OOK modulation circuit based on output substrate modulation according to claim 4 is characterized in that: The common mode detection circuit (21) comprises: the upper end of a capacitor C51 is connected to the upper end of a resistor R51 and is connected to an input positive phase signal DP, the lower end of a capacitor C52 is connected to the lower end of a resistor R52 and is connected to an input negative phase signal DN; the lower end of the capacitor C51 is connected to the lower end of the resistor R51, the upper end of the capacitor C52 and the upper end of the resistor R52, generates a real-time common mode voltage Vcm, and is connected to the gate of a PMOS tube M52, the source of a PMOS tube M58 and the source of an NMOS tube M59; The source of the PMOS tube M52 is connected to the source of the PMOS tube M53 and the drain of the PMOS tube M51; the gate of the PMOS tube M51 is connected to the gate of the PMOS tube M56 and is connected to the first bias signal Vb1; the source of the PMOS tube M51 is connected to the source of the PMOS tube M56 and is connected to the power supply voltage VCCL; the gate of the PMOS tube M53 is connected to the reference voltage Vrn; the drain of the PMOS tube M52 is connected to the drain of the NMOS tube M54, the gate of the NMOS tube M54, and the gate of the NMOS tube M55; the drain of the PMOS tube M53 is connected to the drain of the NMOS tube M55 and the gate of the NMOS tube M57; the drain of the PMOS tube M56 is connected to the drain of the NMOS tube M57, the upper end of the resistor R53, the upper end of the capacitor C53, the gate of the PMOS tube M58, and the input end of the inverter INV51; the drain of the PMOS tube M58 is connected to the drain of the NMOS tube M59, and outputs the common mode control signal D1; The source of the NMOS tube M54, the source of the NMOS tube M55, the source of the NMOS tube M57, the lower end of the resistor R53, and the lower end of the capacitor C53 are connected to the ground signal GND; The circuit composed of capacitor C51, capacitor C52, resistor R51 and resistor R52 detects the positive phase signal DP and the negative phase signal DN to obtain the real-time common mode voltage Vcm; PMOS tube M51, PMOS tube M52, PMOS tube M53, NMOS tube M54, NMOS tube M55, PMOS tube M56 and NMOS tube M57 constitute a two-stage comparator, and the output signal SN of the two-stage comparator is delayed and filtered via resistor R53 and capacitor C53; PMOS tube M58 and NMOS tube M59 constitute a transmission gate, and the signal SN and the output of inverter INV51 are used as the transmission gate control signal to finally generate the common mode control signal D1.

6. The high common mode transient suppression OOK modulation circuit based on output substrate modulation according to claim 4 is characterized in that: The first N-tube substrate modulation signal generating circuit (22) and the second N-tube substrate modulation signal generating circuit (23) are implemented by using the same N-tube substrate modulation signal generating circuit, and the circuit structure includes: The source of the PMOS tube M61, the source of the PMOS tube M65, and the source of the PMOS tube M67 are connected to the power supply voltage VCCL; the gate of the PMOS tube M61, the gate of the PMOS tube M62, the gate of the NMOS tube M63, the gate of the PMOS tube M65, and the gate of the PMOS tube M66 are connected to the reset control signal CT2; the drain of the PMOS tube M61 is connected to the source of the PMOS tube M62; the drain of the PMOS tube M62 is connected to the drain of the NMOS tube M63, the drain of the PMOS tube M66, the gate of the NMOS tube M64, and the gate of the NMOS tube M70; the source of the NMOS tube M63 is connected to the upper end of the resistor R61, the drain of the NMOS tube M64, the source of the NMOS tube M68, the upper end of the resistor R62, and the drain of the NMOS tube M71, and outputs the inverted substrate modulation signal BN; The drain of the PMOS tube M65 is connected to the source of the PMOS tube M66, and the gate of the PMOS tube M67, the gate of the NMOS tube M68, and the gate of the NMOS tube M69 are commonly connected to the reset control signal CT1; the drain of the PMOS tube M67 is connected to the drain of the NMOS tube M68 and the gate of the NMOS tube M71, the lower end of the resistor R62 is connected to the drain of the NMOS tube M69, and the source of the NMOS tube M69 is connected to the drain of the NMOS tube M70 and the common-mode control signal D1; the lower end of the resistor R61, the source of the NMOS tube M64, the source of the NMOS tube M70, and the source of the NMOS tube M71 are commonly connected to the ground signal GND.

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