LVDS transmission system

Abstract

The invention provides an LVDS (Low Voltage Differential Signaling) transmission system which comprises an LVDS sending device and a first receiving device, the LVDS sending device is connected with the first receiving device through a first LVDS bus, the first LVDS bus comprises an LVDS clock line and a plurality of LVDS data lines, the LVDS sending device sends data to the first receiving device through the first LVDS bus, and the first receiving device receives the data from the LVDS clock line. The first receiving device can eliminate delay deviation of the LVDS clock line and the LVDS data lines and receive data from the first LVDS bus. According to the invention, a higher-speed and longer-distance LVDS data transmission scheme can be supported.

Description

Technical Field

[0001] The present invention relates to the field of data transmission, and in particular to an LVDS transmission system and an LVDS receiving device. Background Art

[0002] LVDS (Low Voltage Differential Signaling) low voltage differential signal bus, referred to as LVDS bus, uses extremely low voltage swing and high-speed differential transmission of data, which can realize point-to-point or point-to-multipoint connection. It has the characteristics of high efficiency, low power consumption, high speed, low cost, low clutter interference, and can support higher resolution. LVDS is widely used in telecommunications, communications, consumer electronics, automobiles, and medical instruments that have high requirements for signal integrity, low jitter, and common mode characteristics. The LVDS bus includes an LVDS clock line and multiple LVDS data lines. The LVDS clock line and each LVDS data line use differential signal transmission, that is, the LVDS clock line and each LVDS data line contain a pair of differential signal lines. The Open LDI (Open LVDSdisplay interface) standard is a transmission protocol based on the LVDS bus. It was proposed and drafted by National Semiconductor Corporation in 1999 and uses the LVDS bus as the physical layer. It aims to establish an open standard for digital connections between display sources and display devices. It incorporates the work of other widely used standards such as the Video Electronics Standards Association (VESA) and the American National Standards Institute (ANSI), providing an all-digital, plug-and-play interface that ensures clear, sharp video images on digital display devices. In Open LDI, the data rate transmitted on each LVDS data line is 7 times the clock frequency transmitted on each LVDS clock line.

[0003] In the process of transmitting data signals from the sending device to the receiving device via the LVDS bus, due to differences in transmission media, transmission speed, and transmission path, there will be a certain delay deviation between the clock line and the data signal received by the receiving device, which greatly limits the use of LVDS in many high-speed, long-distance application scenarios. Summary of the invention

[0004] The problem to be solved by the present invention is: how to eliminate the delay deviation between an LVDS clock line and multiple LVDS data lines in a high-speed, long-distance LVDS transmission scenario.

[0005] In order to solve the problems in the prior art, the technical solution adopted by the present invention is: as an LVDS transmission system of the present invention, it includes an LVDS transmitting device and a first receiving device, the LVDS transmitting device is connected to the first receiving device through a first LVDS bus, the first LVDS bus includes an LVDS clock line and multiple LVDS data lines, the LVDS transmitting device sends data to the first receiving device through the first LVDS bus, the first receiving device includes an LVDS alignment module, the LVDS alignment module is used to eliminate the delay deviation of the LVDS clock line and multiple LVDS data lines and receive data from the first LVDS bus.

[0006] Preferably, the LVDS alignment module includes a phase-locked loop module, which is connected to the LVDS clock line and uses the LVDS clock line as a reference clock of the phase-locked loop module to generate one or more sampling clocks for sampling data transmitted on the LVDS data line.

[0007] Furthermore, the LVDS alignment module includes one or more data line delay modules, and the method for the LVDS alignment module to eliminate the delay deviation of the LVDS clock line and multiple LVDS data lines is: the one or more data line delay modules respectively delay one or more LVDS data lines so that the sampling clock can correctly sample the data.

[0008] Furthermore, the LVDS alignment module also includes a reference clock delay module. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is: the reference clock delay module delays the reference clock of the phase-locked loop module, thereby delaying the sampling clock so that the sampling clock can correctly sample the data.

[0009] Furthermore, the LVDS alignment module also includes one or more sampling clock phase adjustment modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is: the one or more sampling clock phase adjustment modules adjust the phase of one or more sampling clocks so that the sampling clock can correctly sample data.

[0010] Preferably, the LVDS transmitting device is also connected to the first receiving device via a control bus, and the LVDS transmitting device controls the LVDS alignment module via the control bus.

[0011] Preferably, the LVDS transmission system further includes a second receiving device, and the first receiving device further includes a sending module, the sending module is connected to the second receiving device, and the first receiving device forwards the data received from the first LVDS bus to the second receiving device through the sending module.

[0012] Furthermore, the transmitting module included in the first receiving device is an LVDS transmitting module, and the LVDS transmitting module is connected to the second receiving device via a second LVDS bus.

[0013] Furthermore, the number of LVDS data lines included in the second LVDS bus is twice the number of LVDS data lines included in the first LVDS bus, and the transmission rate of the LVDS data lines included in the second LVDS bus is half the transmission rate of the LVDS data lines included in the first LVDS bus.

[0014] Preferably, in each clock cycle of the LVDS clock line, one or more pixel point data are transmitted on the LVDS data line.

[0015] As a first receiving device of the present invention, it includes an LVDS alignment module. The first receiving device is connected to an LVDS sending device via a first LVDS bus. The first LVDS bus includes an LVDS clock line and multiple LVDS data lines. The LVDS sending device sends data to the first receiving device via the first LVDS bus. The LVDS alignment module is used to eliminate delay deviations of the LVDS clock line and multiple LVDS data lines and receive data from the first LVDS bus.

[0016] Preferably, the LVDS alignment module includes a phase-locked loop module, which is connected to the LVDS clock line and uses the LVDS clock line as a reference clock of the phase-locked loop module to generate one or more sampling clocks for sampling data transmitted on the LVDS data line.

[0017] Furthermore, the LVDS alignment module includes one or more data line delay modules, and the method for the LVDS alignment module to eliminate the delay deviation of the LVDS clock line and multiple LVDS data lines is: the one or more data line delay modules respectively delay one or more LVDS data lines so that the sampling clock can correctly sample the data.

[0018] Furthermore, the LVDS alignment module also includes a reference clock delay module. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the reference clock delay module delays the reference clock of the phase-locked loop module, thereby delaying the sampling clock so that the sampling clock can correctly sample the data.

[0019] Furthermore, the LVDS alignment module also includes one or more sampling clock phase adjustment modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is: the one or more sampling clock phase adjustment modules adjust the phase of one or more sampling clocks so that the sampling clock can correctly sample data.

[0020] Preferably, the LVDS transmitting device is also connected to the first receiving device via a control bus, and the LVDS transmitting device controls the LVDS alignment module via the control bus.

[0021] Preferably, the first receiving device further comprises a sending module, the sending module is connected to the second receiving device, and the first receiving device forwards the data received from the first LVDS bus to the second receiving device through the sending module.

[0022] Furthermore, the transmitting module included in the first receiving device is an LVDS transmitting module, and the LVDS transmitting module is connected to the second receiving device via a second LVDS bus.

[0023] Furthermore, the number of LVDS data lines included in the second LVDS bus is twice the number of LVDS data lines included in the first LVDS bus, and the transmission rate of the LVDS data lines included in the second LVDS bus is half the transmission rate of the LVDS data lines included in the first LVDS bus.

[0024] Preferably, in each clock cycle of the LVDS clock line, one or more pixel point data are transmitted on the LVDS data line.

[0025] The beneficial effects of the present invention are:

[0026] The present invention provides an LVDS transmission system and an LVDS receiving device. During the LVDS data transmission process, the delay deviation between an LVDS clock line and a plurality of LVDS data lines can be eliminated, the transmission speed of the LVDS data can be improved, and the transmission distance of the LVDS data can be increased, thereby expanding the application scope of the LVDS data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention is further described below in conjunction with the accompanying drawings and embodiments:

[0028] Figure 1 It is a module schematic diagram of an embodiment of the LVDS transmission system of the present invention.

[0029] Figure 2 It is a data transmission timing diagram of an embodiment of the LVDS transmission system of the present invention.

[0030] Figure 3 It is a schematic diagram of a phase-locked loop module of an embodiment of the first receiving device of the present invention.

[0031] Figure 4 It is a timing diagram of a phase-locked loop module of an embodiment of the first receiving device of the present invention.

[0032] Figure 5It is a schematic diagram of a reference clock delay module of an embodiment of the first receiving device of the present invention.

[0033] Figure 6 It is a timing diagram of a reference clock delay module of an embodiment of the first receiving device of the present invention.

[0034] Figure 7 It is a schematic diagram of a sampling clock phase adjustment module of an embodiment of the first receiving device of the present invention.

[0035] Figure 8 It is a timing diagram of a sampling clock phase adjustment module of an embodiment of the first receiving device of the present invention.

[0036] Fig. 9 It is a schematic diagram of a sampling clock phase adjustment module of another embodiment of the first receiving device of the present invention.

[0037] Fig.10 It is a schematic diagram of a sampling clock phase adjustment module of another embodiment of the first receiving device of the present invention.

[0038] Fig.11 It is a timing diagram of a sampling clock phase adjustment module of the first receiving device of the present invention.

[0039] Fig.12 It is a schematic diagram of a data line delay module of an embodiment of the first receiving device of the present invention.

[0040] Fig.13 It is a timing diagram of a data line delay module of an embodiment of the first receiving device of the present invention.

[0041] Fig.14 It is a schematic diagram of an embodiment of the LVDS transmission system of the present invention with a control bus.

[0042] Fig.15 It is a module schematic diagram of another embodiment of the LVDS transmission system of the present invention.

[0043] Fig.16 It is a schematic diagram of another embodiment of the LVDS transmission system of the present invention with a control bus.

[0044] Fig.17 It is a module schematic diagram of another embodiment of the LVDS transmission system of the present invention.

[0045] Fig.18 It is a schematic diagram of an embodiment of the first receiving device in the LVDS transmission system of the present invention having an LVDS transmitting module.

[0046] Fig.19 This is a schematic diagram of the second LVDS bus transmission timing in the LVDS transmission system of the present invention. The meanings of the numbers in the above figures are as follows:

[0047] 100:LVDS transmitter

[0048] 200: first receiving device

[0049] 201: LVDS alignment module

[0050] 202: Sending module

[0051] 211: Phase-locked loop module

[0052] 221: Reference clock delay module

[0053] 231: Sampling clock phase adjustment module

[0054] 241: Data line delay module

[0055] 300: Second receiving device

[0056] 400: First LVDS bus

[0057] 401: LVDS clock line

[0058] 402: LVDS data line

[0059] 500: Control bus

[0060] 600: Second LVDS bus DETAILED DESCRIPTION

[0061] The LVDS transmission system and the first receiving device are further described below in conjunction with the embodiments in the accompanying drawings.

[0062] like Figure 1 As shown, an embodiment of the LVDS transmission system of the present invention is shown. The LVDS transmission system includes an LVDS transmitting device (100) and a first receiving device (200). The LVDS transmitting device is connected to the first receiving device (200) via a first LVDS bus (400). The first LVDS bus (400) includes an LVDS clock line (401) and multiple LVDS data lines (402). The LVDS transmitting device (100) transmits data to the first receiving device (200) via the first LVDS bus (400). The first receiving device (200) includes an LVDS alignment module (201). The LVDS alignment module is used to eliminate the delay deviation between the LVDS clock line (401) and the multiple LVDS data lines (402) and receive data from the first LVDS bus (400). In the present invention, the LVDS clock line (401) and each LVDS data line (402) use differential signal transmission, that is, the LVDS clock line (401) and each LVDS data line (402) include a pair of differential signal lines, such as Figure 1 shown.

[0063] For convenience, in the description of the present invention, unless otherwise specified, the description is based on the LVDS bus including 4 LVDS data lines, such as Figure 1 The first LVDS bus (400) shown includes four LVDS data lines (402), which are respectively represented as LVDS data line A0, LVDS data line A1, LVDS data line A2, and LVDS data line A3. In the present invention, the LVDS clock line (401) included in the first LVDS bus (400) is represented by LVDS clock line CLK_IN.

[0064] The present invention does not limit the number of LVDS data lines included in the LVDS bus. Fig.19 The LVDS bus shown includes eight LVDS data lines A0, A1 to A7.

[0065] The Open LDI (Open LVDS display interface) standard is a transmission protocol based on the LVDS bus and was proposed and drafted by National Semiconductor Corporation in 1999. It uses the LVDS bus as the physical layer and aims to establish an open standard for the digital connection between the display source and the display device. It integrates the work results of other widely used standards such as the Video Electronics Standards Association (VESA) and the American National Standards Institute (ANSI), and provides a fully digital, plug-and-play interface that can ensure clear and sharp video images on digital display devices. In Open LDI, the data rate transmitted on each LVDS data line is 7 times the clock frequency transmitted on each LVDS clock line. For ease of description, in the embodiments of the present invention described below, the data rate transmitted on each LVDS data line is 7 times the clock frequency transmitted on each LVDS clock line, but the present invention does not limit the relationship between the data rate transmitted on the LVDS data line and the clock frequency transmitted on the LVDS clock line, and other quantitative relationships between the two are also within the scope of protection of the present invention.

[0066] like Figure 2 In the illustrated embodiment, a signal timing diagram of the Open LDI protocol transmitting image data on the first LVDS bus (400) based on the LVDS bus is provided. Using the LVDS bus to transmit other protocol data is also within the protection scope of the present invention, that is, the present invention does not limit the data or protocol type transmitted based on the LVDS bus.

[0067] like Figure 2As shown, one pixel data is transmitted in each LVDS clock cycle (in one CLK_IN clock cycle) through LVDS data lines A0, A1, A2, A3 (402). R0, R1 to R7 are 8-bit binary data representing red, G0, G1 to G7 are 8-bit binary data representing green, B0, B1 to B7 are 8-bit binary data representing blue, HSYNC, VSYNC, DE are binary data representing synchronization signals, and RES is a reserved bit. Figure 2 As shown, within one LVDS clock cycle, 7 cycles of serial data (7-bit binary data) are transmitted on each LVDS data line, and the serial data width of one cycle is one UI.

[0068] like Figure 2 In the illustrated embodiment, one pixel data is transmitted in each LVDS clock cycle. The present invention does not limit the number of pixels transmitted in each LVDS clock cycle. Transmission of more than one pixel data in each LVDS clock cycle also falls within the protection scope of the present invention.

[0069] like Figure 3 The figure shows a schematic diagram of a phase-locked loop module of an embodiment of the first receiving device of the present invention. The LVDS alignment module (201) includes a phase-locked loop module (211). The phase-locked loop module (211) is connected to the LVDS clock line (401), and uses the LVDS clock line (401) as a reference clock of the phase-locked loop module (211) to generate a sampling clock for sampling data transmitted on the LVDS data line (402). The phase-locked loop module (211) can also generate multiple sampling clocks, and the present invention does not limit the number of sampling clocks generated by the phase-locked loop module.

[0070] like Figure 4 In the timing diagram shown, the sampling clock frequency is 7 times the reference clock frequency, but the present invention does not limit the proportional relationship between the sampling clock and the reference clock. For example, in another embodiment, the sampling clock uses both the rising edge and the falling edge to sample data, then the frequency of the sampling clock is 3.5 times the reference clock frequency.

[0071] like Figure 4In the timing diagram shown, the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the reference clock input to the phase-locked loop module (211), that is, the rising edge of the sampling clock is aligned with the rising edge of the reference clock. The present invention does not limit the phase relationship between the output sampling clock of the phase-locked loop module (211) and the input reference clock. In different implementations of the phase-locked loop module (211), its output sampling clock may also have a phase difference with the input reference clock, that is, in different implementations of the phase-locked loop module (211), its output sampling clock rising edge may also not be aligned with the rising edge of the input reference clock. In the above description, the alignment of the rising edge of the sampling clock with the rising edge of the reference clock indicates that the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the reference clock input to the phase-locked loop module (211), and there is no phase difference between the two. In other descriptions of the present invention, the alignment of the rising edge of the sampling clock with the falling edge of the reference clock, or the alignment of the falling edge of the sampling clock with the rising edge of the reference clock, or the alignment of the falling edge of the sampling clock with the falling edge of the reference clock may also be used to indicate that the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the reference clock input to the phase-locked loop module (211).

[0072] For the convenience of description, in the following description of the present invention, the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the reference clock input to the phase-locked loop module (211), and the alignment of the rising edge of the sampling clock with the rising edge of the reference clock indicates that the phase of the sampling clock output by the phase-locked loop module (211) is aligned with the phase of the reference clock input to the phase-locked loop module (211).

[0073] The LVDS alignment module (201) may further include a reference clock delay module (221). The method by which the LVDS alignment module (201) eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the reference clock delay module (221) delays the reference clock of the phase-locked loop module (211), thereby delaying the sampling clock so that the sampling clock can correctly sample data. Figure 5The figure shows a schematic diagram of a reference clock delay module of an embodiment of the first receiving device of the present invention. In the embodiment, the LVDS alignment module (201) includes a phase-locked loop module (211) and a reference clock delay module (221). The reference clock delay module (221) is connected to the LVDS clock line (401) and uses the LVDS clock line (401) as an input signal. The output of the reference clock delay module (221) is connected to the phase-locked loop module (211). The output of the reference clock delay module (221) is the reference clock of the phase-locked loop module (211). The reference clock delay module (221) is used to delay the reference clock of the phase-locked loop module (211), thereby delaying the sampling clock so that the sampling clock can correctly sample data. The delay value of the reference clock delay module (221) can be configured. In this embodiment, the phase-locked loop module (211) generates four sampling clocks, namely a first sampling clock, a second sampling clock, a third sampling clock and a fourth sampling clock, which are respectively used to sample the LVDS data lines (402) (A0, A1, A2, A3).

[0074] Figure 6 Based on Figure 5 The timing diagram of the reference clock delay module in the embodiment shown is as follows: Figure 6 As shown, the undelayed reference clock, the undelayed first sampling clock, the undelayed second sampling clock, the undelayed third sampling clock, and the undelayed fourth sampling clock are respectively Figure 5 The reference clock input to the phase-locked loop module (211) when the delay value of the reference clock delay module (221) is configured as 0, and the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock output by the phase-locked loop module (211).

[0075] Figure 6 In the illustrated embodiment, the rising edge of the sampling clock is used to sample the LVDS data, that is, the rising edge of the sampling clock is the sampling edge. The present invention does not limit the sampling edge of the sampling clock. Using the rising edge of the sampling clock to sample the LVDS data, or using the falling edge of the sampling clock to sample the LVDS data, or using the rising edge and the falling edge of the sampling clock to sample the LVDS data are all within the protection scope of the present invention.

[0076] For the convenience of description, in the following description of the present invention, LVDS data is sampled at the rising edge of the sampling clock.

[0077] like Figure 6As shown, there is a delay deviation between the LVDS clock line CLK_IN (401) and the LVDS data lines A0, A1, A2, A3 (402), resulting in that the rising edge of the undelayed reference clock is not aligned with the stable part of the LVDS data lines A0, A1, A2, A3 (402), but is aligned with the unstable part (shown as the grid shaded part) of the LVDS data lines A0, A1, A2, A3 (402), thereby causing the undelayed first sampling clock, the undelayed second sampling clock, the undelayed third sampling clock, and the undelayed fourth sampling clock to fail to correctly sample the LVDS data on the LVDS data lines A0, A1, A2, A3 (402).

[0078] like Figure 6 As shown, the delayed reference clock, the delayed first sampling clock, the delayed second sampling clock, the delayed third sampling clock, and the delayed fourth sampling clock are respectively Figure 5 The delay value of the reference clock delay module (221) is configured as the input reference clock of the phase-locked loop module (211) with the correct delay value and the first sampling clock, the second sampling clock, the third sampling clock and the fourth sampling clock output by the phase-locked loop module (211).

[0079] like Figure 6 As shown, after the delay value of the reference clock delay module (221) is configured as the correct delay value, the input reference clock of the phase-locked loop module (211) output by the LVDS clock line (401) (CLK_IN) after delay is aligned to the stable part of the LVDS data lines A0, A1, A2, A3 (402), so that the delayed first sampling clock, the delayed second sampling clock, the delayed third sampling clock, and the delayed fourth sampling clock are also aligned to the stable part of the LVDS data lines A0, A1, A2, A3 (402), so that the LVDS data lines A0, A1, A2, A3 (402) can be correctly sampled.

[0080] A user can use an LVDS sending device (100) to send a preset data sequence on LVDS data lines A0, A1, A2, A3 (402), and configure the delay of a reference clock delay module (221) to different delay values, and check whether the LVDS data sampled at different delay values ​​is correct, so as to search for a correct delay value.

[0081] The present invention does not limit the method for searching and configuring the correct delay value, and any method for searching and configuring the correct delay value is within the protection scope of the present invention.

[0082] The LVDS alignment module (201) may further include one or more sampling clock phase adjustment modules (231). The method by which the LVDS alignment module (201) eliminates delay deviations of an LVDS clock line and a plurality of LVDS data lines is as follows: the one or more sampling clock phase adjustment modules (231) adjust the phases of one or more sampling clocks so that the sampling clocks can correctly sample data.

[0083] Figure 7 The present invention is a schematic diagram of a clock phase adjustment module of an embodiment of the first receiving device of the present invention. In this embodiment, the LVDS alignment module (201) includes a phase-locked loop module (211) and a sampling clock phase adjustment module (231). The phase-locked loop module (211) is connected to the LVDS clock line (401) and uses the LVDS clock line (401) as a reference clock. The phase-locked loop module (211) outputs a sampling clock. The sampling clock phase adjustment module (231) is used to adjust the phase of the sampling clock generated by the phase-locked loop module (211) so that the adjusted sampling clock can correctly sample the data of the four data lines A0, A1, A2, and A3. The sampling clock phase adjustment module (231) uses the sampling clock output by the phase-locked loop module (211) as input and outputs the sampling clock after phase adjustment. In the present invention, the phase of the sampling clock after phase adjustment refers to the delay relative to the sampling clock input as the sampling clock phase adjustment module (231), the phase value of the sampling clock phase adjustment module (231) can be configured, and when the sampling clock phase adjustment module (231) is configured to a different phase value, the phase of the sampling clock after phase adjustment is adjusted accordingly.

[0084] Figure 8 Based on Figure 7 The timing diagram of the sampling clock phase adjustment module in the embodiment shown is as follows: Figure 8 As shown, there is a delay deviation between the LVDS clock line CLK_IN (401) and the LVDS data lines A0, A1, A2, A3 (402), resulting in that the rising edges of the reference clock and the sampling clock are not aligned with the stable parts of the LVDS data lines A0, A1, A2, A3 (402), but are aligned with the unstable parts (shown as the grid shaded parts) of the LVDS data lines A0, A1, A2, A3 (402), thereby failing to correctly sample the LVDS data on the LVDS data lines A0, A1, A2, A3 (402).

[0085] like Figure 8 As shown, after the phase value of the sampling clock phase adjustment module (231) is configured to be a correct phase value, the rising edge of the sampling clock after phase adjustment is aligned to the stable part of the LVDS data lines A0, A1, A2, A3 (402), so that the LVDS data lines A0, A1, A2, A3 (402) can be correctly sampled.

[0086] A user can send a preset data sequence on LVDS data lines A0, A1, A2, A3 (402) through an LVDS sending device (100), and configure a sampling clock phase adjustment module (231) to different phase values, and then search for a correct phase value by checking whether the LVDS data sampled by the sampling clock after phase adjustment under different phase value configurations is correct.

[0087] The present invention does not limit the method for searching and configuring the correct phase value, and any method for searching and configuring the correct phase value is within the protection scope of the present invention.

[0088] Fig. 9 FIG. 1 is a schematic diagram of a clock phase adjustment module of another embodiment of the first receiving device of the present invention. Figure 7 Compared with the embodiment shown, Fig. 9 In the illustrated embodiment, the LVDS alignment module (201) includes four sampling clock phase adjustment modules (231), the phase-locked loop module (211) generates a sampling clock, and the sampling clock is sent to the four sampling clock phase adjustment modules (231), respectively. The four sampling clock phase adjustment modules (231) respectively adjust the phase of the sampling clock, and respectively generate a first sampling clock after phase adjustment, a second sampling clock after phase adjustment, a third sampling clock after phase adjustment, and a fourth sampling clock after phase adjustment.

[0089] Fig.10 FIG. 1 is a schematic diagram of a clock phase adjustment module of another embodiment of the first receiving device of the present invention. Fig. 9 Compared with the embodiment shown, Fig.10 In the illustrated embodiment, the phase-locked loop module (211) generates a plurality of sampling clocks, namely, a first sampling clock, a second sampling clock, a third sampling clock, and a fourth sampling clock, a total of four sampling clocks, which are respectively connected to four sampling clock phase adjustment modules (231). The four sampling clock phase adjustment modules (231) respectively adjust the phases of the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock, thereby generating a first sampling clock after phase adjustment, a second sampling clock after phase adjustment, a third sampling clock after phase adjustment, and a fourth sampling clock after phase adjustment.

[0090] Fig.11 Based on Fig. 9 or Fig.10 The timing diagram of the sampling clock phase adjustment module of the embodiment shown in the figure, after the phase adjustment, the first sampling clock is used to sample the LVDS data line A0 (402), after the phase adjustment, the second sampling clock is used to sample the LVDS data line A1 (402), after the phase adjustment, the third sampling clock is used to sample the LVDS data line A2 (402), and after the phase adjustment, the fourth sampling clock is used to sample the LVDS data line A3 (402). Fig.11 Based on Fig. 9 hour, Fig.11 The first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock are all Fig. 9 The sampling clock is shown.

[0091] like Fig.11 As shown, there is a delay deviation between the LVDS clock line CLK_IN (401) and the LVDS data lines A0, A1, A2, A3 (402), and there is also a delay deviation between the LVDS data lines A0, A1, A2, A3 (402), resulting in that the rising edges of the first sampling clock, the second sampling clock, the third sampling clock, and the fourth sampling clock are not aligned with the stable part of the LVDS data lines A0, A1, A2, A3 (402), or are not aligned with the middle part of the stable part, so that the LVDS data on the LVDS data lines A0, A1, A2, A3 (402) cannot be correctly sampled or the LVDS data on the LVDS data lines A0, A1, A2, A3 (402) cannot be stably and correctly sampled.

[0092] like Fig.11 As shown, after the phase values ​​of the four sampling clock phase adjustment modules (231) are respectively configured as correct phase values, the rising edges of the first sampling clock after phase adjustment, the second sampling clock after phase adjustment, the third sampling clock after phase adjustment, and the fourth sampling clock after phase adjustment are respectively aligned to the middle part of the stable part of the LVDS data lines A0, A1, A2, A3 (402), so that the LVDS data lines A0, A1, A2, A3 (402) can be stably and correctly sampled.

[0093] A user can send a preset data sequence on LVDS data lines A0, A1, A2, A3 (402) through an LVDS sending device (100), and configure four sampling clock phase adjustment modules (231) to different phase values ​​respectively, and then search for the correct phase value by checking whether the LVDS data sampled by the sampling clock after phase adjustment under different phase value configurations is correct.

[0094] The present invention does not limit the method for searching and configuring the correct phase value, and any method for searching and configuring the correct phase value is within the protection scope of the present invention.

[0095] The LVDS alignment module (201) may further include one or more data line delay modules (241). The method by which the LVDS alignment module (201) eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: one or more data line delay modules (241) respectively delay one or more LVDS data lines so that the sampling clock can correctly sample the data. Fig.12In the illustrated embodiment, four data line delay modules (241) are used as an example to respectively delay four LVDS data lines.

[0096] Fig.12 The figure shows a schematic diagram of a data line delay module of an embodiment of the first receiving device of the present invention. In this embodiment, the LVDS alignment module (201) includes four data line delay modules (241), which are respectively connected to the LVDS data line A0 (402), the LVDS data line A1 (402), the LVDS data line A2 (402), and the LVDS data line A3 (402); the four data line delay modules (241) can respectively delay the connected LVDS data lines A0, A1, A2, and A3 (402), and respectively output the delayed LVDS data lines A0, A1, A2, and A3.

[0097] Fig.13 Based on Fig.12 The data line delay timing diagram of the embodiment shown is as follows: Fig.13 As shown, there is a delay deviation between the reference clock of the phase-locked loop module (211) and the LVDS data lines A0, A1, A2, A3 (402), and there is also a delay deviation between the LVDS data lines A0, A1, A2, A3 (402), resulting in the rising edge of the sampling clock generated by the phase-locked loop module (211) not being aligned with the stable part of the LVDS data lines A0, A1, A2, A3 (402), or not being aligned with the middle part of the stable part, so that the LVDS data on the LVDS data lines A0, A1, A2, A3 (402) cannot be correctly sampled or the LVDS data on the LVDS data lines A0, A1, A2, A3 (402) cannot be stably and correctly sampled.

[0098] like Fig.13 As shown, after the four data line delay modules (241) are respectively configured to the correct delay value, the middle part of the stable part of the delayed LVDS data A0, A1, A2, A3 is aligned with the sampling clock, so that the sampling clock can stably and correctly sample the delayed LVDS data A0, A1, A2, A3.

[0099] A user can send a preset data sequence on LVDS data lines A0, A1, A2, and A3 (402) through an LVDS sending device (100), and configure four data line delay modules (241) to different delay values ​​respectively, and then search for the correct delay value by checking whether the delayed LVDS data sampled by the sampling clock under different delay value configurations is correct.

[0100] The present invention does not limit the method for searching and configuring the correct delay value, and any method for searching and configuring the correct delay value is within the protection scope of the present invention.

[0101] In the present invention, one or more of the reference clock delay module (221), the sampling clock phase adjustment module (231), and the data line delay module (241) may exist simultaneously in an embodiment of the present invention, and the present invention does not limit the number or combination of the above functional modules.

[0102] like Fig.14 FIG. 2 is an embodiment of the LVDS transmission system of the present invention with a control bus. Figure 1 Compared with the embodiment shown, Fig.14 The embodiment shown in Figure 1 On the basis of the illustrated embodiment, the LVDS transmitting device (100) is also connected to the first receiving device (200) via a control bus (500); the LVDS transmitting device (100) controls the alignment module (201) of the first receiving device (200) via the control bus (500).

[0103] In this embodiment, a method for eliminating delay deviations of an LVDS clock line (401) and a plurality of LVDS data lines (402) in an LVDS transmission system is as follows: an LVDS transmitting device (100) transmits a preset data sequence on LVDS data lines A0, A1, A2, and A3 (402), and controls an alignment module (201) through a control bus (500) to search for and configure a correct phase value of a sampling clock phase adjustment module (231) in the above description of the present invention, or controls an alignment module (201) through a control bus (500) to search for and configure a correct delay value of a data line delay module (241) in the above description of the present invention, or controls an alignment module (201) through a control bus (500) to search for and configure a correct delay value of a reference clock delay module (221) in the above description of the present invention.

[0104] like Fig.15 FIG. 2 is another embodiment of the LVDS transmission system of the present invention. Figure 1 Compared with the embodiment shown, Fig.15 The embodiment shown in Figure 1 Based on the illustrated embodiment, the LVDS transmission system further includes a second receiving device (300), and the first receiving device (200) further includes a sending module (202), the sending module (202) is connected to the second receiving device (300), and the first receiving device (200) forwards the data received from the first LVDS bus (400) to the second receiving device (300) through the sending module (202).

[0105] exist Fig.15In the illustrated embodiment, the alignment module (201) in the first receiving device (200) can eliminate the delay deviation of the LVDS clock line (401) and multiple LVDS data lines (402) in the first LVDS bus (400) and receive data from the first LVDS bus (400), and then forward the data received from the first LVDS bus (400) to the second receiving device (300) through the sending module (202). The first receiving device (200) acts as a bridge between the LVDS sending device (100) and the second receiving device (300), thereby extending the transmission distance between the LVDS sending device (100) and the second receiving device (300). The method for eliminating the delay deviation of the LVDS clock line (401) and multiple LVDS data lines (402) in the first LVDS bus (400) by the alignment module (201) has been described in detail. Figures 3 to 13 The above is described in the embodiment shown and will not be described in detail.

[0106] When the first receiving device (200) forwards the data received from the first LVDS bus (400) to the second receiving device (300) via the sending module (202), the data can be modified, added or deleted.

[0107] like Fig.16 FIG. 2 is another embodiment of the LVDS transmission system of the present invention with a control bus. Fig.15 Compared with the embodiment shown, Fig.16 The embodiment shown in Fig.15 On the basis of the embodiment shown, the LVDS transmitting device (100) is further connected to the first receiving device (200) via a control bus (500), and the LVDS transmitting device (100) controls the alignment module (201) of the first receiving device (200) via the control bus (500). The role of the control bus (500) in the alignment module (201) in eliminating the delay deviation of the LVDS clock line (401) and the plurality of LVDS data lines (402) has been described in detail. Fig.14 The above is described in the embodiment shown and will not be described in detail.

[0108] like Fig.17 As shown, in another embodiment of the LVDS transmission system of the present invention, Fig.15 Compared with the embodiment shown, Fig.17 The embodiment shown in Fig.15 On the basis of the embodiment shown, a plurality of cascaded first receiving devices (200) are added between the LVDS transmitting device (100) and the second receiving device (300), and the first receiving devices (200) are connected via an LVDS bus. Fig.15 Compared with the embodiment shown, Fig.17The illustrated embodiment can further extend the transmission distance between the LVDS transmitting device (100) and the second receiving device (300).

[0109] like Fig.18 The figure shows another embodiment of the LVDS transmission system of the present invention. In this embodiment, the sending module (202) included in the first receiving device (200) is an LVDS sending module, and the LVDS sending module is connected to the second receiving device (300) via a second LVDS bus (600). The second LVDS bus (600) includes an LVDS clock line CLK_OUT and 8 LVDS data lines A0_OUT, A1_OUT to A7_OUT.

[0110] The present invention does not limit the number of LVDS data lines included in the second LVDS bus (600). Fig.18 In the illustrated embodiment, the number of LVDS data lines included in the second LVDS bus (600) is twice the number of LVDS data lines (402) included in the first LVDS bus. In other embodiments, the number of LVDS data lines included in the second LVDS bus (600) may be equal to the number of LVDS data lines (402) included in the first LVDS bus or may be other multiples of the number of LVDS data lines (402) included in the first LVDS bus.

[0111] like Fig.19 As shown, based on Fig.18 The second LVDS bus (600) is a transmission timing diagram. Two pixel data are transmitted in each LVDS clock cycle (in one CLK_OUT clock cycle) through the LVDS data lines A0_OUT, A1_OUT to A7_OUT. Among them, RU0, RU1 to RU7 are 8-bit binary data representing red for the first pixel, GU0, GU1 to GU7 are 8-bit binary data representing green for the first pixel, BU0, BU1 to BU7 are 8-bit binary data representing blue for the first pixel, RL0, RL1 to RL7 are 8-bit binary data representing red for the second pixel, GL0, GL1 to GL7 are 8-bit binary data representing green for the second pixel, BL0, BL1 to BL7 are 8-bit binary data representing blue for the second pixel, HSYNC, VSYNC, DE are binary data representing synchronization signals, RES is a reserved bit, and CNTL and CNTE are two custom control bits. Fig.19 As shown, within one LVDS clock cycle, 7 cycles of serial data (7-bit binary data) are transmitted on each LVDS data line, and the serial data width of one cycle is one UI.

[0112] Fig.19In the illustrated embodiment, the transmission rate of the LVDS data lines included in the second LVDS bus (600) can be half the transmission rate of the LVDS data lines included in the first LVDS bus (400). Because the number of LVDS data lines included in the second LVDS bus (600) is twice the number of LVDS data lines (402) included in the first LVDS bus, the total transmission rate of the second LVDS bus (600) is equal to the total transmission rate of the first LVDS bus (400).

[0113] In other embodiments of the present invention, the second LVDS bus may also include another LVDS clock line and LVDS data line, which is not limited by the present invention. The sending module (202) of the present invention may also be other types of sending modules, such as a sending module supporting DP / eDP, MIPI, HDMI and other protocols, which is not limited by the present invention.

[0114] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

[0115] In summary, the present invention fully meets the needs of industrial development in terms of structural design, practicality and cost-effectiveness, and the disclosed structure also has an unprecedented innovative structure with novelty, creativity and practicality, and complies with the provisions of relevant new patent requirements, so an application is filed in accordance with the law.

Claims

1. An LVDS transmission system, characterized in that: The LVDS transmission system includes an LVDS transmitting device and a first receiving device, wherein the LVDS transmitting device is connected to the first receiving device via a first LVDS bus. The first LVDS bus includes an LVDS clock line and a plurality of LVDS data lines, The LVDS transmitting device transmits data to the first receiving device via the first LVDS bus, The first receiving device includes an LVDS alignment module, which is used to eliminate delay deviations of an LVDS clock line and multiple LVDS data lines and receive data from a first LVDS bus.

2. An LVDS transmission system according to claim 1, characterized in that: The LVDS alignment module includes a phase-locked loop module, which is connected to the LVDS clock line and uses the LVDS clock line as the phase-locked loop module reference clock to generate one or more sampling clocks for sampling data transmitted on the LVDS data line.

3. An LVDS transmission system according to claim 2, characterized in that: The LVDS alignment module includes one or more data line delay modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is: the one or more data line delay modules respectively delay one or more LVDS data lines so that the sampling clock can correctly sample the data.

4. The LVDS transmission system according to claim 2, wherein: The LVDS alignment module also includes a reference clock delay module. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the reference clock delay module delays the reference clock of the phase-locked loop module, thereby delaying the sampling clock so that the sampling clock can correctly sample data.

5. The LVDS transmission system according to claim 2, wherein: The LVDS alignment module further includes one or more sampling clock phase adjustment modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more sampling clock phase adjustment modules adjust the phase of one or more sampling clocks so that the sampling clocks can correctly sample data.

6. The LVDS transmission system according to claim 1, wherein: The LVDS transmitting device is also connected to the first receiving device via a control bus, and the LVDS transmitting device controls the LVDS alignment module via the control bus.

7. The LVDS transmission system according to claim 1, wherein: The LVDS transmission system further includes a second receiving device, and the first receiving device further includes a sending module, which is connected to the second receiving device. The first receiving device forwards data received from the first LVDS bus to the second receiving device through the sending module.

8. The LVDS transmission system according to claim 7, wherein: The transmitting module included in the first receiving device is an LVDS transmitting module, and the LVDS transmitting module is connected to the second receiving device via a second LVDS bus.

9. The LVDS transmission system according to claim 8, wherein: The number of LVDS data lines included in the second LVDS bus is twice the number of LVDS data lines included in the first LVDS bus, and the transmission rate of the LVDS data lines included in the second LVDS bus is half the transmission rate of the LVDS data lines included in the first LVDS bus.

10. The LVDS transmission system according to claim 1, wherein: In each clock cycle of the LVDS clock line, one or more pixel point data are transmitted on the LVDS data line.

11. A first receiving device, comprising an LVDS alignment module, characterized in that: The first receiving device is connected to the LVDS transmitting device via a first LVDS bus. The first LVDS bus includes an LVDS clock line and a plurality of LVDS data lines, The LVDS transmitting device transmits data to the first receiving device via the first LVDS bus, The LVDS alignment module is used to eliminate delay deviations of an LVDS clock line and multiple LVDS data lines and receive data from a first LVDS bus.

12. The first receiving device according to claim 11, characterized in that: The LVDS alignment module includes a phase-locked loop module, which is connected to the LVDS clock line and uses the LVDS clock line as the phase-locked loop module reference clock to generate one or more sampling clocks for sampling data transmitted on the LVDS data line.

13. The first receiving device according to claim 12, wherein: The LVDS alignment module includes one or more data line delay modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is: the one or more data line delay modules respectively delay one or more LVDS data lines so that the sampling clock can correctly sample the data.

14. The first receiving device according to claim 12, wherein: The LVDS alignment module also includes a reference clock delay module. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the reference clock delay module delays the reference clock of the phase-locked loop module, thereby delaying the sampling clock so that the sampling clock can correctly sample data.

15. The first receiving device according to claim 12, wherein: The LVDS alignment module further includes one or more sampling clock phase adjustment modules. The method by which the LVDS alignment module eliminates the delay deviation of the LVDS clock line and multiple LVDS data lines is as follows: the one or more sampling clock phase adjustment modules adjust the phase of one or more sampling clocks so that the sampling clocks can correctly sample data.

16. The first receiving device according to claim 11, wherein: The LVDS transmitting device is also connected to the first receiving device via a control bus, and the LVDS transmitting device controls the LVDS alignment module via the control bus.

17. The first receiving device according to claim 11, wherein: The first receiving device further includes a sending module, which is connected to the second receiving device. The first receiving device forwards data received from the first LVDS bus to the second receiving device through the sending module.

18. The first receiving device according to claim 17, wherein: The transmitting module included in the first receiving device is an LVDS transmitting module, and the LVDS transmitting module is connected to the second receiving device via a second LVDS bus.

19. The first receiving device according to claim 18, wherein: The number of LVDS data lines included in the second LVDS bus is twice the number of LVDS data lines included in the first LVDS bus, and the transmission rate of the LVDS data lines included in the second LVDS bus is half the transmission rate of the LVDS data lines included in the first LVDS bus.

20. The first receiving device according to claim 11, wherein: In each clock cycle of the LVDS clock line, one or more pixel point data are transmitted on the LVDS data line.

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