LED load transient control circuit and control method thereof
By designing the LED load transient control circuit, sampling the slope of the output voltage and controlling the driving capability of the buffer, the current overshoot and undershoot problems during transient switching of the LED load is solved, and the stable driving of the LED string is achieved.
Patent Information
- Application Number
- CN202411930938.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-06-06
- Estimated Expiration
- 2044-12-26
AI Technical Summary
The current overshoot and undershoot problems caused by transient switching of LED loads, resulting in damage to the LED string or darkening of the brightness.
A LED load transient control circuit is designed, including a VOUT voltage slope sampling circuit, a buffer pull-up circuit, a buffer pull-down circuit and a buffer Buffer. By sampling the drop and rising slopes of the output voltage, it is converted into a voltage signal VSLP, and compared with the reference voltage VREF1, VREF2, and VREF3, the driving capability of the external short-circuit MSHUNT drive stage Buffer is controlled, thereby adjusting the slope of the LED driving voltage VOUT.
Effectively control the overshoot and undershoot of the LED driving current to prevent the LED string from being damaged and keep the LED brightness stable.
Smart Images

Figure CN119584380B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a control circuit and a control method thereof, in particular to an LED load transient control circuit and a control method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art
[0002] The LED headlights of cars integrate high beam (HB) and low beam (LB) into a single headlight group. Figure 2 and Figure 3 As shown, an LED driver is required for multi-beam applications. However, when switching from a LED string with a higher number of LEDs to a LED string with a lower number of LEDs, there will be a current overshoot problem due to the discharge of the output capacitor. In severe cases, this current overshoot will damage the LED string. Similarly, when switching from a LED string with a lower number of LEDs, there will be a current undershoot problem due to the charging of the output capacitor. This current overshoot will cause the LED string to dim or even go out.
[0003] For this current overshoot and undershoot, traditional solutions, such as Figure 4 As shown in the figure, the slow switch method is adopted to increase the Miller capacitance of the parallel MOS tube, so that the MOS tube is turned on and off more slowly, so that the output voltage VOUT voltage drops and rises slowly, thereby reducing the output capacitor discharge and charging current. This method requires additional off-chip capacitors, which increases the system's BOM cost and PCB area, and the output voltage VOUT voltage drop slope is difficult to control.
[0004] In summary, it is necessary to design a low-cost and flexible LED load transient control system to solve the current overshoot and undershoot problems of LED lamps. Summary of the invention
[0005] The technical problem to be solved by the present invention is to provide an LED load transient control circuit and a control method thereof, so as to solve the current overshoot and undershoot problems caused by transient switching of the LED load.
[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:
[0007] An LED load transient control circuit, comprising V OUT Voltage slope sampling circuit, buffer pull-up circuit, buffer pull-down circuit and buffer Buffer, V OUT The first input terminal of the voltage slope sampling circuit is connected to the LED driving voltage V OUT , V OUT The second input terminal of the voltage slope sampling circuit is connected to the reference voltage VREF1 , V OUT The output end of the voltage slope sampling circuit is connected to the first input end of the buffer pull-up circuit and generates a voltage signal V SLP The second input terminal of the buffer pull-up circuit is connected to the reference voltage V REF2 The output end of the buffer pull-up circuit is connected to the pull-up current end of the buffer Buffer, and the first input end of the buffer pull-down circuit is connected to the reference voltage V REF3 The second input terminal of the buffer pull-down circuit is connected to the voltage signal V SLP The output end of the buffer pull-down circuit is connected to the pull-down current end of the buffer Buffer, the input end of the buffer Buffer is connected to the control signal Shunt, and the output end of the buffer Buffer is connected to the external short-circuit M SHUNT of the gate.
[0008] Furthermore, the V OUT The voltage slope sampling circuit includes capacitor C1, resistor R1 and operational amplifier OP1. One end of capacitor C1 is used as V OUT The first input terminal of the voltage slope sampling circuit is connected to the LED drive voltage V OUT The other end of capacitor C1 is connected to the inverting input of operational amplifier OP1 and one end of resistor R1. The non-inverting input of operational amplifier OP1 is used as V OUT The second input terminal of the voltage slope sampling circuit is connected to the reference voltage V REF1 The output of the operational amplifier OP1 is connected to the other end of the resistor R1 and serves as V OUT The output end of the voltage slope sampling circuit generates a voltage signal V SLP .
[0009] Furthermore, the voltage signal V SLP With LED drive voltage V OUT The slope information.
[0010] Furthermore, the buffer pull-up circuit comprises an operational amplifier OP2, a capacitor C2, an NMOS tube MN1, a PMOS tube MP1, a PMOS tube MP2 and a resistor R2, and the inverting input terminal of the operational amplifier OP2 serves as the first input terminal of the buffer pull-up circuit and is connected to the voltage signal V SLP The non-inverting input terminal of the operational amplifier OP2 is used as the second input terminal of the buffer pull-up circuit and is connected to the reference voltage V REF2The output end of the operational amplifier OP2 is connected to one end of the capacitor C2 and the gate of the NMOS tube MN1 at the node A. The source of the NMOS tube MN1 is connected to one end of the resistor R2. The drain of the NMOS tube MN1 is connected to the drain of the PMOS tube MP1, the gate of the PMOS tube MP1 and the gate of the PMOS tube MP2. The source of the PMOS tube MP1 and the source of the PMOS tube MP2 are connected to the power supply V CC The drain of the PMOS tube MP2 serves as the output end of the buffer pull-up circuit and generates a pull-up current I SOURCE , the other end of the capacitor C2 and the other end of the resistor R2 are grounded.
[0011] Furthermore, the buffer pull-down circuit comprises an operational amplifier OP3, a capacitor C3, an NMOS tube MN2, a PMOS tube MP3, a PMOS tube MP4, a resistor R3, an NMOS tube MN3 and an NMOS tube MN4, and the non-inverting input terminal of the operational amplifier OP3 serves as the first input terminal of the buffer pull-down circuit and is connected to the reference voltage V REF3 The inverting input terminal of the operational amplifier OP3 is used as the second input terminal of the buffer pull-down circuit and is connected to the voltage signal V SLP The output end of the operational amplifier OP3 is connected to one end of the capacitor C3 and the gate of the NMOS tube MN2 at the node B. The source of the NMOS tube MN2 is connected to one end of the resistor R3. The drain of the NMOS tube MN2 is connected to the drain of the PMOS tube MP3, the gate of the PMOS tube MP3 and the gate of the PMOS tube MP4. The source of the PMOS tube MP3 and the source of the PMOS tube MP4 are connected to the power supply V CC The drain of the PMOS tube MP4 is connected to the drain of the NMOS tube MN3, the gate of the NMOS tube MN3 and the gate of the NMOS tube MN4. The drain of the NMOS tube MN4 serves as the output end of the buffer pull-down circuit and generates a pull-down current I SINK The other end of the capacitor C3, the other end of the resistor R3, the source of the NMOS transistor MN3 and the source of the NMOS transistor MN4 are grounded.
[0012] A control method for an LED load transient control circuit comprises the following steps:
[0013] When the LED driving voltage V OUT When descending:
[0014] V SLP =V REF1 +C 1 *|dV OUT / dt|, due to the negative feedback loop control, we get V SLP =V REF2 , so the LED driving voltage V OUT The downward slope
[0015] |dV OUT / dt|=(V REF2 -V REF1 ) / C 1 ;
[0016] When the LED driving voltage V OUT When rising:
[0017] V SLP =V REF1 -C 1 *|dV OUT / dt|, due to the negative feedback loop control, we get V SLP =V REF3 , so the LED driving voltage V OUT The rising slope
[0018] |dV OUT / dt|=(V REF1 -V REF3 ) / C 1 ;
[0019] By changing the reference voltage V REF1 , reference voltage V REF2 , reference voltage V REF3 The value of adjusting the LED driving voltage V OUT The rising and falling slopes of the LED drive current I LED The overshoot and undershoot size.
[0020] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides an LED load transient control circuit and a control method thereof, which converts the falling and rising slopes of the output voltage into a voltage having a V OUT Slope information voltage V SLP and the reference voltage V REF1 、V REF2 Compare and convert into current I SOURCE and I SINK , control external short-circuit M SHUNT的 The driving capability of the driver-level buffer controls V OUT Falling and rising slopes; by changing the reference voltage V REF2 and V REF3 The size of V OUT The falling slope and rising slope are improved to solve the current overshoot and undershoot problems caused by transient switching of LED load. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a schematic diagram of an LED load transient control circuit of the present invention.
[0022] Figure 2 It is a schematic diagram of a driving circuit of an LED headlight assembly in the prior art.
[0023] Figure 3 It is a waveform diagram of current overshoot and undershoot generated by switching between high and low beams in the LED headlight group driving circuit of the prior art.
[0024] Figure 4 The present invention is a schematic diagram of a circuit for alleviating overshoot and undershoot by using a slow switching method in the prior art. DETAILED DESCRIPTION
[0025] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.
[0026] like Figure 1 As shown, the LED load transient control circuit of the present invention comprises V OUT Voltage slope sampling circuit, buffer pull-up circuit, buffer pull-down circuit and buffer Buffer, V OUT The first input terminal of the voltage slope sampling circuit is connected to the LED driving voltage V OUT , V OUT The second input terminal of the voltage slope sampling circuit is connected to the reference voltage V REF1 , V OUT The output end of the voltage slope sampling circuit is connected to the first input end of the buffer pull-up circuit and generates a voltage signal V SLP The second input terminal of the buffer pull-up circuit is connected to the reference voltage V REF2 The output end of the buffer pull-up circuit is connected to the pull-up current end of the buffer Buffer, and the first input end of the buffer pull-down circuit is connected to the reference voltage V REF3 The second input terminal of the buffer pull-down circuit is connected to the voltage signal V SLP The output end of the buffer pull-down circuit is connected to the pull-down current end of the buffer Buffer, the input end of the buffer Buffer is connected to the control signal Shunt, and the output end of the buffer Buffer is connected to the external short-circuit M SHUNT of the gate.
[0027] V OUT The voltage slope sampling circuit includes capacitor C1, resistor R1 and operational amplifier OP1. One end of capacitor C1 is used as V OUTThe first input terminal of the voltage slope sampling circuit is connected to the LED drive voltage V OUT The other end of capacitor C1 is connected to the inverting input of operational amplifier OP1 and one end of resistor R1. The non-inverting input of operational amplifier OP1 is used as V OUT The second input terminal of the voltage slope sampling circuit is connected to the reference voltage V REF1 The output of the operational amplifier OP1 is connected to the other end of the resistor R1 and serves as V OUT The output end of the voltage slope sampling circuit generates a voltage signal V SLP .
[0028] Voltage signal V SLP With LED drive voltage V OUT The slope information.
[0029] The buffer pull-up circuit comprises an operational amplifier OP2, a capacitor C2, an NMOS tube MN1, a PMOS tube MP1, a PMOS tube MP2 and a resistor R2. The inverting input terminal of the operational amplifier OP2 is used as the first input terminal of the buffer pull-up circuit and is connected to the voltage signal V SLP The non-inverting input terminal of the operational amplifier OP2 is used as the second input terminal of the buffer pull-up circuit and is connected to the reference voltage V REF2 The output end of the operational amplifier OP2 is connected to one end of the capacitor C2 and the gate of the NMOS tube MN1 at the node A. The source of the NMOS tube MN1 is connected to one end of the resistor R2. The drain of the NMOS tube MN1 is connected to the drain of the PMOS tube MP1, the gate of the PMOS tube MP1 and the gate of the PMOS tube MP2. The source of the PMOS tube MP1 and the source of the PMOS tube MP2 are connected to the power supply V CC The drain of the PMOS tube MP2 serves as the output end of the buffer pull-up circuit and generates a pull-up current I SOURCE , the other end of capacitor C2 and the other end of resistor R2 are grounded. SOURCE Determine the external short-circuit M SHUNT The pull-up capability of the gate-level buffer.
[0030] The buffer pull-down circuit comprises an operational amplifier OP3, a capacitor C3, an NMOS tube MN2, a PMOS tube MP3, a PMOS tube MP4, a resistor R3, an NMOS tube MN3 and an NMOS tube MN4. The positive input terminal of the operational amplifier OP3 is used as the first input terminal of the buffer pull-down circuit and is connected to the reference voltage V REF3 The inverting input terminal of the operational amplifier OP3 is used as the second input terminal of the buffer pull-down circuit and is connected to the voltage signal V SLPThe output end of the operational amplifier OP3 is connected to one end of the capacitor C3 and the gate of the NMOS tube MN2 at the node B. The source of the NMOS tube MN2 is connected to one end of the resistor R3. The drain of the NMOS tube MN2 is connected to the drain of the PMOS tube MP3, the gate of the PMOS tube MP3 and the gate of the PMOS tube MP4. The source of the PMOS tube MP3 and the source of the PMOS tube MP4 are connected to the power supply V CC The drain of the PMOS tube MP4 is connected to the drain of the NMOS tube MN3, the gate of the NMOS tube MN3 and the gate of the NMOS tube MN4. The drain of the NMOS tube MN4 serves as the output end of the buffer pull-down circuit and generates a pull-down current I SINK The other end of the capacitor C3, the other end of the resistor R3, the source of the NMOS transistor MN3 and the source of the NMOS transistor MN4 are grounded. SINK Determine the external short-circuit M SHUNT The pull-down capability of the gate-level buffer.
[0031] A control method for an LED load transient control circuit comprises the following steps:
[0032] When the LED driving voltage V OUT When descending:
[0033] V SLP =V REF1 +C 1 *|dV OUT / dt|, due to the negative feedback loop control, we get V SLP =V REF2 , so the LED driving voltage V OUT The downward slope
[0034] |dV OUT / dt|=(V REF2 -V REF1 ) / C 1 ;
[0035] When the LED driving voltage V OUT When rising:
[0036] V SLP =V REF1 -C 1 *|dV OUT / dt|, due to the negative feedback loop control, we get V SLP =V REF3 , so the LED driving voltage V OUT The rising slope
[0037] |dV OUT / dt|=(V REF1 -VREF3 ) / C 1 ;
[0038] By changing the reference voltage V REF1 , reference voltage V REF2 , reference voltage V REF3 The value of adjusting the LED driving voltage V OUT The rising and falling slopes of the LED drive current I LED The overshoot and undershoot size.
[0039] The present invention provides an LED load transient control circuit and a control method thereof, which converts the falling and rising slopes of the output voltage into a voltage having a V OUT Slope information voltage V SLP and the reference voltage V REF1 、V REF2 Compare and convert into current I SOURCE and I SINK , control external short-circuit M SHUNT的 The driving capability of the driver-level buffer controls V OUT Falling and rising slopes; by changing the reference voltage V REF2 and V REF3 The size of V OUT The falling slope and rising slope are improved to solve the current overshoot and undershoot problems caused by transient switching of LED load.
[0040] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.
Claims
1. An LED load transient control circuit, characterized in that: Contains V OUT Voltage slope sampling circuit, buffer pull-up circuit, buffer pull-down circuit and buffer Buffer, V OUT The first input terminal of the voltage slope sampling circuit is connected to the LED driving voltage V OUT , V OUT The second input terminal of the voltage slope sampling circuit is connected to the reference voltage V REF1 , V OUT The output end of the voltage slope sampling circuit is connected to the first input end of the buffer pull-up circuit and generates a voltage signal V SLP The second input terminal of the buffer pull-up circuit is connected to the reference voltage V REF2 The output end of the buffer pull-up circuit is connected to the pull-up current end of the buffer Buffer, and the first input end of the buffer pull-down circuit is connected to the reference voltage V REF3 The second input terminal of the buffer pull-down circuit is connected to the voltage signal V SLP The output end of the buffer pull-down circuit is connected to the pull-down current end of the buffer Buffer, the input end of the buffer Buffer is connected to the control signal Shunt, and the output end of the buffer Buffer is connected to the external short-circuit M SHUNT The gate of When the LED driving voltage V OUT When descending: V SLP =V REF1 +C1*|dV OUT / dt|, due to the negative feedback loop control, we get V SLP =V REF2 , so the LED driving voltage V OUT The downward slope |dV OUT / dt|=(V REF2 -V REF1 ) / C1; When the LED driving voltage V OUT When rising: V SLP =V REF1 -C1*|dV OUT / dt|, due to the negative feedback loop control, we get V SLP =V REF3 , so the LED driving voltage V OUT The rising slope |dV OUT / dt|=(V REF1 -V REF3 ) / C1; By changing the reference voltage V REF1 , reference voltage V REF2 , reference voltage V REF3 The value of adjusting the LED driving voltage V OUT The rising and falling slopes of the LED drive current I LED The overshoot and undershoot size.
2. The LED load transient control circuit according to claim 1, characterized in that: The V OUT The voltage slope sampling circuit includes capacitor C1, resistor R1 and operational amplifier OP1. One end of capacitor C1 is used as V OUT The first input terminal of the voltage slope sampling circuit is connected to the LED drive voltage V OUT The other end of capacitor C1 is connected to the inverting input of operational amplifier OP1 and one end of resistor R1. The non-inverting input of operational amplifier OP1 is used as V OUT The second input terminal of the voltage slope sampling circuit is connected to the reference voltage V REF1 The output of the operational amplifier OP1 is connected to the other end of the resistor R1 and serves as V OUT The output end of the voltage slope sampling circuit generates a voltage signal V SLP .
3. The LED load transient control circuit according to claim 2, characterized in that: The voltage signal V SLP With LED drive voltage V OUT The slope information.
4. The LED load transient control circuit according to claim 1, characterized in that: The buffer pull-up circuit comprises an operational amplifier OP2, a capacitor C2, an NMOS tube MN1, a PMOS tube MP1, a PMOS tube MP2 and a resistor R2. The inverting input terminal of the operational amplifier OP2 serves as the first input terminal of the buffer pull-up circuit and is connected to the voltage signal V SLP The non-inverting input terminal of the operational amplifier OP2 is used as the second input terminal of the buffer pull-up circuit and is connected to the reference voltage V REF2 The output end of the operational amplifier OP2 is connected to one end of the capacitor C2 and the gate of the NMOS tube MN1 at the node A. The source of the NMOS tube MN1 is connected to one end of the resistor R2. The drain of the NMOS tube MN1 is connected to the drain of the PMOS tube MP1, the gate of the PMOS tube MP1 and the gate of the PMOS tube MP2. The source of the PMOS tube MP1 and the source of the PMOS tube MP2 are connected to the power supply V CC The drain of the PMOS tube MP2 serves as the output end of the buffer pull-up circuit and generates a pull-up current I SOURCE , the other end of the capacitor C2 and the other end of the resistor R2 are grounded.
5. The LED load transient control circuit according to claim 1, characterized in that: The buffer pull-down circuit comprises an operational amplifier OP3, a capacitor C3, an NMOS transistor MN2, a PMOS transistor MP3, a PMOS transistor MP4, a resistor R3, an NMOS transistor MN3 and an NMOS transistor MN4. The positive input terminal of the operational amplifier OP3 is used as the first input terminal of the buffer pull-down circuit and is connected to a reference voltage V REF3 The inverting input terminal of the operational amplifier OP3 is used as the second input terminal of the buffer pull-down circuit and is connected to the voltage signal V SLP The output end of the operational amplifier OP3 is connected to one end of the capacitor C3 and the gate of the NMOS tube MN2 at the node B. The source of the NMOS tube MN2 is connected to one end of the resistor R3. The drain of the NMOS tube MN2 is connected to the drain of the PMOS tube MP3, the gate of the PMOS tube MP3 and the gate of the PMOS tube MP4. The source of the PMOS tube MP3 and the source of the PMOS tube MP4 are connected to the power supply V CC The drain of the PMOS tube MP4 is connected to the drain of the NMOS tube MN3, the gate of the NMOS tube MN3 and the gate of the NMOS tube MN4. The drain of the NMOS tube MN4 serves as the output end of the buffer pull-down circuit and generates a pull-down current I SINK The other end of the capacitor C3, the other end of the resistor R3, the source of the NMOS transistor MN3 and the source of the NMOS transistor MN4 are grounded.
Citation Information
Patent Citations
Output buffer, gate driving circuit and control method of gate driving circuit
CN103944553A
Differential current mode analog front-end circuit for capacitive touch sensing in touchscreen panels
CN106648198A