Printed circuit board and method of manufacturing the same

Abstract

The invention provides a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a first insulating layer; a first wiring layer embedded in the first insulating layer on one side of the first insulating layer; the glass layer is arranged on the other side, opposite to the side, of the first insulating layer; the second wiring layer is arranged on the glass layer; and a first via layer connecting the first wiring layer and the second wiring layer to each other and including a first via portion penetrating the glass layer and a second via portion penetrating the first insulating layer. In a cross-sectional view of the printed circuit board, at least one of the first via portion and the second via portion has a width substantially narrowing toward the first wiring layer.

Description

[0001] This application claims the benefit of priority of Korean Patent Application No. 10-2023-0118607 filed on September 6, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0192933 filed on December 27, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board and a method for manufacturing the printed circuit board. Background Art

[0003] In order to process data that is increasing exponentially due to the recent development of artificial intelligence (AI) technology and the like, multi-chip packages including memory chips such as high bandwidth memory (HBM) and processor chips such as central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs) are being used. Therefore, substrates with large-area structures are required, and efforts are continuing to overcome problems involving flatness and warpage control. Summary of the invention

[0004] An aspect of the present disclosure may provide a printed circuit board including a glass layer and a method of manufacturing the printed circuit board.

[0005] Another aspect of the present disclosure may provide a printed circuit board having improved flatness and capable of preventing warping, and a method of manufacturing the printed circuit board.

[0006] Another aspect of the present disclosure may provide a printed circuit board capable of improving reliability and a method of manufacturing the printed circuit board.

[0007] According to one aspect of the present disclosure, a printed circuit board may include: a first insulating layer; a first wiring layer embedded in the first insulating layer on one side of the first insulating layer; a glass layer disposed on the other side of the first insulating layer opposite to the one side; a second wiring layer disposed on the glass layer; and a first via layer connecting the first wiring layer and the second wiring layer to each other and including a first via portion penetrating the glass layer and a second via portion penetrating the first insulating layer. In a cross-sectional view of the printed circuit board, at least one of the first via portion and the second via portion may have a width that is substantially gradually narrowed toward the first wiring layer.

[0008] According to another aspect of the present disclosure, a printed circuit board may include: an insulating layer; a first wiring layer disposed on one side of the insulating layer; a glass layer disposed on the other side of the insulating layer opposite to the one side; a via layer including a first through-hole, a second through-hole, a portion of a first metal layer, and a portion of a second metal layer, the second through-hole penetrating the insulating layer and exposing at least a portion of the first wiring layer, the first through-hole penetrating the glass layer and connected to the second through-hole, the portion of the first metal layer disposed on the at least partially exposed portion of the first wiring layer and a wall of each of the first through-hole and the second through-hole, the portion of the second metal layer disposed on the first metal layer and filling at least a portion of each of the first through-hole and the second through-hole; and a second wiring layer disposed on the glass layer and connected to the via layer.

[0009] According to another aspect of the present disclosure, a method for manufacturing a printed circuit board may include: forming a first insulating layer in which a first wiring layer is embedded; forming a glass layer on the first insulating layer; forming a first through hole penetrating the glass layer; forming a second through hole penetrating the first insulating layer and exposing at least a portion of the first wiring layer; forming a first via layer in the first through hole and the second through hole; and forming a second wiring layer connected to the first via layer on the glass layer.

[0010] According to another aspect of the present disclosure, a printed circuit board may include: a first insulating layer; a glass layer disposed on the first insulating layer; a plurality of wiring layers including a first wiring layer attached to the first insulating layer and a second wiring layer disposed on the glass layer; and a via layer connecting the first wiring layer and the second wiring layer to each other and including a first via portion disposed in the glass layer and a second via portion extending from the first via portion and disposed in the first insulating layer. The surface roughness of one surface of the glass layer opposite to the first insulating layer may be less than the surface roughness of another surface of the glass layer opposite to the one surface of the glass layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram illustrating an example of an electronic device system; Figure 2 is a schematic perspective view showing an example of an electronic device; Figure 3 is a schematic cross-sectional view of a portion of a printed circuit board according to a first exemplary embodiment; FIG. 4A to FIG. 4Cis a schematic cross-sectional view showing a part of a method of manufacturing a printed circuit board according to a first exemplary embodiment; FIG. 5A to FIG. 5J is a schematic cross-sectional view showing a portion of a printed circuit board and a method of manufacturing the printed circuit board according to first to tenth modifications of the first exemplary embodiment; Figure 5K It shows that according to Fig.5I A ninth variation of the first exemplary embodiment shown in Figure 5J A plan view of a portion of a method of manufacturing a printed circuit board according to a tenth variation of the first exemplary embodiment shown in FIG. Figure 6 is a schematic cross-sectional view of a portion of a printed circuit board according to a second exemplary embodiment; FIG. 7A to FIG. 7C is a schematic cross-sectional view showing a part of a method of manufacturing a printed circuit board according to a second exemplary embodiment; Figure 8 shows a schematic cross-sectional view of a portion of a printed circuit board and a method of manufacturing the printed circuit board according to a first modification of the second exemplary embodiment; Fig. 9 is a schematic cross-sectional view of a portion of a printed circuit board according to a third exemplary embodiment; FIG. 10A to FIG. 10C is a schematic cross-sectional view showing a part of a method of manufacturing a printed circuit board according to a third exemplary embodiment; Fig.11A and Fig. 11B is a schematic cross-sectional view showing a portion of a printed circuit board and a method of manufacturing the printed circuit board according to a first modification and a second modification of the third exemplary embodiment; FIG. 12A to FIG. 12E Schematic cross-sectional views showing printed circuit boards according to first to fifth application examples of the first exemplary embodiment; FIG. 13A to FIG. 13D It shows the manufacturing Fig. 12A A schematic cross-sectional view of a method for printing a circuit board according to a first application example of the first exemplary embodiment shown in FIG. FIG. 14A to FIG. 14D It shows the manufacturing Fig. 12B A schematic cross-sectional view of a method for printing a circuit board according to a second application example of the first exemplary embodiment shown in FIG. Fig.15A and Fig. 15B schematic cross-sectional views showing printed circuit boards according to sixth and seventh application examples of the first exemplary embodiment; and FIG. 16A to FIG. 16D It shows the manufacturing Fig.15ASchematic cross-sectional view of a method of printing a circuit board according to a sixth application example of the first exemplary embodiment is shown in FIG. DETAILED DESCRIPTION

[0012] Exemplary embodiments of the present disclosure will now be described in detail hereinafter with reference to the accompanying drawings.

[0013] Electronic Devices Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0014] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the mainboard 1010. These components may be connected to other electronic components to be described below through various signal lines 1090.

[0015] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM) or flash memory); application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors or microcontrollers; and logic chips, such as analog-to-digital converters or application-specific integrated circuits (ASICs). The chip-related components 1020 are not limited thereto, but may also include other types of chip-related electronic components. In addition, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0016] The network-related components 1030 may include components compatible with or operating according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) Protocol, Fourth Generation Mobile Communication Technology (4G) Protocol, and Fifth Generation Mobile Communication Technology (5G) Protocol, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include components compatible with or operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0017] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, but may also include passive components of a chip component type for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. Examples of other electronic components may include a camera 1050, an antenna 1060, a display 1070, a battery 1080, and the like. The other electronic components are not limited thereto, but may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes, and the like.

[0019] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto but may be any other electronic device capable of processing data.

[0020] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0021] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board having electronic components (including active components and / or passive components) mounted on its upper surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are embedded. In addition, the electronic device is not necessarily limited to the smart phone 1100, and may be any other electronic device as described above.

[0022] Printed circuit board and method for manufacturing the same Figure 3 is a schematic cross-sectional view of a portion of a printed circuit board according to a first exemplary embodiment. Specifically, Figure 3 1 is a cross-sectional view showing an insulating structure between a first wiring layer 121 and a second wiring layer 122 of the printed circuit board according to the first exemplary embodiment.

[0023] Reference Figure 3 The printed circuit board according to the first exemplary embodiment may include a first insulating layer 111, a first wiring layer 121 embedded in one side of the first insulating layer 111, a glass layer 110 disposed on the other side of the first insulating layer 111 opposite to the one side, a second wiring layer 122 disposed on the glass layer 110, and a first via layer 130 connecting the first wiring layer 121 and the second wiring layer 122 to each other, and the first via layer 130 includes a first via portion 131 penetrating the glass layer 110 and a second via portion 132 penetrating the first insulating layer 111. The first via layer 130 may include a seed layer 125 and a plating layer 126.

[0024] The printed circuit board according to the first exemplary embodiment may include a first insulating layer 111 and a glass layer 110 between a first wiring layer 121 and a second wiring layer 122. That is, the insulating structure between the first wiring layer 121 and the second wiring layer 122 in the printed circuit board according to the first exemplary embodiment is not constituted by a single layer or a separate organic insulating layer, but may include the glass layer 110 therein. Since the glass layer 110 is included in the insulating structure between the first wiring layer 121 and the second wiring layer 122, the printed circuit board may be excellent in flatness and may resist warping during a manufacturing stage.

[0025] The printed circuit board according to the first exemplary embodiment may not use the glass layer 110 as a core, but may include the glass layer 110 and the first insulating layer 111 as a buildup layer. Figure 3 , other build-up insulating layers may be additionally provided on the upper and lower sides, a core layer may be additionally provided on the lower side, or a solder resist layer may be provided on the lower side, so that the first wiring layer 121 is provided on the outermost side of the printed circuit board with the embedded pattern to form a so-called coreless printed circuit board. Figure 3 Only an insulating structure between the first wiring layer 121 and the second wiring layer 122 and an interlayer connection using the first via layer 130 are shown, and modifications thereof, other exemplary embodiments, and various examples of application to a printed circuit board will be described later with reference to other drawings.

[0026] The first insulating layer 111 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric exemplified by glass cloth) and a resin. For example, the insulating material may be a non-photosensitive insulating material such as an Ajinomoto built-up film (ABF) or a prepreg (PPG), but is not limited thereto, and another type of polymer material may be used as the insulating material. Alternatively, the insulating material may be a photosensitive insulating material such as a photosensitive dielectric (PID). In addition, the insulating material may include an adhesive sheet such as a bonding sheet (BS). Specifically, the first insulating layer 111 may preferably include an Ajinomoto built-up film (ABF), but is not limited thereto, and may include another organic insulating material. In addition, the first insulating layer 111 may be formed on Figure 3 The first insulating layer 111 is shown as one insulating layer, but is not necessarily limited thereto. If necessary, the first insulating layer 111 may be composed of a plurality of insulating layers, and may also include a configuration that can be used by those skilled in the art.

[0027] The first wiring layer 121 may be embedded in one side of the first insulating layer 111. That is, the first wiring layer 121 may be provided on one side of the first insulating layer 111 so that one surface of the first wiring layer 121 is exposed from one surface of the first insulating layer 111. At this time, the exposure of one surface of the first wiring layer 121 from one surface of the first insulating layer 111 means that one surface of the first wiring layer 121 is not covered by the first insulating layer 111. Even if one surface of the first wiring layer 121 is covered by another component further included under the first insulating layer 111, this may be understood to have the same meaning as described above. That is, this may mean that one surface of the first wiring layer 121 is not covered by the first insulating layer 111, and the other surface of the first wiring layer 121 opposite to the one surface and the side surface of the first wiring layer 121 are covered by the first insulating layer 111. At this time, unless another adhesive member is additionally included between the first wiring layer 121 and the first insulating layer 111, the other surface and the side surface of the first wiring layer 121 may be in contact with the first insulating layer 111.

[0028] The first wiring layer 121 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The first wiring layer 121 may preferably include copper (Cu), but is not limited thereto.

[0029] The first wiring layers 121 may each perform various functions according to the design. For example, the first wiring layer 121 may include a signal pattern, a power pattern, a ground pattern, etc. Each of these patterns may have various forms, such as a line, a plane, and a pad. The first wiring layer 121 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the first wiring layer 121 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the first wiring layer 121 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). The first wiring layer 121 may include a sputtering layer without an electroless plating layer (e.g., a chemical copper plating layer), or if necessary, the first wiring layer 121 may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer).

[0030] The first wiring layer 121 may be formed using any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-tightening (TT) process, and a subtractive process, but is not limited thereto. Any technology may be used without limitation as long as the technology can construct a circuit on a printed circuit board. In addition, the first wiring layer 121 may be formed using different technologies according to the purpose of use and design.

[0031] The glass layer 110 may include glass (amorphous solid). For example, the glass may include pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, the glass layer 110 is not limited thereto, and optional glass materials such as fluorine glass, phosphate glass, or chalcogenide glass may also be used as materials for the glass layer 110. In addition, the glass layer 110 may also include other additives to form glass with specific physical properties. These additives may include magnesium, sodium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates of these and other elements (such as calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda)) and / or oxides. The glass layer 110 is a layer that is distinguished from a material including glass fiber (e.g., glass fabric exemplified by glass cloth) or the like (such as copper clad laminate (CCL) or prepreg (PPG)), and may be understood as, for example, plate glass or glass sheet.

[0032] The printed circuit board including the glass layer 110 according to the first exemplary embodiment may be basically excellent in flatness, and may also be advantageous in controlling warpage by a low coefficient of thermal expansion (CTE) and the like. In particular, since the printed circuit board according to the first exemplary embodiment may have the glass layer 110 as part of the buildup layer, this may be more advantageous in controlling warpage even in the subsequent step of stacking another insulating layer. That is, even if other insulating layers are sequentially stacked on the glass layer 110, flatness can be further improved, which is more advantageous in forming a high-density fine circuit with a fine pitch. In particular, unlike the case where the glass layer 110 is used as a core layer, the glass layer 110 may be included in a coreless substrate, which is advantageous in controlling warpage (a problem of the coreless substrate). In addition, the glass layer 110 used in the coreless substrate may also be able to control warpage, thereby increasing reliability, for example, realizing an asymmetric substrate.

[0033] In addition, the glass layer 110 can reduce the number of layers in the printed circuit board and further increase the degree of freedom in design by virtue of the feature that the glass has variable dielectric properties (eg, Dk (dielectric constant) of 2.5 to 11).

[0034] The second wiring layer 122 may be included on the glass layer 110. The second wiring layer 122 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The second wiring layer 122 may preferably include copper (Cu), but is not limited thereto.

[0035] The second wiring layer 122 may each perform various functions according to the design. For example, the second wiring layer 122 may include a signal pattern, a power pattern, a ground pattern, etc. Each of these patterns may have various forms, such as a line, a plane, and a pad. The second wiring layer 122 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the second wiring layer 122 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the second wiring layer 122 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). The second wiring layer 122 may include a sputtering layer without an electroless plating layer (e.g., a chemical copper plating layer), or if necessary, the second wiring layer 122 may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer).

[0036] The second wiring layer 122 may be formed by any of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via-tightening (TT) process, and a subtractive process, but is not limited thereto. Any technology may be used without restriction as long as the technology can construct a circuit on a printed circuit board. In addition, the second wiring layer 122 may also be formed using different methods depending on the purpose and design of use. In addition, the second wiring layer 122 may be formed simultaneously with the first via layer 130, but is not limited thereto.

[0037] The first via layer 130 may connect the first wiring layer 121 and the second wiring layer 122 to each other and penetrate at least a portion of each of the first insulating layer 111 and the glass layer 110. Figure 3 As shown in , the first via layer 130 may include a first via portion 131 penetrating the glass layer 110 and a second via portion 132 penetrating a portion of the first insulating layer 111. That is, the first via layer 130 may be formed to fill a through hole penetrating a portion of the first insulating layer 111 and a through hole penetrating the glass layer 110, and the first via portion 131 penetrating the glass layer 110 and the second via portion 132 penetrating a portion of the first insulating layer 111 may be integrally formed. Hereinafter, the expression "penetrating the first insulating layer 111" may mean penetrating at least a portion of the first insulating layer 111.

[0038] The first via layer 130 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The first via layer 130 may preferably include copper (Cu), but is not limited thereto. The first via layer 130 may include a filled via that fills the via hole, but may also include a conformal via disposed along the wall of the via hole. The first via layer 130 may each perform various functions according to the design. For example, the first via layer 130 may include a ground via, a power via, a signal via, and the like.

[0039] The first via layer 130 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). The first via layer 130 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), or the first via layer 130 may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) as required. More specifically, the first via layer 130 may include a seed layer 125 and a plating layer 126 disposed on the seed layer 125.

[0040] The seed layer 125 may include an electroless plating layer (eg, a chemical copper plating layer), but is not limited thereto, and the seed layer 125 may also include a sputtering layer. The seed layer 125 may include copper (Cu), but is not limited thereto. Figure 3 As shown, the seed layer 125 may be composed of a single metal layer, but is not limited thereto, and the seed layer 125 may be composed of a plurality of metal layers. For example, in the case where the seed layer 125 includes a sputtered layer, the seed layer may further include a metal layer containing titanium (Ti). Since the seed layer 125 is formed to contact the glass layer 110, in the case where the seed layer 125 includes a sputtered layer, the adhesion with the glass layer 110 can be further ensured, but the seed layer 125 is not necessarily limited thereto. In addition, in addition to the above-mentioned metals, any material may be used for the seed layer 125 without restriction as long as the material can be used as a plating lead-in wire for electroplating. For example, an inorganic carbon-based conductive material or an organic carbon-based conductive material may be used for the seed layer 125.

[0041] The seed layer 125 may be conformally disposed along the inner wall of the first through hole formed in the glass layer 110 and the inner wall of the second through hole formed in the first insulating layer 111. That is, the seed layer 125 may contact the glass layer 110 and the first insulating layer 111, and may also contact the first wiring layer 121. For example, the seed layer 125 may extend continuously on the inner wall of the first through hole, the inner wall of the second through hole, and the portion of the first wiring layer 121 exposed by the first insulating layer 111. The seed layer 125 may form a boundary with the glass layer 110, and may form a boundary with the first insulating layer 111 and a boundary with the first wiring layer 121, respectively. In addition, the seed layer 125 may extend above the glass layer 110, and may serve as a seed layer for the second wiring layer 122.

[0042] The plating layer 126 may include an electrolytic plating layer (e.g., an electrolytic copper plating layer), and may be formed by performing electrolytic plating using the seed layer 125 as a plating lead-in. The plating layer 126 may include copper (Cu), but is not limited thereto, and may include the same metal as the seed layer 125. The plating layer 126 may be disposed on the seed layer 125, and may fill the first through hole penetrating the glass layer 110 and the second through hole penetrating the first insulating layer 111.

[0043] In addition, the formation of the seed layer 125 and the formation of the plating layer 126 can be performed simultaneously, and the first via portion 131 and the second via portion 132 of the first via layer 130 can be formed integrally. This means that the boundary between the first via portion 131 and the second via portion 132 of the first via layer 130 may not be confirmed, and the seed layer 125 formed in the first via portion 131 may extend to the second via portion 132, and the plating layer 126 formed in the first via portion 131 may extend to the second via portion 132. In addition, the boundary between the plating layer 126 and the seed layer 125 can be confirmed. That is, the integral formation of the first via portion 131 and the second via portion 132 of the first via layer 130 is in contrast to combining the first via portion 131 (penetrating the glass layer 110) and the second via portion 132 (penetrating the first insulating layer 111) after they are formed separately, and means that the first via layer 130 can be formed as a whole through a series of processes. At this time, the first via layer 130 and the second wiring layer 122 can be formed integrally. This may be a result of forming the second wiring layer 122 when forming the first via layer 130 .

[0044] The first via portion 131 penetrating the glass layer 110 and the second via portion 132 penetrating the first insulating layer 111 may have different widths. In addition, at least one of the first via portion 131 and the second via portion 132 may have a width that gradually narrows toward the first wiring layer 121 to have a so-called tapered shape. For example, each of the first via portion 131 and the second via portion 132 may have a width that gradually narrows toward the first wiring layer 121. The width and shape of the first via portion 131 and the second via portion 132 of the first via layer 130 may be measured and confirmed by imaging a cross section of a printed circuit board cut in a stacking direction passing through the central axis of the first via layer 130 using a scanning electron microscope or the like.

[0045] At the interface between the first insulating layer 111 and the glass layer 110, the second via portion 132 may have a smaller width than the first via portion 131. The interface between the first insulating layer 111 and the glass layer 110 may be identified as a boundary between the first insulating layer 111 and the glass layer 110 in a cross-sectional view, and the width of the second via portion 132 and the width of the first via portion 131 located on a line extending from the boundary line may be compared. That is, referring to Figure 3 , the width of the second via portion 132 at its uppermost side may be smaller than the width of the first via portion 131 at its lowermost side. This may be a result of forming a second through hole penetrating the first insulating layer 111 after forming a first through hole penetrating the glass layer 110 in the method of manufacturing a printed circuit board. After forming the first through hole penetrating the glass layer 110, the second through hole penetrating the first insulating layer 111 may be formed to have a smaller width than the first through hole. However, the first through hole portion 131 and the second through hole portion 132 are not necessarily limited thereto, and at the interface between the first insulating layer 111 and the glass layer 110, the width of the second through hole portion 132 may be substantially the same as the width of the first through hole portion 131. This means that when forming the second through hole penetrating the first insulating layer 111 after forming the first through hole penetrating the glass layer 110, the glass layer 110 may be used as a mask for the second through hole.

[0046] At the interface between the glass layer 110 and the second wiring layer 122, the first via portion 131 may have a smaller width than the second wiring layer 122. This means that when the first via layer 130 and the second wiring layer 122 are formed, the second wiring layer 122 may be formed to have a larger width than the first via layer 130 to serve as a pad for the first via layer 130. In addition, the width of the first via portion 131 of the first via layer 130 is not greater than the width of all lines in the second wiring layer 122, and the width of the second wiring layer 122 directly connected to the first via layer 130 may be greater than the width of the first via portion 131 of the first via layer 130.

[0047] In the cross-sectional view, the first via portion 131 may have a width that gradually narrows toward the first wiring layer 121, and the second via portion 132 may have a width that gradually narrows toward the first wiring layer 121. The width of the first via portion 131 and the width of the second via portion 132 may gradually narrow in substantially the same direction. This is a result of forming a first through hole penetrating the glass layer 110 after forming the glass layer 110 on the first insulating layer 111, and then forming a second through hole penetrating the first insulating layer 111 in the same direction. Based on Figure 3 Since the through hole is formed from the upper side to the lower side, the width of each of the first via portion 131 and the second via portion 132 at the lower side may be narrower than the width at the upper side. Figure 3 131 and 132 are shown as tapering substantially along a straight line in a cross-sectional view, but it is not necessarily limited thereto. Each of the side surfaces of the first via portion 131 and the second via portion 132 may be curved. Figure 3, the first via portion 131 and the second via portion 132 are shown to taper at substantially the same inclination, but are not necessarily limited thereto. The first via portion 131 and the second via portion 132 may taper to different degrees. That is, the side surface of the first via portion 131 and the side surface of the second via portion 132 may have different slopes in a cross-sectional view. The formation of the first through hole penetrating the glass layer 110 and the formation of the second through hole penetrating the first insulating layer 111 may be performed in different processes, and because the glass layer 110 and the first insulating layer 111 include different materials, the glass layer 110 and the first insulating layer 111 may be processed to different degrees.

[0048] The surface roughness of the glass layer 110 at the interface between the first insulating layer 111 and the glass layer 110 may be smaller than the surface roughness of the glass layer 110 at the interface between the first via layer 130 and the glass layer 110, and may be smaller than the surface roughness of the glass layer 110 at the interface between the second wiring layer 122 and the glass layer 110. That is, referring to Figure 3 , the surface roughness of the lower surface of the glass layer 110 may be less than the surface roughness of the upper surface of the glass layer 110, and the surface roughness of the lower surface of the glass layer 110 may be less than the surface roughness of the inner surface of the glass layer 110 in the direction toward the first via layer 130. This may be a result of performing an etching process on the glass layer 110 when forming the first through hole penetrating the glass layer 110. That is, since the upper surface and the inner surface of the glass layer 110 may be processed by etching when forming the first through hole for forming the first via portion 131 of the first via layer 130, surface roughness may appear on the upper surface and the inner surface of the glass layer 110, and since the lower surface of the glass layer 110 in contact with the first insulating layer 111 is not etched, the lower surface of the glass layer 110 may have a lower surface roughness than the upper surface and the inner surface of the glass layer 110. When the glass layer 110 is processed and surface roughness is formed on the upper and inner side surfaces of the glass layer 110 , adhesion between the first via layer 130 and the glass layer 110 and adhesion between the second wiring layer 122 and the glass layer 110 may be improved.

[0049] The surface roughness of the glass layer 110 can be measured by imaging a cross section of a printed circuit board cut in the stacking direction using a scanning electron microscope or the like. For example, in order to measure the surface roughness on the cut surface of the glass layer 110, a known surface roughness measurement method such as a center line average roughness (Ra) calculation method or a ten-point average roughness (Rz) calculation method may be considered. However, the surface roughness measurement method is not limited thereto, and any method may be used without limitation as long as the method can measure the surface roughness. As a non-limiting example, the surface roughness may be measured by marking the average position of the surface of the first wiring layer 121 as an imaginary line (or may be referred to as an average line), and then obtaining the average value of the absolute value of the height difference relative to the average line, or obtaining the average value of the height difference between the five highest points and the five lowest points relative to the average line. In addition, the surface roughness measurement method is not limited thereto, but only when the comparative surface of the glass layer 110 is measured using the same method, the size comparison will be clearer. As a non-limiting example, the lower surface of the glass layer 110 may have a roughness (Ra) value of about 0.1 nm to 0.2 nm, and the upper surface and / or the inner surface of the glass layer 110 may have a roughness (Ra) value of about 0.4 nm to 0.6 nm. Alternatively, the lower surface of the glass layer 110 may have a roughness (Rz) value of about 1 nm to 3 nm, and the upper surface and / or the inner surface of the glass layer 110 may have a roughness (Rz) value of about 4 nm to 7 nm.

[0050] In the first via layer 130, the first via portion 131 may be deeper than the second via portion 132. That is, the first via portion 131 penetrating the glass layer 110 may be deeper than the second via portion 132 penetrating the first insulating layer 111. This may mean that the insulation distance of the glass layer 110 is greater than the insulation distance of the first insulating layer 111, and may mean that, with reference to Figure 3 , the distance between the upper surface and the lower surface of the glass layer 110 is greater than the distance between the upper surface of the first wiring layer 121 and the upper surface of the first insulating layer 111. The thickness of the glass layer 110 may be thicker than the thickness of the first insulating layer 111, but is not necessarily limited thereto. Since the glass layer 110 cannot be directly formed on the first wiring layer 121, the glass layer 110 is formed on the first insulating layer 111 after the first insulating layer 111 is formed on the first wiring layer 121. At this time, since the glass layer 110 is formed after the first insulating layer 111 is thinly formed, the first via portion 131 penetrating the glass layer 110 may be deeper than the second via portion 132 penetrating the first insulating layer 111.

[0051] The depth of the first via portion 131 and the depth of the second via portion 132 may be measured by imaging a cross section of the printed circuit board cut in the stacking direction using a scanning electron microscope or the like. Each of the depth of the first via portion 131 and the depth of the second via portion 132 of the first via layer 130 may refer to: in a cross-sectional view, the vertical distance between the upper surface and the lower surface of each of the first via portion 131 and the second via portion 132 of the first via layer 130. However, because the first via portion 131 and the second via portion 132 are integrally formed and the boundary therebetween may not be clear, the depth of the first via portion 131 may be understood as the vertical distance between the upper surface and the lower surface of the glass layer 110, and the depth of the second via portion 132 may be understood as the vertical distance from the upper surface of the first wiring layer 121 to the upper surface of the first insulating layer 111. That is, in the insulation distance between the first wiring layer 121 and the second wiring layer 122, the insulation distance corresponding to the area of ​​the glass layer 110 can be understood as the depth of the first via portion 131, and the insulation distance corresponding to the area of ​​the first insulating layer 111 can be understood as the depth of the second via portion 132.

[0052] FIG. 4A to FIG. 4C 1 is a schematic cross-sectional view showing a part of a method for manufacturing a printed circuit board according to a first exemplary embodiment. The method for manufacturing a printed circuit board includes: forming a first insulating layer 111 in which a first wiring layer 121 is embedded; forming a glass layer 110 on the first insulating layer 111; forming a first through hole H1 penetrating at least a portion of the glass layer 110; forming a second through hole H2 penetrating at least a portion of the first insulating layer 111; forming a first via layer 130 in the first through hole H1 and the second through hole H2; and forming a second wiring layer 122 on the first insulating layer 111.

[0053] Reference Figure 4A , the method of manufacturing a printed circuit board may include forming a first insulating layer 111 and a glass layer 110 .

[0054] At this time, the first wiring layer 121 may be provided on the insulating material 100. The insulating material 100 may be any component, and the insulating material 100 may be a carrier substrate, a core layer, a built-up insulating layer, or even another glass layer. In the case where the insulating material 100 is a carrier substrate, the first wiring layer 121 may be located at the outermost side of the coreless structure. In the case where the insulating material 100 is a core layer, the first wiring layer 121 may be located on a core-type substrate. In the case where the insulating material 100 is a built-up insulating layer, the first wiring layer 121 may be located in the middle of the built-up body of the substrate to have a sandwich structure. In the case where the insulating material 100 is a glass layer, the same sandwich structure may be repeatedly stacked. That is, in the printed circuit board according to the first exemplary embodiment, the insulating material 100 is represented as an arbitrary component to represent only the portion where the sandwich structure is formed between the first wiring layer 121 and the second wiring layer 122. This means that the sandwich structure may be applied to the printed circuit boards according to the first application example to the fifth application example in various ways. In addition, the insulating material 100 does not have to be composed of only one insulating material, and may have various structures as described above.

[0055] Thereafter, the method of manufacturing a printed circuit board may include forming a first insulating layer 111 to embed the first wiring layer 121 .

[0056] The first insulating layer 111 may be provided on the insulating material 100 to embed the first wiring layer 121 provided on the insulating material 100. As a method of forming the first insulating layer 111, a known insulating layer stacking method may be used, and one of various methods may be used according to the insulating material of the first insulating layer 111. At this time, the first insulating layer 111 may further include a temporary layer such as a protective layer. In the case where the first insulating layer 111 further includes a temporary layer, the temporary layer may be removed before forming the glass layer 110, so that the first insulating layer 111 is formed as shown in FIG. Figure 4A As shown in .

[0057] Thereafter, the method of manufacturing a printed circuit board may include forming a glass layer 110 on the first insulating layer 111 .

[0058] The glass layer 110 may be formed on the first insulating layer 111 by curing the first insulating layer 111 after forming the glass layer 110 on the first insulating layer 111 before curing the first insulating layer 111 or in a semi-cured state of the first insulating layer 111. After forming the first insulating layer 111 including the temporary layer, if the temporary layer is removed immediately before forming the glass layer 110, the glass layer 110 may be attached to the first insulating layer 111 using the adhesive force of the first insulating layer 111. However, forming the glass layer 110 on the first insulating layer 111 is not necessarily limited thereto, and the glass layer 110 may be formed after forming an adhesive member on the first insulating layer 111.

[0059] Reference Figure 4B , the method of manufacturing a printed circuit board may include forming a first through hole H1 penetrating the glass layer 110 and forming a second through hole H2 penetrating the first insulating layer 111 .

[0060] Forming the first through hole H1 penetrating the glass layer 110 may include forming the first hole h1 by removing a portion of the glass layer 110 and a portion of the first insulating layer 111. The first hole h1 may be formed using a mechanical processing method. As a non-limiting example, the first hole h1 may be formed by emitting a laser (e.g., ultraviolet (UV)) laser. At this time, the laser processing may be performed once, but may also be performed multiple times.

[0061] The first hole h1 may be formed to penetrate the glass layer 110, and a portion of the first insulating layer 111 may be processed together when penetrating the glass layer 110. That is, the formation of the first hole h1 is performed as a step of penetrating the glass layer 110, and at this time, a portion of the first insulating layer 111 is removed together, so that the first hole h1 may penetrate at least a portion of the first insulating layer 111. Figure 4B 1 and 2 show that the first hole h1 penetrates only a portion of the first insulating layer 111, but is not limited thereto. The first hole h1 may penetrate the first insulating layer 111 to expose a portion of the upper surface of the first wiring layer 121. In addition, the first hole h1 is not limited thereto, and may be formed to penetrate only the glass layer 110 without removing the first insulating layer 111. In this case, the first hole h1 may not penetrate any portion of the first insulating layer 111.

[0062] Thereafter, the first through hole H1 may be formed by removing at least a portion of the glass layer 110. The formation of the first through hole H1 by removing at least a portion of the glass layer 110 may be performed by an etching process. As a non-limiting example, wet etching may be used in the etching process. The removal of at least a portion of the glass layer 110 may be performed by expanding the first hole h1 formed in the glass layer 110 to form the first through hole H1. That is, the first through hole H1 may be formed by removing a portion of the glass layer 110 adjacent to the first hole h1. However, the first insulating layer 111 may not be removed when removing the glass layer 110, and therefore, the region of the first hole h1 formed in the first insulating layer 111 may not be expanded. When forming the first through hole H1, a portion of the upper surface of the first insulating layer 111 may be exposed.

[0063] At this time, in the case where the etching process is performed by wet etching, a portion of the glass layer 110 on the upper side thereof may be removed, and thus, the thickness of the glass layer 110 may be reduced. As a non-limiting example, in the case where a portion of the glass layer 110 on the upper side thereof is removed, the reduced thickness of the glass layer 110 may correspond to half of the diameter of the first through hole H1. That is, the difference between the thickness of the glass layer 110 before the first through hole H1 is formed and the thickness of the glass layer 110 after the first through hole H1 is formed may correspond to half of the width of the first through hole H1 at its uppermost side (i.e., the above-mentioned diameter of the first through hole H1). When at least a portion of the glass layer 110 is removed, surface roughness may occur on the upper surface of the glass layer 110 and the inner side surface of the glass layer 110 (the wall surface constituting the first through hole H1).

[0064] In addition, Figure 4B 1 and 2 show that the first through hole H1 forms an angle with the upper surface of the glass layer 110, but it is not necessarily limited thereto. The first through hole H1 may be formed to have a curved surface on its upper side. In addition, the first hole h1 is shown to form an angle with the first insulating layer 111, but it is not necessarily limited thereto. The first hole h1 may also be formed to have a curved surface, or the first hole h1 may have a conical shape so as not to have a bottom surface.

[0065] In addition, Figure 4B , the formation of the first through hole H1 penetrating the glass layer 110 is shown to be performed by two steps, but it is not necessarily limited thereto. Any via hole processing method for forming a so-called through glass via (TGV) (a via penetrating the glass layer 110) may be used without limitation. If necessary, the glass layer 110 and the first through hole H1 may be formed on the first insulating layer 111 by attaching the glass layer 110 having the first through hole H1 formed therein to the first insulating layer 111, and any method may be used without limitation as long as the method can form the first through hole H1 in the glass layer 110.

[0066] Thereafter, a second through hole H2 penetrating at least a portion of the first insulating layer 111 may be formed. As a method of forming the second through hole H2, a known method for penetrating the first insulating layer 111 may be used. As a non-limiting example, a UV laser, a CO2 laser, or an yttrium aluminum garnet crystal (YAG) laser may be used to perform the process. As the second through hole H2 is formed, at least a portion of the first wiring layer 121 may be exposed. The second through hole H2 may be formed to have a greater width than the first hole h1, and thus the first hole h1 may be included in the second through hole H2. In addition, after the second through hole H2 is formed, the inner side surface of the first insulating layer 111 (forming the inner wall of the second through hole H2) and a portion of the upper surface of the first insulating layer 111 (forming the bottom surface of the first through hole H1) may be surface treated. The surface treatment may be performed by a desmearing process for removing residues generated in the first insulating layer 111, and in addition, a pre-treatment for forming the first via layer 130 may be performed.

[0067] Reference Figure 4C , the method of manufacturing a printed circuit board may include forming a first via layer 130 and forming a second wiring layer 122 .

[0068] The formation of the first via layer 130 and the formation of the second wiring layer 122 may include forming a seed layer 125. The seed layer 125 may be formed along the inner wall and bottom surface of the first through hole H1 and the second through hole H2, and may extend onto the glass layer 110. That is, the seed layer 125 may be conformally formed along the upper surface of the glass layer, the inner wall and bottom surface of the first through hole H1, and the inner wall and bottom surface of the second through hole H2. As a method of forming the seed layer 125, a deposition technique such as sputtering may be used, but the method of forming the seed layer 125 is not limited thereto. Since the seed layer 125 extends onto the glass layer 110, in the case of using the sputtering technique, the adhesion between the seed layer 125 and the glass layer 110 may be stronger, which may be more conducive to the subsequent plating step. However, the method of forming the seed layer 125 is not limited thereto, and the seed layer 125 may be formed by an electroless plating (e.g., chemical copper plating) process. In addition, one of various methods may be used according to the material of the seed layer 125, and the seed layer 125 may be formed using a known method.

[0069] Thereafter, a plating layer 126 may be formed on the seed layer 125 to form the first via layer 130 and the second wiring layer 122. The formation of the plating layer 126 may be performed by electroplating using the seed layer 125 as a plating lead-in. The plating layer 126 may be formed to fill the first through hole H1 and the second through hole H2, and the plating layer 126 may form the first via portion 131 of the first via layer 130 together with the seed layer 125 located in the first through hole H1, and the plating layer 126 may form the second via portion 132 of the first via layer 130 together with the seed layer 125 located in the second through hole H2. At this time, since the plating layer 126 is formed by performing one plating to simultaneously fill the second through hole H2 and the first through hole H1, the first through hole portion 131 and the second through hole portion 132 may be formed in the same step. This is different from a structure in which the glass layer 110 and the first insulating layer 111 are connected to each other by bonding after forming a via hole in the glass layer 110 and a via hole in the first insulating layer 111 in that the first via portion 131 penetrating the glass layer 110 and the second via portion 132 penetrating the first insulating layer 111 are integrally formed, and a boundary between the first via portion 131 and the second via portion 132 is unclear. Since the first via portion 131 and the second via portion 132 are integrally formed, problems such as separation or misalignment between the first via portion 131 and the second via portion 132 can be prevented.

[0070] Furthermore, the second wiring layer 122 may be formed by forming a plating resist on the seed layer 125, performing plating, removing the plating resist, and then removing a portion of the seed layer 125. However, the formation of the second wiring layer 122 is not necessarily limited thereto, and the second wiring layer 122 may be patterned using a known method, for example, by forming a plating layer 126 on the seed layer 125, and then removing a portion of the plating layer 126 and a portion of the seed layer 125.

[0071] exist FIG. 4A to FIG. 4C In the method for manufacturing a printed circuit board according to the first exemplary embodiment, only the insulating structure of the first insulating layer 111 and the glass layer 110 between the first wiring layer 121 and the second wiring layer 122 and the sandwich connector of the first via layer 130 are shown. As described above, the printed circuit board may have a sandwich structure between the first wiring layer 121 and the second wiring layer 122 at one of the various positions. This will be described below in the first to fifth application examples.

[0072] FIG. 5A to FIG. 5J : is a schematic cross-sectional view showing a part of a printed circuit board and a method of manufacturing the printed circuit board according to first to tenth modifications of the first exemplary embodiment.

[0073] FIG. 5A to FIG. 5J1 shows a step after forming the glass layer 110 in the method of manufacturing a printed circuit board according to the first exemplary embodiment, and various shapes of the first via layer 130 and the method of manufacturing a printed circuit board will be mainly described below. FIG. 5A to FIG. 5J In each of the embodiments, the last step may correspond to the printed circuit board according to each of the first to tenth modifications of the first exemplary embodiment.

[0074] Reference Figure 5A In the method of manufacturing a printed circuit board according to the first modification of the first exemplary embodiment, when the first through hole H1 is formed by removing at least a portion of the glass layer 110, the inner wall of the first through hole H1 may have a curved surface. Also in the printed circuit board according to the first modification, the first through hole H1 may have a greater width at the upper portion than at the lower portion, and the first through hole H1 may have a width that is substantially gradually narrowed downward. That is, the first through hole H1 may have a width that is substantially gradually narrowed toward the first wiring layer 121.

[0075] The reason why the inner wall of the first through hole H1 has a curved surface and the first through hole H1 has a substantially narrowed width is that a portion of the glass layer 110 is removed by etching when the first through hole H1 is formed. That is, when the first through hole H1 is formed, a curved surface may appear in the lower region where the etchant of the first through hole H1 is concentrated. However, the formation of the first through hole H1 is not necessarily limited to this. In the case where the etchant is more concentrated on the lower side when the first through hole H1 is formed, the glass layer 110 may be removed so that the width of the first through hole H1 at the central portion is wider than that at the upper and lower portions. However, even in this case, the first insulating layer 111 may not react with the etchant that removes the glass layer 110, and therefore, the first hole h1 formed in the first insulating layer 111 may be maintained when the first through hole H1 is formed.

[0076] Hereinafter, in the method for manufacturing a printed circuit board according to the first variation of the first exemplary embodiment, the width of the second through hole H2 on its upper side may be substantially the same as the width of the first through hole H1 on its lower side. This is because, when the second through hole H2 is formed by removing at least a portion of the first insulating layer 111, the glass layer 110 may be used as a mask for the second through hole H2. That is, the second through hole H2 may be formed by removing the first insulating layer 111 forming the bottom surface of the first through hole H1, and as a result, the width of the second through hole H2 on its upper side may be substantially the same as the width of the first through hole H1 on its lower side. Also in this case, the second through hole H2 may be formed using a UV laser, a CO2 laser, a YAG laser, or the like, and accordingly, the second through hole H2 may have a tapered shape with a substantially constant amount of change.

[0077] In the printed circuit board according to the first variation of the first exemplary embodiment, the side surface of the first via portion 131 may be substantially curved. This may be a result of the shape of the first through hole H1 as described above. In addition, at the interface between the glass layer 110 and the first insulating layer 111, the width of the first via portion 131 may be substantially the same as the width of the second through hole portion 132. This may be a result of the shape of the second through hole H2. In the printed circuit board according to the first variation of the first exemplary embodiment, since the side surface of the first via portion 131 of the first via layer 130 may be substantially curved, the contact area between the glass layer 110 and the first via portion 131 may be increased, which is more advantageous in improving adhesion. In addition, the shapes of the first via portion 131 and the second via portion 132 are not limited to Figure 5A , and the first via portion 131 may have a curved surface having a varying radius of curvature (such as a curved surface formed because the first via portion 131 is asymmetric), or the first via portion 131 may have a curved surface with an uneven surface.

[0078] Reference Figure 5B In the method of manufacturing a printed circuit board according to the second modification of the first exemplary embodiment, when the second through hole H2 is formed by removing at least a portion of the first insulating layer 111, the width of the second through hole H2 on its upper side may be substantially the same as the width of the first through hole H1 on its lower side. This is because, when the second through hole H2 is formed by removing at least a portion of the first insulating layer 111, the glass layer 110 may be used as a mask for the second through hole H2. However, the formation of the second through hole H2 is not necessarily limited thereto, and a separate mask may be used to form the second through hole H2 to correspond to the width of the bottom surface of the first through hole H1. That is, since the second through hole H2 may be formed by removing the first insulating layer 111 forming the bottom surface of the first through hole H1, the width of the second through hole H2 on its upper side may be substantially the same as the width of the first through hole H1 on its lower side. Also in this case, the second through hole H2 may be formed using a UV laser, a CO2 laser, a YAG laser, or the like, and accordingly, the second through hole H2 may have a tapered shape with a substantially constant amount of change. In addition, the first through hole H1 and the second through hole H2 may have a tapered shape with a substantially constant amount of change, but are not necessarily limited thereto.

[0079] In the printed circuit board according to the second modification of the first exemplary embodiment, at the boundary between the glass layer 110 and the first insulating layer 111, the width of the first via portion 131 and the width of the second via portion 132 may be substantially the same. This may be a result of forming the second through hole H2 as described above. At this time, the first via portion 131 and the second via portion 132 are formed to have a width such as Figure 5BIn the case of substantially the same slope as shown in , no bending may occur between the first via portion 131 and the second via portion 132 at the boundary between the glass layer 110 and the first insulating layer 111, and the first via portion 131 and the second via portion 132 may have a tapered shape with a constant inclination, but is not limited thereto.

[0080] Reference Figure 5C In the method of manufacturing a printed circuit board according to the third modification of the first exemplary embodiment, when the second through hole H2 is formed by removing at least a portion of the first insulating layer 111, the tapering degree of the second through hole H2 may be different from the tapering degree of the first through hole H1. As a non-limiting example, the inclination angle formed by the inner wall of the second through hole H2 and the first wiring layer 121 may be greater than the inclination angle formed by the inner wall of the first through hole H1 and the first insulating layer 111. That is, the inner wall of the second through hole H2 may be formed to be closer to vertical than the inner wall of the first through hole H1. This may be the result of the difference between the degree of removal of the glass layer 110 when the first through hole H1 is formed by removing at least a portion of the glass layer 110 and the degree of removal of the first insulating layer 111 when the second through hole H2 is formed by removing at least a portion of the first insulating layer 111, or may be the result of the difference in thickness between the glass layer 110 and the first insulating layer 111. A portion of the glass layer 110 may be removed by etching as a chemical technique, while the first insulating layer 111 may be removed by a physical technique, and thus the first insulating layer 111 may be removed to a higher degree and at a higher speed than the glass layer 110. In addition, the first insulating layer 111 may be formed to have a thickness substantially smaller than that of the glass layer 110, and thus the second through hole H2 formed in the first insulating layer 111 may be tapered to a lower degree than the first through hole H1 formed in the glass layer 110.

[0081] In the printed circuit board according to the third modification of the first exemplary embodiment, at the interface between the glass layer 110 and the first insulating layer 111, the width of the first via portion 131 may be substantially the same as the width of the second via portion 132, and the inclination angle formed by the side surface of the first via portion 131 and the first insulating layer 111 may be substantially different from the inclination angle formed by the side surface of the second via portion 132 and the first wiring layer 121. More preferably, each of the inclination angle formed by the side surface of the first via portion 131 and the upper surface of the first insulating layer 111 and the inclination angle formed by the side surface of the second via portion 132 and the upper surface of the first wiring layer 121 may be an acute angle, and the inclination angle formed by the side surface of the second via portion 132 and the upper surface of the first wiring layer 121 (i.e., one surface of the first wiring layer 121 in contact with the second via portion 132) may be greater than the inclination angle formed by the side surface of the first via portion 131 and the upper surface of the first insulating layer 111 (i.e., one surface of the first insulating layer 111 in contact with the glass layer 110). This may be a result depending on the shape of the first through hole H1 formed in the glass layer 110 and the shape of the second through hole H2 formed in the first insulating layer 111. At this time, the tilt angle formed by the two intersecting surfaces can be measured by imaging the cross section of the printed circuit board cut in the stacking direction using a scanning electron microscope, and the tilt angle formed by the two intersecting surfaces can be measured in each of the five arbitrary regions using the angle formed by the actual slope between the via portion and the first insulating layer 111 or the angle formed by the actual slope between the via portion and the first wiring layer 121. In addition, any known method for measuring the actual tilt angle formed by the two intersecting surfaces can be used without restriction, as long as the tilt angle is not measured at only one point relative to the uneven slope. In addition, the comparison between the tilt angles is not necessarily limited to the comparison based on the measurement, and it can be understood that the second via portion 132 penetrating the first insulating layer 111 has a shape that is substantially closer to vertical than the first via portion 131 penetrating the glass layer 110.

[0082] Reference Figure 5DIn the method of manufacturing a printed circuit board according to the fourth modification of the first exemplary embodiment, forming the first hole h1 by removing a portion of the glass layer 110 and the first insulating layer 111 may include forming a plurality of first holes h1. That is, a plurality of first holes h1 may be formed to form the first through hole H1. If a plurality of first holes h1 are formed, an etchant may penetrate more easily when forming the first through hole H1 and the first through hole H1 may be formed to be wider. At this time, an area of ​​the first hole h1 formed in a portion of the first insulating layer 111 may not react when forming the first through hole H1, and may not be included in the second through hole H2 even when forming the second through hole H2 penetrating a portion of the first insulating layer 111. That is, at least some of the first holes h1 may be maintained in both forming the first through hole H1 and forming the second through hole H2, and therefore, an area of ​​the first hole h1 formed in at least a portion of the first insulating layer 111 is retained in a subsequent step of forming the first via layer 130.

[0083] In the printed circuit board according to the fourth modification of the first exemplary embodiment, the first via layer 130 may include a protrusion that is disposed at the lower side of the first via portion 131 and embedded in at least a portion of the first insulating layer 111. The protrusion may be a result of forming the first via layer 130 in a retained first hole h1 that is not included in the first through hole H1 and the second through hole H2 among the plurality of first holes h1. At this time, the seed layer 125 may be conformally disposed along the boundary of the above-mentioned retained first hole h1, and the protrusion may be formed by filling the above-mentioned retained first hole h1 with a plating layer 126 on the seed layer 125. Since the above-mentioned retained first hole h1 may penetrate only a portion of the first insulating layer 111, rather than completely penetrating the first insulating layer 111, the protrusion may not contact the first wiring layer 121, and may be disposed to be spaced apart from the second via portion 132 of the first via layer 130 along the boundary between the second via portion 132 and the first insulating layer 111. Since the first via layer 130 includes the protrusion, the contact area between the first via layer 130 and the first insulating layer 111 may be increased, which is advantageous in ensuring adhesion.

[0084] Reference Figure 5E In the method of manufacturing a printed circuit board according to the fifth modification of the first exemplary embodiment, the first through hole H1 penetrating the glass layer 110 may be substantially perpendicular to the upper surface of the first insulating layer 111. This may be a result of forming the first through hole H1 more quickly by controlling the degree of etching when the first through hole H1 is formed by removing at least a portion of the glass layer 110. In addition, the formation of the first through hole H1 is not limited thereto, and may be performed by mechanical processing such as laser processing instead of etching. In addition, in Figure 5E, it is shown that the inner wall of the first through hole H1 is substantially perpendicular to the upper surface and the lower surface of the glass layer 110 adjacent to the first through hole H1. However, the first through hole H1 is not limited thereto, and each of the upper edge region and the lower edge region of the inner wall of the first through hole H1 may have a curved surface, and the other region between the upper edge region and the lower edge region may be substantially perpendicular to the upper surface and the lower surface of the glass layer 110. That is, this means that in a cross-sectional view, the inner wall portion of the first through hole H1 may be substantially perpendicular to the upper surface of the first insulating layer 111 and the upper surface and the lower surface of the glass layer 110, and means that the inner wall portion of the first through hole H1 is not a tapered shape with an inclination.

[0085] In the printed circuit board according to the fifth modification of the first exemplary embodiment, the first via portion 131 of the first via layer 130 may be substantially perpendicular to the upper surface of the first insulating layer 111, and may be substantially perpendicular to the upper and lower surfaces of the glass layer 110. In addition, the first via portion 131 of the first via layer 130 may be substantially perpendicular to the second wiring layer 122. This may be a result of forming the first via layer 130 after forming the first via hole H1 so that the first via hole H1 is substantially perpendicular to the upper surface of the first insulating layer 111 and the upper and lower surfaces of the glass layer 110. At this time, the upper and lower sides of the first via layer 130 do not need to form an angle with the upper and lower surfaces of the glass layer 110, and may be curved as described above.

[0086] Reference Fig. 5F , in the method for manufacturing a printed circuit board according to the sixth variation of the first exemplary embodiment, the first hole h1 may be wider than the second through hole H2. This may be the result of processing a large area by overlapping lasers when forming the first hole h1. Since the first hole h1 may be wider than the second through hole H2 penetrating the first insulating layer 111, the first insulating layer 111 may have a step shape in a region where the first hole h1 and the second through hole H2 are adjacent to each other. Thereafter, when forming the seed layer 125, the seed layer 125 may be conformally disposed along the boundary of the first hole h1 and the second through hole H2, and the first via layer 130 may be formed by forming a plating layer 126 on the seed layer 125.

[0087] In the printed circuit board according to the sixth modification of the first exemplary embodiment, the first via layer 130 may have a protrusion. The protrusion may be provided at the lower side of the first via portion 131, and may have a step starting from the upper surface of the first insulating layer 111. The protrusion may be an area corresponding to the first hole h1. Since the first via layer 130 may have a protrusion, the contact area between the first via layer 130 and the first insulating layer 111 may be increased, which is conducive to ensuring adhesion.

[0088] Reference Figure 5GIn the method of manufacturing a printed circuit board according to the seventh modification of the first exemplary embodiment, when forming the first hole h1, the upper side of the first wiring layer 121 may be exposed by forming the first hole h1 to penetrate the first insulating layer 111. This may be a result of a method in which the first hole h1 is formed to have a larger area by overlapping the laser when forming the first hole h1 or performing the process for forming the first hole h1 for a longer time. Since the upper side of the first wiring layer 121 is exposed through the first hole h1, the formation of the second through hole penetrating the first insulating layer 111 may be omitted, thereby reducing one step of the process. At this time, the first hole h1 may be substantially perpendicular to the upper surface of the first insulating layer 111, and may be substantially perpendicular to the first wiring layer 121.

[0089] In the printed circuit board according to the seventh modification of the first exemplary embodiment, the second via portion 132 of the first via layer 130 may be substantially perpendicular to the upper surface of the first insulating layer 111, and may be substantially perpendicular to the upper surface of the first wiring layer 121. This may be a result depending on the shape of the first hole h1 when forming the first hole h1, and may be a result of omitting the formation of the second through hole.

[0090] Reference Figure 5H In the method of manufacturing a printed circuit board according to the eighth variation of the first exemplary embodiment, the second through hole H2 may be wider than the first through hole H1. At the interface between the first insulating layer 111 and the glass layer 110, the width of the second through hole H2 may be greater than the width of the first through hole H1. This may be the result of processing using a laser such as a UV laser when forming the second through hole H2 that penetrates the first insulating layer 111. At this time, as the UV laser, a laser that can process only the first insulating layer 111 while transmitting through the glass layer 110 may be used. Also in this case, the seed layer 125 may be conformally formed along the boundary between the first through hole H1 and the second through hole H2. In addition, in Figure 5H 2 shows that, in the cross-sectional view, the second through hole H2 tapers at a substantially constant inclination, but the second through hole H2 is not necessarily limited thereto, and a side surface of the second through hole H2 may be curved.

[0091] In the printed circuit board according to the eighth modification of the first exemplary embodiment, at the interface between the first insulating layer 111 and the glass layer 110, the width of the second via portion 132 may be greater than the width of the first via portion 131. This is caused by the shapes of the first through hole H1 and the second through hole H2. Since the second via portion 132 penetrating the first insulating layer 111 may be wider than the first via portion 131, the first via layer 130 may have an anchoring effect, and the first via layer 130 may have more improved adhesion.

[0092] Reference Fig.5I, the method of manufacturing a printed circuit board according to the ninth modification of the first exemplary embodiment may include forming a plurality of first through holes H1. A plurality of first holes h1 may be formed, and the plurality of first holes h1 may be formed to correspond to the plurality of first through holes H1, respectively. At this time, the plurality of first holes h1 and the plurality of first through holes H1 may refer to the plurality of first holes h1 and the plurality of first through holes H1 being connected to one wiring pattern of the first wiring layer 121, rather than the plurality of first holes h1 being formed in the same layer as the plurality of first through holes H1. A plurality of first through holes H1 are formed in the glass layer 110, and the second through holes H2 are formed to penetrate the first insulating layer 111 in such a manner that the plurality of first through holes H1 are connected to one second through hole H2 (to be connected to one first wiring layer 121). At this time, when forming the second through hole H2, in the case where the first hole h1 formed in a portion of the glass layer 110 and the first insulating layer 111 is not included in the second through hole H2, a portion of the first hole h1 may remain in the first insulating layer 111. Thereafter, when forming the first via layer 130, the seed layer 125 may be conformally disposed along the corresponding inner walls of the plurality of first through holes H1. If the first holes h1 are retained, the seed layer 125 may also be conformally disposed along the boundaries of the first holes h1. The plating layer 126 may fill the plurality of first through holes H1 and the plurality of first holes h1.

[0093] In a printed circuit board according to a ninth variation of the first exemplary embodiment, at least one via in the first via layer 130 may include one second via portion 132 and a plurality of first via portions 131, and the plurality of first via portions 131 may be in contact with one second via portion 132 for connection. That is, the plurality of first via portions 131 may be formed to penetrate the glass layer 110, and the one second via portion 132 may be formed to penetrate the first insulating layer 111 and be connected to the first wiring layer 121. The first via layer 130 may also have a protrusion. The protrusion may have a shape depending on the first hole h1, may be disposed on the lower side of the first via portion 131, and may refer to a portion of the first via layer 130 embedded in the first insulating layer 111. The protrusion may be an area spaced apart from the second via portion 132. Each of the plurality of first via portions 131 may have a width that gradually narrows toward the first wiring layer 121. This may be that although a plurality of first through holes H1 are formed, from the first via portion 132 based on Fig. 5F Since a plurality of first via portions 131 may be formed, the contact area between the first via layer 130 and the glass layer 110 may be increased, thereby creating a better structure for ensuring adhesion of the first via layer 130 .

[0094] Reference Figure 5JIn the method of manufacturing a printed circuit board according to the tenth modification of the first exemplary embodiment, the width of the second through hole H2 may be adjusted so that the plurality of first holes h1 are included in the second through hole H2. That is, when forming the second through hole H2 penetrating the first insulating layer 111, the second through hole H2 may be formed to be connected to the first through hole H1 by sufficiently ensuring the width of the second through hole H2.

[0095] In the printed circuit board according to the tenth modification of the first exemplary embodiment, one second via portion 132 of the first via layer 130 may be connected to the plurality of first via portions 131, and the first via layer 130 may not have a protrusion. This may be a shape depending on the relationship between the first hole h1, the first through hole H1, and the second through hole H2. Since the width of the second via portion 132 can be sufficiently ensured, sufficient adhesion and connection reliability can be ensured between the first via portion 131 and the second via portion 132.

[0096] Figure 5K It shows that according to Fig.5I A ninth variation of the first exemplary embodiment shown in or Figure 5J 1 is a plan view of a portion of a method for manufacturing a printed circuit board according to a tenth variation of the first exemplary embodiment shown in FIG. In particular, Figure 5K The ninth modification relates to the formation of the plurality of first holes h1 and the plurality of first through holes H1 or the tenth modification to the formation of the plurality of first holes h1 and the plurality of first through holes H1 and may correspond to a top plan view of the glass layer 110 when viewed from above.

[0097] A plurality of first holes h1 spaced apart from each other may be formed in the glass layer 110, and a plurality of first through holes H1 may be formed based on the plurality of first holes h1. Thereafter, the plurality of first through holes H1 may be filled by forming the first via layer 130. In this case, since the upper side of the glass layer 110 does not change when the second through hole H2 is formed after the first through hole H1 is formed, only a top plan view of the glass layer 110 when viewed from above is shown, and descriptions about forming the second through hole H2 and forming the second wiring layer 122 on the first via layer 130 are omitted. In addition, the shape and number of the first holes h1 and the shape and number of the first through holes H1 are merely exemplary and may be modified in various ways.

[0098] Furthermore, in the various modifications related to the printed circuit board and the method of manufacturing the printed circuit board according to the first exemplary embodiment, FIG. 5A to FIG. 5J , only the insulating structure of the first insulating layer 111 and the glass layer 110 between the first wiring layer 121 and the second wiring layer 122 and the interlayer connector of the first via layer 130 are shown, and the printed circuit board may have the interlayer structure between the first wiring layer 121 and the second wiring layer 122 at one of the various positions.

[0099] Figure 6 is a schematic cross-sectional view of a portion of a printed circuit board according to a second exemplary embodiment.

[0100] Reference Figure 6 , the printed circuit board according to the second exemplary embodiment may further include an adhesive layer 140 between the first insulating layer 111 and the glass layer 110. The adhesive layer 140 may improve the adhesion between the first insulating layer 111 and the glass layer 110. Because the surface of the glass is smooth and has a low surface roughness, it is difficult to ensure that the glass layer 110 adheres to another component. Therefore, by further including the adhesive layer 140 between the first insulating layer 111 and the glass layer 110, the adhesion between the glass layer 110 and the first insulating layer 111 may be improved. The adhesive layer 140 may include an inorganic oxide film or an organic film.

[0101] In the case where the adhesive layer 140 includes an inorganic oxide film, the adhesive layer 140 may be a thin oxide film including a metal oxide. The metal oxide may include at least one of Al2O3, SiO2, TiO2, ZnO, ZrO2, HfO2, and La2O3, but may also include a metal oxide doped with different metal elements. The metal oxide may preferably include aluminum oxide (Al2O3). In the case where the adhesive layer 140 includes an inorganic oxide film, the adhesive layer 140 may be formed using a thin film deposition technique such as an atomic layer deposition (ALD) technique or a molecular vapor deposition (MVD) technique. Since the adhesive layer 140 is formed using a thin film deposition technique, the adhesive layer 140 may include an oxide film thinner than the first insulating layer 111 and the glass layer 110. As a non-limiting example, the adhesive layer 140 may include a thin oxide film having a thickness of less than 0.1 μm, preferably, having a thickness of about 0.001 μm to 0.05 μm.

[0102] In the case where the adhesive layer 140 includes an organic film, the adhesive layer 140 may be a thin organic film including an organic material. As the organic material, a primer resin for adhesion or a promoter for adhesion, such as an adhesion promoter (AP), may be used. In the case where the adhesive layer 140 includes an organic material, the adhesive layer 140 may be formed using a coating method. As a non-limiting example, the material of the adhesive layer 140 may be coated on the first insulating layer 111 by spraying or by dipping, but the coating method is not limited thereto. Any coating method may be used without limitation as long as a thin organic film can be formed on the first insulating layer 111.

[0103] In addition, the material of the adhesive layer 140 is not limited thereto, and any other material may be used without limitation as long as the material can be disposed between the first insulating layer 111 and the glass layer 110 to serve as a means capable of ensuring adhesion between the first insulating layer 111 and the glass layer 110 .

[0104] The first via layer 130 may be provided to penetrate the adhesive layer 140. More specifically, the first via portion 131 of the first via layer 130 may be provided to penetrate the adhesive layer 140. That is, the opening of the adhesive layer 140 may have the same width as the first through hole H1 of the glass layer 110. In addition, the adhesive layer 140 is not necessarily limited thereto, and the opening of the adhesive layer 140 may have the same width as the second through hole H2 of the first insulating layer 111. In this case, the second via portion 132 of the first via layer 130 may penetrate the adhesive layer 140, and at least a portion of the first via portion 131 of the first via layer 130 may be provided on the adhesive layer 140. This will be described in more detail in the following manufacturing method.

[0105] FIG. 7A to FIG. 7C is a schematic cross-sectional view showing a part of a method of manufacturing a printed circuit board according to a second exemplary embodiment.

[0106] Reference Fig. 7A , the method of manufacturing a printed circuit board may further include forming an adhesive layer 140 after forming the first insulating layer 111. Thereafter, the glass layer 110 may be formed on the adhesive layer. The adhesive layer 140 may be formed using one of various methods according to the type of the adhesive layer 140, and needless to say, a known method may also be used.

[0107] Reference Figure 7B In the case where the adhesive layer 140 includes an inorganic oxide film, when the first hole h1 is formed, the first hole h1 may not penetrate the adhesive layer 140. That is, unlike the case where the first hole h1 may penetrate a portion of the first insulating layer 111 when the first hole h1 is formed, in the case where the adhesive layer 140 includes an inorganic oxide film, the adhesive layer 14 may also serve as a barrier for the first insulating layer 111.

[0108] Thereafter, even when the first through hole H1 is formed by removing a portion of the glass layer 110 , the adhesive layer 140 may not react.

[0109] Thereafter, an opening may be formed in the adhesive layer 140 to correspond to the width of the first through hole H1 at the lower side. By removing a portion of the adhesive layer 140 exposed by the first through hole H1, an opening may be formed in the adhesive layer 140 and the first insulating layer 111 may be exposed to form the second through hole H2. As a method of removing a portion of the adhesive layer 140, an etching process such as dry etching or wet etching may be used. However, the method of removing a portion of the adhesive layer 140 is not limited thereto, and any method may be used without limitation as long as the adhesive layer 140 can be selectively removed. When the opening is formed by removing a portion of the adhesive layer 140, the glass layer 110 may not react, and the first insulating layer 111 may not react. That is, only the adhesive layer 140 may be selectively removed.

[0110] Thereafter, the upper side of the first wiring layer 121 may be exposed by forming a second through hole H2 penetrating the first insulating layer 111. At this time, a portion of the adhesive layer 140 may be removed to correspond to the first through hole H1, and accordingly, a portion of the upper surface of the first insulating layer 111 may be exposed through the opening of the first through hole H1 and the adhesive layer 140.

[0111] Reference Figure 7C , the method of manufacturing a printed circuit board may include forming a first via layer 130 to fill the first through hole H1 and the second through hole H2. At this time, the seed layer 125 is conformally disposed along the boundary of the area exposed by the first through hole H1 and the second through hole H2. Therefore, the seed layer 125 may extend on the inner wall of the first through hole H1 and may extend to the upper surface of the first insulating layer 111 exposed by the opening of the adhesive layer 140. As a result, the first via portion 131 of the first via layer 130 may penetrate the adhesive layer 140.

[0112] Figure 8 A schematic cross-sectional view for explaining a part of a printed circuit board and a method of manufacturing the printed circuit board according to a first modification of the second exemplary embodiment is shown.

[0113] exist Figure 8 , a step after forming the glass layer 110 in the method for manufacturing a printed circuit board according to the second exemplary embodiment is shown, and a schematic diagram corresponding to Figure 7B and Figure 7C steps.

[0114] Reference Figure 8 In the case where the adhesive layer 140 includes an organic film, when the first hole h1 is formed, the first hole h1 may penetrate the adhesive layer 140 and at least a portion of the first insulating layer 111 may be removed.

[0115] Thereafter, when forming the second through hole H2 penetrating the first insulating layer 111, the adhesive layer 140 may be processed simultaneously with the first insulating layer 111. That is, since both the first insulating layer 111 and the adhesive layer 140 include an organic material, the opening of the adhesive layer 140 may be formed simultaneously when the second through hole H2 is formed by performing one process. Since the second through hole H2 and the opening of the adhesive layer 140 are formed simultaneously, the opening of the adhesive layer 140 may correspond to the second through hole H2, and the opening may have substantially the same width as the second through hole H2. At this time, a portion of the adhesive layer 140 may be exposed through the first through hole H1.

[0116] Thereafter, by forming the first via layer 130 , the first via portion 131 of the first via layer 130 may be formed on the adhesive layer 140 . That is, the second via portion 132 penetrating the first insulating layer 111 may penetrate the adhesive layer 140 .

[0117] In addition, in the configuration other than the adhesive layer 140, the same configuration as that in the printed circuit board and the method of manufacturing a printed circuit board according to the first exemplary embodiment and its modifications can be applied to the printed circuit board and the method of manufacturing a printed circuit board according to the second exemplary embodiment and its modifications, and therefore, its repeated description will be omitted.

[0118] Fig. 9 is a schematic cross-sectional view of a portion of a printed circuit board according to a third exemplary embodiment.

[0119] Reference Fig. 9 , the printed circuit board according to the third exemplary embodiment may further include a second insulating layer 112 on the glass layer 110, a second wiring layer 122 may be provided on the second insulating layer 112, and the first via layer 130 may further have a third via portion 133 penetrating the second insulating layer 112. As an example, the first wiring layer 121 and the second wiring layer 122 may be spaced apart from an interface between the first insulating layer 111 and the glass layer 110, and may be spaced apart from an interface between the second insulating layer 112 and the glass layer 110.

[0120] The second insulating layer 112 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric exemplified by glass cloth) and a resin. For example, the insulating material may be a non-photosensitive insulating material such as an Ajinomoto built-up film (ABF) or a prepreg (PPG), but is not limited thereto, and another type of polymer material may be used as the insulating material. Alternatively, the insulating material may be a photosensitive insulating material such as a photosensitive dielectric (PID). In addition, the insulating material may include an adhesive sheet such as a bonding sheet (BS). The second insulating layer 112 may include an insulating material substantially the same as the insulating material of the first insulating layer 111. Specifically, the second insulating layer 112 may preferably include an Ajinomoto built-up film (ABF), but is not limited thereto, and may include an organic insulating material different from the organic insulating material of the first insulating layer 111. In addition, the second insulating layer 112 may include an organic insulating material different from the organic insulating material of the first insulating layer 111. Fig. 9 The second insulating layer 112 is shown as one insulating layer, but is not necessarily limited thereto. If necessary, the second insulating layer 112 may be composed of a plurality of insulating layers, and may also include a configuration that can be used by those skilled in the art.

[0121] Since the second insulating layer 112 may also be provided on the glass layer 110, the second wiring layer 122 may be provided on the second insulating layer 112. That is, the second wiring layer 122 may be provided in contact with the second insulating layer 112. This makes it possible to solve the problem of relatively poor adhesion between the glass layer 110 and the second wiring layer 122. In this case, even if the seed layer 125 includes an electroless plating layer (e.g., a chemical copper plating layer), adhesion can be ensured on the second insulating layer 112.

[0122] The first via layer 130 may further include a third via portion 133 penetrating the second insulating layer 112. The third via portion 133 may be located on the first via portion 131, and the first via portion 131, the second via portion 132, and the third via portion 133 may all be integrally formed. In addition, the third via portion 133 may be integrally formed with the second wiring layer 122.

[0123] In the cross-sectional view, at least one of the first via portion 131, the second via portion 132, and the third via portion 133 may have a width that gradually narrows toward the first wiring layer 121. For example, each of the first via portion 131, the second via portion 132, and the third via portion 133 may have a width that gradually narrows toward the first wiring layer 121. This may be the result of forming a third through hole penetrating the second insulating layer 112, a first through hole penetrating the glass layer 110, and a second through hole penetrating the first insulating layer 111 after stacking the first insulating layer 111, the glass layer 110, and the second through hole penetrating the first insulating layer 111, and then forming the first via layer 130. That is, since the regions where the first via portion 131, the second via portion 132, and the third via portion 133 of the first via layer 130 are to be formed are processed in the same direction to form through holes, each of the first via portion 131, the second via portion 132, and the third via portion 133 may have a width that gradually narrows toward the first wiring layer 121. In addition, in Fig. 9 131, the second via portion 132, and the third via portion 133 are shown as tapering in a substantially straight line manner in a cross-sectional view, but are not necessarily limited thereto. Each of the side surfaces of the first via portion 131, the second via portion 132, and the third via portion 133 may be curved. In addition, Fig. 9 1 and 13 show that the first via portion 131, the second via portion 132, and the third via portion 133 taper at substantially the same inclination, but are not necessarily limited thereto. The first via portion 131, the second via portion 132, and the third via portion 133 may taper to different degrees. That is, the side surface of the first via portion 131, the side surface of the second via portion 132, and the side surface of the third via portion 133 may have different slopes in a cross-sectional view. The formation of the first through hole penetrating the glass layer 110 and the formation of the second through hole penetrating the first insulating layer 111 may be performed in different processes, and because the glass layer 110 and the first insulating layer 111 include different materials, the glass layer 110 and the first insulating layer 111 may be processed to different degrees.

[0124] At the interface between the glass layer 110 and the second insulating layer 112, the first via portion 131 may have a smaller width than the third via portion 133. This may be a result of forming the first via hole penetrating the glass layer 110 after forming the third via hole penetrating the second insulating layer 112.

[0125] The second insulating layer 112 may be thinner than the glass layer 110, but is not necessarily limited thereto. The long insulating distance between the first wiring layer 121 and the second wiring layer 122 may increase the overall thickness of the printed circuit board. Therefore, if the adhesion of the glass layer 110 can be improved, the second insulating layer 112 may be formed sufficiently thin. That is, if the adhesion between the glass layer 110 and the second insulating layer 112 can be ensured to the extent that the second insulating layer 112 is not separated from the glass layer 110, it is preferred that the second insulating layer 112 is formed sufficiently thin. In addition, since the second insulating layer 112 is thinner than the glass layer 110, the first via portion 131 in the first via layer 130 may be deeper than the third via portion 133.

[0126] FIG. 10A to FIG. 10C is a schematic cross-sectional view showing a part of a method of manufacturing a printed circuit board according to a third exemplary embodiment.

[0127] Reference Fig. 10A The method of manufacturing a printed circuit board according to the third exemplary embodiment may further include forming a second insulating layer 112 on the glass layer 110 after forming the glass layer 110. The second insulating layer 112 may be formed on the glass layer 110 using a known insulating layer stacking method.

[0128] Reference Fig. 10B , before forming the first through hole H1 penetrating the glass layer 110, the third through hole H3 penetrating the second insulating layer 112 may be formed. The formation of the third through hole H3 may be performed using a known method for forming a via hole by processing an insulating layer, and may be performed using the same process as the process of forming the second through hole H2 penetrating the first insulating layer 111. At this time, even if the third through hole H3 penetrating the second insulating layer 112 is formed, the glass layer 110 may not be damaged.

[0129] Thereafter, the first through hole H1 penetrating the glass layer 110 may be formed. The formation of the first through hole H1 may be performed by forming the first hole h1. In addition, in the method of manufacturing a printed circuit board according to the third exemplary embodiment, since the first through hole H1 penetrating the glass layer 110 is formed after the second insulating layer 112 is formed on the glass layer 110, it is preferable to set etching conditions when forming the first through hole H1 so that the thickness of the glass layer 110 is not reduced. Thus, it is possible to prevent the thickness of the glass layer 110 from being reduced when the first through hole H1 is formed.

[0130] In addition, Fig. 10B , the first through hole H1 is shown to taper at a substantially constant inclination, but the first through hole H1 is not necessarily limited thereto, and the inner wall of the first through hole H1 may be uneven. In some cases, a step portion may be formed in the first through hole H1 due to the concentration of the etchant.

[0131] Thereafter, a second through hole H2 penetrating the first insulating layer 111 may be formed.

[0132] Reference Fig. 10C , a first via layer 130 may be formed. The first via layer 130 may include a third via portion 133 filling the third via hole H3, the seed layer 125 may be disposed along the inner wall of the third via hole H3, and the first via portion 131, the second via portion 132, and the third via portion 133 may be formed simultaneously.

[0133] Fig.11A and Fig. 11B : is a schematic cross-sectional view showing a part of a printed circuit board and a method of manufacturing the printed circuit board according to a first modification and a second modification of the third exemplary embodiment.

[0134] exist Fig.11A and Fig. 11B In each of the steps, steps after forming the second insulating layer 112 in the method of manufacturing a printed circuit board according to the third exemplary embodiment are shown, and various shapes of the first via layer 130 and a method of manufacturing the same will be mainly described below. Fig.11A and Fig. 11B In each of the embodiments, the last step may correspond to the printed circuit board according to the first modification or the second modification of the third exemplary embodiment.

[0135] Reference Fig.11A In the method of manufacturing a printed circuit board according to the first modification of the third exemplary embodiment, when forming the first through hole H1 penetrating the glass layer 110, the upper portion of the first through hole H1 may be wider than the lower portion of the third through hole H3. This may be the result of the etchant entering a portion below the second insulating layer 112 in the case where wet etching is used when forming the first through hole H1. Since the etchant used to remove a portion of the glass layer 110 does not react with the second insulating layer 112, only the glass layer 110 disposed below the second insulating layer 112 may be removed. In this case, the width of the upper portion of the first through hole H1 may be greater than the width of the lower portion of the third through hole H3. Thereafter, the second through hole H2 penetrating the first insulating layer 111 may be formed. Thereafter, the first via layer 130 may be formed. Also in this case, the seed layer 125 may be conformally disposed along the corresponding inner wall of the through hole.

[0136] In the printed circuit board according to the first modification of the third exemplary embodiment, at the interface between the glass layer 110 and the second insulating layer 112, in the first via layer 130, the first via portion 131 may be wider than the third via portion 133. This may be caused by the shape of the through hole generated when forming the first through hole H1 penetrating the glass layer 110. As the width of the first via portion 131 of the first via layer 130 increases, the contact area between the first via layer 130 and the second insulating layer 112 may be increased, which may be beneficial to ensure adhesion.

[0137] Reference Fig. 11B In the method of manufacturing a printed circuit board according to the second modification of the third exemplary embodiment, when forming the first through hole H1 penetrating the glass layer 110, the first through hole H1 may be formed to have a step. That is, the first through hole H1 may have a step in the glass layer 110. This may occur in an area where the etchant is concentrated when forming the first through hole H1. In the area where the etchant is concentrated, the glass layer 110 is further removed to have a flat surface. In addition, in Fig. 11B , it is shown that the first through hole H1 has a flat surface as a step, but the first through hole H1 is not necessarily limited thereto. The first through hole H1 can be understood as having an inflection point where the degree of width variation changes, rather than having a substantially constant width variation. At this time, it goes without saying that the inner wall of the first through hole H1 may have a curved surface. Thereafter, a second through hole H2 penetrating the first insulating layer 111 may be formed. Thereafter, a first via layer 130 may be formed. Also in this case, the seed layer 125 may be conformally disposed along the corresponding inner wall of the through hole.

[0138] In the printed circuit board according to the second modification of the third exemplary embodiment, the first via portion 131 of the first via layer 130 may have a step between the upper surface and the lower surface of the glass layer 110. Without being limited thereto, the first via portion 131 of the first via layer 130 may have an inflection portion in the glass layer 110, and may have a curved surface. This may be caused by the shape of the first through hole H1 penetrating the glass layer 110 in the above-mentioned method of manufacturing a printed circuit board. As the width of the first via portion 131 of the first via layer 130 increases, and a point where a width change occurs in the first via portion 131 of the first via layer 130, the contact area between the first via layer 130 and the second insulating layer 112 and the contact area between the first via layer 130 and the glass layer 110 may be increased, which may be beneficial to ensure adhesion.

[0139] In addition, in the configuration other than the shape of the first via layer 130 and the second insulating layer 112, the same configuration as that in the printed circuit board and the method of manufacturing a printed circuit board according to the first exemplary embodiment and its variations and the printed circuit board and the method of manufacturing a printed circuit board according to the second exemplary embodiment and its variations can be applied to the printed circuit board and the method of manufacturing a printed circuit board according to the third exemplary embodiment, and therefore, a repeated description thereof will be omitted.

[0140] The above has focused on the insulation structure between the first wiring layer 121 and the second wiring layer 122, and described the printed circuit board and the method for manufacturing the printed circuit board according to the first exemplary embodiment to the third exemplary embodiment. Hereinafter, a printed circuit board to which such an insulation structure is applied will be schematically described with reference to the accompanying drawings. Although various application examples to which the sandwich structure according to the first exemplary embodiment is applied are shown for the purpose of convenience, the application examples are not limited thereto. The sandwich structures according to the second exemplary embodiment and the third exemplary embodiment and their variations can be applied, and various combinations thereof can also be applied.

[0141] FIG. 12A to FIG. 12E Schematic cross-sectional views of printed circuit boards according to first to fifth application examples of the first exemplary embodiment are shown. FIG. 12A to FIG. 12E In each of the first to fifth application examples, the printed circuit board may be a coreless type printed circuit board. In addition, in each of the first to fifth application examples, the first wiring layer 121 is disposed above the second wiring layer 122, and therefore, the positional relationship in the vertical direction is different from that in the first to third exemplary embodiments. However, this is described in a relative manner only for the sake of convenience, and the above differences will be more clearly understood by referring to the accompanying drawings.

[0142] Reference Fig. 12A The printed circuit board according to the first application example of the first exemplary embodiment may further include a buildup insulating layer 151 disposed on the glass layer 110 and covering at least a portion of the second wiring layer 122, a buildup wiring layer 152 disposed on the buildup insulating layer 151, and a buildup via layer 153 penetrating at least a portion of the buildup insulating layer 151 to connect the buildup wiring layer 152 and the second wiring layer 122 to each other. That is, compared with the structure of the printed circuit board according to the first exemplary embodiment, the printed circuit board according to the first application example of the first exemplary embodiment may further include other buildup layers.

[0143] The buildup insulating layer 151 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric exemplified by glass cloth) and a resin. For example, the insulating material may be a non-photosensitive insulating material such as an Ajinomoto built-up film (ABF) or a prepreg (PPG), but is not limited thereto, and another type of polymer material may be used as the insulating material. Alternatively, the insulating material may be a photosensitive insulating material such as a photosensitive dielectric (PID). In addition, the insulating material may include an adhesive sheet such as a bonding sheet (BS). Specifically, the buildup insulating layer 151 may preferably include an Ajinomoto built-up film (ABF), but is not limited thereto, and may include another organic insulating material. In addition, the buildup insulating layer 151 is shown as being composed of Fig. 12A The insulating layer 151 may be composed of one layer in the stacked insulating layer 151, but is not necessarily limited thereto. If necessary, the stacked insulating layer 151 may be composed of a plurality of insulating layers, and may also include a configuration that can be used by those skilled in the art.

[0144] The buildup wiring layer 152 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The buildup wiring layer 152 may preferably include copper (Cu), but is not limited thereto. The buildup wiring layer 152 may each perform various functions according to the design. For example, the buildup wiring layer 152 may include a signal pattern, a power pattern, a ground pattern, etc. Each of these patterns may have various forms, such as a line, a plane, and a pad. The buildup wiring layer 152 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the buildup wiring layer 152 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the buildup wiring layer 152 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). The buildup wiring layer 152 may include a sputtering layer but not an electroless plating layer (e.g., a chemical copper plating layer), or, as required, the buildup wiring layer 152 may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer). The buildup wiring layer 152 may be formed using any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a hole sealing (TT) process, and a subtractive process, but is not limited thereto. Any technology may be used without limitation as long as the technology can construct a circuit on a printed circuit board. In addition, the buildup wiring layer 152 may be formed using different technologies depending on the purpose of use and design.

[0145] The stacked via layer 153 may include micro vias. The micro vias may be filled vias that fill the via holes or conformal vias that are arranged along the walls of the via holes. The micro vias may be arranged as stacked vias and / or staggered vias. The stacked via layer 153 may include a metal, and the metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof, and may preferably include copper (Cu), but is not limited thereto. The stacked via layer 153 may preferably include copper (Cu), but is not limited thereto. The stacked via layer 153 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but is not limited thereto. The stacked via layer 153 may include a sputtering layer without an electroless plating layer, or if necessary, the stacked via layer 153 may include both a sputtering layer and an electroless plating layer. The stacked via layer 153 may each perform various functions according to the design. For example, the build-up via layer 153 may include a ground via, a power via, a signal via, and the like.

[0146] In addition, in the printed circuit board according to the first application example of the first exemplary embodiment, the first wiring layer 121 and the first insulating layer 111 may be located at the outermost side of the printed circuit board. That is, the first wiring layer 121 may be used as a connection pad of the printed circuit board and may perform a function for connecting with an electronic component or the like mounted on the printed circuit board.

[0147] The printed circuit board according to the first application example of the first exemplary embodiment may include a solder resist layer 160 disposed on the first insulating layer 111 and covering at least a portion of the first wiring layer 121. The solder resist layer 160 may be disposed on the outermost side of the printed circuit board to play a role in protecting the printed circuit board. The solder resist layer 160 may be disposed on the first insulating layer 111 (based on Fig. 12A ), and may also be disposed on the stacked insulating layer 151 (based on Fig. 12A The solder resist layer 160 may include an insulating material, and may include a liquid solder resist or a film type solder resist, but is not limited thereto, and any other type of insulating material may be used. The solder resist layer 160 at the uppermost side may have an opening that exposes at least a portion of the first wiring layer 121, and the solder resist layer 160 at the lowermost side may have an opening that exposes at least a portion of the buildup wiring layer 152.

[0148] Reference Fig. 12B, in the printed circuit board according to the second application example of the first exemplary embodiment, the first wiring layer 121 may be disposed on the buildup insulating layer 151, and the first insulating layer 111 may be disposed on the buildup insulating layer 151. Here, the first wiring layer 121 may be considered as the buildup wiring layer 152 disposed under the buildup insulating layer 151. That is, the printed circuit board may be constructed by disposing the structure of the printed circuit board according to the first exemplary embodiment on another buildup layer.

[0149] The printed circuit board according to the second application example of the first exemplary embodiment may further include a stacked insulation layer 151 disposed on one side of the first insulation layer 111, a stacked wiring layer 152 embedded in the stacked insulation layer 151 on one side of the stacked insulation layer 151, and a stacked via layer 153 penetrating at least a portion of the stacked insulation layer 151 to connect the stacked wiring layer 152 and the first wiring layer 121 to each other.

[0150] Reference Fig. 12C , the printed circuit board according to the third application example of the first exemplary embodiment may have a structure in which the first insulating layer 111 is repeatedly disposed on the glass layer 110. That is, the printed circuit board may be constructed by repeatedly arranging the sandwich structure of the printed circuit board according to the first exemplary embodiment. In this case, the second wiring layer 122 may be provided as the first wiring layer 121 of the next structure. At this time, the first insulating layer 111 may be provided on the glass layer 110. In addition, the second wiring layer 122 may also be provided on the outermost side of the printed circuit board, and the solder resist layer 160 may also be provided on the glass layer 110.

[0151] Reference Fig.12D , the printed circuit board according to the fourth application example of the first exemplary embodiment may have a structure combining a sandwich structure and a stacking structure. In other words, in the sandwich structure according to the first exemplary embodiment as a stacking structure, the insulating structure consisting only of an insulating layer may be replaced by an insulating structure including a first insulating layer 111 and a glass layer 110. However, also in this case, considering the stacking direction of the coreless printed circuit board, when controlling the flatness and bending characteristics of the printed circuit board, the sandwich structure according to the first exemplary embodiment is applied to the structure based on Fig.12D The uppermost side may be more preferred.

[0152] Reference Fig.12E , a printed circuit board according to a fifth application example of the first exemplary embodiment may have a structure in which a coreless type printed circuit board is constructed with only the sandwich structure according to the first exemplary embodiment.

[0153] also, FIG. 12A to FIG. 12EThis is merely an example showing how the sandwich structure according to the first exemplary embodiment can be applied to other sandwich structures, and the number of insulating layers and the number of wiring layers can be freely modified, and the wiring patterns of the wiring layers can also be modified in various ways. In addition, the printed circuit boards according to the first to fifth application examples are not limited to FIG. 12A to FIG. 12E The configuration shown in FIG. 1 may include other configurations, or may be omitted in some cases. FIG. 12A to FIG. 12E That is, the printed circuit board may also include any configuration that can be used by those skilled in the art.

[0154] As a non-limiting example, the printed circuit board according to any one of the first application example to the fifth application example may further include a surface treatment layer disposed on at least a portion of the wiring layer exposed by the opening of the solder resist layer 160. The surface treatment layer may include any one of nickel (Ni), palladium (Pd), and gold (Au), and may be implemented by a plurality of metal layers. For example, the surface treatment layer may be at least a portion of an electroless nickel electroless palladium immersion gold (ENEPIG) structure, or may be at least a portion of an electroless nickel immersion gold (ENIG) structure. The surface treatment layer is not limited thereto, and may include an organic solderability preservative (OSP) structure containing an organic material. The surface treatment layer may improve adhesion and signal transmission between the wiring layer and a connector such as solder.

[0155] FIG. 13A to FIG. 13D It shows the manufacturing basis Fig. 12A Schematic cross-sectional view of a method for printing a circuit board according to a first application example of the first exemplary embodiment is shown in FIG.

[0156] Reference Fig.13A The method may further include: forming a first wiring layer 121 on the carrier substrate C before forming the first insulating layer 111 .

[0157] The carrier substrate C is used to support the insulating layer and the wiring layer when the insulating layer and the wiring layer are formed, and may be formed of an insulating material or a metal material. Fig.13A , it is shown that the carrier substrate C includes a core CO and a seed layer C1 formed on both sides of the core CO, but the carrier substrate C is not limited thereto, and the carrier substrate C may be formed as a single layer, or the seed layer C1 may be formed as a double layer. That is, although one example of the carrier substrate C is shown, any carrier substrate C may be used in the present disclosure without particular limitation, as long as the carrier substrate C can be used by those skilled in the art and can be separated or removed after being used as a support substrate. As a non-limiting example, a stop layer including different metal layers may be further formed on the carrier substrate C.

[0158] The first wiring layer 121 may be formed on the carrier substrate C, and the first insulating layer 111 may also be provided on the carrier substrate C to embed the first wiring layer 121. That is, it is understood that in reference to FIG. 4A to FIG. 4C In the method of manufacturing a printed circuit board according to the first exemplary embodiment described, the insulating material 100 corresponds to the carrier substrate C.

[0159] Fig. 13B and Fig. 13C The method of forming the sandwich structure of the printed circuit board according to the first exemplary embodiment may be substantially the same, and therefore, a detailed description thereof will be omitted. In addition, the formation of the through hole penetrating the glass layer 110 and the first insulating layer 111 is briefly expressed, and detailed information thereon may be replaced with the description of the printed circuit board and the method of manufacturing the printed circuit board according to the first exemplary embodiment.

[0160] Reference Fig.13D The method may include: forming a buildup insulation layer 151 , a buildup wiring layer 152 , and a buildup via layer 153 on the glass layer 110 , removing the carrier substrate C, and forming a solder resist layer 160 .

[0161] The buildup insulating layer 151 may be formed on the glass layer 110 using a known buildup layer stacking method, and the buildup wiring layer 152 and the buildup via layer 153 may be formed using any method for building up insulating layers and wiring layers available to those skilled in the art.

[0162] The carrier substrate C may be removed by applying one of various methods according to the shape of the carrier substrate C. For example, when removing the carrier substrate C, the seed layer may be removed sequentially after removing the core included in the carrier substrate, or the carrier substrate may be removed as a whole, that is, the core and the seed layer may be removed simultaneously. The carrier substrate C may be removed using a known process for separating a carrier without limitation.

[0163] In addition, despite the Fig.13D Although not shown in the figure, a portion of the first wiring layer 121 may be removed together when the carrier substrate C is removed, and a so-called recessed portion where a step appears may be formed between the first wiring layer 121 and the first insulating layer 111. This may be a result of removing a portion of the first wiring layer 121 when the seed layer C1 of the carrier substrate C is removed by an etchant.

[0164] After removing the carrier substrate C, the method may include forming a solder resist layer 160 on each of the first insulating layer 111 and the buildup insulating layer 151. The solder resist layer 160 may be formed using any method for buildup insulating layers and wiring layers available to those skilled in the art.

[0165] FIG. 14A to FIG. 14D It shows the manufacturing basis Fig. 12BSchematic cross-sectional view of a method for printing a circuit board according to a second application example of the first exemplary embodiment is shown in FIG.

[0166] Reference Fig.14A , the method of manufacturing a printed circuit board according to the second application example of the first exemplary embodiment includes forming a buildup insulating layer 151, a buildup wiring layer 152, and a buildup via layer 153 on a carrier substrate C. Thereafter, the method may include forming a first insulating layer 111 on the buildup insulating layer 151. At this time, the buildup insulating layer 151 may have a sandwich structure between the first wiring layer 121 and the buildup wiring layer 152. That is, it can be understood that in reference to FIG. 4A to FIG. 4C In the method of manufacturing the printed circuit board according to the first exemplary embodiment, the insulating material 100 corresponds to the carrier substrate C.

[0167] FIG. 14A to FIG. 14C The other configurations in the method for forming the sandwich structure of the printed circuit board according to the first exemplary embodiment may be substantially the same as the configurations in the method for forming the sandwich structure of the printed circuit board according to the first exemplary embodiment, and therefore, a detailed description thereof will be omitted. In addition, the formation of the through hole penetrating the glass layer 110 and the first insulating layer 111 is briefly expressed, and the detailed information thereon may be replaced by the description of the printed circuit board and the method for manufacturing the printed circuit board according to the first exemplary embodiment as described above.

[0168] Reference Fig.14D The method may further include removing the carrier substrate C and forming the solder resist layer 160, which may be performed in substantially the same manner as described in the first application example, and therefore, a repeated description thereof will be omitted. Figures 14A to 14D , the buildup wiring layer 152 may be disposed on the buildup insulating layer 151 and / or in the buildup insulating layer 151 .

[0169] Fig.15A and Fig. 15B Schematic cross-sectional views of printed circuit boards according to sixth and seventh application examples of the first exemplary embodiment are shown.

[0170] Reference Fig.15A and Fig. 15B In each of the sixth application example and the seventh application example, the printed circuit board may be a core type printed circuit board. In addition, in each of the sixth application example and the seventh application example, the layers are stacked upward and downward from the core layer 157, and therefore, the positional relationship in the vertical direction is different from the positional relationship in the vertical direction in the first exemplary embodiment to the third exemplary embodiment. However, this is described in a relative manner only for the sake of convenience, and the above difference will be more clearly understood by referring to the drawings.

[0171] Reference Fig.15A, the printed circuit board according to the sixth application example of the first exemplary embodiment may include a core layer 157 disposed on one side of the first insulating layer 111 and a through hole 158 penetrating the core layer 157. The core layer 157 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber (for example, glass fabric exemplified by glass cloth) and a resin. The insulating material may be a photosensitive material and / or a non-photosensitive material. As the insulating material, solder resist (SR), Ajinomoto deposited film (ABF), FR-4, bismaleimide triazine (BT), resin coated copper (RCC), copper clad laminate (CCL), etc. may be used. However, the insulating material is not limited thereto, and another type of polymer material may be used as the insulating material. In addition, a material including an inorganic filler (such as silica) and a reinforcing material (such as glass fiber) and a resin may also be used, but the insulating material is not limited thereto. For example, a prepreg may be used, but the insulating material is not limited thereto. In addition, as a non-limiting example, the core layer 157 may include a glass substrate, and the material constituting the core layer 157 may not be limited.

[0172] The through-hole 158 may include a metal layer formed on the wall of the through hole penetrating the core layer 157 and a plug filling the space between the metal layers. The metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and may preferably include copper (Cu), but is not limited thereto. The plug may include ink as an insulating material. The metal layer may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but is not limited thereto. The metal layer may include a sputtering layer without an electroless plating layer, or the metal layer may include both a sputtering layer and an electroless plating layer. The through-hole 158 may each perform various functions according to the design. For example, the through-hole 158 may include a ground via, a power via, a signal via, etc.

[0173] In the printed circuit board according to the sixth application example of the first exemplary embodiment, the wiring layer in contact with the core layer 157 may be positioned as the first wiring layer 121, and the sandwich structure according to the first exemplary embodiment may be applied to the core layer 157. Fig.15A 1 shows that the sandwich structure according to the first exemplary embodiment is disposed on the outermost side of the printed circuit board, but the sandwich structure according to the first exemplary embodiment is not limited thereto. Needless to say, another build-up insulating layer and another build-up wiring layer may be further disposed on the glass layer 110. As another example, the above-mentioned first insulating layer, first wiring layer, glass layer, second wiring layer, and first via layer may also be disposed on the other side of the core layer opposite to the side on which the first insulating layer 111, the glass layer 110, etc. are disposed so that the printed circuit board is in a symmetrical form.

[0174] Reference Fig. 15B , the printed circuit board according to the seventh application example of the first exemplary embodiment may have an asymmetric substrate structure that is asymmetric with respect to the core layer 157. The buildup layers including the buildup insulation layer 151, the buildup wiring layer 152, and the buildup via layer 153 may be stacked on the upper side of the core layer 157, and the sandwich structure of the printed circuit board according to the first exemplary embodiment may be applied to the lower side of the core layer. That is, the sandwich structure according to the first exemplary embodiment may be provided on one side of the core layer 157, the buildup layers may be provided on the other side of the core layer 157, and the sandwich structure according to the first exemplary embodiment and the buildup layers may be connected to each other through the through vias 158. Since the printed circuit board according to the first exemplary embodiment includes the glass layer 110 in the sandwich structure, the flatness and the warping characteristics may be improved, and accordingly, the warping may be suppressed even if an asymmetric substrate is implemented.

[0175] also, Fig.15A and Fig. 15B This is merely an example showing how the sandwich structure according to the first exemplary embodiment can be applied to other printed circuit boards, the number of insulating layers and the number of wiring layers can be freely modified, and the wiring patterns of the wiring layers can also be modified in various ways. In addition, the printed circuit boards according to the sixth application example and the seventh application example are not limited to Fig.15A and Fig. 15B The configuration shown in FIG. 1 may also include other configurations, or may be omitted in some cases. Fig.15A and Fig. 15B That is, the printed circuit board may also include a configuration that can be used by those skilled in the art. Needless to say, each of the printed circuit boards according to the sixth application example and the seventh application example may further include a surface treatment layer disposed on a portion of the wiring layer exposed by the opening of the solder resist layer 160.

[0176] FIG. 16A to FIG. 16D It shows the manufacturing Fig.15A Schematic cross-sectional view of a method of printing a circuit board according to a sixth application example of the first exemplary embodiment is shown in FIG.

[0177] The method of manufacturing the printed circuit board according to the sixth application example of the first exemplary embodiment may further include: forming the first wiring layer 121 on the core layer 157, and forming the first insulating layer 111 on the core layer 157 to cover at least a portion of the first wiring layer 121. That is, it can be understood that in reference to FIG. 4A to FIG. 4C In the method of manufacturing a printed circuit board according to the first exemplary embodiment, the insulating material 100 corresponds to the core layer 157 .

[0178] FIG. 16A to FIG. 16DThe other configurations in the method of forming the sandwich structure of the printed circuit board according to the first exemplary embodiment may be substantially the same as the configurations in the method of forming the sandwich structure of the printed circuit board according to the first exemplary embodiment, and therefore, a detailed description thereof will be omitted. In addition, the formation of the through hole penetrating the glass layer 110 and the first insulating layer 111 is briefly described, and the detailed information thereon may be replaced with the description of the printed circuit board and the method of manufacturing the printed circuit board according to the first exemplary embodiment as described above.

[0179] In addition, the printed circuit boards and the methods of manufacturing the printed circuit boards according to the first to seventh application examples are not limited to the configurations shown in the drawings, and may also include other configurations, or may omit any configuration shown in the drawings in some cases. That is, the printed circuit board may also include a configuration that can be used by those skilled in the art without being limited to the configuration shown in the drawings.

[0180] As described above, according to exemplary embodiments in the present disclosure, a printed circuit board including a glass layer and a method of manufacturing the printed circuit board may be provided.

[0181] In addition, a printed circuit board capable of preventing warping and having improved flatness and a method of manufacturing the printed circuit board can be provided.

[0182] In addition, a printed circuit board capable of improving reliability and a method of manufacturing the printed circuit board can be provided.

[0183] While exemplary embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a first insulating layer; a first wiring layer embedded in the first insulating layer on one side of the first insulating layer; a glass layer disposed on the other side of the first insulating layer opposite to the one side; A second wiring layer, disposed on the glass layer; as well as a first via layer connecting the first wiring layer and the second wiring layer to each other and including a first via portion penetrating the glass layer and a second via portion penetrating the first insulating layer, Wherein, in the cross-sectional view of the printed circuit board, at least one of the first via portion and the second via portion has a width that gradually narrows toward the first wiring layer.

2. The printed circuit board according to claim 1, wherein: The first via portion and the second via portion are integrated.

3. The printed circuit board according to claim 1, wherein: The second via portion has a smaller width than the first via portion at an interface between the first insulating layer and the glass layer.

4. The printed circuit board according to claim 1, wherein: At an interface between the glass layer and the second wiring layer, the second wiring layer has a greater width than the first via portion.

5. The printed circuit board according to claim 1, wherein: At an interface between the glass layer and the first insulating layer, the first via portion and the second via portion have the same width.

6. The printed circuit board according to claim 5, wherein: An inclination angle between a side surface of the first via portion and one surface of the first insulating layer in contact with the glass layer is smaller than an inclination angle between a side surface of the second via portion and one surface of the first wiring layer in contact with the second via portion.

7. The printed circuit board according to claim 1, wherein: The first via layer includes a protrusion that is disposed at one side of the first via and embedded in at least a portion of the first insulating layer.

8. The printed circuit board according to claim 7, wherein: The protrusion is spaced apart from the second via portion and is disposed along a boundary between the second via portion and the first insulating layer.

9. The printed circuit board according to claim 1, wherein: The first via layer includes a protrusion that is provided at one side of the first via portion and has a step starting from one surface of the first insulating layer that contacts the glass layer.

10. The printed circuit board according to claim 1, wherein: In the cross-sectional view of the printed circuit board, the first via portion is substantially perpendicular to one surface of the first insulating layer in contact with the glass layer.

11. The printed circuit board according to claim 1, wherein: In the cross-sectional view of the printed circuit board, the second via portion is substantially perpendicular to one surface of the first wiring layer in contact with the second via portion.

12. The printed circuit board according to claim 1, wherein: The second via portion has a greater width than the first via portion at an interface between the first insulating layer and the glass layer.

13. The printed circuit board according to claim 1, wherein: At least one first via in the first via layer includes one second via portion and a plurality of first via portions, each of the plurality of first via portions being in contact with the one second via portion.

14. The printed circuit board according to claim 13, wherein: The at least first via hole includes a protrusion portion disposed at one side of at least one of the plurality of first via portions and embedded in at least a portion of the first insulating layer.

15. The printed circuit board according to claim 13, wherein: In the cross-sectional view of the printed circuit board, each of the plurality of first via portions has a width that gradually narrows toward the first wiring layer.

16. The printed circuit board of claim 1, further comprising an adhesive layer interposed between the glass layer and the first insulating layer.

17. The printed circuit board according to claim 16, wherein: The first via portion penetrates at least a portion of the adhesive layer.

18. The printed circuit board according to claim 16, wherein: The second via portion penetrates at least a portion of the adhesive layer.

19. The printed circuit board according to claim 16, wherein: The adhesive layer includes an inorganic oxide film or an organic film.

20. The printed circuit board of claim 1, further comprising a second insulating layer disposed on the glass layer, in, The second wiring layer is provided on the second insulating layer, The first via layer includes a third via portion penetrating the second insulating layer.

21. The printed circuit board of claim 20, wherein: In the cross-sectional view of the printed circuit board, each of the first via portion, the second via portion, and the third via portion has a width that gradually narrows toward the first wiring layer.

22. The printed circuit board of claim 20, wherein: At an interface between the glass layer and the second insulating layer, the first via portion has a smaller width than the third via portion, and The second via portion has a smaller width than the first via portion at an interface between the glass layer and the first insulating layer.

23. The printed circuit board of claim 20, wherein: The first via portion has a greater width than the third via portion at an interface between the glass layer and the second insulating layer.

24. The printed circuit board of claim 20, wherein: The first via portion has a step between one surface of the glass layer contacting the second insulating layer and another surface of the glass layer opposite to the one surface.

25. The printed circuit board of claim 1, wherein: A surface roughness of the glass layer at an interface between the first insulating layer and the glass layer is smaller than a surface roughness of the glass layer at an interface between the first via layer and the glass layer.

26. The printed circuit board of claim 25, wherein: The surface roughness of the glass layer at the interface between the first insulating layer and the glass layer is smaller than the surface roughness of the glass layer at the interface between the second wiring layer and the glass layer.

27. The printed circuit board of claim 1, wherein: The first via portion has a greater depth than the second via portion.

28. The printed circuit board of claim 1, further comprising: A stacked insulating layer is disposed on the glass layer and covers at least a portion of the second wiring layer; A build-up wiring layer is disposed on the build-up insulating layer; as well as A build-up via layer penetrates at least a portion of the build-up insulating layer to connect the build-up wiring layer and the second wiring layer to each other.

29. The printed circuit board of claim 1, further comprising: A stacked insulating layer is disposed on the one side of the first insulating layer; a build-up wiring layer embedded in the build-up insulating layer on one side of the build-up insulating layer; as well as A build-up via layer penetrates at least a portion of the build-up insulating layer to connect the build-up wiring layer and the first wiring layer to each other.

30. The printed circuit board of claim 1, further comprising a solder resist layer disposed on the one side of the first insulating layer and covering at least a portion of the first wiring layer. 31 . The printed circuit board of claim 30 , further comprising a surface finishing layer disposed on at least a portion of the first wiring layer exposed through the opening of the solder resist layer.

32. The printed circuit board of claim 1, further comprising a solder resist layer disposed on the glass layer and covering at least a portion of the second wiring layer.

33. The printed circuit board of claim 1, further comprising: a core layer, one side of the core layer being disposed on the one side of the first insulating layer; as well as The through hole penetrates at least a portion of the core layer.

34. The printed circuit board of claim 33, wherein: The first insulating layer, the first wiring layer, the glass layer, the second wiring layer and the first via layer are also disposed on the other side of the core layer opposite to the one side, and The through vias connect the first wiring layers, which are respectively provided on opposite sides of the core layer, to each other.

35. The printed circuit board of claim 33, further comprising: A stacked insulating layer is disposed on the other side of the core layer opposite to the one side of the core layer; A build-up wiring layer is respectively arranged on the other side of the core layer opposite to the one side and on the build-up insulating layer; as well as A build-up via layer penetrates at least a portion of the build-up insulating layer to connect the build-up wiring layers to each other.

36. A printed circuit board comprising: Insulation layer; A first wiring layer is provided on one side of the insulating layer; a glass layer disposed on the other side of the insulating layer opposite to the one side; a via layer including a first through hole, a second through hole, a portion of a first metal layer, and a portion of a second metal layer, the second through hole penetrating the insulating layer and exposing at least a portion of the first wiring layer, the first through hole penetrating the glass layer and connected to the second through hole, a portion of the first metal layer being disposed on the at least partially exposed portion of the first wiring layer and a wall of each of the first through hole and the second through hole, and a portion of the second metal layer being disposed on the first metal layer and disposed in at least a portion of each of the first through hole and the second through hole; as well as A second wiring layer is disposed on the glass layer and connected to the via layer.

37. The printed circuit board of claim 36, wherein: The portion of the first metal layer extends continuously on the at least partially exposed portion of the first wiring layer and the wall of each of the first and second vias.

38. The printed circuit board of claim 36, wherein: Another portion of each of the first metal layer and the second metal layer extends onto the glass layer, and The second wiring layer includes the other portion of each of the first metal layer and the second metal layer extending onto the glass layer.

39. A method of manufacturing a printed circuit board, the method comprising: forming a first insulating layer in which a first wiring layer is embedded; forming a glass layer on the first insulating layer; forming a first through hole penetrating the glass layer; forming a second through hole penetrating the first insulating layer and exposing at least a portion of the first wiring layer; forming a first via layer in the first through hole and the second through hole; as well as A second wiring layer connected to the first via layer is formed on the glass layer.

40. The method of claim 39, wherein: When forming the first via layer, the first through hole and the second through hole are filled simultaneously.

41. The method of claim 39, wherein: The step of forming the first via layer includes forming a seed layer along inner walls of the first through hole and the second through hole and forming a plating layer on the seed layer.

42. The method of claim 39, wherein: The step of forming the first through hole includes forming a first hole penetrating the glass layer and removing a portion of the first insulating layer, and forming the first through hole by removing a portion of the glass layer adjacent to the first hole.

43. The method of claim 42, wherein: The first hole is formed by emitting a laser to process the glass layer and the first insulating layer, and The first through hole is formed by etching.

44. The method of claim 42, wherein: When forming the first through hole, at least a portion of the first hole is expanded, and at least a portion of an upper portion of the glass layer is removed.

45. The method of claim 39, further comprising forming an adhesive layer on the first insulating layer before forming the glass layer, in, The glass layer is formed on the adhesive layer.

46. ​​The method of claim 45, further comprising forming an opening by removing at least a portion of the adhesive layer after forming the first through hole.

47. The method of claim 45, further comprising: Before forming the first through hole, forming a second insulating layer on the glass layer; as well as A third through hole is formed penetrating at least a portion of the second insulating layer.

48. The method of claim 39, further comprising: Before forming the first insulating layer, forming the first wiring layer on the carrier substrate; as well as The carrier substrate is removed after forming the second wiring layer.

49. The method according to claim 39, further comprising forming the first wiring layer on the buildup layer before forming the first insulating layer, in, The buildup layer includes a buildup insulating layer, a buildup wiring layer disposed on and / or in the buildup insulating layer, and a buildup via layer penetrating at least a portion of the buildup insulating layer to connect the buildup wiring layer and the first wiring layer to each other.

50. The method of claim 39, further comprising forming the first wiring layer on the core layer before forming the first insulating layer.

51. The method according to claim 39, further comprising forming a buildup layer on the glass layer after forming the second wiring layer, in, The buildup layer includes a buildup insulating layer, a buildup wiring layer disposed on the buildup insulating layer, and a buildup via layer penetrating at least a portion of the buildup insulating layer to connect the buildup wiring layer and the second wiring layer to each other.

52. A printed circuit board comprising: a first insulating layer; A glass layer, disposed on the first insulating layer; a plurality of wiring layers including a first wiring layer attached to the first insulating layer and a second wiring layer disposed on the glass layer; as well as a via layer connecting the first wiring layer and the second wiring layer to each other and including a first via portion provided in the glass layer and a second via portion extending from the first via portion and provided in the first insulating layer, The surface roughness of one surface of the glass layer opposite to the first insulating layer is smaller than the surface roughness of another surface of the glass layer opposite to the one surface of the glass layer.

53. The printed circuit board of claim 52, wherein: The second via portion has a width smaller than a width of the first via portion at an interface between the first insulating layer and the glass layer.

54. The printed circuit board of claim 52, wherein: At an interface between the glass layer and the first insulating layer, the first via portion and the second via portion have the same width.

55. The printed circuit board of claim 52, wherein: The via layer includes a protrusion portion disposed at one side of the first via portion and embedded in at least a portion of the first insulating layer.

56. The printed circuit board of claim 55, wherein: The protrusion is spaced apart from the second via portion and is disposed along a boundary between the second via portion and the first insulating layer.

57. The printed circuit board of claim 52, wherein: The second via portion has a width greater than a width of the first via portion at an interface between the first insulating layer and the glass layer.

58. The printed circuit board of claim 52, wherein: At least one first via in the via layer includes one second via portion and a plurality of first via portions, each of the plurality of first via portions being in contact with the one second via portion.

59. The printed circuit board of claim 52, further comprising an adhesive layer interposed between the glass layer and the first insulating layer, in, The via layer penetrates at least a portion of the adhesive layer.

60. The printed circuit board of claim 52, wherein: The plurality of wiring layers are spaced apart from an interface between the first insulating layer and the glass layer.

61. The printed circuit board of claim 52, further comprising a second insulating layer disposed on the glass layer, in, The second wiring layer is provided on the second insulating layer, and The via layer further includes a third via portion penetrating the second insulating layer.

62. The printed circuit board of claim 61, wherein: The plurality of wiring layers are spaced apart from an interface between the second insulating layer and the glass layer.

63. The printed circuit board of claim 52, wherein: The surface roughness of the one surface of the glass layer is smaller than the surface roughness of a wall surface of a through hole in the glass layer in which the first via portion is provided.

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