Metal film resistor and preparation method thereof

Abstract

The invention provides a metal film resistor and a preparation method thereof, and the method comprises the steps: removing an original SAB mask pattern from an original HiR mask pattern in a silicon-based high-resistance resistor technology through Boolean operation NOT, and enabling the original HiR mask pattern to serve as a contact region of a subsequent CT contact hole; and then defining a metal film resistor mask pattern by using an original SAB mask pattern in a silicon-based high-resistance resistor process through Boolean operation, and then forming a metal film resistor covering the patterned low-resistance metal layer. In the process of port migration from the silicon-based high-resistance resistor process to the metal film resistor process, a mask pattern in the silicon-based high-resistance resistor process does not need to be changed, and the consistency of a resistor length definition mode between two ports can be realized only by performing required Boolean operation on the mask pattern in the silicon-based high-resistance resistor process; according to the invention, the change of the layout of the rear-end CT process is avoided, and the lengths of the designed resistors of the two ports have consistent definition, so that the risks of complex operation and poor contact between the CT and the MET1 caused by the change of the layout of the rear-end CT process are avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a metal film resistor and a preparation method thereof. Background Art

[0002] In the current advanced logic chip process, the high resistance (Hi-R) layer is a key element in circuit design for reducing voltage and current. High resistance can be divided into active resistance and passive resistance. Active resistance usually uses the resistance characteristics of transistors in a specific working area; passive resistance is a high-resistance thin film conductive layer prepared in a specific area of ​​the device. Since passive resistance is not affected by current and voltage and has stable performance, it is used in most integrated circuit designs.

[0003] There are two main technologies for passive resistors. Figure 6 The metal film resistor used to realize the high resistance layer is also called the high resistance metal layer (Hi-R metal layer); the other is Figure 5 The polysilicon resistor is formed by doping the polysilicon material.

[0004] For Figure 5 The polysilicon resistor is generally prepared by: Figure 1 As shown, a doped polysilicon layer 101 is formed on a substrate 100; Figure 2 As shown, the polysilicon layer 101 is then patterned using a HiR mask to form a patterned polysilicon layer 102 in a preset area (an area where a resistor is to be formed); Figure 3 As shown, a SAB film 104 is then formed, and the SAB film 104 is patterned based on the SAB mask 103 to obtain Figure 4 The patterned SAB film 104 shown; Figure 5 As shown, the Salicide process is then used to form a metal silicide layer 105 in the remaining area of ​​the patterned polysilicon layer 102 as an ohmic contact layer for subsequent contact holes (Contact, CT); Figure 5 As shown, finally, a CT contact hole 106 is formed on the metal silicide layer 105. Therefore, for the polysilicon resistor, Figure 5 As shown, the designed resistance length is defined by the boundary of the patterned SAB film 104, such as Figure 5 In L1. Figure 6The metal film resistor 107 is generally prepared by forming the metal film resistor 107 in a predetermined area (area where the resistor needs to be formed) of the substrate 100; and then directly forming CT contact holes 106 at both ends of the metal film resistor 107. Therefore, for the metal film resistor 107, its designed resistance length is defined by the boundaries of the CT contact holes 106 at both ends, that is, Figure 6 When it is necessary to switch between these two types of resistors, the different resistor length definitions will cause the resistor length to offset during the migration process. At this time, the layout of the back-end CT contact hole process needs to be changed, such as Figure 7 As shown, Figure 6 The CT contact hole 106 is moved from the outside to the inside along the arrow direction after calculation, so that the designed resistance length of the metal film (i.e., L2) is consistent with the designed resistance length of the polysilicon resistor (i.e., L1), and both are the boundaries of the patterned SAB film 104. This requires very complex calculations, and there may be a risk of poor connection with MET1 (the first metal layer) when moving the CT contact hole, affecting the reliability of the circuit. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, the object of the present invention is to provide a metal thin film resistor and a preparation method thereof, which is used to solve the problem that in the process of migrating the port of the metal thin film resistor to the port of the polysilicon resistor in the prior art, the resistance length is offset during the migration process due to the different boundary definition methods of the designed resistance lengths of the two. It is necessary to change the layout of the back-end CT process to make the designed resistance lengths of the two consistent, which brings about complex calculations and subsequent poor contact between CT and MET1.

[0006] To achieve the above object and other related objects, the present invention provides a method for preparing a metal thin film resistor, the method comprising the following steps:

[0007] Providing a substrate, and sequentially forming a low-resistance metal layer and a first hard mask layer on the substrate;

[0008] The first hard mask layer is etched and patterned based on the modified HiR mask to obtain a patterned first hard mask layer, and the area where the patterned first hard mask layer is located defines a subsequent CT contact hole formation area; wherein the modified HiR mask pattern is obtained by performing a Boolean operation of the original HiR mask pattern NOT the original SAB mask pattern;

[0009] Etching the low-resistance metal layer based on the patterned first hard mask layer to form a patterned low-resistance metal layer and removing the patterned first hard mask layer;

[0010] forming a high-resistance metal layer and a second hard mask layer in sequence on the substrate and the patterned low-resistance metal layer;

[0011] The second hard mask layer is etched and patterned based on the modified SAB mask to obtain a patterned second hard mask layer, and the area where the patterned second hard mask layer is located defines a subsequent metal thin film resistor formation area; wherein the modified SAB mask pattern is obtained by performing a Boolean operation on the original SAB mask pattern to obtain a metal thin film resistor mask pattern;

[0012] Etching the high-resistance metal layer based on the patterned second hard mask layer to form the metal thin film resistor;

[0013] The CT contact hole penetrating the metal film resistor and the patterned second hard mask layer is formed on the patterned low-resistance metal layer.

[0014] Optionally, the substrate is a silicon-based substrate.

[0015] Optionally, a shallow trench isolation structure is formed in the substrate; and the metal film resistor is formed above the shallow trench isolation structure.

[0016] Furthermore, a metal gate structure is formed on the shallow trench isolation structure, and the metal gate structure is isolated from the metal thin film resistor by an insulating layer.

[0017] Optionally, the material of the low-resistance metal layer is titanium nitride material, and the material of the high-resistance metal layer is titanium nitride material.

[0018] Furthermore, the thickness of the low-resistance metal layer is more than ten times the thickness of the high-resistance metal layer.

[0019] Optionally, the first hard mask layer is a silicon nitride layer and / or a silicon oxide layer, and the second hard mask layer is a silicon nitride layer and / or a silicon oxide layer.

[0020] Optionally, the method of forming the CT contact hole includes:

[0021] forming a dielectric layer with a flat surface on the substrate and the patterned second hard mask layer;

[0022] Sequentially etching the dielectric layer, the patterned second hard mask layer and the metal film resistor to form a CT hole;

[0023] The CT hole is filled with a metal conductive material to obtain the CT contact hole.

[0024] Optionally, the method for obtaining the patterned first hard mask layer includes:

[0025] forming a first photoresist layer on the first hard mask layer;

[0026] patterning the first photoresist layer using the modified HiR mask to obtain a patterned first photoresist layer;

[0027] Etching the first hard mask layer based on the patterned first photoresist layer to obtain the patterned first hard mask layer;

[0028] removing the patterned first photoresist layer;

[0029] The method for obtaining the patterned second hard mask layer comprises:

[0030] forming a second photoresist layer on the second hard mask layer;

[0031] patterning the second photoresist layer using the modified SAB mask to obtain a patterned second photoresist layer;

[0032] Etching the second hard mask layer based on the patterned second photoresist layer to obtain the patterned second hard mask layer;

[0033] The patterned second photoresist layer is removed.

[0034] The present invention also provides a metal film resistor, which is prepared by using any one of the above methods for preparing a metal film resistor.

[0035] As described above, the metal thin film resistor and the preparation method thereof of the present invention are obtained by performing a Boolean operation NOT on the original SAB mask pattern of the original HiR mask pattern in the silicon-based high-resistance resistor process to obtain a modified HiR mask pattern as the area for ohmic contact of the subsequent CT contact hole, that is, the patterned low-resistance metal layer area, and then the original SAB mask pattern in the silicon-based high-resistance resistor process is obtained by a Boolean operation to obtain a modified SAB mask pattern, so that the modified SAB mask pattern defines a metal thin film resistor mask pattern, and then a metal thin film resistor covering the patterned low-resistance metal layer is formed based on the metal thin film resistor mask pattern, and finally a CT contact hole connected to the patterned low-resistance metal layer is formed. Since the area between the patterned low-resistance metal layers is actually the original SAB mask pattern, and the metal film resistor is formed on the patterned low-resistance metal layer, the designed resistance length of the metal film resistor finally formed can be defined by the boundary of the original SAB mask pattern, and the boundary of the original SAB mask pattern is also the resistance length definition method of the silicon-based high-resistance resistor in the silicon-based high-resistance resistor process. Therefore, in the process of migrating the silicon-based high-resistance resistor process to the metal film resistor process port, there is no need to change the mask pattern in the silicon-based high-resistance resistor process. The consistency of the resistance length definition method between the two ports can be achieved by only performing the required Boolean operation on the mask pattern in the silicon-based high-resistance resistor process; avoiding changing the layout of the back-end CT process so that the designed resistance lengths of the two ports have a consistent definition, thereby avoiding the complex calculations caused by changing the layout of the back-end CT process and the risk of poor contact between CT and MET1. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figures 1 to 5 It shows a schematic diagram of the cross-sectional structure of each step in the process of preparing a polysilicon resistor in the prior art.

[0037] Figure 6 It is a schematic diagram showing the cross-sectional structure of a metal film resistor 107 in the prior art.

[0038] Figure 7 A schematic diagram of the top view of the structure showing that when the design length of the metal film resistor needs to be consistent with the design length of the polysilicon resistor, the CT contact hole needs to be moved.

[0039] Figures 8 to 26 It is a schematic diagram showing the steps in the method for preparing the metal thin film resistor of the present invention.

[0040] Component number description

[0041] 100 Substrate

[0042] 101 Polysilicon Layer

[0043] 102 Patterned polysilicon layer

[0044] 103 SAB mask layer

[0045] 104 SAB Mask

[0046] 105 Metal silicide layer

[0047] 106 CT contact hole

[0048] 107 Metal Film Resistor

[0049] 200 Substrate

[0050] 201 Shallow Trench Isolation Structure

[0051] 202 Metal Gate Structure

[0052] 203 Gate metal layer

[0053] 204 Work function layer

[0054] 205 High K gate dielectric layer

[0055] 206 Insulation layer

[0056] 207 Low resistance metal layer

[0057] 208 first hard mask layer

[0058] 209 first photoresist layer

[0059] 210 Patterned first photoresist layer

[0060] 211 Patterned first hard mask layer

[0061] 212 Patterned low-resistance metal layer

[0062] 213 High resistance metal layer

[0063] 214 second hard mask layer

[0064] 215 second photoresist layer

[0065] 216 Patterned second photoresist layer

[0066] 217 Patterned second hard mask layer

[0067] 218 Metal Film Resistor

[0068] 219 dielectric layer

[0069] 220 CT hole

[0070] 221 CT contact hole

[0071] 222 Original HiR mask pattern

[0072] 223 Original SAB mask pattern

[0073] 223a Original SAB pattern

[0074] 224 Modified HiR mask pattern

[0075] 224a Modified HiR pattern

[0076] 225 Modified SAB mask pattern DETAILED DESCRIPTION

[0077] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0078] Please refer to 8 to Fig.24 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0079] This embodiment provides a method for preparing a metal thin film resistor, the method comprising the following steps:

[0080] S1, providing a substrate, and sequentially forming a low-resistance metal layer and a first hard mask layer on the substrate;

[0081] S2, etching and patterning the first hard mask layer based on the modified HiR mask to obtain a patterned first hard mask layer, wherein the area where the patterned first hard mask layer is located defines a subsequent CT contact hole formation area; wherein the modified HiR mask pattern is obtained by performing a Boolean operation of the original HiR mask pattern NOT the original SAB mask pattern;

[0082] S3, etching the low-resistance metal layer based on the patterned first hard mask layer to form a patterned low-resistance metal layer and removing the patterned first hard mask layer;

[0083] S4, sequentially forming a high-resistance metal layer and a second hard mask layer on the substrate and the patterned low-resistance metal layer;

[0084] S5, etching and patterning the second hard mask layer based on the modified SAB mask to obtain a patterned second hard mask layer, wherein the area where the patterned second hard mask layer is located defines a subsequent metal thin film resistor formation area; wherein the modified SAB mask pattern is obtained by performing a Boolean operation on the original SAB mask pattern to obtain a metal thin film resistor mask pattern;

[0085] S6, etching the high-resistance metal layer based on the patterned second hard mask layer to form the metal thin film resistor;

[0086] S7, forming the CT contact hole penetrating the metal thin film resistor and the patterned second hard mask layer on the patterned low-resistance metal layer.

[0087] The preparation method of the metal thin film resistor of this embodiment is to use Boolean operation to NOT the original SAB mask pattern of the original HiR mask pattern in the silicon-based high-resistance resistor process to obtain a modified HiR mask pattern as the area for subsequent CT contact holes to make ohmic contacts, that is, the patterned low-resistance metal layer area, and then use Boolean operation to obtain a modified SAB mask pattern from the original SAB mask pattern in the silicon-based high-resistance resistor process, so that the modified SAB mask pattern defines a metal thin film resistor mask pattern, and then based on the metal thin film resistor mask pattern, a metal thin film resistor covering the patterned low-resistance metal layer is formed, and finally a CT contact hole connected to the patterned low-resistance metal layer is formed. Since the area between the patterned low-resistance metal layers is actually the original SAB mask pattern, and the metal film resistor is formed on the patterned low-resistance metal layer, the designed resistance length of the metal film resistor finally formed can be defined by the boundary of the original SAB mask pattern, and the boundary of the original SAB mask pattern is also the resistance length definition method of the silicon-based high-resistance resistor in the silicon-based high-resistance resistor process. Therefore, in the process of migrating the silicon-based high-resistance resistor process to the metal film resistor process port, there is no need to change the mask pattern in the silicon-based high-resistance resistor process. The consistency of the resistance length definition method between the two ports can be achieved by only performing the required Boolean operation on the mask pattern in the silicon-based high-resistance resistor process; avoiding changing the layout of the back-end CT process so that the designed resistance lengths of the two ports have a consistent definition, thereby avoiding the complex calculations caused by changing the layout of the back-end CT process and the risk of poor contact between CT and MET1.

[0088] The method for preparing the metal film resistor of this embodiment is described in detail below with reference to the specific drawings.

[0089] like Figure 8 As shown, step S1 is first performed to provide a substrate 200 , and a low-resistance metal layer 207 and a first hard mask layer 208 are sequentially formed on the substrate 200 .

[0090] It should be noted that, for ease of understanding, this embodiment only shows a portion of the substrate 200 related to the preparation of the metal thin film resistor. In practice, the substrate 200 also includes other regions required for the preparation of the device.

[0091] As an example, the substrate 200 may include a semiconductor compound, an insulating material, a conductor material, or any combination thereof, and may be a single-layer structure or a multi-layer structure. Therefore, the substrate 200 may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors; or may include a layered substrate such as, for example, Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. In this embodiment, the substrate 200 is selected to be a silicon-based substrate.

[0092] The metal thin film resistor is generally formed in a specific area of ​​the device, for example, mostly formed on the shallow trench isolation structure 201 of the device. Figure 8 As shown, in this embodiment, a shallow trench isolation structure 201 is formed in the substrate 200, and the subsequently formed metal thin film resistor is formed above the shallow trench isolation structure 201. In addition, in order to facilitate understanding, only a part of the shallow trench isolation structure 201 is shown in the drawings, and other parts not related to the preparation of the metal thin film resistor of this embodiment are not shown.

[0093] Furthermore, a metal gate structure 202 is formed on the shallow trench isolation structure 201, and an insulating layer 206 with a flush surface is formed on the metal gate structure 202 and the shallow trench isolation structure 201, and the subsequent metal thin film resistor is stacked and prepared with the insulating layer 206 as the base layer. Figure 8 As shown, as an example, the metal gate structure 202 includes a gate metal layer 203, a work function layer 204 and a high-K gate dielectric layer 205 from the inside to the outside. Generally, aluminum material is selected as the gate metal layer 203, titanium nitride material and / or tantalum nitride material is selected as the work function layer 204, and silicon oxynitride material is selected as the high-K dielectric layer 205, but it is not limited thereto. Other suitable materials that can be used as the metal gate structure 202 are also available. This is just an illustration. It should be noted here that the metal gate structure 202 is prepared synchronously with the metal gate structure of the active area of ​​the device. This structure has no effect on the metal thin film resistor prepared subsequently, so an insulating layer 206 is required for electrical isolation.

[0094] As an example, the material of the low-resistance metal layer 207 can be any suitable low-resistance metal material, such as aluminum, copper, titanium nitride, tantalum nitride, etc. Preferably, the material of the low-resistance metal layer 207 is titanium nitride, which is easy to etch and not easy to diffuse.

[0095] As an example, the first hard mask layer 208 is selected to be a single-layer structure of a silicon nitride layer or a silicon oxide layer, or a stacked-layer structure of a silicon nitride layer and a silicon oxide layer, wherein the silicon nitride layer is located at the lower layer and the silicon oxide layer is located at the upper layer.

[0096] like Fig. 9 , Fig.10 and Fig.13 As shown, step S2 is then performed, in which the first hard mask layer 208 is etched and patterned based on the modified HiR mask to obtain a patterned first hard mask layer 211, and the area where the patterned first hard mask layer 211 is located defines the subsequent CT contact hole formation area; wherein the modified HiR mask pattern 224 is obtained by a Boolean operation of the original HiR mask pattern 222 NOT the original SAB mask pattern 223.

[0097] in, Fig. 9 Schematic diagram of the superposition of the original HiR mask pattern 222 and the original SAB mask pattern 223 relative to the low-resistance metal layer 207 in the silicon-based high-resistance resistor process, Fig.10 The modified HiR mask pattern 224 of the relatively low-resistance metal layer 207 is shown as a result of a Boolean NOT operation between the original HiR mask pattern 222 and the original SAB mask pattern 223. It should be noted that the mask pattern mentioned in this embodiment only shows the mask pattern of the part related to the process of preparing the metal thin film resistor. In practice, the entire mask pattern also includes the mask pattern of the other regional structures of the device. The mask pattern of this part is not changed in this embodiment, so it is not shown here. For example, the original HiR mask pattern 222 refers to the mask pattern used in the HiR process, which includes not only Fig. 9 The mask pattern prepared on the shallow trench isolation structure shown in the figure also includes the mask pattern prepared on other regions of the device (not shown in the figure). Similarly, the original SAB mask pattern 223 refers to the mask pattern used in the preparation SAB process, which includes not only Fig. 9 The mask pattern prepared on the shallow trench isolation structure shown in the figure also includes mask patterns prepared on other regions of the device (not shown in the figure).

[0098] like Figures 11 to 13 As shown, as a specific example, the method for forming the patterned first hard mask layer 211 includes the following steps:

[0099] S21, such as Fig.11 As shown, a first photoresist layer 209 is formed on the first hard mask layer 208;

[0100] S22, such as Fig.10 and Fig.12As shown, the first photoresist layer 209 is patterned using the modified HiR mask 224 to obtain a patterned first photoresist layer 210;

[0101] S23, such as Fig.13 As shown, the first hard mask layer 208 is etched based on the patterned first photoresist layer 210 to obtain the patterned first hard mask layer 211;

[0102] S24, such as Fig.13 As shown, the patterned first photoresist layer 210 is removed.

[0103] like Fig.14 and Fig.15 As shown, step S3 is then performed to etch the low-resistance metal layer 207 based on the patterned first hard mask layer 211 to form a patterned low-resistance metal layer 212 and remove the patterned first hard mask layer 211 .

[0104] in, Fig.15 The plan view of the relative positions of the modified HiR pattern 224a and the original SAB pattern 223a after forming the patterned low-resistance metal layer 212 is shown. It can be seen from the figure that the distance L2 between the modified HiR pattern 224a is the boundary of the original SAB pattern 223a.

[0105] like Fig.16 As shown, step S4 is then performed to sequentially form a high-resistance metal layer 213 and a second hard mask layer 214 on the substrate 200 and the patterned low-resistance metal layer 212 .

[0106] As an example, the material of the high-resistance metal layer 213 can be any metal material suitable for use as a high-resistance resistor in a device, such as titanium nitride, tantalum nitride, etc. Preferably, when the material of the low-resistance metal layer 207 is titanium nitride, the material of the high-resistance metal layer 213 is also titanium nitride, which is easy to etch and difficult to diffuse. In addition, the resistance of titanium nitride can be adjusted by thickness, and the thicker the titanium nitride, the smaller the resistance. In this embodiment, when the materials of the low-resistance metal layer 207 and the high-resistance metal layer 213 are both titanium nitride, the thickness of the low-resistance metal layer 207 is more than ten times the thickness of the high-resistance metal layer 213.

[0107] As an example, the second hard mask layer 214 is selected to be a single-layer structure of a silicon nitride layer or a silicon oxide layer, or a stacked-layer structure of a silicon nitride layer and a silicon oxide layer, wherein the silicon nitride layer is located at the lower layer and the silicon oxide layer is located at the upper layer.

[0108] like Fig.17 , Fig.18 and Fig. 22As shown, step S5 is then performed, in which the second hard mask layer 214 is etched and patterned based on the modified SAB mask to obtain a patterned second hard mask layer 217, and the area where the patterned second hard mask layer 217 is located defines the subsequent metal film resistor formation area; wherein the modified SAB mask pattern 225 is obtained by performing a Boolean operation on the original SAB mask pattern 223 to obtain a metal film resistor mask pattern.

[0109] in, Fig.17 Schematic diagram of the original SAB mask pattern 223 relative to the high-resistance metal layer 213 in the silicon-based high-resistance resistor process, Fig.18 The diagram shows a comparison between the modified SAB mask pattern 225 obtained by performing a Boolean operation on the original SAB mask pattern 223 and the high-resistance metal layer 213 .

[0110] like Figures 19 to 22 As shown, as a specific example, the method for forming the patterned second hard mask layer 217 includes the following steps:

[0111] S51, such as Fig.19 As shown, a second photoresist layer 215 is formed on the second hard mask layer 214;

[0112] S52, such as Fig.18 and Fig. 20 As shown, the second photoresist layer 215 is patterned using the modified SAB mask to obtain a patterned second photoresist layer 216;

[0113] S53, such as Fig.21 As shown, the second hard mask layer 214 is etched based on the patterned second photoresist layer 216 to obtain the patterned second hard mask layer 217;

[0114] S54, such as Fig. 22 As shown, the patterned second photoresist layer 216 is removed.

[0115] like Fig. 22 and Fig.23 As shown, step S6 is then performed to etch the high-resistance metal layer 213 based on the patterned second hard mask layer 217 to form the metal thin film resistor 218 .

[0116] like Fig.26 As shown, step S7 is finally performed to form a CT contact hole 221 on the patterned low-resistance metal layer 212 that penetrates the metal thin film resistor 218 and the patterned second hard mask layer 217 .

[0117] like Figure 24 to Figure 26As shown, as a specific example, the method for forming the CT contact hole 221 includes the following steps:

[0118] S71, such as Fig.24 As shown, a dielectric layer 219 with a flat surface is formed on the substrate 200 and the patterned second hard mask layer 217, that is, the dielectric layer 219 covers the entire structure on the insulating layer 206 and has a flat surface. After the dielectric layer 219 is formed, its surface can be flattened by a CMP process;

[0119] S72, such as Fig.25 As shown, the dielectric layer 219, the patterned second hard mask layer 217 and the metal film resistor 218 are sequentially etched to form a CT hole 220, that is, the CT hole 220 exposes the surface of the patterned low-resistance metal layer 212;

[0120] S73, such as Fig.26 As shown, the CT hole 220 is filled with a metal conductive material to obtain the CT contact hole 221. For example, the CT hole 220 can be filled with a PVD process and the metal material outside the CT hole 220 can be ground with a CMP process to retain only the metal material of the CT hole 220 to obtain the CT contact hole 221.

[0121] This embodiment further provides a metal thin film resistor, which is prepared by the method for preparing the metal thin film resistor of this embodiment.

[0122] In summary, the present invention provides a metal thin film resistor and a preparation method thereof, wherein the original HiR mask pattern in the silicon-based high-resistance resistor process is NOT replaced by the original SAB mask pattern through Boolean operation to obtain a modified HiR mask pattern as a region for subsequent CT contact holes to make ohmic contacts, that is, a patterned low-resistance metal layer region, and then the original SAB mask pattern in the silicon-based high-resistance resistor process is obtained through Boolean operation to obtain a modified SAB mask pattern, so that the modified SAB mask pattern defines a metal thin film resistor mask pattern, and then a metal thin film resistor covering the patterned low-resistance metal layer is formed based on the metal thin film resistor mask pattern, and finally a CT contact hole connected to the patterned low-resistance metal layer is formed. Since the area between the patterned low-resistance metal layers is actually the original SAB mask pattern, and the metal film resistor is formed on the patterned low-resistance metal layer, the design resistance length of the metal film resistor formed finally can be defined by the boundary of the original SAB mask pattern, and the boundary of the original SAB mask pattern is also the resistance length definition method of the silicon-based high-resistance resistor in the silicon-based high-resistance resistor process, so that in the process of migrating the silicon-based high-resistance resistor process to the metal film resistor process port, there is no need to change the mask pattern in the silicon-based high-resistance resistor process, and only by performing the required Boolean operation on the mask pattern in the silicon-based high-resistance resistor process, the consistency of the resistance length definition method between the two ports can be achieved; avoiding changing the layout of the back-end CT process so that the design resistance length of the two ports has a consistent definition, thereby avoiding the complex calculation caused by changing the layout of the back-end CT process and the risk of poor contact between CT and MET1. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0123] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a metal thin film resistor, characterized in that: The preparation method comprises the following steps: Providing a substrate, and sequentially forming a low-resistance metal layer and a first hard mask layer on the substrate; The first hard mask layer is etched and patterned based on the modified HiR mask to obtain a patterned first hard mask layer, and the area where the patterned first hard mask layer is located defines a subsequent CT contact hole formation area; wherein the modified HiR mask pattern is obtained by performing a Boolean operation of the original HiR mask pattern NOT the original SAB mask pattern; Etching the low-resistance metal layer based on the patterned first hard mask layer to form a patterned low-resistance metal layer and removing the patterned first hard mask layer; forming a high-resistance metal layer and a second hard mask layer in sequence on the substrate and the patterned low-resistance metal layer; The second hard mask layer is etched and patterned based on the modified SAB mask to obtain a patterned second hard mask layer, and the area where the patterned second hard mask layer is located defines a subsequent metal thin film resistor formation area; wherein the modified SAB mask pattern is obtained by performing a Boolean operation on the original SAB mask pattern to obtain a metal thin film resistor mask pattern; Etching the high-resistance metal layer based on the patterned second hard mask layer to form the metal thin film resistor; The CT contact hole penetrating the metal film resistor and the patterned second hard mask layer is formed on the patterned low-resistance metal layer.

2. The method for preparing a metal thin film resistor according to claim 1, characterized in that: The substrate is a silicon-based substrate.

3. The method for preparing a metal thin film resistor according to claim 1, characterized in that: A shallow trench isolation structure is formed in the substrate; and the metal film resistor is formed above the shallow trench isolation structure.

4. The method for preparing a metal thin film resistor according to claim 3, characterized in that: A metal gate structure is formed on the shallow trench isolation structure, and the metal gate structure is isolated from the metal film resistor by an insulating layer.

5. The method for preparing a metal thin film resistor according to claim 1, characterized in that: The material of the low-resistance metal layer is titanium nitride material, and the material of the high-resistance metal layer is titanium nitride material.

6. The method for preparing a metal thin film resistor according to claim 5, characterized in that: The thickness of the low-resistance metal layer is more than ten times the thickness of the high-resistance metal layer.

7. The method for preparing a metal thin film resistor according to claim 1, characterized in that: The first hard mask layer is a silicon nitride layer and / or a silicon oxide layer, and the second hard mask layer is a silicon nitride layer and / or a silicon oxide layer.

8. The method for preparing a metal thin film resistor according to claim 1, characterized in that: The method of forming the CT contact hole comprises: forming a dielectric layer with a flat surface on the substrate and the patterned second hard mask layer; Sequentially etching the dielectric layer, the patterned second hard mask layer and the metal film resistor to form a CT hole; The CT hole is filled with a metal conductive material to obtain the CT contact hole.

9. The method for preparing a metal thin film resistor according to claim 1, characterized in that: The method for obtaining the patterned first hard mask layer comprises: forming a first photoresist layer on the first hard mask layer; patterning the first photoresist layer using the modified HiR mask to obtain a patterned first photoresist layer; Etching the first hard mask layer based on the patterned first photoresist layer to obtain the patterned first hard mask layer; removing the patterned first photoresist layer; The method for obtaining the patterned second hard mask layer comprises: forming a second photoresist layer on the second hard mask layer; patterning the second photoresist layer using the modified SAB mask to obtain a patterned second photoresist layer; Etching the second hard mask layer based on the patterned second photoresist layer to obtain the patterned second hard mask layer; The patterned second photoresist layer is removed.

10. A metal film resistor, characterized in that: The metal film resistor is prepared by the method for preparing the metal film resistor as claimed in any one of claims 1 to 9.

Images