Laterally diffused metal oxide semiconductor (LDMOS) transistor and manufacturing method thereof

Abstract

The invention discloses a laterally diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof. A laterally diffused metal oxide semiconductor (LDMOS) transistor includes a first gate. The LDMOS transistor also includes a first source region on a first side of the first gate. The LDMOS transistor also includes a drain region on a second side of the first gate, wherein the second side is opposite the first side. The LDMOS transistor also includes a first spacer surrounding the first gate. The first spacer includes a first portion on a first side of the first gate, wherein a top surface of the first portion is substantially coplanar with a top surface of the first gate. The first spacer further includes a second portion on a second side of the first gate, wherein the second portion includes a first corner structure extending above a top surface of the first gate.

Description

Technical Field

[0001] The present disclosure relates to laterally diffused metal oxide semiconductor (LDMOS) transistors and methods of manufacturing the same. Background Art

[0002] As technology advances in the field of semiconductor integrated circuits (ICs), materials, designs, and manufacturing processes have resulted in ever-shrinking IC device sizes. The reduction in IC device size has in turn increased the portability of systems that include IC devices. Portable systems typically utilize batteries as the basis for powering IC devices. In addition, increased speed performance is designed into IC devices.

[0003] Laterally diffused metal oxide semiconductor (LDMOS) transistors can be used for radio frequency (RF) and microwave applications. In some cases, LDMOS transistors are used in power amplifier circuits. Therefore, in some cases, LDMOS transistors are included in portable IC devices, such as mobile phones. Summary of the invention

[0004] According to a first aspect of the present disclosure, a laterally diffused metal oxide semiconductor (LDMOS) transistor is provided, comprising: a first gate; a first source region located on a first side of the first gate; a drain region located on a second side of the first gate, wherein the second side is opposite to the first side; a first spacer surrounding the first gate, wherein the first spacer comprises: a first portion located on the first side of the first gate, wherein a top surface of the first portion is substantially coplanar with a top surface of the first gate; and a second portion located on the second side of the first gate, wherein the second portion comprises a first corner structure extending above a top surface of the first gate.

[0005] According to a second aspect of the present disclosure, a laterally diffused metal oxide semiconductor (LDMOS) transistor is provided, comprising: a first gate; a second gate; a drain region located between the first gate and the second gate, wherein each of the first gate and the second gate can be used to control the voltage at the drain region; a first spacer surrounding the first gate, wherein the first spacer comprises: a first portion located on a side of the first gate closest to the drain region, wherein the first portion comprises a first corner structure extending above a top surface of the first gate; and a second spacer surrounding the second gate, wherein the second spacer comprises: a second portion located on a side of the second gate closest to the drain region, wherein the second portion comprises a second corner structure extending above a top surface of the second gate.

[0006] According to a third aspect of the present disclosure, a method for manufacturing a laterally diffused metal oxide semiconductor (LDMOS) transistor is provided, the method comprising: forming a gate on a substrate; depositing a spacer material on the gate and the substrate; depositing a photoresist on the spacer material; patterning the photoresist, wherein patterning the photoresist comprises: removing the photoresist from the spacer material located on a first side of the gate, and retaining the photoresist on the spacer material located on a second side of the gate, wherein the second side is opposite to the first side; using the patterned photoresist as a mask to etch the spacer material, wherein etching the spacer material comprises: forming a first portion of the spacer material located on the first side of the gate, the top surface of the first portion being substantially coplanar with the top surface of the gate; and forming an angle structure in a second portion of the spacer material located on the second side of the gate, wherein the angle structure extends above the top surface of the gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0008] Figure 1 is a cross-sectional view of a laterally diffused metal oxide semiconductor (LDMOS) transistor according to some embodiments.

[0009] Figure 2 is a graph of drain voltage (Vd) versus gate-drain capacitance (Cgd) according to some embodiments.

[0010] Figure 3 is a graph of total gate charge (Qg) versus gate voltage (Vg) according to some embodiments.

[0011] Figure 4 is a flow chart of a method of fabricating a LDMOS transistor according to some embodiments.

[0012] Figure 5 is a cross-sectional view of an LDMOS transistor at an intermediate stage of fabrication according to some embodiments.

[0013] Figure 6A-6E are cross-sectional views of an LDMOS transistor at various intermediate stages of fabrication in accordance with some embodiments.

[0014] Figure 7A-7E are cross-sectional views of an LDMOS transistor at various intermediate stages of fabrication in accordance with some embodiments.

[0015] Figure 8A-8E are cross-sectional views of an LDMOS transistor at various intermediate stages of fabrication in accordance with some embodiments.

[0016] Figure 9A-9E are cross-sectional views of an LDMOS transistor at various intermediate stages of fabrication in accordance with some embodiments.

[0017] Figures 10A-10E are cross-sectional views of an LDMOS transistor at various intermediate stages of fabrication in accordance with some embodiments.

[0018] Fig.11 is a schematic diagram of a buck converter including an LDMOS transistor according to some embodiments. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. Other components, values, operations, materials, arrangements, etc. are also considered. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (one or more) elements or (one or more) features as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0021] As the size of integrated circuit (IC) devices decreases, more IC devices are incorporated into portable systems, such as mobile phones, smart watches, and other Internet of Things (IoT) systems. In some cases, portable systems rely on batteries to power IC devices. In order to extend the use of portable devices, IC devices are expected to have lower power consumption. In addition, as the functionality of portable systems increases, customers expect higher performance speeds.

[0022] The present description includes a lateral diffused metal oxide semiconductor (LDMOS) transistor including a horn structure on a drain side spacer. The horn structure extends upward beyond the top surface of the gate surrounded by the spacer. Compared with other LDMOS transistors that do not include a horn structure, the LDMOS transistor including the horn structure allows a silicide layer to be formed across the entire top surface of the gate. By forming a silicide layer across the entire top surface of the gate, the resistance between the gate and the contact structure is reduced compared to other methods. Compared to other methods, the reduced resistance helps to reduce the power consumption of the LDMOS transistor including the horn structure. For example, the LDMOS transistor includes a resistor protection oxide (RPO) that overlaps the gate structure partially. The gate being partially overlapped by the RPO reduces the portion of the gate that can be covered by the silicide layer.

[0023] The gate being overlapped by the RPO also reduces the ability to reduce the gate size because the RPO compresses the smaller gate, increasing the risk of device failure. In some cases, maintaining a larger gate size to support the RPO results in a higher gate-drain capacitance (Cgd) or total gate charge (Qg). The total gate charge Qg is the amount of charge injected into the gate to switch the transistor between a non-conductive (OFF) state and a conductive (ON) state. The gate-drain capacitance Cgd affects the delay between applying a voltage to the gate to change the ON / OFF state of the transistor and the change in current at the drain of the transistor. Reducing the total gate charge Qg helps save battery power in portable systems. Minimizing the gate-drain capacitance Cgd increases the speed at which the transistor can fully switch between the ON / OFF state.

[0024] In some cases, adding RPO to the LDMOS transistor will also reduce the size of the silicide layer above the drain. Similar to the reduced silicide layer above the gate, the reduced silicide layer above the drain increases the resistance between the drain and the contact electrically connected to the drain. The increased resistance between the contact and at least one of the gate or drain of the LDMOS transistor also increases the heat generation of the LDMOS transistor. Therefore, the heat dissipation problem of the LDMOS transistor including RPO is also exacerbated compared to the LDMOS transistor including the corner structure described herein.

[0025] Figure 1 1 is a cross-sectional view of an LDMOS transistor 100 according to some embodiments. The LDMOS transistor 100 includes a plurality of gates 150a and 150b. The LDMOS transistor 100 includes a shared drain 170 located between the gates 150a and 150b. Although the following description of the LDMOS transistor 100 details a multi-gate structure, a person of ordinary skill in the art will understand that the description is also applicable to an LDMOS transistor having a single gate structure.

[0026] LDMOS transistor 100 includes substrate 110. Deep well 120 is in substrate 110. A plurality of first doped regions 130a and 130b are located above deep well 120 and extend to the top surface of substrate 110. Second doped regions 135 are located between first doped regions 130a and 130b. Second doped regions 135 also extend to the top surface of substrate 110.

[0027] The first source region 140a is in the upper portion of the first doped region 130a. The second source region 140b is in the upper portion of the first doped region 130b. Each of the first source region 140a and the second source region 140b is a split source region. For the clarity of the drawings, different parts of the split source region are only labeled in the first source region 140a. The first source region 140a includes a first region 142a and a second region 144a. The second region 144a is located between the first region 142a and the adjacent gate 150a. The first source silicide layer 145a is located above the first source region 140a. The second source silicide layer 145b is located above the second source region 140b.

[0028] The first gate 150a is adjacent to the first source region 140a. The first gate 150a is located above the interface of the first doped region 130a and the second doped region 135. The first gate silicide layer 155a is located above the first gate 150a. The first spacer surrounds the first gate 150a. The first spacer includes a first spacer portion 160a adjacent to the first source 140a. The top surface of the first spacer portion 160a is substantially coplanar with the top surface of the first gate 150a. The first spacer also includes a second spacer portion 165a located between the first gate 150a and the drain 170. The second spacer portion 165a includes a bottom region 167a extending from the top surface of the substrate 110 and being substantially coplanar with the top surface of the first gate 150a. The portion of the bottom region 167a farthest from the first gate 150a has a substantially flat top surface. The portion of the bottom region 167a closest to the first gate 150a has a curved top surface. The second spacer portion 165a also includes a top region 169a, also referred to as a corner structure. The top region 169a extends above the top surface of the first gate 150a. The top region 169a extends to a point above the first gate 150a.

[0029] The drain region 170 is located in the second doping region 135 between the first gate 150 a and the second gate 150 b. The drain silicide layer 175 is located on the drain region 170 .

[0030] The second gate 150b is similar to the first gate 150a. In some embodiments, the dimensions Lg1, Lg2, and Ld marked on the second gate 150b are also applicable to the first gate 150a. The second silicide layer 155b is similar to the first silicide layer 155a. The second spacer surrounds the second gate 150b. The second spacer includes a third spacer portion 160b similar to the first spacer portion 160a. The second spacer also includes a fourth spacer portion 165b similar to the second spacer portion 165a. In some embodiments, the dimensions L1 and L2 marked on the second spacer portion 165a are also applicable to the fourth spacer portion 165b.

[0031] The substrate 110 includes a semiconductor material. In some embodiments, the substrate 110 is lightly doped or intrinsically doped. In some embodiments, the substrate 110 is undoped. In some embodiments, the substrate 110 includes silicon. In some embodiments, the substrate 110 includes a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate 110 has a top surface that is in direct contact with the first gate 150a and the second gate 150b. In some embodiments, the substrate 110 includes a top surface that is in direct contact with the deep well 120, and the deep well 120 and other components are grown on the substrate 110, for example, using an epitaxial process.

[0032] The deep well 120 includes a first dopant type. The deep well 120 provides electrical isolation for the substrate 110. In some embodiments, the first dopant type is a p-type, for example, boron (B) or boron difluoride (BF 2 ). In some embodiments, the first dopant type is n-type, for example, phosphorus (P) or arsenic (Ar). In some embodiments, the deep well 120 is formed by implanting a dopant having the first dopant type into the substrate 110. In some embodiments, an annealing process is performed after the implantation process to more uniformly distribute the dopant within the deep well 120. In some embodiments, the deep well 120 is formed by growing a doped epitaxial layer on top of the substrate. In some embodiments, the epitaxial layer is grown after the epitaxial growth and then doped. In some embodiments, the epitaxial layer is doped in situ while the epitaxial growth occurs. In some embodiments, the dopant concentration of the deep well 120 is about 10 15 Dopant / cm 3 Up to 10 17 Dopant / cm 3If the dopant concentration is too high, then in some cases, the risk of current leakage increases. If the dopant concentration is too low, then in some cases, the risk of failing to electrically isolate the substrate 110 increases. In some embodiments, the thickness of the deep well 120 is in a range from about 2 micrometers (μm) to about 3 μm. If the thickness of the deep well 120 is too low, then in some cases, the risk of failing to adequately isolate the substrate 110 increases. If the thickness of the deep well 120 is too high, then in some cases, the size of the LDMOS transistor 100 increases without significantly improving performance.

[0033] The deep well 120 extends continuously under both the first gate 150a and the second gate 150b. In some embodiments, the deep well 120 is discontinuous at a position below the second doped region 135 that is offset relative to both the first gate 150a and the second gate 150b in a plan view.

[0034] The first doped regions 130a and 130b are above the deep well 120. Each of the first doped regions 130a and 130b has a first dopant type. In some embodiments, the first doped regions 130a and 130b are formed by implanting dopants having the first dopant type into the substrate 110. In some embodiments, an annealing process is performed after the implantation process to more uniformly distribute the dopant within the first doped regions 130a and 130b. In some embodiments, the first doped regions 130a and 130b are formed by growing a doped epitaxial layer above the substrate 110 or the deep well 120. In some embodiments, the epitaxial layer is grown after epitaxial growth and then doped. In some embodiments, the epitaxial layer is doped in situ while the epitaxial growth occurs. In some embodiments, the dopant concentration of the first doped regions 130a and 130b is about 10 17 Dopant / cm 3 Up to 10 18 Dopant / cm 3 If the dopant concentration is too large, then in some cases, the risk of current leakage increases. If the dopant concentration is too small, then in some cases, the risk of failing to adequately suppress parasitic bipolar junction transistor (BJT) interactions increases. In some embodiments, the thickness of the first doped regions 130a and 130b is in the range of about 1 μm to about 2 μm. If the thickness of the first doped regions 130a and 130b is too small, then in some cases, the risk of failing to adequately suppress parasitic BJT interactions increases. If the thickness of the first doped regions 130a and 130b is too large, then in some cases, the size of the LDMOS transistor 100 increases without significantly improving performance.

[0035] In some embodiments, the first doped region 130a is identical to the first doped region 130b. In some embodiments, the first doped region 130a is different from the first doped region 130b in at least one of dopant concentration, thickness, dopant type, or other suitable parameters.

[0036] The second doped region 135 is above the deep well 120. The second doped region 135 has a second dopant type opposite to the first dopant type. In some embodiments, the second doped region 135 is formed by implanting dopants having the second dopant type into the substrate 110. In some embodiments, an annealing process is performed after the implantation process to more uniformly distribute the dopant within the second doped region 135. In some embodiments, the second doped region 135 is formed by growing a doped epitaxial layer above the substrate 110 or the deep well 120. In some embodiments, the epitaxial layer is grown after epitaxial growth and then doped. In some embodiments, the epitaxial layer is doped in situ while the epitaxial growth occurs. In some embodiments, the dopant concentration of the second doped region 135 is about 10 17 Dopant / cm 3 Up to 10 18 Dopant / cm 3 If the dopant concentration is too large, then in some cases, the risk of current leakage increases. If the dopant concentration is too small, then in some cases, the risk of failing to adequately suppress parasitic BJT interactions increases. In some embodiments, the thickness of the second doped region 135 is in the range of about 1 μm to about 2 μm. If the thickness of the second doped region 135 is too small, then in some cases, the risk of failing to adequately suppress parasitic BJT interactions increases. If the thickness of the second doped region 135 is too large, then in some cases, the size of the LDMOS transistor 100 increases without significant performance improvement.

[0037] In some embodiments, the thickness of the second doping region 135 is equal to the thickness of the first doping regions 130a and 130b. In some embodiments, the thickness of the second doping region 135 is different from the thickness of at least one of the first doping region 130a or the first doping region 130b.

[0038] The source regions 140a and 140b are in the corresponding first doped regions 130a and 130b. Each of the source regions 140a and 140b is a split source region. In some embodiments, at least one of the source regions 140a and 140b is not a split source region. The source region 140a includes a first dopant type region 142a and a second dopant type region 144a. The first dopant type region 142a has a first dopant type; and the second dopant type region 144a has a second dopant type. In some embodiments, the thickness of the source regions 140a and 140b is in the range of about 0.2 μm to about 0.3 μm. If the thickness of the source regions 140a and 140b is too large, in some cases, the risk of current leakage increases. If the thickness of the source regions 140a and 140b is too small, in some cases, the resistance of the source regions 140a and 140b increases beyond the design specifications. In some embodiments, the source regions 140a and 140b are formed by ion implantation. In some embodiments, an annealing process is performed after the ion implantation. In some embodiments, the dopant concentration of the source regions 140a and 140b is about 10 20 Dopant / cm 3 Up to 10 21 Dopant / cm 3 If the dopant concentration is too large, the risk of current leakage increases in some cases. If the dopant concentration is too small, the resistance of the source regions 140a and 140b increases beyond the design specification in some cases.

[0039] Silicide layers 145a and 145b are above the corresponding source regions 140a and 140b. Silicide layers 145a and 145b help reduce the resistance between the corresponding source regions 140a and 140b and the contact structure in the IC device including the LDMOS transistor 100. Silicide layers 145a and 145b include silicon and at least one metal. In some embodiments, at least one metal includes titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals). In some embodiments, silicide layers 145a and 145b also include germanium. In some embodiments, silicide layers 145a and 145b are self-aligned silicide (salicide) layers. In some embodiments, silicide layers 145a and 145b are formed by depositing a layer including at least one of the above-mentioned metals and then performing an annealing process. In some embodiments, the layer including at least one metal is deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, or other suitable deposition methods.

[0040] The gates 150a and 150b are located above the top surfaces of the first doped regions 130a and 130b and above the top surface of the second doped region 135. In some embodiments, the gates 150a and 150b include an electrode layer and a gate dielectric layer located between the electrode layer and the substrate 110. In some embodiments, the gates 150a and 150b further include at least one of a work function layer, an interface layer, a diffusion barrier layer, or other suitable layers. In some embodiments, the gate dielectric layer is located between the sidewalls of the electrode layer and the corresponding spacers surrounding the gates 150a or 150b. In some embodiments, the sidewalls of the electrode layer are in direct contact with the corresponding spacers surrounding the gates 150a or 150b.

[0041] In some embodiments, the electrode layer includes titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination thereof. For example, the metal fill layer may include aluminum, tungsten, cobalt, copper, and / or other suitable materials. In some embodiments, the electrode layer is formed by CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, the gate dielectric layer includes a high-k dielectric material, such as HfO 2 、HfSiO、HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x 、ZrO、ZrO 2 、ZrSiO 2 、AlO、AlSiO、Al 2 O 3 、TiO、TiO 2 、LaO、LaSiO、Ta 2 O 3 、 2 O 5 , Y 2 O 3 、SrTiO 3 、BaZrO、BaTiO 3 (BTO), (Ba,Sr)TiO 3 (BST), Si 3 N 4 、HfO2-alumina (HfO 2 —Al 2 O 3) alloy, other suitable high-k dielectric material, or a combination thereof. High-k dielectric material generally refers to a dielectric material with a high dielectric constant, for example, a dielectric constant greater than that of silicon oxide (k≈3.9). In some embodiments, the gate dielectric layer is formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. In some embodiments, at least one of gates 150a or 150b is a dummy gate (non-operating).

[0042] The gates 150a and 150b overlap the interface between the second doped region 135 and the corresponding one of the first doped regions 130a or 130b. In some embodiments, the length Lg1 of the gate 150b overlapping the first doped region 130b is in the range of about 0.1 μm to about 0.5 μm. If the length Lg1 is too large, in some cases, the overall size of the LDMOS transistor 100 increases without significant performance improvement. If the length Lg1 is too small, in some cases, the risk of a short circuit between the source 140b and the drain 170 increases. In some embodiments, the length Lg2 of the gate 150b overlapping the second doped region 135 is in the range of about 0.1 μm to about 0.5 μm. If the length Lg2 is too large, in some cases, the overall size of the LDMOS transistor 100 increases without significant performance improvement. If the length Lg2 is too small, in some cases, the risk of a short circuit between the source 140b and the drain 170 increases. In some embodiments, the gate 150b is completely above one of the first doped region 130b or the second doped region 135. As described above, the lengths Lg1 and Lg2 described with respect to the gate 150b are applicable to the gate 150a. In some embodiments, the lengths Lg1 and Lg2 of the gate 150a have the same size as the lengths Lg1 and Lg2 of the gate 150b. In some embodiments, at least one length Lg1 or Lg2 of the gate 150a has a different size than the length Lg1 or Lg2 of the gate 150b.

[0043] The first spacer portion 160a is located between the gate 150a and the source 140a. The first spacer portion 160a provides electrical isolation for the gate 150a. In some embodiments, the first spacer portion 160a includes a single dielectric material. In some embodiments, the first spacer portion 160a includes a plurality of dielectric layers. For example, in some embodiments, the first spacer portion 160a includes silicon oxide, silicon nitride, silicon oxide (ONO) structure. The topmost surface of the first spacer portion 160a is substantially coplanar with the top surface of the gate 150a. In some embodiments, the first spacer portion 160a is formed by depositing one or more layers of dielectric material and then defining the shape of the first spacer portion 160a by an etching process. In some embodiments, the one or more layers of dielectric material are deposited using CVD, oxidation or other suitable deposition processes. In some embodiments, the etching process includes an anisotropic etching process. In some embodiments, the etching process includes a wet etching process or a dry etching process.

[0044] The second spacer portion 165a is located between the gate 150a and the drain 170. The second spacer portion 165a provides electrical isolation for the gate 150a. In some embodiments, the second spacer portion 165a includes a single dielectric material. In some embodiments, the second spacer portion 165a includes a plurality of dielectric layers. For example, in some embodiments, the second spacer portion 165a includes silicon oxide, silicon nitride, silicon oxide (ONO) structure. The topmost surface of the second spacer portion 165a extends above the top surface of the gate 150a. In some embodiments, the second spacer portion 165a is formed by depositing one or more layers of dielectric material and then defining the shape of the second spacer portion 165a by an etching process. In some embodiments, the one or more layers of dielectric material are deposited using CVD, oxidation or other suitable deposition processes. In some embodiments, the etching process includes an anisotropic etching process. In some embodiments, the etching process includes a wet etching process or a dry etching process.

[0045] The second spacer portion 165a includes a bottom region 167a and a top region 169a. The topmost surface of the bottom region 167a is substantially coplanar with the top surface of the gate 150a. In some embodiments, the portion of the bottom region 167a farthest from the gate 150a has a substantially planar top surface. In some embodiments, the portion of the bottom region 167a closest to the gate 150 has a curved top surface. In some embodiments, the thickness L2 of the bottom region 167a from the surface of the first doped region 130a or the second doped region 135 (also the thickness of the gate 150b) is in the range of about 0.1 μm to about 0.3 μm. If the thickness L2 is too large, then in some cases, the size of the LDMOS transistor 100 is increased without significantly improving the performance. If the thickness L2 is too small, then in some cases, the distance between the channel under the gate 150a and the silicide layer 155a is reduced and the risk of short circuit increases.

[0046] The top region 169a extends beyond the top surface of the gate 150a. In some embodiments, the top region 169a has a tapered profile. In some embodiments, the tapered profile includes a uniform tapered profile. In some embodiments, the tapered profile includes a curved tapered profile. In some embodiments, the top region 169a tapers to a point at a position farthest from the substrate 110. The material of the top region 169a is the same material as at least a portion of the bottom region 167a. In some embodiments where the bottom region 167a includes multiple layers of dielectric material, the top region 169a includes only the material of the topmost layer of the bottom region 167a. In some embodiments where the bottom region 167a includes multiple layers of dielectric material, the top region 169a includes the material of the topmost layer of the bottom region 167a and the material of at least one lower layer. In some embodiments, the thickness L1 of the top region 169a above the top surface of the gate 150a is in the range of greater than zero (0) to about two-thirds (2 / 3) L2. If the thickness L1 is too large, in some cases, the size of the LDMOS transistor 100 increases without significant performance improvement.

[0047] The top region 169a provides increased electrical isolation between the gate 150a and other structures within the LDMOS transistor 100 while avoiding the inclusion of a separate insulating material outside the second spacer portion 165a. Avoiding the inclusion of a separate insulating material outside the second spacer portion 165a helps reduce manufacturing costs and improve the efficiency of manufacturing the LDMOS transistor 100 compared to other methods. In addition, compared to other methods that do not include the top region 169a, such as methods that include RPO, the LDMOS transistor 100 is able to extend the silicide layer 155a across the entire top surface of the gate 150a to reduce the resistance at the gate 150a. The weight reduction of the structure, such as RPO, also allows for a greater reduction in the size of the gate 150a to facilitate reducing the size of the LDMOS transistor 100. In addition, compared to other methods, the ability to reduce the size of the gate 150a due to the presence of the top region 169a helps improve the performance of the LDMOS transistor 100. For example, compared to other methods that do not include the top region 169a, the Cgd and Qg of the LDMOS transistor 100 are reduced.

[0048] Figure 1 is a cross-sectional view of the LDMOS transistor 100. One of ordinary skill in the art will appreciate that in some embodiments, the first spacer portion 160a and the second spacer portion 165a are portions of a continuous first spacer surrounding the gate 150a. For example, in some embodiments, in a plan view, the second spacer portion 165a extends along the entire length of the gate 150a between the gate 150a and the drain 170; and the first spacer portion 160a extends around the remainder of the gate 150a. In some embodiments, the second spacer portion 165a extends around approximately half of the gate 150a in a plan view, i.e., the half closest to the drain 170, and the first spacer portion 160a extends around the other half of the gate 150a, i.e., the half closest to the source 140a.

[0049] The above description of the first spacer portion 160a is applicable to the third spacer portion 160b adjacent to the gate 150b. In some embodiments, the first spacer portion 160a has the same size, shape and material as the third spacer portion 160b. In some embodiments, the first spacer portion 160a is different from the third spacer portion 160b in at least one of material, size or shape.

[0050] The above description of the second spacer portion 165a is applicable to the fourth spacer portion 165b adjacent to the gate 150b. In some embodiments, the second spacer portion 165a has the same size, shape and material as the fourth spacer portion 165b. In some embodiments, the second spacer portion 165a is different from the fourth spacer portion 165b in at least one of material, size or shape.

[0051] The drain region 170 is located in the second doped region 135. The drain region 170 includes a second dopant type. In some embodiments, the thickness of the drain region 170 is in a range of about 0.2 μm to about 0.3 μm. If the thickness of the drain region 170 is too large, then in some cases, the risk of current leakage increases. If the thickness of the drain region 170 is too small, then in some cases, the resistance of the drain region 170 increases beyond the design specification. In some embodiments, the drain region 170 is formed by ion implantation. In some embodiments, an annealing process is performed after the ion implantation. In some embodiments, the dopant concentration of the drain region 170 is in a range of about 10 20 Dopant / cm 3 Up to 10 21 Dopant / cm 3 If the dopant concentration is too large, the risk of current leakage increases in some cases. If the dopant concentration is too small, the resistance of the drain region 170 increases beyond the design specification in some cases.

[0052] In some embodiments, the distance Ld between the drain region 170 and the gate 150b is in a range of about 0.2 μm to about 6 μm. If the distance Ld is too small, then in some cases, the risk of a short circuit between the gate 150b and the drain 170 increases. If the distance Ld is too large, then in some cases, the operating speed of the LDMOS transistor 100 decreases. The size of the distance Ld is determined in part based on the designed operating voltage of the LDMOS transistor 100. In some embodiments, the designed operating voltage of the LDMOS transistor 100 is in a range of about 6 volts (V) to about 60V. If the operating voltage of the LDMOS transistor 100 is too large, then in some embodiments, the risk of damage to the LDMOS transistor 100 and other components in the IC device increases. If the operating voltage of the LDMOS transistor 100 is too small, then in some cases, the risk of insufficient power of components in the IC device increases. In some embodiments, the breakdown electric field at the distance Ld is about 0.9×10 5 V / cm to about 1.1×10 5V / cm, where V is the operating voltage of the LDMOS transistor 100. If the breakdown electric field of the LDMOS transistor 100 is designed to be too large, in some embodiments, the speed of the LDMOS transistor 100 decreases. If the breakdown electric field of the LDMOS transistor 100 is designed to be too small, in some cases, the risk of a short circuit between the drain 170 and the gate 150b increases.

[0053] The above description of the distance between the drain 170 and the gate 150b is applicable to the distance between the drain 170 and the gate 150a. In some embodiments, the distance between the drain 170 and the gate 150b is equal to the distance between the drain 170 and the gate 150a. In some embodiments, the distance between the drain 170 and the gate 150b is different from the distance between the drain 170 and the gate 150a.

[0054] The silicide layer 175 is above the drain region 170. The silicide layer 175 helps reduce the resistance between the drain region 170 and the contact structure in the IC device including the LDMOS transistor 100. The silicide layer 175 includes silicon and at least one metal. In some embodiments, the at least one metal includes titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals). In some embodiments, the silicide layer 175 also includes germanium. In some embodiments, the silicide layer 175 is a self-aligned silicide (salicide) layer. In some embodiments, the silicide layer 175 is formed by depositing a layer including at least one of the above metals and then performing an annealing process. In some embodiments, the layer including at least one metal is deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, or other suitable deposition methods.

[0055] Figure 2 2 is a graph 200 of drain voltage (Vd) versus gate-drain capacitance (Cgd) according to some embodiments. Graph 200 is based on an LDMOS transistor designed to have an operating voltage of 6V. Graph 200 includes a first curve 210 indicating the performance of an LDMOS transistor without a corner, for example, an LDMOS transistor including an RPO layer that overlaps a gate portion. Graph 200 also includes a second curve 220 indicating the performance of an LDMOS transistor with a corner, for example, LDMOS transistor 100 ( Figure 1). The graph 200 indicates that the Cgd of the second curve 220 is significantly less than the Cgd of the first curve 210. When the drain voltage Vd increases to the 6V operating voltage, the curve 220 indicates that the Cgd is about 10% to about 40% less than the curve 210. The reduction in Cgd of the curve 220 indicates that the LDMOS transistor including the corner will have less delay when switching between the ON / OFF states.

[0056] Figure 3 3 is a graph 300 of total gate charge (Qg) versus gate voltage (Vg) according to some embodiments. Graph 300 is based on an LDMOS transistor designed to have an operating voltage of 6V. Graph 300 includes a first curve 310 indicating the performance of an LDMOS transistor without a corner, for example, an LDMOS transistor including an RPO layer that overlaps a gate portion. Graph 300 also includes a second curve 320 indicating the performance of an LDMOS transistor with a corner, for example, LDMOS transistor 100 ( Figure 1 ). The graph 300 indicates that the Qg of the second curve 320 is significantly less than the Qg of the first curve 310. As the gate voltage Vg increases toward the 6V operating voltage, the curve 320 indicates that the Qg is about 20% to about 30% less than the curve 310. This reduction in the Qg of the curve 320 indicates that the LDMOS transistor including the corner will have less delay when switching between the ON / OFF states.

[0057] Figure 4 4 is a flow chart of a method 400 for making an LDMOS transistor according to some embodiments. In some embodiments, the method 400 may be used to make the LDMOS transistor 100 ( Figure 1 In some embodiments, the method 400 may be used to manufacture a semiconductor device other than the LDMOS transistor 100 ( Figure 1 ) other than the LDMOS transistor. For clarity, initially Figure 5 and Figure 6A-6E The cross-sectional view of the method 400 is discussed. In focusing on the Figure 6A-6E After an initial description of some embodiments, Figures 7A-10E Some other LDMOS transistors that may be fabricated by method 400 are discussed.

[0058] Method 400 includes operation 405, wherein a well is implanted into a substrate. In some embodiments, a plurality of wells of different depths, dopant concentrations, or dopant types are implanted into the substrate. In some embodiments, the implantation process includes ion implantation of a dopant substance. The power of the implantation process is determined based on the designed depth of the well in the substrate. The dopant concentration is determined based on the designed performance of the corresponding well. The dopant type is determined based on the design of the LDMOS transistor. In some embodiments, operation 405 is replaced by an operation including epitaxial growth of one or more layers on the substrate. The one or more epitaxial layers are doped in situ or doped after the epitaxial process to define the well.

[0059] In operation 410, a gate is formed over a substrate. In some embodiments, the gate comprises a dummy gate. In some embodiments, the dummy gate undergoes a subsequent replacement gate process. In some embodiments, the gate is an active gate. In some embodiments where the gate is a dummy gate, forming the gate comprises depositing a polysilicon layer and patterning the polysilicon layer to define the gate. In some embodiments where the gate is an active gate, forming the gate comprises depositing a gate dielectric layer over the substrate and depositing an electrode layer over the gate dielectric layer. The electrode layer and the gate dielectric layer are then patterned to define the gate. In some embodiments, patterning comprises a combination of photolithography and etching processes.

[0060] In some embodiments, depositing the gate dielectric layer comprises CVD, oxidation, or other suitable processes. In some embodiments, depositing the electrode layer comprises CVD, PVD, electroplating, ALD, or other suitable processes. In some embodiments, the gate dielectric layer comprises silicon oxide. In some embodiments, the gate dielectric layer comprises a high-k dielectric material. In some embodiments, the electrode layer comprises a metal-containing layer. In some embodiments, forming the gate comprises forming additional layers, for example, at least one work function layer, an interface layer, a diffusion barrier layer, or other suitable layers.

[0061] Figure 5 4 is a cross-sectional view of an LDMOS transistor 500 at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 500 corresponds to operation 410 ( Figure 4 ) and then formed into an LDMOS transistor 100 ( Figure 1 ). LDMOS transistor 500 includes substrate 110; deep well 120; first doped regions 130a and 130b; second doped region 135; and gates 150a and 150b. In some embodiments, deep well 120; first doped regions 130a and 130b; and second doped region 135 utilize operation 405 ( Figure 4 ) is formed. In some embodiments, gates 150a and 150b are formed using operation 410 ( Figure 4 )form.

[0062] Returning to method 400, in operation 415, a spacer material is deposited over the gate and the substrate. The spacer material includes at least one dielectric material. In some embodiments, the spacer material is blanket deposited over the substrate. In some embodiments, the spacer material is deposited over less than the entire substrate. In some embodiments, depositing the spacer material includes performing CVD, oxidation, or other suitable processes.

[0063] In some embodiments, depositing the spacer material comprises depositing a single layer of dielectric material. In some embodiments, depositing the spacer material comprises depositing multiple layers of a single dielectric material. In some embodiments, depositing the spacer material comprises depositing multiple layers of different dielectric materials. For example, in some embodiments, depositing the spacer material comprises depositing silicon oxide or silicon nitride. In some embodiments, depositing the spacer material comprises depositing a combination of silicon oxide and silicon nitride, for example, an ONO structure.

[0064] Fig. 6A 4 is a cross-sectional view of an LDMOS transistor 600A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 600A corresponds to operation 415 ( Figure 4 ) structure. Figure 5 ), the LDMOS transistor 600A includes a spacer material 610 located on the substrate 110 and the gates 150a and 150b. The spacer material 610 includes a monolayer of silicon oxide. In some embodiments, the thickness of the spacer material 610 is in the range of about 1000 angstroms (Å) to about 2000Å. If the thickness of the spacer material 610 is too large, then in some cases, the size of the LDMOS transistor 600A increases without significantly improving the performance. If the thickness of the spacer material 610 is too small, then in some cases, the spacer material 610 will not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the spacer material 610 is deposited using CVD, oxidation or other suitable processes. In some embodiments, the spacer material 610 is a conformal layer. In some embodiments, the spacer material 610 is a non-conformal layer.

[0065] Back to Figure 4, in operation 420, a photoresist is formed on the spacer material. In some embodiments, the photoresist is formed by spin coating or other suitable processes. In some embodiments, a baking process is performed after the photoresist is formed on the spacer material. In some embodiments, the photoresist includes a positive photoresist. In some embodiments, the photoresist includes a negative photoresist. In some embodiments, the photoresist includes a resin, a polymer or other suitable material. The maximum thickness of the photoresist is sufficient to cover the top surface of the spacer material. If the maximum thickness of the photoresist is too small, in some cases, the photoresist remaining after patterning is not enough to form a corner structure in the spacer material. In some embodiments, the maximum thickness of the photoresist is less than about 1.5 times the thickness of the gate formed in operation 410. If the maximum thickness of the photoresist is too large, in some cases, the photoresist material is wasted without significant performance improvement.

[0066] Figure 6B 4 is a cross-sectional view of an LDMOS transistor 600B at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 600B corresponds to operation 420 ( Figure 4 ) structure. Fig. 6A ), the LDMOS transistor 600B includes a photoresist 620 located above the spacer material 610. In some embodiments, the photoresist 620 includes a resin, a polymer, or other suitable material. The photoresist 620 extends above the topmost surface of the spacer material 610. In some embodiments, the thickness t1 of the photoresist 620 is less than 1.5 times the thickness t2 of the gate 150b (or the gate 150a). If the thickness of the photoresist 620 is too large, in some cases, the photoresist is wasted without significantly improving the performance. In some embodiments, the thickness t1 of the photoresist 620 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 620 is deposited using spin coating or other suitable processes.

[0067] Back to Figure 4, in operation 425, patterning the photoresist. The photoresist is patterned using a combination of photolithography and etching. In some embodiments, the etching is a wet etch. In some embodiments, the etching is a dry etch. The photoresist is patterned to remove portions of the photoresist except for portions of the photoresist along the sidewalls of the spacer material closest to the drain region of the LDMOS. In some embodiments, after patterning of the photoresist, the top surface of the remaining photoresist is substantially coplanar with the topmost surface of the spacer material. In some embodiments in which the LDMOS transistor includes multiple gates, the remaining photoresist defines a discontinuous structure in which there is no photoresist in the area of ​​the spacer material above the drain region.

[0068] Figure 6C 4 is a cross-sectional view of an LDMOS transistor 600C at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 600C corresponds to operation 425 ( Figure 4 ) structure. With LDMOS transistor 600B ( Figure 6B ), the LDMOS transistor 600C includes the remaining photoresists 620a and 620b, which are located closest to the spacer material 610 to form a drain region (e.g., drain region 170) in the second doped region 135 ( Figure 1 ) is located on the sidewall. Figure 6B ) is removed using a combination of photolithography and etching. The remaining photoresists 620a and 620b define a discontinuous structure with an opening between the remaining photoresists 620a and the remaining photoresists 620b, wherein the underlying spacer material 610 is exposed. In some embodiments, the top surfaces of the remaining photoresists 620a and 620b are substantially coplanar with the topmost surface of the spacer material 610.

[0069] Back to Figure 4In operation 430, the spacer material is etched using the patterned photoresist as a mask. The etchant used to etch the spacer material is based on the material of the spacer material. In some embodiments, etching includes wet etching. In some embodiments, etching includes dry etching. In some embodiments, the etchant includes at least one of hydrofluoric acid (HF), sulfur peroxide mixture (SPM), ammonium peroxide mixture (APM), or other suitable etchants. Since the patterned photoresist protects the sidewalls of the spacer material closest to the drain region of the LDMOS, the etching process removes less spacer material close to the drain region. Therefore, on the side of the gate closest to the drain region, an angle structure is formed by the spacer material. In some embodiments, the thickness of the angle structure is in the range of greater than zero to about two-thirds (2 / 3) of the thickness of the gate structure. If the thickness of the angle structure is too large, then in some cases, the angle structure interferes with the formation of the contact structure and has a negative impact on the performance of the LDMOS transistor.

[0070] Fig.6D 4 is a cross-sectional view of an LDMOS transistor 600D at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 600D corresponds to operation 430 ( Figure 4 ) structure. Figure 6C ), the LDMOS transistor 600D includes an angle structure that is closest to a drain region (eg, drain region 170) to be formed in the second doped region 135 ( Figure 1 ) in the spacer material 610. The etching process removes the spacer material 610 ( Figure 6C ) to define a first spacer portion 635a, a second spacer portion 630a, a third spacer portion 635b, and a fourth spacer portion 630b. The second spacer portion 630a and the fourth spacer portion 630b include an angle structure. The first spacer portion 635a and the third spacer portion 635b do not have an angle structure. The thickness L2 of the gate 150b is in the range of about 0.1 μm to about 0.3 μm. If the thickness L2 is too large, in some cases, the size of the LDMOS transistor 600D increases without significantly improving the performance. If the thickness L2 is too small, in some cases, the silicide layer (e.g., the silicide layer 155a) ( Figure 1 ) and the channel under the gate 150b is reduced and the risk of short circuit increases. In some embodiments, the thickness of the corner structure is in the range of greater than zero to about two-thirds (2 / 3) of the thickness of the gate structure. If the thickness of the corner structure is too large, then in some cases, the corner structure interferes with the formation of the contact structure and has a negative impact on the performance of the LDMOS transistor.

[0071] Back to Figure 4, in operation 435, a source / drain (S / D) region is formed. In some embodiments, the S / D region is formed by ion implantation. In some embodiments, the S / D region is formed as follows: a portion of the underlying substrate is removed to define a recess; and the S / D region is grown in the recess. In some embodiments, the S / D region is grown in the recess using epitaxy. In some embodiments, the S / D region is doped after growing the S / D region. In some embodiments, the S / D region is doped in situ during the growth of the S / D region. In some embodiments, an annealing process is performed after doping or implantation of ions.

[0072] In operation 440, a silicide structure is formed on the S / D region and on the gate. The silicide structure is formed as follows: a metal-containing film is deposited on the S / D region and the gate, and then the LDMOS transistor is annealed to cause a reaction to form a silicide. In some embodiments in which the electrode layer of the gate includes a metal, a silicon layer is deposited on the gate to provide silicon to react with the metal-containing film to form a silicide. The silicide structure formed by operation 440 on the gate extends over the entire length of the gate. This helps to reduce the resistance between the gate and the contact structure to improve device performance and reduce power consumption. In some embodiments, the metal-containing film includes at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals). In some embodiments, the silicide structure also includes germanium. In some embodiments, the silicide structure is a self-aligned silicide (salicide) layer. In some embodiments, the metal-containing film is deposited using CVD, PVD, ALD, electroplating, or another suitable deposition method.

[0073] In operation 445, an interlayer dielectric (ILD) is deposited on the substrate. The ILD covers the gate and includes a spacer material of the corner structure. In some embodiments, the top surface of the ILD is higher than the top surface of the corner structure. In some embodiments, the top surface of the ILD is substantially coplanar with the top surface of the corner structure. In some embodiments, the ILD includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials. In some embodiments, the ILD is deposited using CVD, ALD or other suitable deposition processes. In some embodiments, a chemical mechanical polishing (CMP) process is performed after the ILD is deposited.

[0074] In operation 450, a contact structure is formed to be electrically connected to the S / D region. The contact structure includes a conductive element extending through the ILD. The contact structure falls on the silicide layer of the corresponding S / D region to provide electrical connection with the corresponding S / D region. The contact structure is formed by etching the ILD to define an opening in the ILD and then depositing a conductive material in the opening. In some embodiments, the etching of the ILD includes a combination of photolithography and etching processes. In some embodiments, the etching is a wet etching. In some embodiments, the etching is a dry etching. In some embodiments, the conductive material is deposited in the opening using CVD, PVD, ALD, electroplating or other suitable deposition processes. In some embodiments, an additional layer, for example, a barrier layer, is deposited between the conductive material and the ILD in the opening. In some embodiments, a CMP process is performed after the formation of the contact structure.

[0075] Fig. 6E 4 is a cross-sectional view of an LDMOS transistor 600E at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 600E corresponds to operation 450 ( Figure 4 ) structure. Fig.6D ) Compared with LDMOS transistor 600E, LDMOS transistor 600E includes S / D regions, silicide layers, ILD and contact structures. For the clarity of the drawings, Fig. 6E The split region of the source regions 140a and 140b is not marked.

[0076] Source region 140a is in first doped region 130a. Silicide layer 145a is above source region 140a. Source region 140b is in first doped region 130b. Silicide layer 145b is above source region 140b. Drain region 170 is in second doped region 135. Silicide layer 175 is above drain region 170. Details of embodiments of these features are described above with respect to LDMOS transistor 100 ( Figure 1 )describe.

[0077] The ILD 640 is above the gates 150a and 150b and the spacer structures surrounding the gates 150a and 150b. The top surface of the ILD 640 is higher than the topmost vertices of the corner structures in the second spacer portion 630a and the fourth spacer portion 630b. In some embodiments, the top surface of the ILD 640 is substantially coplanar with the topmost vertices of the corner structures in the second spacer portion 630a and the fourth spacer portion 630b. In some embodiments, the ILD 640 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0078] The first source contact 650a extends through the ILD 640 to be electrically connected to the silicide layer 145a to provide an electrical connection to the source region 140a. The second source contact 650b extends through the ILD 640 to be electrically connected to the silicide layer 145b to provide an electrical connection to the source region 140b. The drain contact 660 extends through the ILD 640 to be electrically connected to the silicide layer 175 to provide an electrical connection to the drain region 170. For simplicity, in some cases, the first source contact 650a, the second source contact 650b, and the drain contact 660 are collectively referred to as contacts.

[0079] Each contact has a sidewall that is substantially perpendicular to the top surface of substrate 110. In some embodiments, at least one of the contacts has a tapered profile. In some embodiments, the contacts independently include at least one of copper, aluminum, tungsten, cobalt, alloys thereof, or other suitable conductive materials. In some embodiments, each contact includes the same conductive material. In some embodiments, at least one contact includes a conductive material different from at least one other contact. In some embodiments, at least one contact also includes a barrier layer to assist in preventing the conductive material from diffusing into ILD 640.

[0080] Back to Figure 4 , one of ordinary skill in the art will appreciate that modifications to method 400 are within the scope of this description. In some embodiments, method 400 includes at least one additional operation. For example, in some embodiments, method 400 also includes epitaxially growing semiconductor material above the substrate to implant the well into the epitaxial layer. In some embodiments, at least one operation of method 400 is excluded. For example, in some embodiments, where the gate is a dummy gate and the dummy gate is intended to be retained in the final product, operations 435 and 440 are excluded. In some embodiments, the order of the operations of method 400 is modified. For example, in some embodiments, operation 435 is performed before operation 415.

[0081] Fig. 7A 4 is a cross-sectional view of an LDMOS transistor 700A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 700A corresponds to operation 415 ( Figure 4 ) structure. Figure 5), the LDMOS transistor 700A includes a spacer material 710 located on the substrate 110 and the gates 150a and 150b. The spacer material 710 has an ONO structure. The spacer material includes a first silicon oxide layer 712; a silicon nitride layer 714 on the first silicon oxide layer 712; and a second silicon oxide layer 716 on the silicon nitride layer 714. In some embodiments, the total thickness of the spacer material 710 is in the range of about 700A to about 2800A. If the thickness of the spacer material 710 is too large, then in some cases, the size of the LDMOS transistor 700A increases without significant performance improvement. If the thickness of the spacer material 710 is too small, then in some cases, the spacer material 710 will not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the thickness of the first silicon oxide layer 712 is in the range of about 100A to about 300A. If the thickness of the first silicon oxide layer 712 is too large, then in some cases, the size of the LDMOS transistor 700A increases without significant performance improvement. If the thickness of the first silicon oxide layer 712 is too small, in some cases, the spacer material 710 will not be able to provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the thickness of the silicon nitride layer 714 is in the range of about 200A to about 500A. If the thickness of the silicon nitride layer 714 is too large, in some cases, the size of the LDMOS transistor 700A increases without significant performance improvement. If the thickness of the silicon nitride layer 714 is too small, in some cases, the spacer material 710 will not be able to provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the thickness of the second silicon oxide layer 716 is in the range of about 500A to about 2000A. If the thickness of the second silicon oxide layer 716 is too large, in some cases, the size of the LDMOS transistor 700A increases without significant performance improvement. If the thickness of the second silicon oxide layer 716 is too small, in some cases, the spacer material 710 will not be able to provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the spacer material 710 is deposited using CVD, oxidation, or other suitable processes. In some embodiments, the spacer material 710 comprises a conformal layer. In some embodiments, the spacer material 710 comprises a non-conformal layer.

[0082] Figure 7B 4 is a cross-sectional view of an LDMOS transistor 700B at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 700B corresponds to operation 420 ( Figure 4 ) structure. Fig. 7A), the LDMOS transistor 700B includes a photoresist 720 located above the spacer material 710. In some embodiments, the photoresist 720 includes a resin, a polymer, or other suitable material. The photoresist 720 extends above the topmost surface of the spacer material 710. In some embodiments, the thickness t1 of the photoresist 720 is less than 1.5 times the thickness t2 of the gate 150b (or the gate 150a). If the thickness of the photoresist 720 is too large, in some cases, the photoresist is wasted without significantly improving the performance. In some embodiments, the thickness t1 of the photoresist 720 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 720 is deposited using spin coating or other suitable processes.

[0083] Figure 7C 4 is a cross-sectional view of an LDMOS transistor 700C at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 700C corresponds to operation 425 ( Figure 4 ) structure. With LDMOS transistor 700B ( Figure 7B ), the LDMOS transistor 700C includes remaining photoresists 720a and 720b located closest to the spacer material 710 where a drain region (eg, drain region 170) will be formed in the second doped region 135 ( Figure 1 ) is located on the sidewall. Photoresist 720 ( Figure 7B ) is removed using a combination of photolithography and etching except for the remaining photoresists 720a and 720b. The remaining photoresists 720a and 720b define a discontinuous structure with an opening between the remaining photoresists 720a and the remaining photoresists 720b, wherein the underlying spacer material 710 is exposed. In some embodiments, the top surfaces of the remaining photoresists 720a and 720b are substantially coplanar with the topmost surface of the spacer material 710.

[0084] Fig.7D 4 is a cross-sectional view of an LDMOS transistor 700D at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 700D corresponds to operation 430 ( Figure 4 ) structure. Figure 7C ), the LDMOS transistor 700D includes an angle structure that is closest to the drain region (eg, drain region 170) to be formed in the second doped region 135 ( Figure 1 ) in the spacer material 710. The etching process removes the spacer material 710 ( Figure 7C) to define a first spacer portion 735a, a second spacer portion 730a, a third spacer portion 735b, and a fourth spacer portion 730b. The second spacer portion 730a and the fourth spacer portion 730b include an angle structure. The first spacer portion 735a and the third spacer portion 735b do not have an angle structure. The thickness L2 of the gate 150b is in the range of about 0.1 μm to about 0.3 μm. If the thickness L2 is too large, in some cases, the size of the LDMOS transistor 700D increases without significantly improving the performance. If the thickness L2 is too small, in some cases, the silicide layer (e.g., the silicide layer 155a) ( Figure 1 ) and the channel under the gate 150b is reduced and the risk of short circuit is increased. In some embodiments, the thickness of the corner structure is in the range of greater than zero to about two-thirds (2 / 3) of the thickness of the gate structure. If the thickness of the corner structure is too large, then in some cases, the corner structure interferes with the formation of the contact structure and has a negative impact on the performance of the LDMOS transistor. The corner structure of the LDMOS transistor 700D includes only the second silicon oxide layer 716. In some embodiments, the corner structure also includes a portion of the silicon nitride layer 714 and / or a portion of the first silicon oxide layer 712.

[0085] Fig. 7E 4 is a cross-sectional view of an LDMOS transistor 700E at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 700E corresponds to operation 450 ( Figure 4 ) structure. Fig.7D ) Compared with LDMOS transistor 700E, LDMOS transistor 700E includes S / D regions, silicide layers, ILD and contact structures. For the clarity of the drawings, Fig. 7E The split region of the source regions 140a and 140b is not marked. Fig. 7E Details of the S / D regions and silicide layers are discussed.

[0086] The ILD 740 is above the gates 150a and 150b and the spacer structures surrounding the gates 150a and 150b. The top surface of the ILD 740 is higher than the apex of the corner structures in the second spacer portion 730a and the fourth spacer portion 730b. In some embodiments, the top surface of the ILD 740 is substantially coplanar with the apex of the corner structures in the second spacer portion 730a and the fourth spacer portion 730b. In some embodiments, the ILD 740 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0087] The first source contact 750a extends through the ILD 740 to be electrically connected to the silicide layer 145a to provide an electrical connection to the source region 140a. The second source contact 750b extends through the ILD 740 to be electrically connected to the silicide layer 145b to provide an electrical connection to the source region 140b. The drain contact 760 extends through the ILD 740 to be electrically connected to the silicide layer 175 to provide an electrical connection to the drain region 170. For simplicity, in some cases, the first source contact 750a, the second source contact 750b, and the drain contact 760 are collectively referred to as contacts.

[0088] Each contact has a sidewall that is substantially perpendicular to the top surface of substrate 110. In some embodiments, at least one of the contacts has a tapered profile. In some embodiments, the contacts independently include at least one of copper, aluminum, tungsten, cobalt, alloys thereof, or other suitable conductive materials. In some embodiments, each contact includes the same conductive material. In some embodiments, at least one contact includes a conductive material different from at least one other contact. In some embodiments, at least one contact also includes a barrier layer to assist in preventing the conductive material from diffusing into ILD 740.

[0089] Fig. 8A 4 is a cross-sectional view of an LDMOS transistor 800A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 800A corresponds to operation 415 ( Figure 4 ) structure. Figure 5 ), the LDMOS transistor 800A includes a spacer material 810 located on the substrate 110 and the gates 150a and 150b. The spacer material 810 includes a single layer of silicon nitride. In some embodiments, the thickness of the spacer material 810 is in the range of about 1000A to about 2000A. If the thickness of the spacer material 810 is too large, then in some cases, the size of the LDMOS transistor 800A increases without significantly improving the performance. If the thickness of the spacer material 810 is too small, then in some cases, the spacer material 810 will not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the spacer material 810 is deposited using CVD, oxidation or other suitable processes. In some embodiments, the spacer material 810 includes a conformal layer. In some embodiments, the spacer material 810 includes a non-conformal layer.

[0090] Figure 8B 4 is a cross-sectional view of an LDMOS transistor 800B at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 800B corresponds to operation 420 ( Figure 4 ) structure. Fig. 8A ), the LDMOS transistor 800B includes a photoresist 820 located above the spacer material 810. In some embodiments, the photoresist 820 includes a resin, a polymer, or other suitable material. The photoresist 820 extends above the topmost surface of the spacer material 810. In some embodiments, the thickness t1 of the photoresist 820 is less than 1.5 times the thickness t2 of the gate 150b (or the gate 150a). If the thickness of the photoresist 820 is too large, in some cases, the photoresist is wasted without significantly improving the performance. In some embodiments, the thickness t1 of the photoresist 820 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 820 is deposited using spin coating or other suitable processes.

[0091] Figure 8C 4 is a cross-sectional view of an LDMOS transistor 800C at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 800C corresponds to operation 425 ( Figure 4 ) structure. With LDMOS transistor 800B ( Figure 8B ), the LDMOS transistor 800C includes remaining photoresists 820a and 820b located closest to the spacer material 810 where a drain region (eg, drain region 170) will be formed in the second doped region 135 ( Figure 1 ) is located on the side wall. Photoresist 820 ( Figure 8B ) is removed using a combination of photolithography and etching. The remaining photoresists 820a and 820b define a discontinuous structure with an opening between the remaining photoresists 820a and the remaining photoresists 820b, wherein the underlying spacer material 810 is exposed. In some embodiments, the top surfaces of the remaining photoresists 820a and 820b are substantially coplanar with the topmost surface of the spacer material 810.

[0092] Fig.8D 4 is a cross-sectional view of an LDMOS transistor 800D at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 800D corresponds to operation 430 ( Figure 4 ) structure. Figure 8C ), the LDMOS transistor 800D includes an angle structure that is closest to the drain region (eg, drain region 170) to be formed in the second doped region 135 ( Figure 1 ) in the spacer material 810. The etching process removes the spacer material 810 ( Figure 8C) to define a first spacer portion 835a, a second spacer portion 830a, a third spacer portion 835b, and a fourth spacer portion 830b. The second spacer portion 830a and the fourth spacer portion 830b include an angle structure. The first spacer portion 835a and the third spacer portion 835b do not have an angle structure. The thickness L2 of the gate 150b is in the range of about 0.1 μm to about 0.3 μm. If the thickness L2 is too large, then in some cases, the size of the LDMOS transistor 800D increases without significantly improving the performance. If the thickness L2 is too small, then in some cases, the silicide layer (e.g., the silicide layer 155a) ( Figure 1 ) and the channel under the gate 150b is reduced and the risk of short circuit increases. In some embodiments, the thickness of the corner structure is in the range of greater than zero to about two-thirds (2 / 3) of the thickness of the gate structure. If the thickness of the corner structure is too large, then in some cases, the corner structure interferes with the formation of the contact structure and has a negative impact on the performance of the LDMOS transistor.

[0093] Fig. 8E 4 is a cross-sectional view of an LDMOS transistor 800E at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 800E corresponds to operation 450 ( Figure 4 ) structure. Fig.8D ), the LDMOS transistor 800E includes an S / D region, a silicide layer, an ILD, and a contact structure. For the clarity of the drawings, Fig. 8E The split region of the source regions 140a and 140b is not marked. Fig. 8E Details of the S / D regions and silicide layers are discussed.

[0094] The ILD 840 is above the gates 150a and 150b and the spacer structures surrounding the gates 150a and 150b. The top surface of the ILD 840 is higher than the apex of the corner structures in the second spacer portion 830a and the fourth spacer portion 830b. In some embodiments, the top surface of the ILD 840 is substantially coplanar with the apex of the corner structures in the second spacer portion 830a and the fourth spacer portion 830b. In some embodiments, the ILD 840 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0095] The first source contact 850a extends through the ILD 840 to be electrically connected to the silicide layer 145a to provide an electrical connection to the source region 140a. The second source contact 850b extends through the ILD 840 to be electrically connected to the silicide layer 145b to provide an electrical connection to the source region 140b. The drain contact 860 extends through the ILD 840 to be electrically connected to the silicide layer 175 to provide an electrical connection to the drain region 170. For simplicity, in some cases, the first source contact 850a, the second source contact 850b, and the drain contact 860 are collectively referred to as contacts.

[0096] Each contact has a sidewall that is substantially perpendicular to the top surface of substrate 110. In some embodiments, at least one of the contacts has a tapered profile. In some embodiments, the contacts independently include at least one of copper, aluminum, tungsten, cobalt, alloys thereof, or other suitable conductive materials. In some embodiments, each contact includes the same conductive material. In some embodiments, at least one contact includes a conductive material different from at least one other contact. In some embodiments, at least one contact also includes a barrier layer to assist in preventing the conductive material from diffusing into ILD 840.

[0097] Fig.9A 4 is a cross-sectional view of an LDMOS transistor 900A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 900A corresponds to operation 415 ( Figure 4 ) structure. Figure 5), the LDMOS transistor 900A includes a spacer material 910 located on the substrate 110 and the gates 150a and 150b. The spacer material 910 has a multi-layer structure. The spacer material 910 includes a silicon oxide layer 912; and a silicon nitride layer 914 on the silicon oxide layer 912. In some embodiments, the total thickness of the spacer material 910 is in the range of about 1000A to about 2000A. If the thickness of the spacer material 910 is too large, then in some cases, the size of the LDMOS transistor 900A increases without significant improvement in performance. If the thickness of the spacer material 910 is too small, then in some cases, the spacer material 910 will not be able to provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the thickness of the silicon oxide layer 912 is in the range of about 500A to about 1000A. If the thickness of the silicon oxide layer 912 is too large, then in some cases, the size of the LDMOS transistor 900A increases without significant improvement in performance. If the thickness of silicon oxide layer 912 is too small, in some cases, spacer material 910 will not provide sufficient electrical isolation for gates 150a and 150b. In some embodiments, the thickness of silicon nitride layer 914 is in the range of about 500A to about 1000A. If the thickness of silicon nitride layer 914 is too large, in some cases, the size of LDMOS transistor 900A increases without significant performance improvement. If the thickness of silicon nitride layer 914 is too small, in some cases, spacer material 910 will not provide sufficient electrical isolation for gates 150a and 150b. In some embodiments, spacer material 910 is deposited using CVD, oxidation or other suitable processes. In some embodiments, spacer material 910 includes a conformal layer. In some embodiments, spacer material 910 includes a non-conformal layer.

[0098] Fig. 9B 4 is a cross-sectional view of an LDMOS transistor 900B at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 900B corresponds to operation 420 ( Figure 4 ) structure. Fig.9A), LDMOS transistor 900B includes a photoresist 920 located above the spacer material 910. In some embodiments, the photoresist 920 includes a resin, a polymer, or other suitable material. The photoresist 920 extends above the topmost surface of the spacer material 910. In some embodiments, the thickness t1 of the photoresist 920 is less than 1.5 times the thickness t2 of the gate 150b (or the gate 150a). If the thickness of the photoresist 920 is too large, in some cases, the photoresist is wasted without significantly improving the performance. In some embodiments, the thickness t1 of the photoresist 920 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 920 is deposited using spin coating or other suitable processes.

[0099] Fig. 9C 4 is a cross-sectional view of an LDMOS transistor 900C at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 900C corresponds to operation 425 ( Figure 4 ) structure. Fig. 9B ), the LDMOS transistor 900C includes remaining photoresists 920a and 920b located closest to the spacer material 910 where a drain region (eg, drain region 170) will be formed in the second doped region 135 ( Figure 1 ) is located on the side wall. Photoresist 920 ( Fig. 9B ) is removed using a combination of photolithography and etching. The remaining photoresists 920a and 920b define a discontinuous structure with an opening between the remaining photoresists 920a and the remaining photoresists 920b, wherein the underlying spacer material 910 is exposed. In some embodiments, the top surfaces of the remaining photoresists 920a and 920b are substantially coplanar with the topmost surface of the spacer material 910.

[0100] Fig.9D 4 is a cross-sectional view of an LDMOS transistor 900D at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 900D corresponds to operation 430 ( Figure 4 ) structure. Fig. 9C ), the LDMOS transistor 900D includes an angle structure that is closest to the drain region (eg, drain region 170) to be formed in the second doped region 135 ( Figure 1 ) in the spacer material 910. The etching process removes the spacer material 910 ( Fig. 9C) to define a first spacer portion 935a, a second spacer portion 930a, a third spacer portion 935b, and a fourth spacer portion 930b. The second spacer portion 930a and the fourth spacer portion 930b include an angle structure. The first spacer portion 935a and the third spacer portion 935b do not have an angle structure. The thickness L2 of the gate 150b is in the range of about 0.1 μm to about 0.3 μm. If the thickness L2 is too large, then in some cases, the size of the LDMOS transistor 900D increases without significantly improving the performance. If the thickness L2 is too small, then in some cases, the silicide layer (e.g., the silicide layer 155a) ( Figure 1 ) and the channel under the gate 150b is reduced and the risk of short circuit increases. In some embodiments, the thickness L1 of the corner structure is in the range of greater than zero to about two-thirds (2 / 3) of the thickness of the gate structure. If the thickness L1 of the corner structure is too large, then in some cases, the corner structure interferes with the formation of the contact structure and has a negative impact on the performance of the LDMOS transistor. The corner structure of the LDMOS transistor 900D includes both the silicon oxide layer 912 and the silicon nitride layer 914. In some embodiments, the corner structure includes only a portion of the silicon nitride layer 914. In some embodiments, the thickness L3 of the silicon oxide layer 712 in the corner structure is in the range of greater than zero to about one-half (1 / 2) L1. If the thickness L3 is too large, then in some cases, the corner structure interferes with the formation of the contact structure and has a negative impact on the performance of the LDMOS transistor.

[0101] Fig.9E 4 is a cross-sectional view of an LDMOS transistor 900E at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 900E corresponds to operation 450 ( Figure 4 ) structure. Fig.9D ), the LDMOS transistor 900E includes an S / D region, a silicide layer, an ILD, and a contact structure. For the clarity of the drawings, Fig.9E The split region of the source regions 140a and 140b is not marked. Fig.9E Details of the S / D regions and silicide layers are discussed.

[0102] The ILD 940 is above the gates 150a and 150b and the spacer structures surrounding the gates 150a and 150b. The top surface of the ILD 940 is higher than the topmost vertices of the corner structures in the second spacer portion 930a and the fourth spacer portion 930b. In some embodiments, the top surface of the ILD 940 is substantially coplanar with the topmost vertices of the corner structures in the second spacer portion 930a and the fourth spacer portion 930b. In some embodiments, the ILD 940 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0103] The first source contact 950a extends through the ILD 940 to be electrically connected to the silicide layer 145a to provide an electrical connection to the source region 140a. The second source contact 950b extends through the ILD 940 to be electrically connected to the silicide layer 145b to provide an electrical connection to the source region 140b. The drain contact 960 extends through the ILD 940 to be electrically connected to the silicide layer 175 to provide an electrical connection to the drain region 170. For simplicity, in some cases, the first source contact 950a, the second source contact 950b, and the drain contact 960 are collectively referred to as contacts.

[0104] Each contact has a sidewall that is substantially perpendicular to the top surface of substrate 110. In some embodiments, at least one of the contacts has a tapered profile. In some embodiments, the contacts independently include at least one of copper, aluminum, tungsten, cobalt, alloys thereof, or other suitable conductive materials. In some embodiments, each contact includes the same conductive material. In some embodiments, at least one contact includes a conductive material different from at least one other contact. In some embodiments, at least one contact also includes a barrier layer to assist in preventing conductive material from diffusing into ILD 940.

[0105] Fig. 10A 4 is a cross-sectional view of an LDMOS transistor 1000A at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 1000A corresponds to operation 415 ( Figure 4 ) structure. Figure 5), the LDMOS transistor 1000A includes a spacer material 1010 located on the substrate 110 and the gates 150a and 150b. The spacer material 1010 has a multi-layer structure. The spacer material 1010 includes a silicon nitride layer 1012; and a silicon oxide layer 1014 on the silicon nitride layer 1012. In some embodiments, the total thickness of the spacer material 1010 is in the range of about 1000A to about 2000A. If the thickness of the spacer material 1010 is too large, then in some cases, the size of the LDMOS transistor 1000A increases without significant improvement in performance. If the thickness of the spacer material 1010 is too small, then in some cases, the spacer material 1010 will not provide sufficient electrical isolation for the gates 150a and 150b. In some embodiments, the thickness of the silicon nitride layer 1012 is in the range of about 500A to about 1000A. If the thickness of the silicon nitride layer 1012 is too large, then in some cases, the size of the LDMOS transistor 1000A increases without significant improvement in performance. If the thickness of silicon nitride layer 1012 is too small, in some cases, spacer material 1010 will not be able to provide sufficient electrical isolation for gates 150a and 150b. In some embodiments, the thickness of silicon oxide layer 1014 is in the range of about 500A to about 1000A. If the thickness of silicon oxide layer 1014 is too large, in some cases, the size of LDMOS transistor 1000A increases without significant performance improvement. If the thickness of silicon nitride layer 1014 is too small, in some cases, spacer material 1010 will not be able to provide sufficient electrical isolation for gates 150a and 150b. In some embodiments, spacer material 1010 is deposited using CVD, oxidation or other suitable processes. In some embodiments, spacer material 1010 includes a conformal layer. In some embodiments, spacer material 1010 includes a non-conformal layer.

[0106] Fig. 10B 4 is a cross-sectional view of an LDMOS transistor 1000B at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 1000B corresponds to operation 420 ( Figure 4 ) structure. Fig. 10A), the LDMOS transistor 1000B includes a photoresist 1020 located above the spacer material 1010. In some embodiments, the photoresist 1020 includes a resin, a polymer, or other suitable material. The photoresist 1020 extends above the topmost surface of the spacer material 1010. In some embodiments, the thickness t1 of the photoresist 1020 is less than 1.5 times the thickness t2 of the gate 150b (or the gate 150a). If the thickness of the photoresist 1020 is too large, in some cases, the photoresist is wasted without significantly improving the performance. In some embodiments, the thickness t1 of the photoresist 1020 is measured at a position between the gates 150a and 150b. In some embodiments, the photoresist 1020 is deposited using spin coating or other suitable processes.

[0107] Fig. 10C 4 is a cross-sectional view of an LDMOS transistor 1000C at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 1000C corresponds to operation 425 ( Figure 4 ) structure. Fig. 10B ), the LDMOS transistor 1000C includes the remaining photoresists 1020a and 1020b, which are located closest to the spacer material 1010 to form a drain region (e.g., drain region 170) in the second doped region 135 ( Figure 1 ) is located on the side wall. Photoresist 1020 ( Fig. 10B ) is removed using a combination of photolithography and etching. The remaining photoresists 1020a and 1020b define a discontinuous structure with an opening between the remaining photoresists 1020a and the remaining photoresists 1020b, wherein the underlying spacer material 1010 is exposed. In some embodiments, the top surfaces of the remaining photoresists 1020a and 1020b are substantially coplanar with the topmost surface of the spacer material 1010.

[0108] Fig. 10D 4 is a cross-sectional view of an LDMOS transistor 1000D at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 1000D corresponds to operation 430 ( Figure 4 ) structure. Fig. 10C ), the LDMOS transistor 1000D includes an angle structure that is closest to a drain region (eg, drain region 170) to be formed in the second doped region 135 ( Figure 1 ) in the spacer material 1010. The etching process removes the spacer material 1010 ( Fig. 10C) to define a first spacer portion 1035a, a second spacer portion 1030a, a third spacer portion 1035b, and a fourth spacer portion 1030b. The second spacer portion 1030a and the fourth spacer portion 1030b include an angle structure. The first spacer portion 1035a and the third spacer portion 1035b do not have an angle structure. The thickness L2 of the gate 150b is in the range of about 0.1 μm to about 0.3 μm. If the thickness L2 is too large, in some cases, the size of the LDMOS transistor 1000D increases without significantly improving the performance. If the thickness L2 is too small, in some cases, the silicide layer (e.g., the silicide layer 155a) ( Figure 1 ) and the channel under the gate 150b is reduced and the risk of short circuit is increased. In some embodiments, the thickness L1 of the corner structure is in the range of greater than zero to about two-thirds (2 / 3) of the thickness of the gate structure. If the thickness L1 of the corner structure is too large, then in some cases, the corner structure interferes with the formation of the contact structure and has a negative impact on the performance of the LDMOS transistor. The corner structure of the LDMOS transistor 1000D includes only the silicon oxide layer 1014. In some embodiments, the corner structure of the LDMOS transistor 1000D includes both the silicon nitride layer 1012 and the silicon oxide layer 1014.

[0109] Fig.10E 4 is a cross-sectional view of an LDMOS transistor 1000E at an intermediate stage of fabrication according to some embodiments. In some embodiments, the LDMOS transistor 1000E corresponds to operation 450 ( Figure 4 ) structure. Fig. 10D ), the LDMOS transistor 1000E includes an S / D region, a silicide layer, an ILD, and a contact structure. For the clarity of the drawings, Fig.10E The split region of the source regions 140a and 140b is not marked. Fig.10E Details of the S / D regions and silicide layers are discussed.

[0110] The ILD 1040 is above the gates 150a and 150b and the spacer structures surrounding the gates 150a and 150b. The top surface of the ILD 1040 is higher than the topmost vertices of the corner structures in the second spacer portion 1030a and the fourth spacer portion 1030b. In some embodiments, the top surface of the ILD 1040 is substantially coplanar with the topmost vertices of the corner structures in the second spacer portion 1030a and the fourth spacer portion 1030b. In some embodiments, the ILD 1040 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.

[0111] The first source contact 1050a extends through the ILD 1040 to be electrically connected to the silicide layer 145a to provide an electrical connection to the source region 140a. The second source contact 1050b extends through the ILD 1040 to be electrically connected to the silicide layer 145b to provide an electrical connection to the source region 140b. The drain contact 1060 extends through the ILD 1040 to be electrically connected to the silicide layer 175 to provide an electrical connection to the drain region 170. For simplicity, in some cases, the first source contact 1050a, the second source contact 1050b, and the drain contact 1060 are collectively referred to as contacts.

[0112] Each contact has a sidewall that is substantially perpendicular to the top surface of substrate 110. In some embodiments, at least one of the contacts has a tapered profile. In some embodiments, the contacts independently include at least one of copper, aluminum, tungsten, cobalt, alloys thereof, or other suitable conductive materials. In some embodiments, each contact includes the same conductive material. In some embodiments, at least one contact includes a conductive material different from at least one other contact. In some embodiments, at least one contact also includes a barrier layer to assist in preventing the conductive material from diffusing into ILD 1040.

[0113] Fig.11 1 is a schematic diagram of a buck converter 1100 including an LDMOS transistor 1110 according to some embodiments. In some embodiments, the LDMOS transistor 1110 is similar to the LDMOS transistor 100 ( Figure 1 ), LDMOS transistor 600E( Fig. 6E )、LDMOS transistor 700E( Fig. 7E )、LDMOS transistor 800E( Fig. 8E )、LDMOS transistor 900E( Fig.9E ), or LDMOS transistor 1000E ( Fig.10E Buck converter 1100 includes a sensing and switching circuit 1120, an inductor 1130, a capacitor 1140, and an output 1150 for providing an output voltage to a load. In some embodiments, buck converter 1100 includes a gate driver for providing a drive voltage to a gate of LDMOS transistor 1100.

[0114] The sensing and switching circuit 1120 is configured to control the voltage provided to the gate of the LDMOS transistor 1110. The source of the high-side device 1115a is connected to the input voltage V inThe source of the low-side device 1115b is connected to a reference voltage, such as ground. The high-side device 1115a and the low-side device 1115b share a drain, which is connected to the inductor 1130. The capacitor 1140 is connected between the output of the inductor 1130 and the source of the low-side device 1115b. The output voltage (Vout) 1150 is connected to the load.

[0115] LDMOS transistor 1110 includes a high-side device 1115a and a low-side device 1115b. In some embodiments, high-side device 1115a corresponds to gate 150a ( Figure 1 ); low-side device 1115b corresponds to gate 150b ( Figure 1 ). in In some embodiments where the voltage rating is 26.4V, the buck converter 1100 includes a high-side device 1115a having a hot carrier injection (HCI) rating of less than 26.4V. The specific HCI rating of interest is the rated operating area, the HCI 10-year safe operating area, the HCI 0.2-year safe operating area, and / or another suitable HCI rating. To assist in preventing breakdown behavior, the high-side device 1115a of some embodiments has a breakdown voltage (e.g., BV 0.2) greater than 26.4V. dss ). To assist in achieving these operating characteristics, in some exemplary embodiments, the LDMOS high-side device 1115a has a shorter drift region length, for example, length Ld, than other methods.

[0116] Similar principles apply to the low-side device 1115b. in In some embodiments where the HCI rating is 26.4 V, the buck converter 1100 includes a low-side device 1115 b having an HCI rating less than 26.4 V. In some embodiments, the LDMOS low-side device 1115 b has a shorter drift region length, for example, length Ld, than other approaches.

[0117] One aspect of the present description relates to a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS transistor includes a first gate. The LDMOS transistor also includes a first source region located on a first side of the first gate. The LDMOS transistor also includes a drain region located on a second side of the first gate, wherein the second side is opposite to the first side. The LDMOS transistor also includes a first spacer surrounding the first gate. The first spacer includes a first portion located on a first side of the first gate, wherein a top surface of the first portion is substantially coplanar with a top surface of the first gate. The first spacer also includes a second portion located on a second side of the first gate, wherein the second portion includes a first corner structure extending above the top surface of the first gate. In some embodiments, the spacer includes a single layer of silicon oxide. In some embodiments, the spacer includes a single layer of silicon nitride. In some embodiments, the spacer includes a first silicon oxide layer; a silicon nitride layer above the first silicon oxide layer; and a second silicon oxide layer above the silicon nitride layer. In some embodiments, the spacer includes a silicon oxide layer; and a silicon nitride layer above the silicon oxide layer. In some embodiments, the spacer includes a silicon nitride layer; and a silicon oxide layer above the silicon nitride layer. In some embodiments, the first corner structure includes a single material. In some embodiments, the first gate has a first thickness measured in a direction perpendicular to a top surface of the first gate, the first corner structure extends a second thickness above the top surface of the first gate, and the second thickness is less than about two-thirds (2 / 3) of the first thickness. In some embodiments, the LDMOS transistor further includes: a second gate, wherein the drain is located on a second side of the second gate; a second spacer surrounding the second gate, wherein the second spacer includes: a third portion located on the second side of the second gate, wherein the third portion includes the second corner structure. In some embodiments, the second spacer further includes a fourth portion located on a first side of the second gate, the first side is opposite to the second side, and a top surface of the fourth portion is substantially coplanar with a top surface of the second gate.

[0118] One aspect of the present description relates to a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS transistor includes a first gate. The LDMOS transistor also includes a second gate. The LDMOS transistor also includes: a drain region located between the first gate and the second gate, wherein each of the first gate and the second gate can be used to control the voltage at the drain region. The LDMOS transistor also includes a first spacer surrounding the first gate. The first spacer includes a first portion located on a side of the first gate closest to the drain region, wherein the first portion includes a first corner structure extending above a top surface of the first gate. The LDMOS transistor also includes a second spacer surrounding the second gate. The second spacer includes a second portion located on a side of the second gate closest to the drain region, wherein the second portion includes a second corner structure extending above a top surface of the second gate. In some embodiments, at least one of the first corner structure or the second corner structure has a tapered shape. In some embodiments, the first gate has a first thickness measured in a direction perpendicular to the top surface of the first gate, the first corner structure extends a second thickness above the top surface of the first gate, and the second thickness is less than about two-thirds (2 / 3) of the first thickness. In some embodiments, the second gate has a third thickness measured in a direction perpendicular to the top surface of the second gate, the second corner structure extends a fourth thickness above the top surface of the second gate, and the fourth thickness is less than about two-thirds (2 / 3) of the third thickness. In some embodiments, the fourth thickness is equal to the second thickness. In some embodiments, the fourth thickness is different from the second thickness. In some embodiments, the LDMOS transistor further includes: a silicide layer located above the top surface of the first gate, wherein the silicide layer extends across the entire top surface of the first gate.

[0119] One aspect of the present description relates to a method for manufacturing a laterally diffused metal oxide semiconductor (LDMOS) transistor. The method includes forming a gate on a substrate. The method also includes depositing a spacer material on the gate and the substrate. The method also includes depositing a photoresist on the spacer material. The method also includes patterning the photoresist. Patterning the photoresist includes removing the photoresist from the spacer material on a first side of the gate and retaining the photoresist on the spacer material on a second side of the gate, wherein the second side is opposite to the first side. The method also includes etching the spacer material using the patterned photoresist as a mask. Etching the spacer material includes forming a first portion of the spacer material on a first side of the gate, the top surface of the first portion being substantially coplanar with the top surface of the gate; and forming an angle structure in a second portion of the spacer material on a second side of the gate, wherein the angle structure extends above the top surface of the gate. In some embodiments, the method also includes forming a drain region on the second side of the gate. In some embodiments, the method also includes forming a silicide layer over the entire top surface of the gate.

[0120] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis to design or modify other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0121] Example

[0122] Example 1. A laterally diffused metal oxide semiconductor (LDMOS) transistor, comprising: a first gate; a first source region located on a first side of the first gate; a drain region located on a second side of the first gate, wherein the second side is opposite to the first side; a first spacer surrounding the first gate, wherein the first spacer comprises: a first portion located on the first side of the first gate, wherein a top surface of the first portion is substantially coplanar with a top surface of the first gate; and a second portion located on the second side of the first gate, wherein the second portion comprises a first corner structure extending above a top surface of the first gate.

[0123] Example 2. The LDMOS transistor of Example 1, wherein the spacer comprises a single layer of silicon oxide.

[0124] Example 3. The LDMOS transistor of Example 1, wherein the spacer comprises a single layer of silicon nitride.

[0125] Example 4. The LDMOS transistor of Example 1, wherein the spacer comprises: a first silicon oxide layer; a silicon nitride layer over the first silicon oxide layer; and a second silicon oxide layer over the silicon nitride layer.

[0126] Example 5. The LDMOS transistor of Example 1, wherein the spacer comprises: a silicon oxide layer; and a silicon nitride layer over the silicon oxide layer.

[0127] Example 6. The LDMOS transistor of Example 1, wherein the spacer comprises: a silicon nitride layer; and a silicon oxide layer over the silicon nitride layer.

[0128] Example 7. The LDMOS transistor of Example 1, wherein the first corner structure comprises a single material.

[0129] Example 8. An LDMOS transistor according to Example 1, wherein the first gate has a first thickness measured in a direction perpendicular to a top surface of the first gate, the first corner structure extends a second thickness above the top surface of the first gate, and the second thickness is less than approximately two-thirds (2 / 3) of the first thickness.

[0130] Example 9. The LDMOS transistor according to Example 1 further includes: a second gate, wherein the drain is located on a second side of the second gate; a second spacer surrounding the second gate, wherein the second spacer includes: a third portion located on a second side of the second gate, wherein the third portion includes a second corner structure.

[0131] Example 10. The LDMOS transistor of Example 9, wherein the second spacer further comprises a fourth portion located on a first side of the second gate, the first side being opposite to the second side, and a top surface of the fourth portion is substantially coplanar with a top surface of the second gate.

[0132] Example 11. A laterally diffused metal oxide semiconductor (LDMOS) transistor, comprising: a first gate; a second gate; a drain region located between the first gate and the second gate, wherein each of the first gate and the second gate can be used to control the voltage at the drain region; a first spacer surrounding the first gate, wherein the first spacer includes: a first portion located on a side of the first gate closest to the drain region, wherein the first portion includes a first corner structure extending above a top surface of the first gate; and a second spacer surrounding the second gate, wherein the second spacer includes: a second portion located on a side of the second gate closest to the drain region, wherein the second portion includes a second corner structure extending above a top surface of the second gate.

[0133] Example 12. The LDMOS transistor of Example 11, wherein at least one of the first corner structure or the second corner structure has a tapered shape.

[0134] Example 13. An LDMOS transistor according to Example 11, wherein the first gate has a first thickness measured in a direction perpendicular to a top surface of the first gate, the first corner structure extends a second thickness above the top surface of the first gate, and the second thickness is less than approximately two-thirds (2 / 3) of the first thickness.

[0135] Example 14. An LDMOS transistor according to Example 13, wherein the second gate has a third thickness measured in a direction perpendicular to the top surface of the second gate, the second corner structure extends a fourth thickness above the top surface of the second gate, and the fourth thickness is less than approximately two-thirds (2 / 3) of the third thickness.

[0136] Example 15. The LDMOS transistor of Example 14, wherein the fourth thickness is equal to the second thickness.

[0137] Example 16. The LDMOS transistor of Example 14, wherein the fourth thickness is different from the second thickness.

[0138] Example 17. The LDMOS transistor of Example 14, further comprising: a silicide layer located above the top surface of the first gate, wherein the silicide layer extends across the entire top surface of the first gate.

[0139] Example 18. A method for manufacturing a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising: forming a gate on a substrate; depositing a spacer material on the gate and the substrate; depositing a photoresist on the spacer material; patterning the photoresist, wherein patterning the photoresist comprises: removing the photoresist from the spacer material located on a first side of the gate and retaining the photoresist on the spacer material located on a second side of the gate, wherein the second side is opposite to the first side; etching the spacer material using the patterned photoresist as a mask, wherein etching the spacer material comprises: forming a first portion of the spacer material located on the first side of the gate, the top surface of the first portion being substantially coplanar with the top surface of the gate; and forming an angle structure in a second portion of the spacer material located on the second side of the gate, wherein the angle structure extends above the top surface of the gate.

[0140] Example 19. The method of Example 18, further comprising: forming a drain region on a second side of the gate.

[0141] Example 20. The method of Example 18, further comprising: forming a silicide layer over the entire top surface of the gate.

Claims

1. A laterally diffused metal oxide semiconductor (LDMOS) transistor, comprising: a first gate; a first source region, located on a first side of the first gate; a drain region located on a second side of the first gate, wherein the second side is opposite to the first side; A first spacer surrounds the first gate, wherein the first spacer comprises: a first portion located on a first side of the first gate, wherein a top surface of the first portion is substantially coplanar with a top surface of the first gate; and A second portion is located at a second side of the first gate, wherein the second portion includes a first corner structure extending above a top surface of the first gate.

2. The LDMOS transistor according to claim 1, wherein: The spacer includes a single layer of silicon oxide.

3. The LDMOS transistor according to claim 1, wherein: The spacer includes a single layer of silicon nitride.

4. The LDMOS transistor according to claim 1, wherein: The spacer comprises: a first silicon oxide layer; a silicon nitride layer on the first silicon oxide layer; and A second silicon oxide layer is formed on the silicon nitride layer.

5. The LDMOS transistor according to claim 1, wherein: The spacer comprises: a silicon oxide layer; and A silicon nitride layer is disposed on the silicon oxide layer.

6. The LDMOS transistor according to claim 1, wherein: The spacer comprises: a silicon nitride layer; and A silicon oxide layer is formed on the silicon nitride layer.

7. The LDMOS transistor according to claim 1, wherein: The first corner structure comprises a single material.

8. The LDMOS transistor according to claim 1, wherein: The first gate has a first thickness measured in a direction perpendicular to a top surface of the first gate, the first corner structure extends a second thickness above the top surface of the first gate, and the second thickness is less than about two thirds (2 / 3) of the first thickness.

9. A laterally diffused metal oxide semiconductor (LDMOS) transistor comprising: a first gate; A second grid; a drain region located between the first gate and the second gate, wherein each of the first gate and the second gate can be used to control a voltage at the drain region; A first spacer surrounds the first gate, wherein the first spacer comprises: a first portion located on a side of the first gate closest to the drain region, wherein the first portion includes a first corner structure extending above a top surface of the first gate; and A second spacer surrounds the second gate, wherein the second spacer comprises: A second portion is located on a side of the second gate closest to the drain region, wherein the second portion includes a second corner structure extending higher than a top surface of the second gate.

10. A method of manufacturing a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising: forming a gate on the substrate; depositing a spacer material over the gate and the substrate; depositing a photoresist over the spacer material; Patterning the photoresist, wherein patterning the photoresist comprises: removing the photoresist from the spacer material on the first side of the gate, and retaining the photoresist on the spacer material on a second side of the gate, wherein the second side is opposite to the first side; Etching the spacer material using the patterned photoresist as a mask, wherein etching the spacer material comprises; forming a first portion of the spacer material located on a first side of the gate, wherein a top surface of the first portion is substantially coplanar with a top surface of the gate; and A corner structure is formed in a second portion of the spacer material at a second side of the gate, wherein the corner structure extends above a top surface of the gate.

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