Semiconductor device

Abstract

A semiconductor device includes: a semiconductor layer; the gate structure is positioned on the upper surface of the semiconductor layer; the drift region of the second doping type extends into the semiconductor layer from the upper surface of the semiconductor layer, the source region and the drain region of the second doping type are located in the semiconductor layer, and the drain region and the drift region are located on the same side of the gate structure. And the first dielectric layer at least covers a part of the upper surface of the drift region adjacent to the gate structure, wherein the first dielectric layer has a high dielectric constant. According to the invention, the first dielectric layer is made of a material with a high dielectric constant, so that the capacitance between the grid electrode and the drift region is larger, the coupling effect is stronger, the JFET effect of the semiconductor device is relieved, and the saturation current density of the device is increased.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and more specifically, relates to a semiconductor device. Background Art

[0002] For existing RF LDMOS devices, there is a contradiction between the current density and device reliability: high current density is often achieved by increasing the injection concentration of the low-doped region LDD in the RF LDMOS, and the LDD injection concentration is closely related to the electric field strength distribution of the device. A higher LDD injection concentration means a higher electric field strength, so the reliability of the device is lower. The technical solution of the present invention is proposed to solve the problem of high current density and low device reliability of RF LDMOS devices. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device for solving the problems existing in the prior art.

[0004] To achieve the above-mentioned object and other related objects, the present invention provides a semiconductor device, comprising: a semiconductor layer; a gate structure located on the upper surface of the semiconductor layer; a drift region of a second doping type extending from the upper surface of the semiconductor layer to the interior thereof, a source region and a drain region of the second doping type located in the semiconductor layer, the drain region and the drift region being located on the same side of the gate structure, and a first dielectric layer covering at least a portion of the upper surface of the drift region adjacent to the gate structure, wherein the first dielectric layer has a high dielectric constant.

[0005] Preferably, the gate structure comprises a gate dielectric layer and a gate conductor located on a portion of the gate dielectric layer, wherein the gate dielectric layer is further included between the first dielectric layer and the drift region.

[0006] Preferably, the dielectric constant of the first dielectric layer is greater than 3.9.

[0007] Preferably, the first dielectric layer is configured as a single-layer dielectric structure or a composite dielectric structure.

[0008] Preferably, the composite dielectric structure comprises a second dielectric having a high dielectric constant and a third dielectric having a low dielectric constant, wherein an equivalent dielectric constant of the composite dielectric structure is greater than 0.85 times the dielectric constant of the second dielectric.

[0009] Preferably, the first dielectric layer covers the upper surface of the semiconductor layer and the upper surface and side surfaces of the gate structure.

[0010] Preferably, the device further comprises a first field plate located on the first dielectric layer, wherein the first dielectric layer at least covers a region below the first field plate.

[0011] Preferably, at least one second field plate is further included, the first field plate and the at least one second field plate are arranged in sequence along the direction from the gate structure to the drain region, and a field plate dielectric layer is included between adjacent first field plates and second field plates, and between two adjacent second field plates.

[0012] Preferably, the field plate dielectric layer is made of the same material as the first dielectric layer.

[0013] Preferably, the first dielectric layer is also located below the second field plate.

[0014] Preferably, the thickness of the first dielectric layer is set to be greater than 20 nm and less than 500 nm.

[0015] Preferably, it also includes: a well region with a first doping type located in the semiconductor layer and extending below the gate structure; a body contact region located in the well region and adjacent to the source region; an interlayer dielectric layer covering the first dielectric layer; conductive channels formed respectively through the interlayer dielectric layer and extending to the source region, drain region and gate structure; and a metal layer located on the conductive channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A cross-sectional view showing a semiconductor device according to a first embodiment of the present invention;

[0017] Figure 2 A cross-sectional view showing a semiconductor device according to a second embodiment of the present invention;

[0018] Figure 3 A cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0019] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0020] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0021] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0022] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0023] Figure 1 A cross-sectional view of a semiconductor device according to a first embodiment of the present invention is shown. Figure 1 As shown, the semiconductor device includes a semiconductor layer, a gate structure 110 located on the upper surface of the semiconductor layer, a drift region 103 of a second doping type extending from the upper surface of the semiconductor layer to the inside thereof, a source region 105 and a drain region 106 of a second doping type located in the semiconductor layer, the drain region 106 and the drift region 103 are located on the same side of the gate structure 110, and a first dielectric layer 112 covering at least a portion of the upper surface of the drift region 103 adjacent to the gate structure 110, wherein the first dielectric layer 112 has a high dielectric constant. In this embodiment, the first dielectric layer 112 extends from the side of the gate structure 110 to the drain region 106. In other embodiments, the first dielectric layer 112 may be located only on the upper surface of a portion of the drift region 103 adjacent to the gate structure 110.

[0024] The gate structure 110 includes a gate dielectric layer 109 located on the upper surface of the semiconductor layer and a gate conductor 108 located on the gate dielectric layer 109, wherein the gate dielectric layer 109 is at least located below the gate conductor 108. Further, the gate structure 110 also includes a gate metal silicide (not shown in the figure) located on the gate conductor 108. In this embodiment, the gate dielectric layer 109 extends from the source region 105 to the drain region 106, and the first dielectric layer 112 is located on the gate dielectric layer 109. In other embodiments, the gate dielectric layer 109 may also be located only below the gate conductor 108, and the first dielectric layer 112 is in contact with the upper surface of the semiconductor layer.

[0025] Preferably, the dielectric constant of the first dielectric layer is greater than 3.9. The first dielectric layer can be set as a single-layer dielectric structure, or as a composite dielectric structure, the composite dielectric structure comprising a second dielectric with a high dielectric constant and a third dielectric with a low dielectric constant, wherein the equivalent dielectric constant of the composite dielectric structure is greater than 0.85 times the dielectric constant of the second dielectric. As an example, the first dielectric layer can be set as a single-layer dielectric such as SiN material, Al2O3 material, HfO2 material, or a composite material of SiN and SiO. The thickness of the first dielectric layer is set to be greater than 20nm and less than 500nm.

[0026] The semiconductor device further includes a well region 104 of a first doping type located in the semiconductor layer, and a body contact region 107 of a first doping type located in the well region 104 and adjacent to the source region 105, the source region 105 is located in the well region 104, the drain region 106 is located in the drift region 103, and a portion of the well region 104 is located below the gate conductor 108. The semiconductor device further includes a drain metal silicide 111 located on the upper surface of the drain region 106, a source metal silicide 140 located on the upper surfaces of the body contact region 107 and the source region 105, and an interlayer dielectric layer 113 covering the semiconductor layer, the gate structure, and the first dielectric layer. The interlayer dielectric layer 113 includes a silicon oxide material.

[0027] The first doping type is set to one of N-type and P-type, and the second doping type is set to the other of N-type and P-type.

[0028] The present invention sets the first dielectric layer to a material with a high dielectric constant, so that the capacitance between the gate and the drift region is larger and the coupling effect is stronger, thereby alleviating the JFET effect of the semiconductor device and increasing the saturation current density of the device.

[0029] Figure 2 A cross-sectional view showing a semiconductor device according to a second embodiment of the present invention, Figure 2 The semiconductor device shown is Figure 1 The difference between the semiconductor devices shown is that the first dielectric layer 212 covers different positions. The other structures are basically the same and will not be described in detail here.

[0030] In this embodiment, the first dielectric layer 212 covers the surface of the entire semiconductor layer, specifically, the first dielectric layer 212 covers the source metal silicide 140, the gate dielectric layer 109, the upper surface of the drain metal silicide 111, and the upper surface and side surface of the gate structure 110. In other embodiments, the first dielectric layer 212 at least covers the upper surface of the gate structure 110 and the side surface closer to the drain region, and the upper surface of the drift region 103.

[0031] The present invention sets the first dielectric layer to cover the side surface of the gate structure to further reduce the JFET effect of the device. On the other hand, the first dielectric layer covers the entire upper surface of the semiconductor layer without etching process, which simplifies the process steps and reduces the process cost.

[0032] Figure 3 A cross-sectional view of a semiconductor device according to a third embodiment of the present invention is shown. The semiconductor device of this embodiment further includes a field plate structure. Specifically, this embodiment is described by taking the semiconductor device being a radio frequency LDMOS as an example.

[0033] See also Figure 3 The semiconductor device comprises a semiconductor layer, a second doping type drift region 103, a gate structure, a first dielectric layer 212, a second doping type source region 105 and a drain region 106. The drift region 103 is located in the semiconductor layer, and the drift region 103 extends from the upper surface of the semiconductor layer to the inside of the semiconductor layer; the gate structure is located on the upper surface of the semiconductor layer, and the drain region 106 and the drift region 103 are located on the same side of the gate structure; the first dielectric layer 212 at least covers a portion of the upper surface of the drift region 103 adjacent to the gate structure, wherein the first dielectric layer 212 has a high dielectric constant.

[0034] As an example, the semiconductor layer includes a substrate 101 and an epitaxial layer 102 stacked from bottom to top, wherein the substrate 101 is a Si substrate, the epitaxial layer 102 is a Si epitaxial layer, and the doping concentration of the epitaxial layer 102 is less than the doping concentration of the substrate 100, that is, the substrate 101 is a low-resistance P-type Si substrate, and the epitaxial layer 102 is a high-resistance P-type Si epitaxial layer. The drift region 103 is located in the epitaxial layer 102.

[0035] As an example, a well region 104 of the first conductivity type is further included. The well region 104 is located in the epitaxial layer 102 , and a portion of the well region 104 is located below the gate conductor 108 .

[0036] As an example, a first conductive type lead-out region 130 is also included, and the lead-out region 130 is a heavily doped region of the first doping type. The lead-out region 130 penetrates the epitaxial layer 102 and extends at least into the substrate 101. The function of the lead-out region 130 is to subsequently introduce the device source into the substrate 101, thereby reducing the source end parasitic inductance.

[0037] As an example, the dielectric constant of the first dielectric layer 212 is greater than 3.9. The first dielectric layer can be set to a single-layer dielectric structure, or to a composite dielectric structure, the composite dielectric structure including a second dielectric with a high dielectric constant and a third dielectric with a low dielectric constant, wherein the equivalent dielectric constant of the composite dielectric structure is greater than 0.85 times the dielectric constant of the second dielectric. As an example, the first dielectric layer can be set to a single-layer dielectric such as SiN material, Al2O3 material, HfO2 material, or a composite material of SiN and SiO. The thickness of the first dielectric layer is set to be greater than 20nm and less than 500nm. The thickness of the first dielectric layer can be set according to the breakdown voltage required by the device. Furthermore, the thickness of the first dielectric layer is set to be greater than 80nm and less than 180nm.

[0038] As an example, the gate structure includes a gate dielectric layer 109 located on the upper surface of the semiconductor layer, and a gate conductor 108 located on the gate dielectric layer 109, and further includes an alloy layer located on the gate conductor 108 to reduce the gate resistance and improve the device RF performance. The gate conductor is preferably a polysilicon material, and further, a polysilicon material of the second doping type. The alloy layer is preferably a WSi material.

[0039] As an example, the source region 105 is located in the well region 104 , and the drain region 106 is located in the drift region 103 .

[0040] As an example, the well region 104 is further provided with a well contact region 107 adjacent to the source region 105 for subsequent electrical connection between the well region 104 and the source, and the lead-out region 130 is in contact with a side of the well contact region 107 away from the source region.

[0041] As an example, a source metal silicide layer 140 and a drain metal silicide layer 111 are also included, the source metal silicide layer 140 is in contact with the lead-out region 130 , the source region 105 and the well contact region 107 , and the drain metal silicide layer 111 is in contact with the drain region 106 .

[0042] As an example, a first field plate 121 is also included, which is located on the first dielectric layer 212 and covers a portion of the gate conductor 108 at one end away from the source region 105, wherein the first dielectric layer is at least located below the first field plate and serves as a field plate dielectric of the first field plate.

[0043] As an example, a second field plate structure is also included, the second field plate structure includes a second field plate dielectric layer 123 and a second field plate electrode 122 stacked from bottom to top, and in the horizontal direction, the second field plate electrode is located between the gate structure and the drain region 111. Specifically, in the horizontal direction, the second field plate electrode covers the part of the first field plate electrode 121 that is away from the end of the gate structure. Furthermore, the first dielectric layer 212 is also located below the second field plate electrode 122.

[0044] As an example, the material of the second field plate dielectric layer 123 is different from that of the first dielectric layer 212 . For example, the second field plate dielectric layer is made of a material with a low dielectric constant.

[0045] As an example, the second field plate dielectric layer 123 is made of the same material as the first dielectric layer 212 to further optimize the electric field distribution of the device.

[0046] It should be noted that the first field plate electrode 121 and the second field plate structure are used to improve the surface electric field of the device, which helps to reduce the electric field concentration, improve the reliability of the device, and can reduce the on-resistance of the device, increase the conduction capability of the device, and improve the RF performance of the device. In other examples, more layers of field plate structures can be set, or the first field plate electrode and the second field plate structure are not set, and the number of layers of the field plate structure can be selected according to actual needs.

[0047] As an example, an interlayer dielectric layer 113 is further included, and the interlayer dielectric layer 113 covers the second field plate structure and the gate structure.

[0048] As an example, it also includes a first contact hole 181, which extends from the upper surface of the interlayer dielectric layer 113 to the inside of the device. The first contact hole 181 includes at least three parts. The first part of the first contact hole 181 is electrically connected to the source metal silicide layer 140, the first field plate electrode 121 and the second field plate electrode 122, the second part of the first contact hole 181 is electrically connected to the drain metal silicide layer 111, and the third part of the first contact hole 181 is electrically connected to the gate conductor.

[0049] As an example, it also includes a first metal layer 191, which is located on the interlayer dielectric layer 113. The first metal layer 191 includes at least three parts. The first part, the first metal layer 191 is electrically connected to the first part, the first contact hole 181, the second part, the first metal layer 191 is electrically connected to the second part, the first contact hole 181, and the third part, the first metal layer 191 is electrically connected to the third part, the first contact hole 181.

[0050] As an example, a passivation layer 200 is also included, and the passivation layer 200 covers the upper surface of the interlayer dielectric layer 113 and the first metal layer 191. The passivation layer 200 is provided with a first opening to expose a first part of the first metal layer 191 to form a source pad, and the passivation layer 200 is provided with a second opening to expose a second part of the first metal layer 191 to form a drain pad. The passivation layer 200 is provided with a third opening to expose a third part of the first metal layer 191 to form a gate pad.

[0051] It should be noted that an intermetallic dielectric layer, a second contact hole, and a second metal layer may also be included on the interlayer dielectric layer 113 and the first metal layer 191 to connect with the first metal layer. According to the specific actual needs of the device, multiple intermetallic dielectric layers, third contact holes, and third metal layers may be included, which are not limited here. The passivation layer 200 covers the topmost metal layer and the intermetallic dielectric layer.

[0052] As an example, a back metal layer 300 is further included, and the back metal layer 300 is located on the lower surface of the substrate 101 .

[0053] The first dielectric layer of the present invention adopts a material with a higher dielectric constant, so the capacitance between the gate and the drift region is larger and the coupling effect is stronger, thereby alleviating the JFET effect in the RF LDMOS device, thereby increasing the device saturation current density; in addition, since the first dielectric layer also serves as the field plate dielectric of the first field plate electrode and is located below the second field plate electrode, the difference between the peak value and the valley value of the electric field intensity along the surface of the device under the breakdown voltage condition is smaller, that is, the device surface has a more uniform electric field distribution, thereby reducing the peak value of the electric field intensity (i.e. Figure 3 The electric field strength corresponding to points A, B, and C in the figure).

[0054] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Semiconductor layer; a gate structure located on an upper surface of the semiconductor layer; A drift region of a second doping type extending from the upper surface of the semiconductor layer to the interior thereof, a source region and a drain region of a second doping type located in the semiconductor layer, the drain region and the drift region being located on the same side of the gate structure, and A first dielectric layer at least covers a portion of the upper surface of the drift region adjacent to the gate structure, wherein the first dielectric layer has a high dielectric constant.

2. The semiconductor device according to claim 1, wherein: The gate structure includes a gate dielectric layer and a gate conductor located on a portion of the gate dielectric layer, wherein the gate dielectric layer is further included between the first dielectric layer and the drift region.

3. The semiconductor device according to claim 1, wherein: The dielectric constant of the first dielectric layer is greater than 3.

9.

4. The semiconductor device according to claim 1, wherein: The first dielectric layer is configured as a single-layer dielectric structure or a composite dielectric structure.

5. The semiconductor device according to claim 4, wherein: The composite dielectric structure includes a second dielectric having a high dielectric constant and a third dielectric having a low dielectric constant, wherein an equivalent dielectric constant of the composite dielectric structure is greater than 0.85 times the dielectric constant of the second dielectric.

6. The semiconductor device according to claim 1, wherein: The first dielectric layer covers the upper surface of the semiconductor layer and the upper surface and side surfaces of the gate structure.

7. The semiconductor device according to claim 1, wherein: The invention also includes a first field plate located on the first dielectric layer, wherein the first dielectric layer at least covers a region below the first field plate.

8. The semiconductor device according to claim 7, wherein: It also includes at least one second field plate, the first field plate and the at least one second field plate are arranged in sequence along the direction from the gate structure to the drain region, and a field plate dielectric layer is included between adjacent first field plates and second field plates, and between two adjacent second field plates.

9. The semiconductor device according to claim 8, characterized in that: The first dielectric layer is also located below the second field plate.

10. The semiconductor device according to claim 8, wherein: The field plate dielectric layer is made of the same material as the first dielectric layer.

11. The semiconductor device according to claim 1, wherein: The thickness of the first dielectric layer is set to be greater than 20 nm and less than 500 nm.

12. The semiconductor device according to claim 1, wherein: Also includes: a well region having a first doping type and located in the semiconductor layer and extending below the gate structure; a body contact region located in the well region and adjacent to the source region; an interlayer dielectric layer covering the first dielectric layer; Forming conductive channels penetrating the interlayer dielectric layer and extending to the source region, the drain region and the gate structure respectively; as well as A metal layer is located on the conductive path.

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