A reconfigurable logic unit based on ferroelectric reconfigurable transistor design

Abstract

The present invention discloses a reconfigurable logic unit based on a ferroelectric reconfigurable transistor design. The reconfigurable transistor is used to replace the traditional CMOS transistor. The reconfigurable transistor can dynamically switch its own conduction channel type through external signals, thereby exhibiting N-type or P-type bipolarity. The ferroelectric reconfigurable transistor prepared based on the ferroelectric doping technology of mainstream silicon-based materials and with the help of the non-volatile and programmable polarization characteristics of ferroelectric materials has good reliability and low programming power consumption, and is suitable for use in the reconfigurable logic unit to reduce the number of transistors for realizing logic functions.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, relates to a logic operation device, and in particular to a reconfigurable logic unit designed based on a ferroelectric reconfigurable transistor. Background Art

[0002] As the complexity of integrated circuits increases, the use of reconfigurable logic cells is becoming more and more common in the circuit design process, especially in the ECO stage. However, cells built with traditional CMOS transistors have the problem of occupying a large space. Exploring new devices and applying them to the design of reconfigurable logic cells is crucial to further improve the integration of circuits.

[0003] Traditional CMOS transistors can only exhibit a single polarity, which greatly limits the number of transistors used when building reconfigurable logic cells. At the same time, logic cells that can only implement a single logic function such as AND, NOT, XOR, etc. have a single role in the circuit design process and are not convenient for modifying the circuit in the later stages of the design. Although circuits composed of discrete standard cells can implement multiple logic functions, they use too many transistors. Summary of the invention

[0004] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a reconfigurable logic unit designed based on ferroelectric reconfigurable transistors, so as to reduce the number of control signals and the number of transistors while realizing the logic function, and correspondingly reduce the area of ​​the logic unit circuit.

[0005] In order to reduce the number of transistors used while realizing multiple logic functions, the present invention uses reconfigurable transistors to replace traditional CMOS transistors. Reconfigurable transistors can dynamically switch their own conduction channel types through external signals, thereby showing N-type or P-type bipolarity. Based on the ferroelectric doping technology of mainstream silicon-based materials, the ferroelectric reconfigurable transistors prepared by the non-volatile and programmable polarization characteristics of ferroelectric materials have good reliability and low programming power consumption, and are suitable for reconfigurable logic units to reduce the number of transistors that realize logic functions.

[0006] In order to achieve the above-mentioned purpose, the first technical solution of the present invention is a reconfigurable logic unit designed based on a ferroelectric reconfigurable transistor, comprising two ferroelectric reconfigurable transistors, namely T1 and T2; the control polarity gates of T1 and T2 are connected to a control signal C, the control conduction gates are respectively connected to input signals B and B, the drains are respectively connected to input signals A and B, and the sources are connected to provide an output signal Q, thereby realizing a logic AND function or a logic OR function.

[0007] In one embodiment, when the control signal C is a positive pulse voltage, a logic AND function is implemented; when the control signal C is a negative pulse voltage, a logic OR function is implemented.

[0008] In order to achieve the above-mentioned purpose, the second technical solution of the present invention is a reconfigurable logic unit designed based on a ferroelectric reconfigurable transistor, including two ferroelectric reconfigurable transistors, namely T1 and T2; the control polarity gates of T1 and T2 are connected to the control signal C, the control conduction gates are respectively connected to the high level Vdd and the low level Vss, the drains are respectively connected to the input signal D1 and the input signal D0, and the sources are connected to provide the output signal Q to realize the data selection function.

[0009] In one embodiment, when the control signal C is a negative pulse voltage, the output signal Q is equal to the input signal D0; when the control signal C is a positive pulse voltage, the output signal Q is equal to the input signal D1.

[0010] In order to achieve the above-mentioned object, a third technical solution of the present invention is a reconfigurable logic unit designed based on a ferroelectric reconfigurable transistor, comprising six ferroelectric reconfigurable transistors, namely T1, T2, T3, T4, T5 and T6;

[0011] The control polarity gates of T1 and T2 are connected to the control signal C1, the control conduction gates are connected to the high level Vdd and the low level Vss respectively, the drains are connected to the input signal A and the input signal B respectively, and the sources are connected to provide the output signal Q1 to realize the data selection function;

[0012] The control polarity gates of T3 and T4 are connected to the control signal C2, the control conduction gates are connected to the high level Vdd and the low level Vss respectively, the drains are connected to the input signal A and the input signal B respectively, and the sources are connected to provide the output signal Q2 to realize the data selection function;

[0013] The control polarity gates of T5 and T6 are connected to the control signal C3, the control conduction gates are connected to the input signals B and B respectively, the drains are connected to the output signals Q1 and Q2 respectively, and the sources are connected to provide the output signal F, realizing 8 logic functions including logical AND, NAND, OR, NOR, XOR, XNOR and output high and low levels.

[0014] In one embodiment, when the control signals C1, C2, and C3 are all negative pulse voltages, a high level is output; when the control signals C1 and C2 are negative pulse voltages and C3 is a positive pulse voltage, a low level is output; when the control signals C1 and C3 are negative pulse voltages and C2 is a positive pulse voltage, a logic AND function is realized; when the control signal C1 is a negative pulse voltage and C2 and C3 are positive pulse voltages, a logic OR function is realized; when the control signal C1 is a positive pulse voltage and C2 and C3 are negative pulse voltages, a logic OR function is realized; when the control signals C1 and C3 are positive pulse voltages and C2 is a negative pulse voltage, a logic AND function is realized; when the control signals C1 and C2 are positive pulse voltages and C3 is a negative pulse voltage, a logic XOR function is realized; when the control signals C1, C2, and C3 are all positive pulse voltages, a logic XOR function is realized.

[0015] In one embodiment, the ferroelectric reconfigurable transistor is a three-gate ferroelectric reconfigurable transistor having two control polarity gates PG and one control conduction gate Gate. In a ferroelectric reconfigurable transistor, its control signal is connected to any one of the control polarity gates PG, or to both control polarity gates PG at the same time.

[0016] In one embodiment, the substrate of the ferroelectric reconfigurable transistor is lightly doped with P-type, but the reconfigurable characteristics of the transistor are independent of the substrate.

[0017] Compared with the reconfigurable logic unit constructed by traditional CMOS transistors, the present invention can realize multiple logic functions through fewer control signals and transistors, thereby further reducing the area of ​​the logic unit circuit and facilitating more convenient adjustment of the logic functions to be implemented in the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural diagram of a three-gate ferroelectric reconfigurable transistor used in constructing a reconfigurable logic unit of the present invention.

[0019] Figure 2 It is a symbolic schematic diagram of the three-gate ferroelectric reconfigurable transistor of the present invention.

[0020] Figure 3 It is a schematic diagram of the dynamic switching process of the working mode of the three-gate ferroelectric reconfigurable transistor of the present invention.

[0021] Figure 4 It is a schematic diagram of the output characteristic curve of the three-gate ferroelectric reconfigurable transistor of the present invention.

[0022] Figure 5 The invention discloses a reconfigurable logic unit circuit diagram and a truth table thereof for realizing logic AND or logic OR functions.

[0023] Figure 6 The invention discloses a reconfigurable logic unit circuit diagram and a truth table thereof for realizing a data selection function.

[0024] Figure 7 It is a reconfigurable logic unit circuit diagram for realizing 8 different logic functions of the present invention.

[0025] Figure 8 It is a traditional reconfigurable logic unit circuit diagram.

[0026] Fig. 9 It is a waveform diagram of the XOR and NAND logic functions realized by the unit circuit of the present invention. DETAILED DESCRIPTION

[0027] The embodiments of the present invention are described in detail below with reference to the accompanying drawings and examples.

[0028] The reconfigurable logic unit constructed using traditional CMOS transistors realizes different logic functions by controlling the conduction of a part of the transistors in the control unit through control signals. The reconfigurable logic unit constructed using ferroelectric reconfigurable transistors of the present invention can also control the polarity of a part of the transistors through control signals, thereby greatly reducing the number of transistors required to realize multiple logic functions, and the logic functions that can be realized are more extensive, and the reconfigurable logic unit can realize the same function with fewer transistors than the conventional one.

[0029] like Figure 1 As shown, the ferroelectric reconfigurable transistor used in the present invention to construct a reconfigurable logic unit is a three-gate ferroelectric reconfigurable transistor, which is based on the ferroelectric doping technology of mainstream silicon-based materials. With the help of the non-volatile and programmable polarization characteristics of ferroelectric materials, charge storage in semiconductor materials is realized, and a ferroelectric programmable transistor with non-volatility can be stably realized by applying a small pulse programming signal. The transistor has three gates, namely Gate and two PGs, of which the two PG gates can be used as control polarity gates to control the polarity of the transistor, and the other Gate gate is a control conduction gate, which has a function similar to that of the gate in a traditional CMOS transistor, and is used to control the conduction of the transistor. According to the signal applied to the control polarity gate, the ferroelectric reconfigurable transistor can realize different operating modes, and the reconfigurable transistor realized based on the ferroelectric doping technology is compatible with non-Feng storage computing architecture, which can further improve the energy efficiency of the device. When a positive (negative) pulse voltage is applied to its PG gate, the corresponding semiconductor surface will complete the adsorption of electrons (holes), thereby realizing N-type (P-type) doping. Then, by applying high or low levels to its Gate, the corresponding transistor can be turned on or off.

[0030] like Figure 2 and Figure 3As shown, unlike the polarity determination of traditional CMOS transistors, the reconfigurable transistor can dynamically switch between different operating modes in the circuit due to the different signals received by the control polarity gate. When a positive (negative) pulse voltage is applied to its control polarity gate, the corresponding semiconductor surface will complete the adsorption of electrons (holes), thereby realizing N-type (P-type) doping, and then applying high or low levels to its control conduction gate can turn on or off the corresponding transistor. Figure 4 This is the output characteristic curve of the reconfigurable transistor, verifying its reconfigurable characteristics.

[0031] Figure 5 The circuit diagram and truth table of a reconfigurable logic unit that uses reconfigurable transistors to implement logical AND, OR, and logical OR functions. Pass transistor logic (PTL) is a mature logic family. Using PTL to build unit circuits can reduce the number of transistors required to perform logic functions, thereby reducing the energy and area of ​​the logic computing system. Using reconfigurable transistors to build reconfigurable logic unit circuits in a PTL manner is simple and efficient, and the number of transistors used and the control signals are greatly reduced. Figure 5 Two ferroelectric reconfigurable transistors, T1 and T2, are used in the constructed unit circuit. The control signal C is connected to the control polarity gates of T1 and T2, the input signals B and B are connected to the control conduction gates of T1 and T2 respectively, the input signals A and B are connected to the drains of T1 and T2 respectively, and the sources of T1 and T2 are connected to provide the output signal Q. According to the actual needs of the circuit, different logical functions can be realized by inputting different control signals C, such as AND (A·B) or OR (A+B).

[0032] according to Figure 5 As shown in the truth table, when the control signal C is a positive pulse voltage, no matter how the input signals A and B are combined, the logic and function is realized; when the control signal C is a negative pulse voltage, no matter how the input signals A and B are combined, the logic or function is realized.

[0033] Figure 6 The circuit diagram and truth table of the reconfigurable logic unit for realizing the data selection function by using reconfigurable devices. Multiplexers are common modules of data paths and data exchange structures, and are widely used in many applications. The transistor-level two-to-one data selector built by traditional CMOS transistors requires four transistors, while the reconfigurable logic unit circuit only requires two reconfigurable transistors, which reduces the number of transistors by half, and can play a good role in more reconfigurable unit circuit designs. Figure 6The circuit in is also constructed based on transfer transistor logic. The control conduction gates of the two reconfigurable transistors T1 and T2 are connected to the high level Vdd and the low level Vss respectively, the control polarity gates are connected to the control signal C, the drains are connected to the input signals D1 and D0 respectively, and the sources are connected to provide the output signal Q. By inputting different control signals C, the data D0 or D1 output can be selected.

[0034] according to Figure 6 As shown in the truth table, when the control signal C is a negative pulse voltage, the output signal Q is equal to the input signal D0, that is, the output D0 is selected; when the control signal C is a positive pulse voltage, the output signal Q is equal to the input signal D1, that is, the output D1 is selected.

[0035] Figure 7 The circuit diagram and truth table of a reconfigurable logic unit that can realize 8 different logic functions are constructed to synthesize the proposed reconfigurable logic unit. Figure 5 The logic unit shown can only realize the conversion of two different logic functions. In order to adapt to more circuit requirements, a reconfigurable logic unit circuit that can realize 8 different logic functions is further proposed, including logic AND, NAND, OR, NOR, XOR, XOR, and output high and low levels, which are all commonly used logic functions. The circuit consists of two parts. The four ferroelectric reconfigurable transistors T1, T2, T3 and T4 in the left half are controlled by signals C1 and C2, which play the role of data selection and control logic. The two ferroelectric reconfigurable transistors T5 and T6 in the right half are controlled by signal C3, which play the role of control logic.

[0036] Specifically, the control polarity gates of T1 and T2 are connected to the control signal C1, the control conduction gates are respectively connected to the high level Vdd and the low level Vss, the drains are respectively connected to the input signal A and the input signal B, and the sources are connected to provide the output signal Q1 to realize the data selection function.

[0037] The control polarity gates of T3 and T4 are connected to the control signal C2, the control conduction gates are connected to the high level Vdd and the low level Vss respectively, the drains are connected to the input signal A and the input signal B respectively, and the sources are connected to provide the output signal Q2 to realize the data selection function.

[0038] The control polarity gates of T5 and T6 are connected to the control signal C3, the control conduction gates are connected to the input signal B and the input signal B respectively, the drains are connected to the output signal Q1 and the output signal Q2 respectively, and the sources are connected to provide the final output signal F.

[0039] Positive / negative pulse voltages are applied to C1, C2, and C3 signals respectively. There are 8 different combinations, corresponding to 8 logic functions. The function table is shown in Table 1.

[0040] Table 1

[0041]

[0042] Figure 7 and Figure 8 A comparison between a reconfigurable logic cell constructed using conventional CMOS transistors and a reconfigurable logic cell constructed using ferroelectric reconfigurable transistors is shown. Figure 8 The circuit diagram of the conventional unit is shown, and its function table is shown in Table 2 below.

[0043] Table 2

[0044]

[0045] The logic unit proposed in the present invention can also output high and low levels. The traditional unit uses five input signals C0, C1, C2, C3 and C4 to control the transformation of logic functions, but can only realize 6 different logic functions. Compared with the new logic unit, there are 2 more redundant signals. Without considering the inverter required to generate the inverting signal, the traditional unit circuit is limited by the fixed polarity of CMOS transistors, and a total of 1 P-type transistor and 15 N-type transistors are required to form a circuit, while the circuit proposed in the present invention only needs to use 6 reconfigurable transistors. Even considering the transistors required to generate the inverting signal, the number of transistors in the circuit proposed in the present invention is much smaller than that of the traditional unit circuit. The comparison between the reconfigurable logic unit of the present invention and the traditional reconfigurable logic unit is shown in Table 3 below.

[0046] Table 3

[0047] Control Signal Number of transistors Logical functions Traditional logic unit 5 16 6 Logic unit of the present invention 3 6 8

[0048] Fig. 9 The waveform diagram of the reconfigurable logic unit circuit proposed in the present invention to achieve the reconstruction of the logic function. The waveform diagram intuitively shows how the circuit can achieve the dynamic change of the logic function through different inputs of the control signal. Figure 5 From the function table, we can see that to implement XOR function, the control signals C1 and C2 input positive pulse voltage, and C3 input negative pulse voltage, so that transistors T1 to T4 realize N-type doping, and T5 and T6 realize P-type doping. function, the control signal C1 inputs a negative pulse voltage, so that the transistors T1 and T2 can be P-type doped, completing the dynamic change of the logic function, reflecting the logic reconfiguration characteristics of this unit circuit.

[0049] In summary, the present invention optimizes the problem of a large number of transistors in a reconfigurable logic unit implemented using traditional CMOS transistors, and realizes the dynamic change of different logic functions of the unit circuit by connecting the control signal to the gate of the control polarity in the reconfigurable transistor. Compared with the traditional reconfigurable logic unit, the unit circuit of the present invention uses fewer transistors and control signals to achieve the same or even more logic functions, and can replace the traditional unit in the ECO process to achieve a better effect.

Claims

1. A reconfigurable logic unit based on a ferroelectric reconfigurable transistor design, characterized in that: It includes six ferroelectric reconfigurable transistors, namely T1, T2, T3, T4, T5 and T6; The control polarity gates of T1 and T2 are connected to the control signal C1, the control conduction gates are connected to the high level Vdd and the low level Vss respectively, and the drains are connected to the input signal A and the input signal , the source is connected to provide an output signal Q1 to realize the data selection function; The control polarity gates of T3 and T4 are connected to the control signal C2, the control conduction gates are connected to the high level Vdd and the low level Vss respectively, and the drains are connected to the input signal The source of the input signal B is connected to provide the output signal Q2 to realize the data selection function; The control polarity gates of T5 and T6 are connected to the control signal C3, and the control conduction gates are connected to the input signal B and the input signal , the drain is connected to the output signal Q1 and the output signal Q2 respectively, and the source is connected to provide the output signal F, realizing 8 logic functions including logical AND, NAND, OR, NOR, XOR, XOR, and output high and low levels; When the control signals C1, C2, and C3 are all negative pulse voltages, a high level is output; when the control signals C1 and C2 are negative pulse voltages and C3 is a positive pulse voltage, a low level is output; when the control signals C1 and C3 are negative pulse voltages and C2 is a positive pulse voltage, a logic AND function is realized; when the control signal C1 is a negative pulse voltage and C2 and C3 are positive pulse voltages, a logic OR function is realized; when the control signal C1 is a positive pulse voltage and C2 and C3 are negative pulse voltages, a logic OR function is realized; when the control signals C1 and C3 are positive pulse voltages and C2 is a negative pulse voltage, a logic AND function is realized; when the control signals C1 and C2 are positive pulse voltages and C3 is a negative pulse voltage, a logic XOR function is realized; when the control signals C1, C2, and C3 are all positive pulse voltages, a logic XOR function is realized.

2. The reconfigurable logic unit based on the ferroelectric reconfigurable transistor design according to claim 1, characterized in that: The ferroelectric reconfigurable transistor is a three-gate ferroelectric reconfigurable transistor having two control polarity gates PG and one control conduction gate Gate. In a ferroelectric reconfigurable transistor, its control signal is connected to any one of the control polarity gates PG, or to both control polarity gates PG at the same time.

3. The reconfigurable logic unit based on the ferroelectric reconfigurable transistor design according to claim 2, characterized in that: The substrate of the ferroelectric reconfigurable transistor is lightly doped with P type.

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