Micro LED Chips and Their Fabrication Methods

Abstract

The application discloses a Micro LED chip and a manufacturing method thereof. The Micro LED chip comprises a driving backboard, the driving backboard being provided with a pixel driving circuit; a first reflection layer, the first reflection layer being arranged on one side of the driving backboard; a plurality of first conductive film layers arranged at intervals; a plurality of LED light emitting units, the plurality of LED light emitting units being arranged on the side of the first conductive film layer away from the driving backboard; a passivation layer, the passivation layer covering at least the sidewall of the LED light emitting unit; a second reflection layer, the second reflection layer covering at least the sidewall of the passivation layer; a first insulating layer; a second conductive film layer, the second conductive film layer being in contact with the LED light emitting unit; and a plurality of concave reflection layers, the concave reflection layers being arranged on the side of the first insulating layer away from the driving backboard, and each concave reflection layer being arranged around one LED light emitting unit. The concave reflection layer can at least reduce the light crosstalk between the LED light emitting units and converge the light divergence angle, thereby improving the light extraction efficiency of the chip.

Description

Technical Field

[0001] This invention relates to the field of displays, and more specifically, to Micro LED chips and methods for their fabrication. Background Technology

[0002] In the fabrication of high PPI (pixel density) InGaN-based RGB full-color MicroLED chips, the defect density of the InGaN quantum well structure increases with the increase of average In composition. Furthermore, micro / nano fabrication processes easily cause surface and sidewall damage to the MicroLED chip, forming surface / interface states or defect states (non-radiative recombination centers). As the chip size further decreases, the proportion of surface state density increases, leading to a more significant decrease in brightness and efficiency of MicroLEDs operating under low current injection conditions.

[0003] Based on the electro-optical conversion efficiency formula η of MicroLED chips WPE =η IQE ×η extra ×η electr , where η WPE η represents the electro-optical conversion efficiency of an LED device. IQE η represents the internal quantum efficiency of an LED device. extra η represents the light extraction efficiency of an LED device. electr η is the electrical injection efficiency of an LED device. IQE Common methods to improve this include reducing material defect density and optimizing quantum well structures. In addition, improving the light extraction efficiency (η) of LED devices is also crucial. extra ) and electro-injection efficiency (η) electr This also improves the electro-optical conversion efficiency (η). WPE The key to ).

[0004] Therefore, current Micro LED chips and their fabrication methods still need improvement. Summary of the Invention

[0005] The present invention aims to at least alleviate or resolve at least one of the aforementioned problems to some extent.

[0006] In one aspect of the present application, a Micro LED chip is provided. According to an embodiment of the present application, the Micro LED chip comprises: a driving backboard having a pixel driving circuit; a first reflective layer disposed on one side of the driving backboard; a plurality of first conductive film layers disposed at intervals, the first conductive film layers being disposed on a side of the first reflective layer away from the driving backboard; a plurality of LED light emitting units, the plurality of LED light emitting units being disposed on a side of the first conductive film layers away from the driving backboard; a passivation layer covering at least sidewalls of the LED light emitting units; a second reflective layer covering at least sidewalls of the passivation layer; a first insulating layer covering part of a surface of the second reflective layer and part of a surface of the first reflective layer; a second conductive film layer in contact with the LED light emitting units; and a plurality of concave reflective layers disposed on a side of the first insulating layer away from the driving backboard, each of the concave reflective layers being disposed around one of the LED light emitting units. Thus, the concave reflective layers of the Micro LED chip can at least reduce light crosstalk between the LED light emitting units (pixels) and converge light divergence angles, while the light extraction efficiency of the chip can be improved, thereby improving the light emitting performance of the chip.

[0007] According to an embodiment of the present application, the Micro LED chip satisfies at least one of the following conditions: the thickness of the first conductive film layers is 40-100 nm; the material of the first conductive film layers comprises ITO; the material of the first reflective layer comprises at least one of silver and aluminum; the material of the passivation layer comprises at least one of silicon nitride and silicon oxide; the thickness of the passivation layer is 20-200 nm; the second reflective layer is a Bragg reflector, the material of the second reflective layer comprises at least one of tantalum oxide, titanium oxide and silicon oxide; the material of the second conductive film layers comprises ITO; the thickness of the second conductive film layers is 20-100 nm; the material of the concave reflective layers comprises at least one of silver and aluminum; and the material of the first insulating layer comprises at least one of silicon nitride and silicon oxide. Thus, the light emitting performance of the Micro LED chip can be further improved, and the service life of the Micro LED chip can be prolonged.

[0008] In another aspect of the present application, the present application provides a method for manufacturing a Micro LED chip. According to an embodiment of the present application, the method for manufacturing a Micro LED chip comprises: providing a substrate; forming an LED light emitting unit on one side surface of the substrate, the forming of the LED light emitting unit comprising a step of forming a quantum well light emitting layer; sequentially forming a first conductive material layer and a first reflective layer on a side of the LED light emitting unit away from the substrate; binding a driving backplate on a side of the first reflective layer away from the substrate, the driving backplate having a pixel driving circuit; peeling off the substrate; etching the LED light emitting unit to form a plurality of LED light emitting units arranged at intervals; forming a passivation layer on a side of the plurality of LED light emitting units away from the driving backplate, the passivation layer covering at least sidewalls of the LED light emitting units; forming a second reflective layer covering at least sidewalls of the passivation layer; etching the first conductive material layer to form a plurality of first conductive film layers arranged at intervals; forming a first insulating layer covering part of a surface of the second reflective layer and part of a surface of the first reflective layer; etching the passivation layer and the second reflective layer to expose part of a surface of the LED light emitting unit away from the driving backplate; forming a second conductive film layer in contact with the LED light emitting unit; and forming a plurality of concave reflective layers on a side of the first insulating layer away from the driving backplate, each of the concave reflective layers being arranged around one of the LED light emitting units. Thus, the Micro LED chip with good light emitting performance can be obtained by using the method, the concave reflective layers of the Micro LED chip can at least to some extent reduce the light crosstalk between the LED light emitting units, converge the light divergence angle, and improve the light extraction efficiency of the chip, thereby improving the light emitting performance of the chip.

[0009] According to an embodiment of the present application, the substrate is a sapphire substrate, and the forming of the LED light emitting unit comprises: forming an aluminum nitride buffer layer on one side of the substrate; forming a non-doped gallium nitride film layer and at least two inorganic insulating mask layers on a side of the aluminum nitride buffer layer away from the substrate, the inorganic insulating mask layers being located in the non-doped gallium nitride film layer, and each of the inorganic insulating mask layers comprising a hollow region, the hollow regions in different inorganic insulating mask layers being coincident in orthographic projection on the substrate; epitaxially growing a heavily doped n-type gallium nitride layer on a side of the non-doped gallium nitride film layer away from the substrate, the heavily doped n-type gallium nitride layer having an electron concentration of 2×1018cm-1~1×1020cm-1; or forming a periodic n-AlGaN layer on a surface of the non-doped gallium nitride film layer away from the substrate. 18 cm -3 ~1×10 19 cm -3 ; or, forming a periodic n-AlGaN layer on a surface of the non-doped gallium nitride film layer away from the substrate. x Ga 1-xN / n-GaN superlattice structure layer, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; wherein the forming of the non-doped gallium nitride film layer and the at least two inorganic insulating mask layers comprises: epitaxially growing the non-doped gallium nitride film layer, and when growing a non-doped gallium nitride with a thickness of 0.5 μm-1 μm, ammonia and silane are introduced, and a nitride grid structure of silicon with a thickness of 10 nm-25 nm is formed at 1045℃-1065℃ for 10 s-60 s, and then the non-doped gallium nitride continues to nucleate at the opening of the nitride grid structure of silicon and is epitaxially formed on the nitride grid structure of silicon, until the thickness of the non-doped gallium nitride film layer is 3 μm-5 μm; or, epitaxially growing the non-doped gallium nitride film layer, and when growing a non-doped gallium nitride with a thickness of 0.5 μm-1 μm, a nitride film layer or an oxide film layer of silicon with a thickness of 10 nm-25 nm is formed on the surface of the non-doped gallium nitride away from the substrate, and the nitride film layer or the oxide film layer of silicon is etched to form a grid structure or a plurality of spaced strip structures, and the longitudinal section of the strip structure is rectangular or trapezoidal, until the thickness of the non-doped gallium nitride film layer is 3 μm-5 μm. In this way, the defect density in the non-doped gallium nitride material can be reduced by inserting a plurality of inorganic insulating mask layers in the non-doped gallium nitride film layer, so as to facilitate the improvement of the internal quantum efficiency of the LED device, and further facilitate the improvement of the electro-optical conversion efficiency of the LED device.

[0010] According to the embodiment of the present application, the substrate is peeled off by using a laser peeling process, and optionally, the pulse laser wavelength is 355 nm, 266 nm or 248 nm. In the laser peeling process, the inorganic insulating mask layer can absorb part of the laser energy, so as to alleviate the damage of the interface high temperature to the quantum well structure, and further improve the light emitting performance of the chip; the laser peeling can effectively remove the sapphire substrate, and the sapphire substrate is peeled off by using the laser with the pulse laser wavelength of 355 nm, 266 nm or 248 nm, and the peeling effect is better.

[0011] According to the embodiment of the present application, the substrate is a silicon substrate or a silicon carbide substrate, and the forming of the LED light emitting unit comprises: forming an aluminum nitride buffer layer on one side of the substrate; forming a gradually changing Al p Ga 1-p N layer on the surface of the aluminum nitride buffer layer away from the substrate, and along the direction away from the aluminum nitride buffer layer, the value of p linearly changes from 20%-30% to 0; and forming a gradually changing Al p Ga 1-pN layer far away from the side of the substrate forms a non-doped gallium nitride film layer and at least two inorganic insulating mask layers, the inorganic insulating mask layers are located in the non-doped gallium nitride film layer, and each of the inorganic insulating mask layers includes a hollow area, and the hollow areas in different inorganic mask layers are coincident in orthographic projection on the substrate; a heavily doped n-type gallium nitride layer is epitaxially grown on the side of the non-doped gallium nitride film layer far away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; or, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is formed on the surface of the non-doped gallium nitride film layer far away from the substrate, 0.02≤x≤0.05, and the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; wherein forming the non-doped gallium nitride film layer and at least two inorganic insulating mask layers includes: epitaxially growing the non-doped gallium nitride film layer, when growing non-doped gallium nitride with a thickness of 0.5μm~1μm, ammonia and silane are introduced, and a grid-shaped structure of silicon nitride with a thickness of 10nm~25nm is formed at 1045℃~1065℃ for 10s~60s, and then non-doped gallium nitride continues to nucleate at the opening of the grid-shaped structure of silicon nitride and is epitaxially formed on the grid-shaped structure of silicon nitride until the thickness of the non-doped gallium nitride film layer is 3μm~5μm; or, epitaxially growing the non-doped gallium nitride film layer, when growing non-doped gallium nitride with a thickness of 0.5μm~1μm, a silicon nitride film layer or a silicon oxide film layer with a thickness of 10nm~25nm is formed on the surface of the non-doped gallium nitride far away from the substrate, and the silicon nitride film layer or the silicon oxide film layer is etched to form a grid-shaped structure or a plurality of spaced strip-shaped structures, the longitudinal section of the strip-shaped structure is rectangular or trapezoidal, until the thickness of the non-doped gallium nitride film layer is 3μm~5μm. In this way, the gradually changing Al p Ga 1-p N layer is arranged between the aluminum nitride buffer layer and the heavily doped gallium nitride layer or the periodic n-Al x Ga 1- xThe n-Al Ga N / n-GaN superlattice structure can play a good transition role between the n-GaN superlattice structures; the plurality of inorganic insulating mask layers inserted in the undoped gallium nitride film layer can at least reduce the defect density in the undoped gallium nitride material to some extent, thereby being favorable to improving the internal quantum efficiency of the LED device, and further being favorable to improving the electro-optical conversion efficiency of the LED device.

[0012] According to an embodiment of the present application, the substrate is a silicon carbide substrate, and forming the LED light-emitting unit comprises: forming an n-type doped AlGaN buffer layer on one side of the substrate; epitaxially growing a heavily doped n-type gallium nitride layer away from the surface of the substrate on the n-type doped AlGaN buffer layer, the electron concentration of the heavily doped n-type gallium nitride layer being 2×10 18 cm -3 ~1×10 19 cm -3 ; or, forming a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer away from the surface of the substrate on the n-type doped AlGaN buffer layer, 0.02≤x≤0.05, the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer being 2×10 18 cm -3 ~1×10 19 cm -3 ; or, epitaxially growing a heavily doped n-type gallium nitride layer and at least two inorganic insulating mask layers away from the one side of the substrate on the n-type doped AlGaN buffer layer, the electron concentration of the heavily doped n-type gallium nitride layer being 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layers being located in the heavily doped n-type gallium nitride layer, and each of the inorganic insulating mask layers comprising a hollow region, the orthographic projections of the hollow regions in different inorganic insulating mask layers on the substrate being coincident; or, forming a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer and at least two inorganic insulating mask layers away from the one side of the substrate on the n-type doped AlGaN buffer layer, 0.02≤x≤0.05, the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer being 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layers being located in the periodic n-Al x Ga1-x The inorganic insulating mask layers are located in the heavily doped n-type gallium nitride layer, and each of the inorganic insulating mask layers comprises a hollow region, and the hollow regions in different inorganic insulating mask layers are coincident in orthographic projection on the substrate. Thus, the defect density in the material is reduced, the internal quantum efficiency of the LED device is improved, and the electro-optical conversion efficiency of the LED device is improved.

[0013] According to an embodiment of the present application, the substrate is a gallium nitride substrate, and forming the LED light-emitting unit comprises: epitaxially growing a heavily doped n-type gallium nitride layer on one side surface of the substrate, the electron concentration of the heavily doped n-type gallium nitride layer being 2×10 18 cm -3 ~1×10 19 cm -3 ; or forming a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer on one side surface of the substrate, 0.02≤x≤0.05, and the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer being 2×10 18 cm -3 ~1×10 19 cm -3 ; or forming a heavily doped n-type gallium nitride layer and at least two inorganic insulating mask layers on one side of the substrate, the electron concentration of the heavily doped n-type gallium nitride layer being 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layers being located in the heavily doped n-type gallium nitride layer, and each of the inorganic insulating mask layers comprising a hollow region, and the hollow regions in different inorganic insulating mask layers being coincident in orthographic projection on the substrate; or forming a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer and at least two inorganic insulating mask layers on one side of the substrate, 0.02≤x≤0.05, and the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer being 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layers being located in the periodic n-Al x Ga 1-xIn the N / n-GaN superlattice structure layer, each of the inorganic insulating mask layers includes a hollow region, and the hollow regions in different inorganic insulating mask layers have their orthogonal projections onto the substrate coincide. This is beneficial for reducing the defect density within the material, thereby improving the internal quantum efficiency of the LED device, and further improving the electro-optical conversion efficiency of the LED device.

[0014] According to an embodiment of the present invention, forming the LED light-emitting unit further includes: in the heavily doped n-type gallium nitride layer or the periodic n-Al layer x Ga 1-x A lightly doped n-type gallium nitride layer is formed on the side of the N / n-GaN superlattice structure layer away from the substrate, and the electron concentration of the lightly doped n-type gallium nitride layer is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 A first barrier layer is formed on the side of the lightly doped n-type gallium nitride layer away from the substrate; 3 to 5 undoped In layers are sequentially grown on the side of the first barrier layer away from the substrate. y Ga 1-y N / GaN quantum well structure and 3-5 periods of undoped In z Ga 1-z N / GaN quantum well structure, wherein 0.01≤y≤0.03, 0.03≤z≤0.05; in the undoped In z Ga 1-z On the side of the N / GaN quantum well structure away from the substrate, a blue quantum well emitting layer, a green quantum well emitting layer, and a red quantum well emitting layer are grown. On the side of the quantum well emitting layer away from the substrate, an undoped gallium nitride protective layer, an electron blocking layer, a hole injection layer, and an ohmic contact layer are sequentially formed. This is beneficial for further improving the luminous performance of the LED device and providing a better user experience.

[0015] According to an embodiment of the present invention, forming the blue quantum well light-emitting layer includes: in the undoped In... z Ga 1-z On the side of the N / GaN quantum well structure away from the substrate, a first undoped GaN layer and an In layer are sequentially formed. a Ga 1-a N-well layer, second undoped GaN layer, In b Ga 1-b An N-type barrier layer, wherein 0.18 ≤ a ≤ 0.21, 0.01 ≤ b ≤ 0.05; forming the green quantum well emitting layer includes: in the undoped In... z Ga 1-z One to two cycles of In are grown on the side of the N / GaN quantum well structure away from the substrate. cGa 1-c N / n-type GaN quantum well structure and 2-3 periods of In d Ga 1-d N / n-type GaN quantum well structure, growing In c Ga 1- c N / n-type GaN quantum well structure includes sequentially forming a third undoped GaN layer, In c Ga 1-c N potential well layer, a fourth undoped GaN layer and a first n-type GaN barrier layer, growing In d Ga 1-d N / n-type GaN quantum well structure includes sequentially forming a fifth undoped GaN layer, In d Ga 1-d N potential well layer, a sixth undoped GaN layer, a second n-type GaN barrier layer, wherein 0.24≤c≤0.25, 0.25≤d≤0.28; forming the red quantum well light emitting layer includes: growing In z Ga 1-z N / GaN quantum well structure away from the side of the substrate sequentially forming a seventh undoped GaN layer, In e Ga 1-e N potential well layer, an eighth undoped GaN layer, In f Ga 1-f N barrier layer, a ninth undoped GaN layer, In g Ga 1-g N potential well layer, a tenth undoped GaN layer, a p-type doped GaN barrier layer, Al h Ga 1-h N layer, wherein 0.18≤e≤0.21, 0.01≤f≤0.05, 0.35≤g≤0.38, 0.10≤h≤0.30. Thus, the blue quantum well light emitting layer, the green quantum well light emitting layer and the red quantum well light emitting layer all have good light emitting performance and better stability, which is conducive to further improving the light emitting performance of the chip and further prolonging the service life of the chip.

[0016] According to the embodiment of the application, the method for manufacturing the Micro LED satisfies at least one of the following conditions: the thickness of the aluminum nitride buffer layer is 10-50 nm; the temperature for forming the undoped gallium nitride film layer is 1045-1065 DEG C; the temperature for epitaxially growing the heavily doped n-type gallium nitride layer is 1040-1060 DEG C, and silane is an n-type dopant; the periodical n-Al x Ga 1-x N / n-GaN superlattice structure layer, in each period, n-Al x Ga 1-xThe thickness of N is 2-3 nm, and the thickness of n-GaN is 5-10 nm; the periodical n-Al x Ga 1-x The film forming temperature of the N / n-GaN superlattice structure layer is 1060-1080℃; the temperature for forming the lightly doped n-type gallium nitride layer is 1040-1060℃; the thickness of the lightly doped n-type gallium nitride layer is 0.3-0.5 μm; the thickness of the first barrier layer is 15-30 nm; the non-doped In y Ga 1-y In each period of the In y Ga 1-y The thickness of N is 2.5-3.5 nm, and the thickness of GaN is 5-15 nm; the thickness of the first non-doped GaN layer and the thickness of the second non-doped GaN layer are each independently 1-5 nm; the In z Ga 1-z In each period of the In z Ga 1-z The thickness of N is 2.5-3.5 nm, and the thickness of GaN is 5-15 nm; the thickness of the first non-doped GaN layer and the thickness of the second non-doped GaN layer are each independently 1-5 nm; the In a Ga 1-a The thickness of the In b Ga 1-b The thickness of the In c Ga 1-c The thickness of the In d Ga 1-d The thickness of the In e Ga 1-e The thickness of the In g Ga 1-g The thickness of the In f Ga 1-f The thickness of the In h Ga 1-hThe thickness of the N layer is 1nm-2nm; the thickness of the non-doped gallium nitride protective layer is 15nm-30nm; the thickness of the electron blocking layer is 60nm-70nm, and the material of the electron blocking layer is p-type doped Al q Ga 1-q N, in the direction away from the substrate, the value of q linearly changes from 20%-30% to 0; the hole injection layer is a p-Al i Ga 1-i N / p-GaN superlattice structure, the hole concentration of the hole injection layer is 1.5x10 18 cm -3 -3.5x10 18 cm -3 , the thickness of p-Al i Ga 1-i N in each period is 2.5nm-3.5nm, the thickness of p-GaN is 5nm-8nm, and 0.10≤i≤0.20; the material of the ohmic contact layer is heavily doped p-GaN, and the thickness of the ohmic contact layer is 20nm-40nm. It is favorable to further improve the overall performance of the Micro LED chip prepared. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A structure schematic diagram of a Micro LED chip according to one embodiment of the present application is shown;

[0019] Figure 2 A structure schematic diagram of a Micro LED chip according to another embodiment of the present application is shown;

[0020] Figure 3 A partial flow schematic diagram of manufacturing a Micro LED chip according to one embodiment of the present application is shown;

[0021] Figure 4 A structure schematic diagram of an inorganic insulating mask layer according to one embodiment of the present application is shown;

[0022] Figure 5 A structure schematic diagram of an inorganic insulating mask layer according to one embodiment of the present application is shown;

[0023] Figure 6 A structure schematic diagram of a substrate, an aluminum nitride buffer layer, a non-doped gallium nitride layer and an inorganic insulating mask layer in one embodiment of the present application is shown;

[0024] Figure 7Fig. 2 shows a schematic diagram of a structure of a substrate, an aluminum nitride buffer layer, an undoped gallium nitride layer, and an inorganic insulating mask layer according to another embodiment of the present application;

[0025] Figure 8 Fig. 3 shows a schematic diagram of a partial flow of fabricating a Micro LED chip according to an embodiment of the present application;

[0026] Figure 9 Fig. 4 shows a schematic diagram of a partial flow of fabricating a Micro LED chip according to an embodiment of the present application;

[0027] Figure 10 Fig. 5 shows a schematic diagram of a partial flow of fabricating a Micro LED chip according to an embodiment of the present application;

[0028] Figure 11 Fig. 6 shows a schematic diagram of a partial flow of fabricating a Micro LED chip according to an embodiment of the present application;

[0029] Figure 12 Fig. 7 shows a schematic diagram of a partial flow of fabricating a Micro LED chip according to an embodiment of the present application;

[0030] Figure 13 Fig. 8 shows a schematic diagram of a partial flow of fabricating a Micro LED chip according to an embodiment of the present application;

[0031] Figure 14 Fig. 9 shows a schematic diagram of a partial flow of fabricating a Micro LED chip according to an embodiment of the present application;

[0032] Figure 15 Fig. 10 shows a schematic diagram of a partial structure during fabricating a Micro LED chip according to an embodiment of the present application;

[0033] Figure 16 Fig. 11 shows a schematic diagram of a partial structure during fabricating a Micro LED chip according to an embodiment of the present application;

[0034] Figure 17 Fig. 12 shows a schematic diagram of a partial structure during fabricating a Micro LED chip according to an embodiment of the present application;

[0035] Figure 18 Fig. 13 shows a schematic diagram of a partial flow of fabricating a Micro LED chip according to an embodiment of the present application.

[0036] BRIEF DESCRIPTION OF THE DRAWINGS

[0037] 1: first insulating layer; 2: second insulating layer; 3: substrate; 4: aluminum nitride buffer layer; 4': n-doped AlGaN buffer layer; 5: undoped gallium nitride layer; 6: inorganic insulating mask layer; 7: dislocation; 8: graded Al p Ga 1-p N layer; 10: driving backplate; 20: first reflective layer; 30: first conductive material layer; 31: first conductive film layer; 40: LED light emitting unit; 41: heavily doped n-type gallium nitride layer; 41': periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer; 42: lightly doped n-type gallium nitride layer; 43: first barrier layer; 44: quantum well light emitting layer; 45: undoped gallium nitride protective layer; 46: electron blocking layer; 47: hole injection layer; 48: ohmic contact layer; 50: passivation layer; 60: second reflective layer; 70: second conductive film layer; 80: n-type ohmic contact electrode; 90: concave reflective layer. DETAILED DESCRIPTION

[0038] Embodiments of the present application are described in detail below with reference to the attached drawings, which are presented as examples and are not limiting in nature. The embodiments described below are examples only and are not to be construed as limiting the present application.

[0039] In one aspect of the present application, a Micro LED chip is provided. According to embodiments of the present application, referring to Figure 1 and Figure 2, the Micro LED chip can include: a driving backboard 10, the driving backboard 10 has a pixel driving circuit; a first reflective layer 20, the first reflective layer 20 is arranged on one side of the driving backboard 10; a plurality of first conductive film layers 31 arranged at intervals, the first conductive film layers 31 are arranged on the side of the first reflective layer 20 away from the driving backboard 10; a plurality of LED light emitting units, the plurality of LED light emitting units are arranged on the side of the first conductive film layer 31 away from the driving backboard 10; a passivation layer 50, the passivation layer 50 covers at least the sidewall of the LED light emitting unit; a second reflective layer 60, the second reflective layer 60 covers at least the sidewall of the passivation layer 50; a first insulating layer 1, the first insulating layer 1 covers part of the surface of the second reflective layer 60 and part of the surface of the first reflective layer 20; a second conductive film layer 70, the second conductive film layer 70 is in contact with the LED light emitting unit; and a plurality of concave reflective layers 90, the concave reflective layers 90 are arranged on the side of the first insulating layer 1 away from the driving backboard 10, and each concave reflective layer 90 is arranged around one LED light emitting unit. Therefore, the concave reflective layer in the Micro LED chip has a good reflection effect, can reduce the light crosstalk between the LED light emitting units (pixels) and converge the light divergence angle, and can at least improve the light extraction efficiency of the chip to some extent, thereby improving the light emitting performance of the chip.

[0040] According to some specific embodiments of the present application, the concave reflective layer 90 can be a three-dimensional bowl structure as shown in Figure 1 and Figure 2 , and the opening of the concave reflective layer 90 gradually increases in the direction away from the driving backboard 10.

[0041] According to some embodiments of the present application, referring to Figure 1 and Figure 2 , the passivation layer 50 is arranged on the side of the LED light emitting unit 40 away from the driving backboard 10, and the passivation layer 50 can cover the sidewall of the LED light emitting unit, at least part of the surface of the first conductive film layer 31 away from the driving backboard 10, and part of the surface of the LED light emitting unit 40 away from the driving backboard 10; the second reflective layer 60 is arranged on the side of the passivation layer 50 away from the driving backboard 10, and the second reflective layer 60 can cover at least part of the surface of the passivation layer 50 away from the driving backboard 10; and the second conductive film layer 70 can cover at least part of the surface of the first insulating layer 1 away from the driving backboard 10 and at least part of the surface of the second reflective layer 60 away from the driving backboard 10.

[0042] According to some specific embodiments of the present application, referring to Figure 1 and Figure 2The Micro LED chip can further include a plurality of n-type ohmic contact electrodes 80 arranged at intervals, the n-type ohmic contact electrodes 80 can be arranged on the side of the second conductive film layer 70 away from the driving backboard 10, each n-type ohmic contact electrode 80 is arranged around one LED light emitting unit 40; the concave reflecting layer 90 can be arranged on the side of the n-type ohmic contact electrode 80 away from the driving backboard 10, and the concave reflecting layer 90 can be in contact with the n-type ohmic contact electrode 80.

[0043] According to some embodiments of the present application, referring to Figure 1 and Figure 2 , the Micro LED chip can further include a second insulating layer 2, the second insulating layer 2 can be arranged on the side of the second conductive film layer 60 away from the driving backboard 10, the second insulating layer 2 covers at least part of the surface of the second conductive film layer 60, at least part of the surface of the n-type ohmic contact electrode 80 and at least part of the surface of the concave reflecting layer 90. Thus, the second insulating layer can realize electrical insulation between the LED light emitting unit mesa, thereby facilitating further prolonging the service life of the chip.

[0044] It should be noted that Figure 1 and Figure 2 show two LED light emitting units 40, two n-type ohmic contact electrodes 80 and two concave reflecting layers 90, which are not used to limit the present application, and those skilled in the art can set the number of LED light emitting units according to actual needs and set the number of n-type ohmic contact electrodes and concave reflecting layers accordingly.

[0045] According to some embodiments of the present application, referring to Figure 2 , the Micro LED chip can be based on InGaN (indium gallium nitride) material, and the LED light emitting unit 40 can include a heavily doped n-type gallium nitride layer 41 or a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41', a lightly doped n-type gallium nitride layer 42, a first barrier layer 43, a quantum well light emitting layer 44, an undoped gallium nitride protective layer 45, an electron blocking layer 46, a hole injection layer 47 and an ohmic contact layer 48, and the quantum well light emitting layer can include a red quantum well light emitting layer, a green quantum well light emitting layer and a blue quantum well light emitting layer.

[0046] According to some other embodiments of the present application, the Micro LED chip can also be based on AlGaInP (aluminum gallium indium phosphide) material, and the quantum well light emitting layer therein is a red quantum well light emitting layer.

[0047] According to some embodiments of the present application, the thickness of the first conductive film layer 31 can be 40-100 nm, for example, the thickness of the first conductive film layer 31 can be 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, thereby the first conductive film layer has a thinner thickness, better light transmittance (≥85%) and smaller resistance, and the first conductive film layer has good conductivity.

[0048] According to some embodiments of the present application, the material of the first conductive film layer 31 can include ITO (indium tin oxide), for example, the first conductive film layer can be composed of ITO, thereby the first conductive film layer has good conductivity, and the LED light emitting unit can emit light by applying voltage on it.

[0049] According to some embodiments of the present application, the material of the first reflective layer 20 can include at least one of silver and aluminum, thereby the first reflective layer has better reflection, and can at least improve the light extraction efficiency of the chip to some extent, which is conducive to improving the light emitting effect of the chip. According to some specific embodiments of the present application, the material of the first reflective layer 20 can be silver. According to other specific embodiments of the present application, the material of the first reflective layer 20 can be aluminum.

[0050] According to some embodiments of the present application, the material of the passivation layer 50 can include at least one of silicon nitride and silicon oxide, thereby the passivation layer has good insulation, which is conducive to improving the overall performance of the chip.

[0051] According to some embodiments of the present application, the thickness of the passivation layer 50 can be 20-200 nm, for example, the thickness of the passivation layer 50 can be 20 nm, 50 nm, 80 nm, 100 nm, 150 nm, 200 nm, etc.

[0052] According to some embodiments of the present application, the second reflective layer 60 can be a Bragg reflector (DBR), and the material of the second reflective layer 60 can include at least one of tantalum oxide, titanium oxide and silicon oxide, thereby the second reflective layer can further improve the light extraction efficiency of the chip, and further improve the light emitting effect of the chip.

[0053] According to some embodiments of the present application, the material of the second conductive film layer 70 can include ITO, thereby the second conductive film layer has good conductivity, which is conducive to improving the overall performance of the chip.

[0054] According to some embodiments of the present application, the thickness of the second conductive film layer 70 can be 20-100 nm, for example, the thickness of the second conductive film layer 70 can be 20 nm, 40 nm, 50 nm, 80 nm, 100 nm, etc., thereby the second conductive film layer has higher light transmittance and smaller resistance, which is conducive to further improving the overall performance of the chip.

[0055] According to some embodiments of the present application, the material of the n-type ohmic contact electrode 80 can include at least one of metal titanium, metal aluminum and metal gold, thereby the n-type ohmic contact electrode has excellent conductivity, which is conducive to further improving the overall performance of the chip. According to some specific embodiments of the present application, the n-type ohmic contact electrode can include a plurality of metal layers, for example, can include a titanium layer, an aluminum layer, a titanium layer and a gold layer which are sequentially stacked.

[0056] According to some embodiments of the present application, the material of the concave reflecting layer 90 can include at least one of metal silver and metal aluminum, thereby the concave reflecting layer formed by the above-mentioned material has better reflecting effect, which can reduce the light crosstalk between the light emitting units, converge the light divergence angle, and at the same time, can improve the light extraction efficiency of the chip.

[0057] According to some embodiments of the present application, the material of the first insulating layer 1 and the material of the second insulating layer 2 each independently include at least one of a nitride of silicon and an oxide of silicon, that is, the material of the first insulating layer 1 can include at least one of a nitride of silicon and an oxide of silicon, and the material of the second insulating layer 2 can include at least one of a nitride of silicon and an oxide of silicon. Thus, the first insulating layer and / or the second insulating layer has good insulating property, which can well realize electrical insulation.

[0058] In another aspect of the present application, the present application provides a method for manufacturing a Micro LED chip. According to an embodiment of the present application, the method for manufacturing a Micro LED chip can include the following steps:

[0059] S1: providing a substrate.

[0060] The substrate can be a sapphire substrate, a silicon substrate, a silicon carbide substrate or a gallium nitride substrate according to some embodiments of the present application.

[0061] S2: forming an LED light emitting unit on one side surface of the substrate.

[0062] The LED light emitting unit is formed on one side surface of the substrate, wherein the step of forming the LED light emitting unit can include the step of forming a quantum well light emitting layer, which will be described in detail below in combination with the substrate of specific material.

[0063] According to some embodiments of the present application, referenceFigure 3 The substrate 3 is a sapphire substrate. The LED light-emitting unit is formed by: forming an aluminum nitride buffer layer 4 on one side of the substrate 3; forming an undoped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 on the side of the aluminum nitride buffer layer 4 away from the substrate 3, wherein the inorganic insulating mask layers 6 are located within the undoped gallium nitride film layer 5, and each inorganic insulating mask layer includes a hollow region (the hollow region can continue to grow undoped gallium nitride), and the hollow regions in different inorganic insulating mask layers 6 have their orthogonal projections on the substrate coincide; and epitaxially growing a heavily doped n-type gallium nitride layer 41 on the side of the undoped gallium nitride film layer 5 away from the substrate 3, wherein the electron concentration of the heavily doped n-type gallium nitride layer 41 can be 2 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 Alternatively, periodic n-Al formations can be formed on the surface of the undoped gallium nitride film 5 away from the substrate 3. x Ga 1-x N / n-GaN superlattice structure layer 41', where 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice layer 41' can be 2 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 Forming at least two inorganic insulating mask layers can effectively block the upward extension of dislocations and reduce the density of penetrating dislocations, thereby improving the internal quantum efficiency of LED devices. The hollow areas in different inorganic insulating mask layers 6 have the same orthogonal projection on the substrate. During the fabrication of inorganic insulating mask layers, different inorganic insulating mask layers can use the same mask, thereby saving the cost of the mask and reducing the chip manufacturing cost.

[0064] When substrate 3 is a sapphire substrate, the lattice mismatch between the aluminum nitride buffer layer and the sapphire substrate is small (the lattice mismatch is about 13%), which is beneficial to reducing the penetration dislocation density of the undoped gallium nitride film layer grown subsequently, thereby improving the overall performance of the chip.

[0065] According to an embodiment of the present invention, the number of inorganic insulating mask layers 6 can be two (e.g., Figure 3 (as shown), 3-layer, 4-layer, etc.

[0066] According to some embodiments of the present invention, the thickness of the aluminum nitride buffer layer 4 can be 10 nm to 50 nm, for example, the thickness of the aluminum nitride buffer layer 4 can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, etc.

[0067] According to some embodiments of the present invention, when the substrate 3 is a sapphire substrate, forming an undoped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 may include: epitaxially growing an undoped gallium nitride film layer, introducing ammonia and silane during the growth of undoped gallium nitride with a thickness of 0.5 μm to 1 μm, reacting at 1045°C to 1065°C for 10 s to 60 s, forming a silicon nitride mesh structure with a thickness of 10 nm to 25 nm, wherein the mesh structure inorganic insulating mask layer 6 is as follows: Figure 4 As shown, undoped gallium nitride can continue to nucleate at the openings (cutout structure 6') of the silicon nitride grid structure and be epitaxially deposited on the silicon nitride grid structure until the thickness of the undoped gallium nitride film 5 is 3μm to 5μm. The reaction time after introducing ammonia and silane is relatively short, so the silicon nitride will not completely form a film, but a silicon nitride grid structure can be formed. Subsequently, undoped gallium nitride can continue to nucleate at the openings and be epitaxially deposited on the grid structure film (ELOG growth mode, i.e., epitaxial lateral overgrowth mode); the mask layer can prevent dislocations from extending upwards. According to some specific embodiments of the present invention, an MOCVD (metal-organic chemical vapor deposition) device can be used to epitaxially grow the undoped gallium nitride film layer, and the silicon nitride grid structure can be grown in stages in situ. The temperature for forming the undoped gallium nitride film layer 5 can be 1045℃ to 1065℃.

[0068] According to other embodiments of the present invention, when the substrate 3 is a sapphire substrate, forming an undoped gallium nitride film 5 and at least two inorganic insulating mask layers 6 may include: epitaxially growing an undoped gallium nitride film; when growing undoped gallium nitride with a thickness of 0.5 μm to 1 μm, forming a silicon nitride film or a silicon oxide film with a thickness of 10 nm to 25 nm on the surface of the undoped gallium nitride away from the substrate 3; the silicon nitride film or the silicon oxide film being a monolithic structure; and etching the silicon nitride film or the silicon oxide film to form a mesh structure (e.g., Figure 4 (as shown) or multiple spaced strip structures (such as) Figure 5 to Figure 7 As shown), the longitudinal section of the strip structure is rectangular (e.g. Figure 5 and Figure 7 (as shown) or trapezoidal (such as) Figure 6GaN layer 5 is 3-5 μm. In this process, the non-doped gallium nitride film layer can be epitaxially grown by using a MOCVD (metal-organic chemical vapor deposition) device, and the inorganic insulating mask layer can be epitaxially grown by using a PECVD (plasma enhanced chemical vapor deposition) device. A 0.5-1 μm non-doped gallium nitride layer is epitaxially grown, the sample is taken out of the reaction chamber, a 10-25 nm thick silicon nitride film layer or a silicon oxide film layer is grown by PECVD, and the silicon nitride film layer or the silicon oxide film layer is etched into a grid structure or a plurality of spaced strip structures by photolithography and ICP-RIE (inductively coupled plasma etching) processes. The above steps are repeated until the thickness of the non-doped gallium nitride film layer reaches 3-5 μm. This method can effectively reduce the dislocation density in the non-doped gallium nitride film layer, and the residual dislocation distribution can be followed. In the subsequent pixel forming process, the pixels can be distributed in the low-dislocation or no-dislocation region, which is beneficial to the arrangement of small-size pixels. Referring to Figure 6 and Figure 7 , the dislocation density of the non-doped gallium nitride film layer at the position where the strip structure is arranged is low or even free of dislocations 7. The pixels can be formed in the corresponding region in the subsequent process, thereby improving the internal quantum efficiency and light emitting performance of the LED device.

[0069] According to some embodiments of the present application, the substrate 3 can be a silicon substrate or a silicon carbide substrate. Referring to Figure 8 , the forming of the LED light emitting unit can include: forming an aluminum nitride buffer layer 4 on one side of the substrate 3; forming a graded Al p Ga 1-p N layer 8 away from the surface of the aluminum nitride buffer layer 4, the value of p linearly changes from 20-30% to 0 in the direction away from the aluminum nitride buffer layer 4; forming a non-doped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 on the side of the graded Al p GaN 1-p layer 8 away from the substrate 3, the inorganic insulating mask layers 6 are located in the non-doped gallium nitride film layer 5, and each inorganic insulating mask layer 6 includes a hollow area, and the hollow areas in different inorganic insulating mask layers 6 are in superposition in the orthographic projection on the substrate 3; epitaxially growing a heavily doped n-type gallium nitride layer 41 on the side of the non-doped gallium nitride film layer 5 away from the substrate 3, and the electron concentration of the heavily doped n-type gallium nitride layer 41 is 2×10 18 cm -3 -1×10 19 cm -3 ; or, forming a periodic n-Al x Ga 1- x N / n-GaN superlattice structure layer 41' on the surface of the non-doped gallium nitride film layer 5 away from the substrate 3, 0.02≤x≤0.05, and the periodic n-Alx Ga 1-x The electron concentration of the N / n-GaN superlattice layer 41' is 2 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 Set gradient AI p Ga 1-p The N-layer enables the transition from aluminum nitride buffer layer to gallium nitride, which is beneficial to improving chip performance; the inorganic insulating mask layer can effectively reduce dislocation density and prevent dislocations from extending upward.

[0070] According to some specific embodiments of the present invention, when the substrate 3 can be a silicon substrate or a silicon carbide substrate, forming an undoped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 may include: epitaxially growing an undoped gallium nitride film layer, introducing ammonia and silane when growing undoped gallium nitride with a thickness of 0.5 μm to 1 μm, reacting at 1045°C to 1065°C for 10 s to 60 s, forming a silicon nitride mesh structure with a thickness of 10 nm to 25 nm, and subsequently nucleating undoped gallium nitride at the openings (cutout areas) of the silicon nitride mesh structure and epitaxially forming a film on the silicon nitride mesh structure until the thickness of the undoped gallium nitride film layer is 3 μm to 5 μm. In this process, an undoped gallium nitride film can be epitaxially grown using MOCVD (metal-organic chemical vapor deposition) equipment, and a silicon nitride mesh structure can be grown in situ in stages. The temperature for forming the undoped gallium nitride film 5 can be 1045℃~1065℃, which is the same as the temperature for forming the silicon nitride mesh structure.

[0071] According to other specific embodiments of the present invention, when the substrate 3 can be a silicon substrate or a silicon carbide substrate, forming an undoped gallium nitride film layer 5 and at least two inorganic insulating mask layers 6 may include: epitaxially growing an undoped gallium nitride film layer; when growing undoped gallium nitride with a thickness of 0.5 μm to 1 μm, forming a silicon nitride film layer or a silicon oxide film layer with a thickness of 10 nm to 25 nm on the surface of the undoped gallium nitride away from the substrate; the silicon nitride film layer or the silicon oxide film layer is a monolithic structure; etching the silicon nitride film layer or the silicon oxide film layer to form a mesh structure (e.g., Figure 4 (as shown) or multiple spaced strip structures (such as) Figure 8 As shown), the longitudinal section of the strip structure is rectangular (e.g. Figure 8(As shown) or trapezoidal, until the thickness of the undoped gallium nitride film is 3μm to 5μm. In this process, an undoped gallium nitride film can be epitaxially grown using MOCVD (metal-organic chemical vapor deposition) equipment, and an inorganic insulating mask layer can be epitaxially grown using PECVD (plasma-enhanced chemical vapor deposition) equipment. After epitaxially growing 0.5μm to 1μm of undoped gallium nitride, the sample is removed from the reaction chamber, and a silicon nitride film or silicon oxide film with a thickness of 10nm to 25nm is grown using PECVD. The silicon nitride film or silicon oxide film is etched into a grid structure or multiple spaced strip structures using photolithography and ICP-RIE (inductively coupled plasma etching) processes. The above steps are repeated until the thickness of the undoped gallium nitride film reaches 3μm to 5μm. This method can effectively reduce the dislocation density in undoped gallium nitride films. The distribution pattern of the remaining dislocations can be followed, and in the subsequent pixel formation process, the pixels can be distributed in low-dislocation or dislocation-free regions.

[0072] According to some embodiments of the present invention, the substrate 3 may be a silicon carbide substrate, see reference. Figure 9 The formation of an LED light-emitting unit may include: forming an n-type doped AlGaN buffer layer 4' on one side of the substrate 3; and epitaxially growing a heavily doped n-type gallium nitride layer 41 on the surface of the n-type doped AlGaN buffer layer 4' away from the substrate 3, wherein the electron concentration of the heavily doped n-type gallium nitride layer 41 may be 2 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 Alternatively, periodic n-Al atoms can be formed on the surface of the n-type doped AlGaN buffer layer 4' away from the substrate 3. x Ga 1-x N / n-GaN superlattice structure layer 41', where 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice layer 41' can be 2 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 Gallium nitride has a smaller lattice mismatch with silicon carbide substrates. Using silicon carbide as the substrate, a heavily doped n-type gallium nitride layer or a periodic n-Al layer can be applied. x Ga 1-x The N / n-GaN superlattice structure layer has a relatively low dislocation density.

[0073] According to other embodiments of the present invention, the substrate 3 may be a silicon carbide substrate, see reference. Figure 10, forming the LED light emitting unit can include: forming an n-doped AlGaN buffer layer 4' on one side of the substrate 3; epitaxially growing a heavily doped n-type gallium nitride layer 41 and at least two inorganic insulating mask layers 6 on the side of the n-doped AlGaN buffer layer 4' away from the substrate 3, the electron concentration of the heavily doped n-type gallium nitride layer 41 can be 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layer 6 is located in the heavily doped n-type gallium nitride layer 41, and each inorganic insulating mask layer 6 includes a hollow area, and the hollow areas in different inorganic insulating mask layers 6 are coincident in orthographic projection on the substrate 3; according to still some embodiments of the present application, the substrate 3 can be a silicon carbide substrate, referring to Figure 10 , forming an n-doped AlGaN buffer layer 4' on one side of the substrate 3; forming a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41' and at least two inorganic insulating mask layers 6 on the side of the n-doped AlGaN buffer layer 4' away from the substrate 3, wherein 0.02≤x≤0.05, and the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer can be 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layer 6 is located in the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41', and each inorganic insulating mask layer 6 includes a hollow area, and the hollow areas in different inorganic insulating mask layers 6 are coincident in orthographic projection on the substrate. Forming the inorganic insulating mask layer in the process of growing the heavily doped n-type gallium nitride layer or the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer can further reduce the dislocation density in the structure, thereby facilitating further improvement of the light emitting performance of the chip.

[0074] According to some embodiments of the present application, the substrate 3 can be a gallium nitride substrate, referring to Figure 11 , forming the LED light emitting unit can include: epitaxially growing a heavily doped n-type gallium nitride layer 41 on one side surface of the substrate 3, the electron concentration of the heavily doped n-type gallium nitride layer 41 can be 2×10 18 cm -3 ~1×10 19 cm -3 ; or forming a periodic n-Al x Ga 1-xN / n-GaN superlattice structure layer 41', wherein 0.02≤x≤0.05, and periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer 41' can be 2×10 18 cm -3 ~1×10 19 cm -3 As a homogenous substrate of the heavily doped n-type gallium nitride layer, the gallium nitride substrate has a higher matching degree with the heavily doped n-type gallium nitride layer, which is conducive to reducing the dislocation density and improving the internal quantum efficiency of the LED device, thereby improving the light-emitting performance of the chip.

[0075] According to some other embodiments of the present application, the substrate 3 can be a gallium nitride substrate, and referring to Figure 12 , forming the LED light-emitting unit can include: forming a heavily doped n-type gallium nitride layer 41 and at least two inorganic insulating mask layers 6 on one side of the substrate 3, the electron concentration of the heavily doped n-type gallium nitride layer 41 can be 2×10 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer 6 is located in the heavily doped n-type gallium nitride layer 41, and each inorganic insulating mask layer 6 includes a hollow area, and the hollow areas in different inorganic insulating mask layers 6 are coincident in orthographic projection on the substrate 3; or, forming a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41' and at least two inorganic insulating mask layers 6 on one side of the substrate 3, 0.02≤x≤0.05, and periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer 41' can be 2×10 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer 6 is located in the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41', and each inorganic insulating mask layer 6 includes a hollow area, and the hollow areas in different inorganic insulating mask layers 6 are coincident in orthographic projection on the substrate 3. In this way, by forming at least two inorganic insulating mask layers in the heavily doped n-type gallium nitride layer, the dislocation is prevented from extending upward, and the dislocation density is further reduced.

[0076] According to some embodiments of the present application, the temperature for epitaxially growing the heavily doped n-type gallium nitride layer 41 can be 1040-1060 °C, for example, 1040 °C, 1045 °C, 1050 °C, 1055 °C, 1060 °C, etc., and silane is used as the n-type dopant. In this way, n-type doping of gallium nitride can be achieved, and the gallium nitride layer grown at the above temperature has good stability, which is conducive to improving the overall performance of the chip.

[0077] According to some embodiments of the present application, the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41' has a thickness of 2-2.5 μm. x Ga 1-x The thickness of n-Al x Ga 1-x N in each period of the n-Al x Ga 1-x N / n-GaN superlattice structure layer 41' can be 2-3 nm, and the thickness of n-GaN can be 5-10 nm.

[0078] According to some embodiments of the present application, the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41' has a thickness of 2-2.5 μm. x Ga 1-x N / n-GaN superlattice structure layer 41' can be 2-3 nm, and the thickness of n-GaN can be 5-10 nm.

[0079] According to some embodiments of the present application, the thickness of the heavily doped n-type gallium nitride layer 41 or the thickness of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41' can be 2-2.5 μm.

[0080] According to some embodiments of the present application, referring to Figure 9 to Figure 14 , forming the LED light-emitting unit can further include: forming a lightly doped n-type gallium nitride layer 42 on the side of the heavily doped n-type gallium nitride layer 41 or the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41' away from the substrate 3, and the electron concentration of the lightly doped n-type gallium nitride layer 42 can be 1x10 17 cm -3 -5x10 17 cm -3 -5x10 y Ga 1-y N / GaN quantum well structure on the side of the first barrier layer 43 away from the substrate 3, and the number of periods of the non-doped In z Ga 1-zN / GaN quantum well structure (not shown in the figure), wherein 0.01≤y≤0.03, 0.03≤z≤0.05; in non-doped In z Ga 1-z The N / GaN quantum well structure grows a quantum well light emitting layer 44 away from one side of the substrate 3, wherein the quantum well light emitting layer 44 can include a blue quantum well light emitting layer, a green quantum well light emitting layer and a red quantum well light emitting layer; a non-doped gallium nitride protective layer 45, an electron blocking layer 46, a hole injection layer 47 and an ohmic contact layer 48 are sequentially formed away from one side of the substrate 3.

[0081] According to some embodiments of the present application, the temperature for forming the lightly doped n-type gallium nitride layer 42 is 1040-1060°C, for example, 1040°C, 1045°C, 1050°C, 1055°C, 1060°C, etc.

[0082] According to some embodiments of the present application, the thickness of the lightly doped n-type gallium nitride layer 42 can be 0.3-0.5μm, for example, 0.3μm, 0.35μm, 0.4μm, 0.45μm, 0.5μm, etc.

[0083] According to some embodiments of the present application, the thickness of the first barrier layer 43 can be 15-30nm, for example, 15nm, 20nm, 25nm, 30nm, etc.

[0084] According to some embodiments of the present application, the non-doped In y Ga 1-y In each period of the N / GaN quantum well structure, the thickness of In y Ga 1-y N can be 2.5-3.5nm, for example, 2.5nm, 2.8nm, 3nm, 3.2nm, 3.5nm, etc., and the thickness of GaN can be 5-15nm, for example, 5nm, 8nm, 10nm, 13nm, 15nm, etc.

[0085] According to some embodiments of the present application, the non-doped In z Ga 1-z In each period of the N / GaN quantum well structure, the thickness of In z Ga 1-z N is 2.5-3.5nm, for example, 2.5nm, 2.8nm, 3nm, 3.2nm, 3.5nm, etc., and the thickness of GaN is 5-15nm, for example, 5nm, 8nm, 10nm, 13nm, 15nm, etc.

[0086] According to some embodiments of the present application, forming a blue quantum well light emitting layer (blue wavelength 455-465nm) can include: growing a non-doped Inz Ga 1-z N / GaN quantum well structure far from the substrate side of the first undoped GaN layer, In a Ga 1-a N potential well layer, the second undoped GaN layer, In b Ga 1-b N potential barrier layer, wherein 0.18≤a≤0.21, 0.01≤b≤0.05.

[0087] According to some embodiments of the present application, forming a green quantum well light emitting layer (green wavelength 520nm-535nm) can include: growing 1-2 periods of In z Ga 1-z N / GaN quantum well structure far from the substrate side of the first undoped GaN layer, In c Ga 1-c N / n-type GaN quantum well structure and 2-3 periods of In d Ga 1-d N / n-type GaN quantum well structure, growing In c Ga 1-c N / n-type GaN quantum well structure includes the third undoped GaN layer, In c Ga 1-c N potential well layer, the fourth undoped GaN layer and the first n-type GaN potential barrier layer, growing In d Ga 1-d N / n-type GaN quantum well structure includes the fifth undoped GaN layer, In d Ga 1-d N potential well layer, the sixth undoped GaN layer, the second n-type GaN potential barrier layer, wherein 0.24≤c≤0.25, 0.25≤d≤0.28.

[0088] According to some embodiments of the present application, forming a red quantum well light emitting layer (red wavelength 620nm-635nm) can include: growing 1-2 periods of In z Ga 1-z N / GaN quantum well structure far from the substrate side of the first undoped GaN layer, In e Ga 1-e N potential well layer, the eighth undoped GaN layer, In f Ga 1-f N potential barrier layer, the ninth undoped GaN layer, In g Ga 1-g N potential well layer, the tenth undoped GaN layer, p-type doped GaN potential barrier layer, Al h Ga 1-hN layer, wherein 0.18≤e≤0.21, 0.01≤f≤0.05, 0.35≤g≤0.38, 0.10≤h≤0.30.

[0089] According to some embodiments of the present application, the thickness of the first non-doped GaN layer and the thickness of the second non-doped GaN layer can each independently be 1-5 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc.

[0090] According to embodiments of the present application, In a Ga 1-a The thickness of the N well layer can be 2.5-3.5 nm, for example, 2.5 nm, 2.8 nm, 3 nm, 3.2 nm, 3.5 nm, etc.

[0091] According to embodiments of the present application, In b Ga 1-b The thickness of the N barrier layer can be 5-15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, etc.

[0092] According to embodiments of the present application, the thickness of the third non-doped GaN layer, the thickness of the fourth non-doped GaN layer, the thickness of the fifth non-doped GaN layer, the thickness of the sixth non-doped GaN layer, the thickness of the seventh non-doped GaN layer, the thickness of the eighth non-doped GaN layer, the thickness of the ninth non-doped GaN layer, and the thickness of the tenth non-doped GaN layer can each independently be 1-3 nm. The non-doped GaN layer is deposited at a low temperature before the well layer and the barrier layer are grown, the growth temperature of the non-doped GaN layer can be the same as the temperature at which the well layer is formed, and the non-doped GaN layer can improve the surface flatness of the film layer before the quantum well structure is grown.

[0093] According to embodiments of the present application, In c Ga 1-c The thickness of the N well layer, In d Ga 1-d The thickness of the N barrier layer, In e Ga 1-e The thickness of the N well layer, In g Ga 1-g The thickness of the N well layer can each independently be 2.5-3.5 nm, for example, 2.5 nm, 2.8 nm, 3 nm, 3.2 nm, 3.5 nm, etc.

[0094] According to embodiments of the present application, the thickness of the first n-type GaN barrier layer, the thickness of the second n-type GaN barrier layer, In f Ga 1-fThe thickness of the N barrier layer and the thickness of the p-type doped GaN barrier layer can each independently be 5-15 nm, for example, 5 nm, 8 nm, 10 nm, 13 nm, 15 nm, etc.

[0095] According to an embodiment of the present application, Al h Ga 1-h The thickness of the N layer can be 1-2 nm, for example, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, etc.

[0096] According to an embodiment of the present application, the thickness of the undoped GaN protective layer can be 15-30 nm, for example, 15 nm, 18 nm, 20 nm, 23 nm, 25 nm, 28 nm, 30 nm, etc. The quantum well structure is grown under a nitrogen atmosphere, and is converted to a hydrogen atmosphere when the electron blocking layer is subsequently grown, which can etch the quantum well structure. The undoped GaN protective layer can protect the quantum well structure, reducing or even avoiding etching of the quantum well structure under the hydrogen atmosphere.

[0097] According to an embodiment of the present application, the thickness of the electron blocking layer can be 60-70 nm, and the material of the electron blocking layer can be a polarization-induced p-type doped Al q Ga 1-q N, in a direction away from the substrate, the value of q linearly changes from 20-30% to 0.

[0098] According to an embodiment of the present application, the hole injection layer can be a p-Al i Ga 1-i N / p-GaN superlattice structure with 8-16 periods, and the hole concentration of the hole injection layer can be 1.5×10 18 cm -3 -3.5×10 18 cm -3 In each period, the thickness of the p-Al i Ga 1-i N can be 2.5-3.5 nm, the thickness of the p-GaN can be 5-8 nm, and 0.10≤i≤0.20.

[0099] According to an embodiment of the present application, the material of the ohmic contact layer can be heavily doped p-GaN, and the thickness of the ohmic contact layer can be 20-40 nm, for example, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, etc.

[0100] S3: sequentially forming a first conductive material layer and a first reflective layer on a side of the LED light emitting unit away from the substrate.

[0101] It should be noted that the steps after the formation of the LED light emitting unit on the sapphire substrate, silicon substrate, silicon carbide substrate or gallium nitride substrate are the same, therefore, the corresponding drawings of steps S3 to S15 are all illustrated by taking the case of the substrate being a sapphire substrate as an example.

[0102] According to an embodiment of the present application, after the formation of the LED light emitting unit, a first conductive material layer 30 and a first reflective layer 20 are sequentially formed on the side of the LED light emitting unit away from the substrate 3, obtaining a structure as shown in FIG. 3. Figure 15

[0103] According to some embodiments of the present application, the material of the first conductive material layer 30 can be ITO, and a 40nm-100nm thick ITO film layer can be deposited by electron beam evaporation, and a rapid thermal annealing process can be used to improve the light transmittance of the ITO film layer (light transmittance≥85%) and reduce the resistance of the material.

[0104] According to some embodiments of the present application, a 100nm-400nm thick Ag or Al film layer can be deposited by electron beam evaporation to obtain the first reflective layer.

[0105] S4: binding a driving backboard on the side of the first reflective layer away from the substrate.

[0106] According to some embodiments of the present application, the driving backboard 10 is bound on the side of the first reflective layer 20 away from the substrate 3, obtaining a structure as shown in FIG. 4, and the driving backboard 10 has a pixel driving circuit. According to some embodiments of the present application, the driving backboard 10 can be a CMOS (Complementary Metal Oxide Semiconductor) driving backboard of a silicon substrate or a silicon-based CMOS driving backboard. Figure 16

[0107] According to some specific embodiments of the present application, a first binding metal can be deposited on the surface of the first reflective layer 20 away from the substrate 3 by electron beam evaporation, and the first binding metal can include metal chromium, metal platinum, metal nickel, metal titanium, metal silver, etc., for example, the first binding metal can include a chromium layer, a platinum layer, a nickel layer, a titanium layer, a nickel layer and a silver layer which are sequentially stacked; a second binding metal is deposited on the driving backboard, and the second binding metal can include metal chromium, metal platinum, metal silver, metal indium, etc., for example, the second binding metal can include a chromium layer, a platinum layer, a silver layer and an indium layer which are sequentially stacked; and then the driving backboard 10 is bound on the side of the first reflective layer 20 away from the substrate 3. It should be understood by those skilled in the art that the side of the driving backboard provided with the pixel driving circuit is bound with the structure formed in the front.

[0108] S5: peeling off the substrate.

[0109] ​​According to some embodiments of the present application, when the substrate is a sapphire substrate, the substrate can be peeled off by a laser peeling process, optionally, the pulsed laser wavelength is 355nm, 266nm or 248nm, thereby, the sapphire substrate can be effectively peeled off, and when the substrate is peeled off by laser, the inorganic insulating mask layer 6 can absorb part of the laser energy, relieving the damage of the interface high temperature to the quantum well structure, thereby further improving the light emitting performance of the chip.

[0110] According to some other embodiments of the present application, when the substrate is a silicon substrate, the silicon substrate can be peeled off by a wet etching method.

[0111] According to some other embodiments of the present application, when the substrate is a silicon carbide substrate, and the buffer layer is an n-type doped AlGaN buffer layer 4’, the silicon carbide substrate can be peeled off by a wet etching method and / or a grinding method.

[0112] According to some other embodiments of the present application, when the substrate is a silicon carbide substrate, the aluminum nitride buffer layer 4 and the graded Al p Ga 1-p N layer 8 are formed on one side of the substrate 3, the silicon carbide substrate can be peeled off by a wet etching method, a grinding method and / or an ICP-RIE etching method.

[0113] According to some other embodiments of the present application, when the substrate is a gallium nitride substrate, the gallium nitride substrate can be peeled off by a grinding method and / or an ICP-RIE etching method.

[0114] It should be noted that in the process of peeling off the sapphire substrate, a part of the aluminum nitride buffer layer is also etched off.

[0115] After the sapphire substrate is peeled off, the undoped gallium nitride film layer 5 is etched by an ICP-RIE etching method until the heavily doped n-type gallium nitride layer 41 or the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41’ is exposed, and the obtained structure is as shown in Figure 17 , and then the surface is subjected to chemical mechanical polishing.

[0116] S6: etching the LED light emitting units to form a plurality of spaced LED light emitting units.

[0117] According to some embodiments of the present application, referring to Figure 18The LED light emitting units are etched to form a plurality of spaced LED light emitting units 40. According to some embodiments of the present application, the ICP-RIE process and photolithography can be used to etch indium gallium nitride-based RGB three-primary color pixels with different pixel sizes and different pixel pitches, and the LED light emitting units (pixels) can be arranged in a low dislocation region or a dislocation-free region. Subsequently, acetone, ethanol and deionized water are used in sequence for stripping and surface cleaning. According to some embodiments of the present application, when the non-doped gallium nitride film layer or the heavily doped n-type gallium nitride layer is formed in the foregoing process, if the inorganic insulating mask layer is formed, the dislocation-free or low dislocation region alignment mark can be arranged to better arrange the pixels in the dislocation-free or low dislocation region.

[0118] S7: A passivation layer is formed on the side of the plurality of LED light emitting units away from the driving backboard.

[0119] According to an embodiment of the present application, referring to Figure 18 After the plurality of LED light emitting units 40 are formed, a passivation layer 50 is formed on the side of the LED light emitting units away from the driving backboard 10, and the passivation layer 50 covers at least the sidewall of the LED light emitting units 40.

[0120] According to some embodiments of the present application, the etching interface can be repaired by wet etching (25wt% TMAH solution, TMAH refers to tetramethylammonium hydroxide), and a 20nm-40nm thick silicon oxide or silicon nitride passivation layer is deposited by ALD (atomic layer deposition) equipment. According to other embodiments of the present application, a 60nm-200nm thick silicon oxide or silicon nitride passivation layer can be deposited by PECVD equipment.

[0121] S8: A second reflective layer is formed to cover at least the sidewall of the passivation layer.

[0122] According to an embodiment of the present application, referring to Figure 18 After the passivation layer 50 is formed, a second reflective layer 60 can be formed on the side of the passivation layer 50 away from the driving backboard 10, so as to further enhance the light extraction efficiency.

[0123] According to some embodiments of the present application, the PVD (physical vapor deposition) or ALD method can be used to deposit a tantalum oxide, titanium oxide and / or silicon oxide reflective film layer to form a Bragg reflector, i.e., the second reflective layer 60. The second reflective layer can be arranged to further enhance the light extraction efficiency.

[0124] S9: The first conductive material layer is etched to form a plurality of spaced first conductive film layers.

[0125] According to an embodiment of the present application, referring to Figure 18After forming the passivation layer 50 and the second reflective layer 60, the first conductive material layer 30 is etched to form a plurality of first conductive film layers 31 spaced apart from each other. According to some embodiments of the present application, the first conductive material layer 30 can be etched by using photolithography and ICP-RIE process to form the isolation grooves, and acetone, ethanol and deionized water are used for the stripping and surface cleaning treatment.

[0126] S10: Forming a first insulating layer.

[0127] According to an embodiment of the present application, referring to Figure 18 , after etching the first conductive material layer, the first insulating layer 1 is formed to cover part of the surface of the second reflective layer 60 and part of the surface of the first reflective layer 20. According to an embodiment of the present application, the first insulating layer 1 can be formed by using photolithography process and PECVD equipment to deposit the oxide of silicon or nitride of silicon film layer, and acetone, ethanol and deionized water are used for the stripping and surface cleaning treatment.

[0128] S11: Etching the passivation layer and the second reflective layer to expose part of the surface of the LED light emitting unit away from the driving backboard.

[0129] According to an embodiment of the present application, referring to Figure 18 , the passivation layer 50 and the second reflective layer 60 are etched to expose part of the surface of the LED light emitting unit 40 away from the driving backboard 10. According to some embodiments of the present application, the LED light emitting unit 40 (pixel) mesa can be re-doped with n-type gallium nitride layer 41 or periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer 41' by using photolithography process and ICP-RIE etching process, and part of the passivation layer 50 and the second reflective layer 60 on the n-type gallium nitride layer 41 are removed to expose part of the surface of the LED light emitting unit away from the driving backboard.

[0130] S12: Forming a second conductive film layer.

[0131] According to an embodiment of the present application, referring to Figure 18 , the second conductive film layer 70 is formed to contact the LED light emitting unit 40, and the second conductive film layer 70 can cover at least part of the surface of the first insulating layer 1 away from the driving backboard 10 and at least part of the surface of the second reflective layer 60 away from the driving backboard 10. According to some embodiments of the present application, the material of the second conductive film layer 70 can be ITO, and a 20nm-100nm thick ITO film layer can be deposited and combined with RTA (rapid thermal annealing) process to improve the light transmittance of the ITO film layer and reduce the resistance of the material.

[0132] S13: Forming a plurality of concave reflective layers on the side of the first insulating layer away from the driving backboard.

[0133] According to an embodiment of the present application, referring to Figure 18 A plurality of concave reflective layers 90 are formed on the side of the first insulating layer 1 away from the driving backboard 10, and each concave reflective layer 90 is arranged around one LED light emitting unit 40. According to an embodiment of the present application, the concave reflective layer can be obtained by using a nanoimprint method, photolithography and electron beam deposition method to deposit metal silver and / or metal aluminum, which can effectively reduce the light crosstalk between the LED light emitting units, converge the light divergence angle, and improve the light extraction efficiency of the chip.

[0134] According to an embodiment of the present application, referring to Figure 18 Before the concave reflective layer 90 is formed, the method for manufacturing the Micro LED chip can further include: forming a plurality of n-type ohmic contact electrodes 80 arranged at intervals on the side of the second conductive film layer 70 away from the driving backboard 10, and each n-type ohmic contact electrode 80 is arranged around one LED light emitting unit 40. According to an embodiment of the present application, the n-type ohmic contact electrode can be formed by using a photolithography process and electron beam evaporation, and then using acetone, ethanol and deionized water for degumming and surface cleaning treatment, and the n-type ohmic contact electrode can include metal layers such as a titanium layer, an aluminum layer, a titanium layer and a gold layer which are stacked in sequence.

[0135] According to some specific embodiments of the present application, referring to Figure 18 The concave reflective layer 90 can be formed on the side of the n-type ohmic contact electrode 80 away from the driving backboard 10, and the concave reflective layer 90 can be arranged in contact with the n-type ohmic contact electrode 80.

[0136] According to some embodiments of the present application, the method for manufacturing the Micro LED chip can further include: forming a second insulating layer on the side of the second conductive film layer away from the driving backboard.

[0137] According to an embodiment of the present application, referring to Figure 18 A second insulating layer 2 is formed on the side of the second conductive film layer 70 away from the driving backboard 10, and the second insulating layer 2 can cover at least part of the surface of the second conductive film layer 70, at least part of the surface of the n-type ohmic contact electrode 80 and at least part of the surface of the concave reflective layer 90. According to an embodiment of the present application, the oxide of silicon and / or the nitride of silicon insulating layer can be deposited by using a photolithography process and a PECVD device, so as to realize the electrical insulation between the LED light emitting unit (pixel) mesa.

[0138] According to some embodiments of the present application, the quantum well light emitting layer can also be an AlGaInP (aluminum gallium indium phosphide) red quantum well light emitting layer. In the preparation process, a quantum well light emitting layer structure is formed on a gallium arsenide substrate, an ICP-RIE device is used to etch the quantum well light emitting layer structure, a plurality of LED light emitting units are formed, then the LED light emitting units are bound to a transfer substrate (sapphire substrate or silicon substrate) on the side away from the gallium arsenide substrate, the gallium arsenide substrate is peeled off, a driving backboard is bound, the driving backboard has a pixel driving circuit, the driving backboard is arranged on the side of the LED light emitting units away from the transfer substrate, then the transfer substrate is peeled off, and a concave reflecting layer structure is further formed. The finally obtained chip structure is substantially the same as the structure shown in Figure 1 and Figure 2 The difference between the two structures is that the materials of the layers in the LED light emitting units are different, and both are based on AlGaInP. The concave reflecting layer can also reduce the light crosstalk between red light pixels (LED light emitting units), converge the light divergence angle, and improve the light extraction efficiency and light emitting performance of the chip.

[0139] In the description of the present specification, the description of the terms "one embodiment", "another embodiment", "some embodiments", "other embodiments", "some specific embodiments", "other specific embodiments" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments are included in at least one embodiment of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples, without contradiction. In addition, it should be noted that in the present specification, the terms "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth", "ninth", "tenth" are for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0140] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and the person skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A Micro LED chip, characterized in that, The application relates to a display device, and discloses a display device and a manufacturing method thereof. The display device comprises: a driving backboard with pixel driving circuit; a first reflecting layer arranged on one side of the driving backboard; a plurality of first conductive film layers arranged at intervals, which are arranged on the side of the first reflecting layer away from the driving backboard; a plurality of LED light emitting units arranged on the side of the first conductive film layer away from the driving backboard; a passivation layer covering at least the sidewall of the LED light emitting unit; a second reflecting layer covering at least the sidewall of the passivation layer; a first insulating layer covering part of the surface of the second reflecting layer and part of the surface of the first reflecting layer; a second conductive film layer in contact with the LED light emitting unit; and a plurality of concave reflecting layers arranged on the side of the first insulating layer away from the driving backboard, each of the concave reflecting layers surrounding one LED light emitting unit. 2.The Micro LED chip of claim 1, wherein, At least one of the following conditions is met: The thickness of the first conductive film layer is 40-100 nm; The material of the first conductive film layer comprises ITO; The material of the first reflecting layer comprises at least one of silver and aluminum; The material of the passivation layer comprises at least one of silicon nitride and silicon oxide; The thickness of the passivation layer is 20-200 nm; The second reflecting layer is a Bragg mirror, and the material of the second reflecting layer comprises at least one of tantalum oxide, titanium oxide and silicon oxide; The material of the second conductive film layer comprises ITO; The thickness of the second conductive film layer is 20-100 nm; The material of the concave reflecting layer comprises at least one of silver and aluminum; The material of the first insulating layer comprises at least one of silicon nitride and silicon oxide. 3.A method of manufacturing a Micro LED chip, comprising: The application relates to a display device, and discloses a display device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate; forming an LED light emitting unit on one side surface of the substrate, which comprises the step of forming a quantum well light emitting layer; forming a first conductive material layer and a first reflecting layer on the side of the LED light emitting unit away from the substrate in sequence; binding a driving backboard with pixel driving circuit on the side of the first reflecting layer away from the substrate; peeling off the substrate; etching the LED light emitting unit to form a plurality of LED light emitting units arranged at intervals; forming a passivation layer on the side of the LED light emitting units away from the driving backboard, which covers at least the sidewall of the LED light emitting unit; forming a second reflecting layer covering at least the sidewall of the passivation layer; etching the first conductive material layer to form a plurality of first conductive film layers arranged at intervals; forming a first insulating layer covering part of the surface of the second reflecting layer and part of the surface of the first reflecting layer; etching the passivation layer and the second reflecting layer to expose part of the surface of the LED light emitting unit away from the driving backboard; forming a second conductive film layer in contact with the LED light emitting units; forming a plurality of concave reflection layers on the side of the first insulating layer away from the driving backboard, each of the concave reflection layers being arranged around one of the LED light emitting units.

4. The method of claim 3, wherein, The substrate is a sapphire substrate, and forming the LED light emitting units comprises: forming an aluminum nitride buffer layer on one side of the substrate; forming a non-doped gallium nitride film layer and at least two inorganic insulating mask layers on the side of the aluminum nitride buffer layer away from the substrate, the inorganic insulating mask layers being located in the non-doped gallium nitride film layer, and each of the inorganic insulating mask layers comprising a hollow region, the hollow regions in different inorganic insulating mask layers being coincident in orthographic projection on the substrate; A heavily doped n-type gallium nitride layer is epitaxially grown on the side of the non-doped gallium nitride film layer away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; or, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is formed on the surface of the non-doped gallium nitride film layer away from the substrate, 0.02≤x≤0.05, and the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; forming the non-doped gallium nitride film layer and the at least two inorganic insulating mask layers comprises: epitaxially growing the non-doped gallium nitride film layer, and for each growth thickness of 0.5 μm to 1 μm of non-doped gallium nitride, introducing ammonia and silane, reacting at 1045°C to 1065°C for 10 s to 60 s to form a grid-shaped structure of nitride of silicon with a thickness of 10 nm to 25 nm, and subsequently non-doped gallium nitride continues to nucleate at the openings of the grid-shaped structure of nitride of silicon and epitaxially forms a film on the grid-shaped structure of nitride of silicon until the thickness of the non-doped gallium nitride film layer is 3 μm to 5 μm; or epitaxially growing the non-doped gallium nitride film layer, and for each growth thickness of 0.5 μm to 1 μm of non-doped gallium nitride, forming a film layer of nitride of silicon or a film layer of oxide of silicon with a thickness of 10 nm to 25 nm on the surface of non-doped gallium nitride away from the substrate, and etching the film layer of nitride of silicon or the film layer of oxide of silicon to form a grid-shaped structure or a plurality of spaced strip-shaped structures, the longitudinal section of the strip-shaped structure being rectangular or trapezoidal, until the thickness of the non-doped gallium nitride film layer is 3 μm to 5 μm.

5. The method of claim 4, wherein, The substrate is peeled off by a laser lift-off process, and optionally, the wavelength of the pulsed laser is 355 nm, 266 nm or 248 nm.

6. The method of claim 3, wherein, The substrate is a silicon substrate or a silicon carbide substrate, and forming the LED light emitting units comprises: forming an aluminum nitride buffer layer on one side of the substrate; a gradient Al is formed on the surface of the AlN buffer layer away from the substrate p Ga 1-p N layer, in the direction away from the AlN buffer layer, the value of p linearly changes from 20% to 30% to 0; In the graded Al p Ga 1-p N layer, a non-doped gallium nitride film layer and at least two inorganic insulating mask layers are formed on the side away from the substrate, the inorganic insulating mask layers are located in the non-doped gallium nitride film layer, and each of the inorganic insulating mask layers comprises a hollow region, and the hollow regions in different inorganic insulating mask layers are in the same orthographic projection on the substrate. A heavily doped n-type gallium nitride layer is epitaxially grown on the side of the non-doped gallium nitride film layer away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; or, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is formed on the surface of the non-doped gallium nitride film layer away from the substrate, 0.02≤x≤0.05, and the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; forming the non-doped gallium nitride film layer and the at least two inorganic insulating mask layers comprises: epitaxially growing the non-doped gallium nitride film layer, and for each growth thickness of 0.5 μm to 1 μm of non-doped gallium nitride, introducing ammonia and silane, reacting at 1045°C to 1065°C for 10 s to 60 s to form a grid-shaped structure of nitride of silicon with a thickness of 10 nm to 25 nm, and subsequently non-doped gallium nitride continues to nucleate at the openings of the grid-shaped structure of nitride of silicon and epitaxially forms a film on the grid-shaped structure of nitride of silicon until the thickness of the non-doped gallium nitride film layer is 3 μm to 5 μm; or The non-doped gallium nitride film layer is epitaxially grown, and when the non-doped gallium nitride is grown by a thickness of 0.5-1 μm, a nitride film layer or an oxide film layer of silicon with a thickness of 10-25 nm is formed on the surface of the non-doped gallium nitride away from the substrate, the nitride film layer or the oxide film layer of silicon is etched to form a grid structure or a plurality of spaced strip structures, the longitudinal section of the strip structure is rectangular or trapezoidal, and the thickness of the non-doped gallium nitride film layer is 3-5 μm.

7. The method of claim 3, wherein, The substrate is a silicon carbide substrate, and the LED light emitting unit is formed by: forming an n-type doped AlGaN buffer layer on one side of the substrate; A heavily doped n-type gallium nitride layer is epitaxially grown on the surface of the n-type doped AlGaN buffer layer away from the substrate, and the electron concentration of the heavily doped n-type gallium nitride layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; or, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is formed on the surface of the n-type doped AlGaN buffer layer away from the substrate, 0.02≤x≤0.05, and the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is 2×10 18 cm -3 ~1×10 19 cm -3 ; Alternatively, a heavily doped n-type gallium nitride layer and at least two inorganic insulating mask layers are epitaxially grown on the side of the n-type doped AlGaN buffer layer away from the substrate, wherein the electron concentration of the heavily doped n-type gallium nitride layer is 2 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer is located within the heavily doped n-type gallium nitride layer, and each inorganic insulating mask layer includes a cutout region, with the cutout regions in different inorganic insulating mask layers having their orthographic projections onto the substrate overlapping; or, periodic n-Al patterns are formed on the side of the n-type doped AlGaN buffer layer away from the substrate. x Ga 1-x An N / n-GaN superlattice structure layer and at least two inorganic insulating mask layers, 0.02≤x≤0.05, periodic n-Al x Ga 1-x The electron concentration of the N / n-GaN superlattice structure layer is 2 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The inorganic insulating mask layer is located on the periodic n-Al x Ga 1-x In the N / n-GaN superlattice structure layer, each of the inorganic insulating mask layers includes a cutout region, and the orthographic projections of the cutout regions in different inorganic insulating mask layers on the substrate coincide.

8. The method of claim 3, wherein, The substrate is a gallium nitride substrate, and the LED light emitting unit is formed by: An n-type heavily doped gallium nitride layer is epitaxially grown on one side surface of the substrate, and the electron concentration of the n-type heavily doped gallium nitride layer is 2 x 1018cm-3 or more. 18 cm -3 -3 or more. 19 cm -3 ; or, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is formed on one side surface of the substrate, 0.02 ≤ x ≤ 0.05, and the electron concentration of the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer is 2 x 1018cm-3 or more. 18 cm -3 -3 or more. 19 cm -3 ; Or, a heavily doped n-type gallium nitride layer and at least two inorganic insulating mask layers are formed on one side of the substrate, the heavily doped n-type gallium nitride layer has an electron concentration of 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layers are located in the heavily doped n-type gallium nitride layer, and each of the inorganic insulating mask layers comprises a hollow region, the hollow regions in different inorganic insulating mask layers are coincident in orthographic projection on the substrate; or, a periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer and at least two inorganic insulating mask layers are formed on one side of the substrate, 0.02≤x≤0.05, the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer has an electron concentration of 2×10 18 cm -3 ~1×10 19 cm -3 , the inorganic insulating mask layers are located in the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer, and each of the inorganic insulating mask layers comprises a hollow region, the hollow regions in different inorganic insulating mask layers are coincident in orthographic projection on the substrate.

9. The method of any one of claims 4-8, wherein, forming the LED light emitting unit further includes: In the heavily doped n-type gallium nitride layer or the periodic n-Al x Ga 1-x N / n-GaN superlattice structure layer far from the side of the substrate forms a lightly doped n-type gallium nitride layer, and the electron concentration of the lightly doped n-type gallium nitride layer is 1 x 10 17 cm -3 ~5 x 10 17 cm -3 ; forming a first barrier layer on the side of the lightly doped n-type gallium nitride layer away from the substrate; 3-5 periods of non-doped In y Ga 1-y N / GaN quantum well structure and 3-5 periods of non-doped In z Ga 1-z N / GaN quantum well structure, wherein 0.01≤y≤0.03, 0.03≤z≤0.05; In z Ga 1-z N / GaN quantum well structure far from the side of the substrate growth of blue quantum well light emitting layer, green quantum well light emitting layer and red quantum well light emitting layer; forming, on the side of the quantum well light emitting layer away from the substrate, a non-doped gallium nitride protective layer, an electron blocking layer, a hole injection layer and an ohmic contact layer in sequence.

10. The method of claim 9, wherein, forming the blue light quantum well light emitting layer comprises: forming a first non-doped GaN layer, an In z Ga 1-z N / GaN quantum well structure far from the side of the substrate in sequence, an In a Ga 1-a N well layer, a second non-doped GaN layer, an In b Ga 1-b N barrier layer, wherein 0.18≤a≤0.21, 0.01≤b≤0.

05. forming the green light quantum well light-emitting layer comprises: growing In z Ga 1-z N / GaN quantum well structure 1~2 periods of In c Ga 1-c N / n-type GaN quantum well structure and 2~3 periods of In d Ga 1-d N / n-type GaN quantum well structure, growing In c Ga 1-c N / n-type GaN quantum well structure comprises sequentially forming a third undoped GaN layer, In c Ga 1-c N potential well layer, a fourth undoped GaN layer and a first n-type GaN barrier layer, growing In d Ga 1-d N / n-type GaN quantum well structure comprises sequentially forming a fifth undoped GaN layer, In d Ga 1-d N potential well layer, a sixth undoped GaN layer, a second n-type GaN barrier layer, wherein 0.24≤c≤0.25, 0.25≤d≤0.28; forming the red light quantum well light-emitting layer comprises: forming a seventh non-doped GaN layer, an In z Ga 1-z N / GaN quantum well structure on the side away from the substrate in sequence e Ga 1-e N well layer, an eighth non-doped GaN layer, an In f Ga 1-f N barrier layer, a ninth non-doped GaN layer, an In g Ga 1-g N well layer, a tenth non-doped GaN layer, a p-type doped GaN barrier layer, an Al h Ga 1-h N layer, wherein 0.18≤e≤0.21, 0.01≤f≤0.05, 0.35≤g≤0.38, 0.10≤h≤0.

30.

11. The method of claim 10, wherein, At least one of the following conditions is met: The temperature for epitaxially growing the heavily doped n-type gallium nitride layer is 1040-1060 °C; Periodic n-Al x Ga 1-x In the n-Al x Ga 1-x N / n-GaN superlattice structure layer, the thickness of n-Al is 2nm~3nm, and the thickness of n-GaN is 5nm~10nm; The periodic n-Al x Ga 1-x The film forming temperature of the n-GaN superlattice structure layer is 1060-1080°C. The temperature for forming the lightly doped n-type gallium nitride layer is 1040-1060 °C; The thickness of the lightly doped n-type gallium nitride layer is 0.3-0.5 μm; The thickness of the first barrier layer is 15-30 nm; non-doped In y Ga 1-y N / GaN quantum well structure, the thickness of In y Ga 1-y N is 2.5nm~3.5nm, and the thickness of GaN is 5nm~15nm; non-doped In z Ga 1-z N / GaN quantum well structure, the thickness of In z Ga 1-z N is 2.5nm~3.5nm, and the thickness of GaN is 5nm~15nm; The thickness of the first non-doped GaN layer and the thickness of the second non-doped GaN layer are each independently 1-5 nm; The In a Ga 1-a The thickness of the N potential well layer is 2.5 nm to 3.5 nm. The In b Ga 1-b The thickness of the N barrier layer is 5-15 nm. The thickness of the third non-doped GaN layer, the thickness of the fourth non-doped GaN layer, the thickness of the fifth non-doped GaN layer, the thickness of the sixth non-doped GaN layer, the thickness of the seventh non-doped GaN layer, the thickness of the eighth non-doped GaN layer, the thickness of the ninth non-doped GaN layer and the thickness of the tenth non-doped GaN layer are each independently 1-3 nm; the In c Ga 1-c N well layer, the thickness of the In d Ga 1-d N barrier layer, the thickness of the In e Ga 1-e N well layer, the thickness of the In g Ga 1-g N well layer is independently 2.5 nm to 3.5 nm; The thickness of the first n-type GaN barrier layer, the thickness of the second n-type GaN barrier layer, and the In f Ga 1-f The thickness of the N-type barrier layer and the thickness of the p-type doped GaN barrier layer are each independently 5 nm to 15 nm. The Al h Ga 1-h The thickness of the GaN layer is 1 nm to 2 nm. The thickness of the non-doped gallium nitride protective layer is 15-30 nm; The thickness of the electron blocking layer is 60-70 nm, and the material of the electron blocking layer is p-type doped Al q Ga 1-q N, in the direction away from the substrate, the value of q linearly changes from 20-30% to 0. The hole injection layer is a p-Al layer with 8-16 cycles. i Ga 1-i The N / p-GaN superlattice structure has a hole concentration of 1.5 × 10⁻⁶ in the hole injection layer. 18 cm -3 ~3.5×10 18 cm -3 In each cycle, p-Al i Ga 1-i The thickness of N is 2.5nm~3.5nm, and the thickness of p-GaN is 5nm~8nm, with 0.10≤i≤0.20; The material of the ohmic contact layer is heavily doped p-GaN, and the thickness of the ohmic contact layer is 20-40 nm.

12. The method of any one of claims 4-6, wherein, At least one of the following conditions is met: The thickness of the aluminum nitride buffer layer is 10-50 nm; The temperature for forming the non-doped gallium nitride film layer is 1045-1065 °C.

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