Using next acquisition predictor circuit with short branches and return acquisition groups

Abstract

An apparatus includes an instruction cache circuit and an instruction fetch circuit. The instruction fetch circuitry is configured to: retrieve, from the instruction cache circuitry, a fetch group including a plurality of instructions for execution by the processing circuitry; and determining that the fetch group includes control delivery instructions predicted to be employed. A target address associated with the control delivery instruction is directed to instructions within the fetch group. The instruction fetch circuitry is further configured to change instructions within the fetch group in a manner based on the type of control delivery instruction based on the determination.

Description

Background of the Invention Technical Field

[0002] Embodiments described herein relate to computing systems including system-on-chip (SoC). More specifically, embodiments relate to techniques for managing control transfer instructions in a central processor unit.

[0003] Related technical description

[0004] Processor circuits (e.g., central processing units (CPUs)) typically process instructions in a serial order, where a program counter is typically incremented to address the next instruction in the program sequence. A control transfer instruction is an instruction that may cause a deviation from a sequential program order. Control transfer instructions include, for example, branch instructions, call instructions, and return instructions. When the CPU executes one of these control transfer instructions, the program counter may be loaded with a target address associated with the control transfer instruction, rather than being incremented to address the next instruction. Control transfer instructions enable the use of functions, loops, and conditional program flow, among other things.

[0005] To improve performance, many CPUs retrieve many instructions at once in what may be called fetch groups. Fetch groups are retrieved under the assumption that multiple sequential instructions will be executed in succession before a control transfer instruction causes the program flow to deviate, rather than simply retrieving a single instruction at a time. Branch prediction circuitry may be used to predict when a fetch group is likely to include a control transfer instruction that will alter program flow, thereby allowing the CPU to retrieve instructions from the target address of the control transfer instruction rather than from sequential fetch addresses. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0007] Figure 1 A block diagram of an embodiment of a system including instruction cache circuitry and instruction fetch circuitry is illustrated.

[0008] Figure 2 A block diagram of an embodiment of a system having instruction fetch circuitry that processes a fetch group having a call instruction is shown.

[0009] Figure 3 A block diagram of an embodiment of a system having instruction fetch circuitry that processes a fetch group having a backward branch instruction is depicted.

[0010] Figure 4 A block diagram of an embodiment of a system having instruction fetch circuitry that processes a fetch group having a forward branch instruction is illustrated.

[0011] Figure 5A block diagram of an embodiment of a system having an instruction fetch circuit and a next fetch predictor circuit at two points in time is shown.

[0012] Figure 6 A flow chart depicting an embodiment of a method for retrieving an acquisition group using the disclosed techniques.

[0013] Figure 7 A flow chart illustrating an embodiment of a method for retrieving a fetch group including a call instruction.

[0014] Figure 8 A flow chart of an embodiment of a method for retrieving a fetch group including a backward branch instruction is shown.

[0015] Fig. 9 A flow chart of an embodiment of a method for retrieving a fetch group including a forward branch instruction is depicted.

[0016] Fig.10 Various embodiments of systems including coupled integrated circuits are illustrated.

[0017] Fig.11 is a block diagram of an example computer-readable medium according to some embodiments.

[0018] Although the embodiments described in the present disclosure may be subject to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and detailed description of the drawings are not intended to limit the embodiments to the particular forms disclosed, but on the contrary, are intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims. DETAILED DESCRIPTION

[0019] Generally, processor circuitry includes instruction fetch circuitry for retrieving groups of instructions (referred to herein as "fetch groups") from one or more memory circuits. Next fetch predictor circuitry may also be used to predict an address for retrieving a next fetch group (referred to herein as a "fetch address"). The next fetch address may be determined based on a prediction of a current fetch group that includes a control transfer instruction. As used herein, a "control transfer instruction" is an instruction that may cause a subsequent instruction to be executed to have a non-sequential address from the control transfer instruction. Various types of control transfer instructions include, but are not limited to, branch instructions, call instructions, and return instructions.

[0020] In some embodiments, the next acquisition predictor circuit may be limited to predicting a control transfer function within a given acquisition group. The possibility of having more than one control transfer instruction in a given acquisition group may depend on, for example, the number of instructions in the acquisition group. The greater the number of instructions, the greater the possibility of including multiple control transfer instructions. In some embodiments of the processor circuit, since the program flow will deviate from the sequential path to the target address of the adopted control transfer instruction, the instruction at the subsequent address immediately following the adopted control transfer instruction may be discarded or otherwise ignored. Therefore, by avoiding additional processing of the instruction after the adopted control transfer instruction and determining the next acquisition address to retrieve the instruction at the target address, identifying the control transfer instruction within the acquisition group can improve processor bandwidth. However, if a given acquisition group includes two or more control transfer instructions to be adopted, the next acquisition predictor circuit may only be able to identify the first control transfer instruction, causing the second control transfer instruction to be discarded and subsequently re-acquired, or ignored by the next acquisition predictor circuit.

[0021] The present disclosure contemplates a novel digital circuit for use in an instruction fetch circuit of a processor circuit that identifies specific program flow situations in which a next fetch predictor circuit may be unable to accurately identify multiple control transfer instructions in a given fetch group. For example, the instruction fetch circuit of the processor circuit may be configured to retrieve a fetch group including multiple instructions for execution by the processor circuit from an instruction cache circuit. The instruction fetch circuit may determine that the fetch group includes a control transfer instruction that is predicted to be taken, wherein a target address associated with the control transfer instruction is directed to an instruction within the fetch group. Based on the determination, the instruction fetch circuit may change the instructions within the fetch group in a manner based on the type of the control transfer instruction.

[0022] For example, these novel circuits may attempt to identify several typical program flow situations that can be more easily handled without using the next fetch predictor circuit. This may be similar to handling two taken branches per fetch group by allowing the next fetch predictor circuit to identify the second control transfer instruction instead of the first control transfer instruction. Three of these typical situations are short backward branches, short forward branches, and return fetch groups. With respect to backward branches and forward branches, "short" refers to branches where the target of the branch is within the same fetch group as the branch instruction.

[0023] A "short backward branch" is a branch instruction that directs program flow backward (e.g., a program loop) within the same fetch group as the branch instruction. For a short backward branch, a portion of the fetch group may be duplicated in the instruction buffer, effectively resulting in two separate iterations per fetch group for the branch taken.

[0024] A "short forward branch" is a branch instruction that directs program flow forward to a target address within the same fetch group as the branch instruction. Short forward branches can be identified by the novel fetch circuitry, allowing the next fetch predictor circuitry to be trained to predict the subsequent next taken control transfer function in a fetch group or the subsequent instruction after the end of the current fetch group.

[0025] When the control transfer instruction adopted is a call instruction, the program flow deviates from the sequential path to the address indicated in the call instruction. The subsequent return instruction returns the program flow to the instruction immediately following the call instruction. The address of the instruction after the call instruction is the "return address". The "return acquisition group" is an instruction group retrieved using the return address in response to obtaining the return instruction. In some embodiments of the disclosed embodiments, the return acquisition group may be limited to returning the instructions retrieved from the retrieval of the call instruction in one or two acquisition groups. When the call instruction is obtained, the return address (usually the address subsequent to the call instruction) is used to push the return address stack. However, in many programs, at least some instructions at the return address are included in the current acquisition group. Instead of discarding the instructions at the return address and then retrieving these instructions when the return instruction is retrieved at the end of the called function, these instructions are saved in the return acquisition group stack associated with the return address stack. When the return instruction is retrieved, the instructions saved from the return acquisition group stack are retrieved instead of retrieving.

[0026] Identification of such program flow situations can improve the efficiency of the next fetch predictor circuitry, thereby increasing the bandwidth of the processor circuitry. Thus, programs can be executed with increased efficiency, thereby improving user-observed system performance and / or increasing the number of programs that can be executed in parallel.

[0027] Figure 1 A block diagram of one embodiment of a system is illustrated in which cached instructions are retrieved in a fetch group and a control transfer instruction is identified. As illustrated, system 100 includes instruction fetch circuitry 101 coupled to instruction cache circuitry 110 via a plurality of bus conductors. In some embodiments, instruction fetch circuitry 101 and instruction cache circuitry 110 may be included in an integrated circuit as part of the same processor circuit. System 100 may be part of a computing system such as a desktop or laptop computer, a smart phone, a tablet computer, or a wearable smart device.

[0028] As illustrated, instruction cache circuitry 110 is configured to store cached instructions 160 that have been fetched for execution by a processor circuit (not shown) in system 100. In some embodiments, one cache line in instruction cache circuitry 110 may hold one instruction fetch group (e.g., fetch group 165), while in other embodiments, one fetch group may span two or more cache lines, or one cache line may hold two or more fetch groups. Instruction cache circuitry 110 may include random access memory (RAM) circuitry for storing cached instructions 160 in a plurality of cache lines and content addressable memory (CAM) circuitry for storing cache tags corresponding to respective ones of the cache lines.

[0029] As shown, instruction fetch circuitry 101 is configured to retrieve a fetch group 165 including a plurality of instructions for execution by a processor circuit from instruction cache circuitry 110. For example, instruction fetch circuitry 101 may retrieve the instructions of fetch group 165 by issuing a fetch request to instruction cache circuitry 110 using fetch address 180. If instruction cache circuitry 110 currently holds a valid copy of the requested instruction, then fetch group 165 corresponding to fetch address 180 is returned to instruction fetch circuitry 101. Otherwise, instruction cache circuitry 110 may issue a memory request to retrieve the requested instruction from a different memory circuit in system 100, and in some cases, the retrieved instruction may be cached within one or more cache lines.

[0030] The instruction fetch circuit 101 may also be configured to determine that the fetch group 165 includes a control transfer instruction (instruction) 170 that is predicted to be taken. In addition, a target address 175 associated with the control transfer instruction 170 is directed to the instruction within the fetch group 165. For example, the control transfer instruction 170 and the target address 175 may be included as part of one of the cases disclosed above, such as a short backward branch or a short forward branch or a return fetch group. An indication that the fetch group 165 includes the control transfer instruction 170 and the target address 175 may be provided to the instruction fetch circuit 101 along with the fetch address 180. For example, the next fetch predictor circuit may store entries associated with previously retrieved fetch groups that include indications of control transfer functions. If the same fetch group is to be requested again, the entries may provide indicators that may be used to potentially reduce the time used to retrieve instructions to be executed. The following is about Figure 5 Additional information about the next fetch predictor circuit is disclosed.

[0031] As illustrated, instruction fetch circuit 101 may also be configured to, based on determining that fetch group 165 includes a control transfer instruction 170, change the instructions within fetch group 165 in a manner based on the type of control transfer instruction 170. The change may include rearranging the order of the instructions of fetch group 165 in the instruction buffer. For example, if control transfer instruction 170 and target address 175 are part of a short backward branch, the change may include placing a portion of the instructions in fetch group 165 into two separate locations in the instruction buffer. For another example, if control transfer instruction 170 and target address 175 are part of a short forward branch, the change may include omitting a portion of the instructions in fetch group 165 from the instruction buffer. Referring to FIG. 1 , FIG. 1 , a first embodiment of the present invention relates to a first embodiment of the present invention. Referring to FIG. 1 , a first embodiment of the present invention relates to a first embodiment of the present invention. Referring to FIG. 1 , a first embodiment of the present invention relates to a first embodiment of the present invention. Referring to FIG. 1 , a first embodiment of the present invention relates to a first embodiment of the present invention. Figures 2 to 4 Additional details are provided for the three cases disclosed above.

[0032] Please note that if Figure 1 The illustrated system 100 is merely an example. Figure 1 The illustrations have been simplified to highlight features relevant to the present disclosure. Elements that are not used to describe the details of the disclosed concepts have been omitted. For example, instruction cache circuit 110 and instruction fetch circuit 101 may be included as part of the processor circuit. In various embodiments, instruction cache circuit 110 and instruction fetch circuit may be implemented in part or in whole using any suitable combination of sequential logic circuits and combinational logic circuits. In addition, registers and / or memory circuits (such as static random access memory (SRAM)) may be used in these circuits to temporarily hold information (such as instructions and / or address values). The processor circuit may include various additional circuits not illustrated, such as one or more execution circuits, load-store circuits, instruction decoding circuits, and branch prediction circuits.

[0033] exist Figure 1 In the description of , the change of instructions in the instruction buffer may be different based on the type of control transfer function retrieved by the instruction fetch circuit. Figures 2 to 4 Three examples of control transfer instruction types that result in changes to instructions in the instruction buffer are presented in FIG.

[0034] Move to Figure 2 , a block diagram showing an embodiment of a system when an acquisition group is associated with a return acquisition group. System 200 may correspond to system 100 and include Figure 1 The system 200 includes an instruction fetch circuit 101 and an instruction cache circuit 110. In addition, the system 200 includes an instruction buffer circuit 220, a return fetch stack circuit 230, and a return address stack 235. The circuits of the system 200 may be coupled via a plurality of bus conductors. The system 200 depicts how the instructions of the fetch group may be changed in response to determining that the type of control transfer instruction in the fetch group is a call instruction.

[0035] As illustrated, the instruction cache circuit 110 includes cached instructions 260 at a given point in time. In the manner described above, the instruction acquisition circuit 101 is configured to retrieve an acquisition group 265 from the cached instructions 260 in the instruction cache circuit 110. The acquisition group 265 includes a plurality of instructions starting with a first instruction 268 until a last instruction 278 (including the first instruction and the last instruction). Between the first instruction 268 and the last instruction 278, the acquisition group 265 also includes a call instruction (call) 270 and a return target instruction 275. The call instruction 270 is a specific type of control transfer instruction in which program flow is transferred to a target address referenced by a call instruction (e.g., a program subroutine). The call instruction causes the address of the instruction immediately following the call instruction (referred to as a "return address") to be pushed onto a return address stack. When a return instruction (indicating the end of a subroutine) is later acquired, the return address is pulled from the return address stack and the instruction acquisition circuit 101 uses the return address to retrieve a new acquisition group.

[0036] In a typical system, instructions from the return address to the last instruction of the fetch group may be discarded, and a new fetch group may be retrieved based on the target of the call instruction. In the case where the subroutine to be executed is short (e.g., smaller than a full fetch group), the instruction fetch circuitry may retrieve the instructions at the return address in only one fetch after discarding these instructions, resulting in, for example, a reduction in the bandwidth of the system 200 due to retrieving the same set of instructions that were just fetched, thereby wasting cycles and power on fetch operations.

[0037] In this example, in response to determining that the control transfer instruction is a call instruction 270, the instruction fetch circuit 101 is configured to identify the return address 276 of the return target instruction 275 that comes after the call instruction 270 as the associated target address. The instruction fetch circuit 101 may then push the return address 276 onto the return address stack 235. In addition, the instruction fetch circuit 101 is further configured to store a first portion of the fetch group 265 (e.g., fetch group 265a) in the instruction buffer circuit 220, the first portion including instructions from the beginning of the fetch group 265 (the first instruction 268) to the call instruction 270. The instruction fetch circuit 101 is further configured to store a second portion of the fetch group 265 (fetch group 265b) in the return fetch stack circuit 230 (which is different from the instruction buffer circuit 220), the second portion starting with the return target instruction 275 at the return address 276.

[0038] In some cases, as shown, the acquisition group 265b includes all instructions from the return target instruction 275 to the last instruction 278. In other cases, another control transfer instruction may be included after the return target instruction 275 and before the last instruction 278, which may cause the instructions after the second control transfer instruction to be discarded, depending on the type of the second control transfer instruction. It should be noted that in the embodiment where the second control transfer function is included in the acquisition group 265b after the return target instruction 275, the branch history can be used to update the branch prediction circuit (not illustrated) for both the return instruction and the second control transfer instruction that triggers the return to the return target instruction 275. Contrary to the continuous generation of two branch history updates, these two branch history updates can be performed in a single update cycle.

[0039] As illustrated, the instruction fetch circuit 101 is further configured to retrieve a next fetch group based on the target address of the call instruction 270. The next fetch group may then be stored in the instruction buffer circuit 220 after the fetch group 265a, thereby allowing the execution circuit to execute the instructions of the fetch group 265a and then proceed directly to the subroutine at the target of the call instruction 270.

[0040] In response to fetching a return instruction after the call instruction 270, the instruction fetch circuit 101 is configured to pull a return address 276 from the return address stack 235 by signaling the end of the subroutine. As shown, the entry for the return address 276 in the return address stack 235 includes a return fetch stack (RFS) indicator 277, which indicates that the instructions for the return fetch group corresponding to the return address 276 have been stored in the return fetch stack circuit 230. In other embodiments, the instruction fetch circuit 101 may be configured to use the return address 276 (without the RFS indicator 277) to determine whether the entry in the return fetch stack circuit 230 corresponds to the return address 276. In response to determining that the fetch group 265b is stored in the return fetch stack circuit 230, the instruction fetch circuit 101 retrieves the fetch group 265b from the return fetch stack circuit 230 and writes the fetch group 265b to the instruction buffer circuit 220. In some embodiments, fetch group 265b is appended to the fetch group including the return instruction and may be treated as a single unified fetch group. Thus, instruction fetch circuitry 101 does not use instruction cache circuitry 110 to retrieve a fetch group corresponding to return address 276. Thus, use of return fetch stack circuitry 230 may reduce the power and time associated with fetching instructions associated with a return instruction.

[0041] In some embodiments, the instruction fetch circuit 101 may create an entry for a fetch group 265b in the return fetch stack circuit 230 in response to determining that a return instruction is within a specific number of instructions of the target of a call instruction. For example, if the specific number is sixteen, it may be determined whether there are fewer than sixteen instructions between the target of the call instruction (e.g., the beginning of a subroutine) and a subsequent return instruction (the end of the subroutine). The instruction fetch circuit 101 may utilize a training operation when the fetch group 265 is first retrieved. In the training operation, the return fetch stack circuit 230 may not be used, but the number of instructions between the target of the call instruction and the return instruction may be determined. If the number of instructions between the beginning and the end of the subroutine reaches a threshold number, an indication may be made (e.g., in the return fetch group tag circuit) and the indication may be linked to the specific target address of the call instruction. After the training operation, when a given call instruction has a specific target address, the instruction fetch circuit 101 is configured to use the described return fetch stack circuit 230.

[0042] Please note that Figure 2 The embodiment of is an example of a control transfer instruction type that causes a change in the instruction in the instruction buffer. For the sake of clarity, the system 200 has been simplified. Figure 1 As described, the illustrated circuit blocks may be included as part of a processor core, such as may also be included in an integrated circuit (e.g., a system on a chip (or “SoC” for short). Some or all of the instruction buffer circuit 220, the return fetch stack circuit 230, and / or the return address stack may be implemented as data structures in a memory circuit.

[0043] Go to Figure 3 , a block diagram of an embodiment of a system when an acquisition group is associated with a backward branch acquisition group. System 300 may correspond to system 100 and include Figure 1 The instruction fetch circuit 101 and the instruction cache circuit 110 and the instruction fetch circuit 101 and the instruction cache circuit 110 from Figure 2 The system 300 illustrates how instructions of a fetch group may be changed in response to determining that the type of control transfer instruction in the fetch group is a backward branch instruction.

[0044] At a given point in time, as shown in the figure, the instruction cache circuit 110 includes a cached instruction 360. The instruction acquisition circuit 101 is configured to retrieve an acquisition group 365 from the cached instruction 360 in the instruction cache circuit 110, as previously described. The acquisition group 365 begins with a first instruction 368 and ends with a last instruction 378. The acquisition group 365 also includes a backward branch instruction 370 and a branch target instruction 375. The backward branch instruction 370 can be a conditional control transfer instruction, in which the program flow is transferred to the branch target instruction 375 at the branch address 376 in response to a specific condition being true. If the condition is false, the program flow can continue in a sequential manner. The condition can correspond to a plurality of conditions tracked in a conditional code register, such as whether the value of the most recent access is zero, a negative value, or has caused an overflow. In some embodiments, the branch condition can be set or cleared based on the value of the indicated bit at a specific memory address. The backward branch instruction 370 may be used to implement a program loop in which a particular set of instructions is repeatedly executed until the condition of the backward branch instruction 370 is false, then the fetch group immediately following the last instruction of the loop (i.e., the backward branch instruction 370) is retrieved, and program flow resumes sequential order until a subsequent control transfer instruction is fetched.

[0045] In a typical system, instructions that come after the backward branch instruction 370 (e.g., the last instruction 378) may be discarded, and a new fetch group may be retrieved using the branch address 376. In the case where the loop to be executed is short (e.g., all instructions of the loop fit within the instruction buffer circuit 220), repeatedly retrieving instructions may waste both processing time and power. In some embodiments, such a short loop may be written to the instruction buffer circuit 220 once, and conventional branch prediction circuitry is used to predict the final iteration of the loop. In the final iteration, the fetch group that reaches the subsequent address may be fetched.

[0046] However, the branch prediction circuitry may have a finite size entry for collecting branch history, which is used to make predictions. In such cases, the final iteration may not be predicted, resulting in a misprediction, and thus wasting time and power to refresh the instruction buffer circuitry 220 and fetch the correct instruction. Additionally, after the backward branch instruction 370 has been identified as part of a short backward loop, then updates to the branch prediction circuitry may be omitted, especially in the case where the loop count for the short backward branch exceeds the size of the branch history entry.

[0047] For change Figure 3In the example of , the instruction fetch circuit 101 is configured to: in response to determining that the control transfer instruction is a backward branch instruction 370 and the number of instructions within the branch loop reaches a threshold limit, store the first part of the fetch group 365 (e.g., fetch group 365a) followed by the second part of the fetch group 365 (e.g., fetch group 365b) in the instruction buffer circuit 220. The first part and the second part of the fetch group 365 each include at least the instruction at the associated target address (branch target instruction 375) and the backward branch instruction 370. As shown, the branch loop (instructions from the branch target instruction 375 to the backward branch instruction 370 (including the branch target instruction and the backward branch instruction)) is repeated within the instruction buffer circuit 220 as fetch groups 365a and 365b. By including two copies of the branch loop (e.g., unrolling the loop once), accesses to the instruction cache circuit 110, the branch prediction circuit, and the next fetch predictor circuit, etc., can be reduced by up to 50%.

[0048] As illustrated, in order to determine that the control transfer instruction is a backward branch instruction, the instruction acquisition circuit 101 is configured to determine that the backward branch instruction 370 is taken more than a threshold number of consecutive times. For example, in some embodiments, if the number of iterations of the loop during the training operation (e.g., at the first occurrence of the loop during program execution) does not reach a threshold number of times, a short loop that may be small enough to be expanded once in the instruction buffer circuit 220 may not be expanded. In such cases, a single iteration of the loop is written to the instruction buffer circuit 220, and the branch prediction circuit is used during each iteration of the loop to predict the exit from the loop. Using the branch prediction circuit for each iteration when the number of loop iterations is low can reduce the possibility of misprediction at the end of the loop. However, when the number of loop iterations is high, the power and bandwidth saved by executing two iterations of the loop without accessing the branch prediction and next acquisition circuits may exceed the offset loss bandwidth and power due to misprediction. In the case where the loop count exceeds the historical capacity of the branch prediction circuit, the possibility of misprediction increases even if the loop is not expanded. Therefore, saving bandwidth and power when the possibility of misprediction is high can provide overall system benefits in terms of bandwidth and reduce power consumption.

[0049] Note that system 300 is another example of a type of control transfer instruction that results in a change to an instruction in an instruction buffer. For clarity, circuitry of system 300 is omitted. For example, while branch prediction and next fetch predictor circuitry is disclosed, these circuits are not shown in FIG. Figure 3 is ignored in the present invention, but may be included in other embodiments. Figure 1 As described, the illustrated circuit blocks may be included as part of a processor core, such as may also be included in an integrated circuit.

[0050] Go to Figure 4 , a block diagram of an embodiment of a system in which a fetch group is associated with a forward branch fetch group is shown. System 400 may correspond to system 100, and is similar to systems 200 and 300, including Figure 1 and Figure 2 The instruction fetch circuit 101, the instruction cache circuit 110, and the instruction buffer circuit 220 of the system 400 illustrate how the instructions of the fetch group may be changed in response to determining that the type of control transfer instruction in the fetch group is a forward branch instruction.

[0051] As illustrated, the instruction cache circuit 110 includes cached instructions 460 at a given point in time. In a similar manner as previously described, the instruction fetch circuit 101 is configured to retrieve a fetch group 465 from the cached instructions 460 in the instruction cache circuit 110. The fetch group 465 begins with a first instruction 468 and ends with a last instruction 478. The fetch group 465 also includes a forward branch instruction 470 and a branch target instruction 475. The forward branch instruction 470 can be a control transfer instruction in which program flow is transferred to the branch target instruction 475 at the branch address 476, thereby skipping one or more skipped instructions 477. In some embodiments, the forward branch instruction 470 can be a conditional branch instruction that bypasses the skipped instructions 477 only when the indicated condition is met.

[0052] In a typical system, instructions coming after forward branch instruction 470 (e.g., from skipped instruction 477 until last instruction 478) may be discarded and a new fetch group retrieved using branch address 476. In some cases, such as the present example, branch address 476 is included in fetch group 465. Discarding skipped instructions until last instruction 478 and then retrieving the instructions in a second fetch operation may waste both processing time and power.

[0053] For change Figure 4In the example of , the instruction fetch circuit 101 is configured to: store the first part of the fetch group 465 (e.g., fetch group 465a) in the instruction buffer circuit 220 in response to determining that the control transfer instruction is a forward branch instruction 470. As shown, the fetch group 465a includes instructions from the beginning of the fetch group 465 (the first instruction 468) to the forward branch instruction 470. The instruction fetch circuit 101 may also be configured to: identify the second part of the fetch group 465 (e.g., fetch group 465b), which starts with the instruction at the associated target address (branch address 476). Depending on the instructions included in the fetch group 465, the fetch group 465b may include the branch target instruction 475 until the last instruction 478 (including the branch target instruction and the last instruction). However, if a control transfer instruction is included between the branch target instruction 475 and the last instruction 478, the last instruction 478 and other instructions may be omitted from the fetch group 465b.

[0054] In various embodiments, information about the forward branch instruction 470 may or may not be communicated to the branch prediction circuitry. In some embodiments, after the forward branch instruction 470 is identified as a short forward branch, branch history information may not be collected, which in turn may simplify the circuitry of the instruction fetch circuitry 101 and / or improve the efficiency of fetching and executing instructions. Once the forward branch instruction 470 has been identified, the branch prediction circuitry may not be used when subsequently fetching the forward branch instruction 470, and the identified forward branch instruction 470 may be processed by the instruction fetch circuitry 101 as described herein.

[0055] As illustrated, the instruction fetch circuit 101 is further configured to store fetch group 465b in the instruction buffer circuit 220 following fetch group 465a, omitting the skipped instruction 477 between the forward branch instruction 470 and the branch target instruction 475. By retaining the instructions in fetch group 465b, rather than discarding and subsequently re-fetching them, the instruction fetch circuit 101 may increase bandwidth and reduce power consumption of the system 400. Furthermore, handling the forward branch instruction 470 within the fetch group 465 eliminates a second fetch operation for retrieving the instructions of the fetch group 465b, thereby allowing branch prediction circuitry included in the system 400 to predict a second branch instruction that may be included in the fetch group 465b after the forward branch instruction 470. Thus, two branch instructions may be handled within a single fetch group.

[0056] Please note that Figure 4The system of provides another example of a control transfer instruction type that causes a change in the instruction in the instruction buffer. Similar to systems 100 to 300, some circuits of system 400 have been excluded to improve clarity. In other embodiments, for example, additional circuits (such as branch prediction circuits) may be included. As previously disclosed, the illustrated circuit blocks may be included as part of a processor core, such as may be included in an integrated circuit.

[0057] exist Figures 1 to 4 , various embodiments of a system for changing the order of instructions based on determining a particular type of control transfer instruction are shown. Various techniques may be used to determine that a particular type of control transfer instruction is included in a given fetch group. Figure 5 An example of making such a determination is depicted.

[0058] Now move to Figure 5 , illustrates a block diagram of an embodiment of a system for marking references to an acquisition address when determining that an acquisition group includes a particular type of control transfer instruction. System 500 may correspond to any of systems 100 to 400 described previously. System 500 includes Figure 1 The system 500 also includes a next fetch predictor circuit 505.

[0059] As illustrated, the system 500 includes an instruction cache circuit 110 configured to store a plurality of instructions 560. The instruction 560 includes instructions retrieved from an acquisition address 561 and included in an acquisition group 565. The instructions in the acquisition group 565 include an adopted branch instruction 570 that directs program flow to a branch target instruction 575 at a target address 576. In various embodiments, the target address 576 may come before or after the address of the adopted branch instruction 570, resulting in a forward branch or a backward branch. In other embodiments, the adopted branch instruction 570 may be a call instruction, and the branch target instruction 575 may be an instruction immediately following the call instruction (e.g., the target of a subsequent return instruction).

[0060] The next acquisition predictor circuit 505 is configured to use a specific acquisition address to predict the target address of the control transfer instruction in the acquisition group. As shown, the acquisition group 565 includes an adopted branch instruction 575, which directs the program flow to the target address 576. At time t0, the next acquisition predictor circuit 505 includes an entry corresponding to the acquisition address 561, which includes the next predicted target address 580 corresponding to the target address 576.

[0061] As illustrated, the instruction fetch circuit 101 is configured to use the fetch address 561 to retrieve a fetch group 565 from a plurality of instructions 560 in the instruction cache circuit 110. The instruction fetch circuit 101 is also configured to use the predicted target address 580 from the next fetch predictor circuit 505 to determine that the destination of the control transfer instruction (e.g., the taken branch instruction 570) is predicted to be taken and the associated target address 576 is included in the fetch group 565. For example, after the instruction fetch circuit 101 retrieves the fetch group 565, the next fetch predictor circuit 505 uses the fetch address 561 to predict the next fetch address. The entry corresponding to the fetch address 561 includes the predicted target address 580, which includes the target address 576 (the target of the taken branch instruction 570) at time t0. Therefore, the next fetch predictor circuit is configured to transmit the target address 576 to the instruction fetch circuit 101 for use as the next fetch address. However, the instruction fetch circuitry 101 may determine that the target address 576 is included in the current fetch group 565 .

[0062] In response to this determination, the instruction fetch circuitry 101 may also be configured to mark references to the fetch address 561 in the next fetch predictor circuitry 505. For example, the instruction fetch circuitry may mark the entry corresponding to the fetch address 561 in response to determining that both the taken branch instruction 570 and the branch target instruction 575 are included in the fetch group 565 after an initial search of the fetch group 565. As shown at time t1, a tag 585 is added to the entry for the predicted target address 580.

[0063] In some embodiments, after the instruction fetch circuitry 101 retrieves the next fetch group based on the target address 576, it may be determined that both the taken branch instruction 570 and the branch target instruction 575 are included in the fetch group 565. For example, before adding the tag 585 to the entry for the predicted target address 580, the instruction fetch circuitry 101 may be configured to perform the next fetch operation using the target address 576 as the fetch address. After determining that the target address 576 is in the fetch group 565, the instruction fetch circuitry 101 may be configured to determine whether a second control transfer instruction is included in the fetch group 565. If the second control transfer instruction is identified, the instruction fetch circuitry 101 may update the entry for the predicted target address 580 to include a target address 583 corresponding to the second control transfer instruction.

[0064] At a later point in time, the instruction fetch circuitry 101 may also be configured to retrieve a fetch group 565 (including the taken branch instruction 570) from the instruction cache circuitry 110 using the tag subsequent fetch address 561. In response to the tag 585, the instruction fetch circuitry 101 may bypass the next fetch predictor circuitry 505 to determine the target address of the taken branch instruction 570. For example, after a subsequent retrieval of the fetch group 565, the instruction fetch circuitry 101 may use the tag 585 to determine that the fetch group 565 includes the taken branch instruction 570 and the branch target instruction 575 at the associated target address 576. Since the instruction at the target address 576 has already been retrieved, the instruction fetch circuitry 101 may skip the retrieval of the next fetch group based on the target address 576.

[0065] In response to including tag 585 in the entry for predicted target address 580, instruction fetch circuitry 101 may be configured to store the first portion of fetch group 565 in an instruction buffer circuit (e.g., Figures 2 to 4 The instruction fetch circuit 101 may also be configured to store the second portion of the fetch group 565 in the instruction buffer circuit in an order different from the order in which the second portion was fetched relative to the first portion. The first portion may include the first instruction in the fetch group 565 up to and including the taken branch instruction 570. The second portion may be based on the target address 576 and the type of instruction that is the taken branch instruction 570. For example, as described with respect to Figures 2 to 4 As disclosed, the second part may include Figure 2 The instruction at the target of the call instruction as shown, or Figure 3 The repeated closing instructions included in the program loop are shown. Figure 4 As shown, the second portion may include instructions at the target of the forward branch instruction and exclude instructions between the taken forward branch instruction and the target of the taken forward branch instruction.

[0066] Please note that Figure 5 The system 500 is merely an example for demonstrating the disclosed concepts. In other embodiments, additional circuits may be included. For example, instruction buffer circuits (such as Figures 2 to 4 The instruction buffer circuit 220 shown in FIG. Figure 5 As previously described, any of the illustrated circuits may be included in an integrated circuit and implemented in whole or in part using any suitable combination of sequential and combinational logic circuits.

[0067] In summary, various embodiments of a system including an instruction fetch circuit are disclosed, the instruction fetch circuit being configured to: change the order of instructions fetched based on a determination that a control transfer function of a particular type is included. Broadly speaking, apparatus, systems, and methods are contemplated, wherein embodiments of the apparatus, for example, include an instruction cache circuit and an instruction fetch circuit. The instruction fetch circuit may be configured to: retrieve a fetch group including a plurality of instructions for execution by a processing circuit from the instruction cache circuit; and determine that the fetch group includes a control transfer instruction predicted to be taken. A target address associated with the control transfer instruction may be directed to an instruction within the fetch group. The instruction fetch circuit may also be configured to: based on the determination, change the instructions within the fetch group in a manner based on the type of the control transfer instruction.

[0068] In another example, to change the instructions within the fetch group, the instruction fetch circuit may be configured to: in response to determining that the control transfer instruction is a call instruction, identify the address of the instruction following the call instruction as the associated target address. The instruction fetch circuit may also be configured to: store a first portion of the fetch group in an instruction buffer circuit, the first portion including instructions from the beginning of the fetch group to the call instruction; and store a second portion of the fetch group in a return fetch stack circuit different from the instruction buffer circuit, the second portion starting with the instruction at the associated target address. The instruction fetch circuit may also be configured to: retrieve the next fetch group based on the target address of the call instruction.

[0069] In an example, to change the instructions within the fetch group, the instruction fetch circuitry may be configured to: in response to determining that the control transfer instruction is a backward branch instruction, store a first portion of the fetch group followed by a second portion of the fetch group in an instruction buffer. The first portion and the second portion of the fetch group may each include at least the instruction at the associated target address and the backward branch instruction. In an additional example, to determine that the control transfer instruction is a backward branch instruction, the instruction fetch circuitry is configured to: determine that the backward branch instruction has been taken for more than a threshold number of consecutive times.

[0070] In another example, to change the instructions within the fetch group, the instruction fetch circuitry may be configured to: store a first portion of the fetch group in the instruction buffer circuitry in response to determining that the control transfer instruction is a forward branch instruction. The first portion of the fetch group may include instructions from the beginning of the fetch group to the forward branch instruction. The instruction fetch circuitry may also be configured to: identify a second portion of the fetch group, the second portion beginning with the instruction at the associated target address; and store the second portion of the fetch group in the instruction buffer circuitry following the first portion, omitting instructions between the forward branch instruction and the instruction at the associated target address.

[0071] In another example, to make the determination, the instruction fetch circuitry may be configured to, after an initial search of the fetch group, mark references to the fetch address corresponding to the fetch group in response to determining that the control transfer instruction and the instruction at the associated target address are included in the fetch group. The instruction fetch circuitry may also be configured to, after a subsequent search of the fetch group, use the marked references to determine that the fetch group includes the control transfer instruction and the instruction at the associated target address.

[0072] In one example, the instruction fetch circuitry may be further configured to: after the initial retrieval of the fetch group, retrieve a next fetch group based on the associated target address. The instruction fetch circuitry may be further configured to: after the subsequent retrieval of the fetch group, skip retrieval of the next fetch group based on the associated target address.

[0073] Another example of the disclosed system includes an instruction cache circuit, a next fetch predictor circuit, and an instruction fetch circuit. The instruction cache circuit may be configured to store a plurality of instructions. The next fetch predictor circuit may be configured to use a particular fetch address to predict a target address of a control transfer instruction in a fetch group. The instruction fetch circuit may be configured to use the particular fetch address to retrieve the fetch group from the plurality of instructions in the instruction cache circuit; and to use the predicted target address from the next fetch predictor circuit to determine that the control transfer instruction is predicted to be taken and that the destination of the associated target address is included in the fetch group. The instruction fetch circuit may also be configured to mark a reference to the particular fetch address in the next fetch predictor circuit in response to the determination.

[0074] In another example, the instruction fetch circuitry may be further configured to: retrieve the fetch group from the instruction cache circuitry using the particular fetch address subsequent to the tag, including the control transfer instruction predicted to be taken; and bypass the next fetch predictor circuitry in response to the tagged reference to determine the target address of the control transfer instruction predicted to be taken. In an example, the instruction fetch circuitry may be further configured to: store a first portion of the fetch group in an instruction buffer circuitry in an order in which the first portion was fetched; and store a second portion in an instruction buffer circuitry in an order different from the order in which the second portion of the fetch group was fetched relative to the first portion. The second portion may be based on the target address and the type of the control transfer instruction predicted to be taken.

[0075] In another example, in response to determining that the control transfer instruction is a call instruction, the instruction acquisition circuit may be further configured to: identify an address subsequent to the address of the call instruction as the associated target address. In one example, in response to determining that the control transfer instruction is a backward branch instruction, the instruction acquisition circuit may be further configured to: determine that the associated target address corresponding to the target address of the backward branch is between the specific acquisition address and the address of the backward branch instruction, including the specific acquisition address and the backward branch instruction.

[0076] In another example, in order to mark the reference to the particular acquisition address, the instruction acquisition circuit may be further configured to determine that the backward branch instruction is taken more than a threshold number of consecutive times. In another example, in response to determining that the control transfer instruction is a forward branch instruction, the instruction acquisition circuit may be further configured to determine that the associated target address corresponding to the target address of the forward branch is between the address of the forward branch instruction and the last address of the acquisition group. The next acquisition predictor circuit may also be configured to determine whether a second transfer control instruction is included in the acquisition group after the forward branch instruction.

[0077] The above article about Figures 1 to 5 The described circuits and techniques can be implemented using a variety of methods. Figures 6 to 9 Four methods associated with handling specific types of control transfer instructions are described.

[0078] Now go to Figure 6 , illustrates a flow chart of an embodiment of a method for changing the order of instructions fetched based on the type of control transfer function determined. The method 600 may be used in conjunction with a computer circuit system, system, device, element, or component (such as Figures 1 to 5 Any of the systems 100 to 500) shown in the examples can be used in combination. Figure 1 The method 600 is described with reference to the system 100 as an example. Figure 1 References to elements in are included as non-limiting examples.

[0079] As illustrated, method 600 begins at 610 by retrieving, by instruction fetch circuitry, a fetch group including a plurality of instructions for execution by processing circuitry. For example, instruction fetch circuitry 101 retrieves instructions of fetch group 165 from instruction cache circuitry 110. As shown, fetch group 165 includes control transfer instruction 170 having target address 175.

[0080] Method 600 continues at 620 by determining, by the instruction fetch circuitry, that the fetch group includes a control transfer instruction that is predicted to be taken and that the control transfer instruction has an associated target address that is directed to an instruction included in the fetch group. For example, instruction fetch circuitry 101 determines that fetch group 165 includes control transfer instruction 170 having target address 175. Instruction fetch circuitry 101 may further determine that target address 175 is an address that falls within an instruction included in fetch group 165. In some embodiments, the target address 175 may be determined by identifying a tag (such as, for example, a tag included with the fetch address used to retrieve fetch group 165). Figure 5 Such a tag may be added to the corresponding acquisition address in response to a learning operation performed after an initial acquisition of acquisition group 165.

[0081] The method continues at 630 by changing the order of the instructions within the fetch group based on the determination in a manner based on the type of the control transfer instruction. The instructions may be written to an instruction buffer circuit (e.g., Figures 2 to 4 The reordering may be performed by re-arranging the execution order of the instructions when the instruction buffer circuit 220 in the fetch group 165 is used to change the order. In some cases, the reordering may include writing a first portion of the instructions to the instruction buffer, the first portion including instructions from the first instruction in the fetch group 165 up to and including the control transfer instruction 170 that is taken. The first portion may be followed by a second portion determined based on the type of instruction that is the control transfer instruction 170. Figures 7 to 9 Three example types of control transfer instructions are described.

[0082] Please note that Figure 6 The method of system 100 includes elements 610 to 630. Method 600 may end in block 630, or some or all of the blocks of the method may be repeated. For example, method 600 may return to block 610 to retrieve a subsequent acquisition group having a control transfer function of a particular type. In some cases, method 600 may be performed in parallel with other instantiations of the method. For example, an integrated circuit may include multiple instances of system 100. Multiple instances may perform method 600 in an overlapping manner.

[0083] Now go to Figure 7 , illustrates a flow chart of an embodiment of a method for changing the order of instructions fetched based on determining that a fetch group includes a call instruction. Similar to method 600, method 700 can be used in conjunction with any of the computer circuit systems, systems, devices, elements, or components disclosed herein (such as systems 100 to 500). In some embodiments, method 700 may correspond to or be included in the operations of blocks 620 and 630 of method 600. Figure 2The method 700 is described using the system 200 as an example. Figure 2 References to elements in are included as non-limiting examples.

[0084] As illustrated, method 700 begins at 710 by determining, by instruction fetch circuitry, that the control transfer instruction is a call instruction. As illustrated, method 700 begins after block 610 of method 600 has been executed, resulting in instruction fetch circuitry 101 having retrieved a fetch group 265. Instruction fetch circuitry 101 identifies the included control transfer instruction as being a call instruction 270. In some embodiments, identification of a call instruction 270 in a fetch group 265 may be performed during a training operation that occurs when a fetch group 265 is first retrieved. In such embodiments, a tag may be added to a fetch address reference for a fetch group 265, such as Figure 5 shown.

[0085] At 720, the method 700 continues by using the address of the instruction subsequent to the call instruction as the associated target address. The instruction acquisition circuit 101 can identify the address of the instruction (as shown, the return target instruction 275) immediately following the call instruction 270. The return target instruction 275 is located at the return address 276, so the return address 276 is used as the target address. The return address 276 is pushed onto the return address stack 235 to be used later when the return instruction corresponding to the call instruction 270 is acquired. In some embodiments, a return acquisition stack (RFS) indicator 277 is pushed onto the return address stack 235 together with the return address 276. The RFS indicator 277 can signal the instruction acquisition circuit 101 that the instruction for the associated return address is located in the entry in the return acquisition stack circuit 230, and therefore does not need to be acquired from the instruction cache circuit 110.

[0086] The method continues at 730 by storing a first portion of the fetch group in the instruction buffer circuit, the first portion including instructions from the beginning of the fetch group to the call instruction. The first portion of the fetch group 265 (fetch group 265a) includes instructions from the first instruction 268 up to and including the call instruction 270. The instructions of the fetch group 265a are written to the instruction buffer circuit 220 in the order in which they are to be executed by one or more execution circuits (e.g., execution order).

[0087] The method continues at 740 by storing a second portion of the fetch group in a return fetch stack circuit different from the instruction buffer circuit, the second portion starting with the instruction at the associated target address. The second portion of the fetch group 265 (fetch group 265 b) includes instructions from the return target instruction 275 up to and including the last instruction 278. The instructions of the fetch group 265 b are not discarded, but are written to entries in the return stack circuit 230 in execution order.

[0088] The method 700 proceeds to 750 by retrieving the next fetch group based on the target address of the call instruction. To execute the call instruction 270, the instructions included in the call instruction 270 starting at the call target address are fetched as the next fetch group. The instruction fetch circuit 101 may use the call target address to retrieve instructions from the instruction cache circuit 110. The fetched instructions may then be written to the instruction buffer circuit 220 in execution order after the fetch group 265a.

[0089] Method 700 may be performed at 760 by retrieving the second portion from the return fetch stack circuit in response to determining that the next fetch group includes a return instruction. The return instruction corresponding to the call instruction 270 may be included in the next fetch group retrieved using the call target address. In some embodiments, if the return instruction corresponding to the call instruction 270 is included in the next fetch group, the instruction fetch circuit 101 may only use the return fetch stack circuit 230. In the event that the corresponding return instruction is in a fetch group subsequent to the next fetch group (e.g., the subroutine associated with the call instruction 270 is long or includes further control transfer instructions that result in a subsequent fetch operation), the fetch group 265b may not be written to the return fetch stack circuit 230, and the RFS indicator 277 may not be included in the return address stack 235 with the return address 276.

[0090] However, if RFS indicator 277 is present (or a different indication is present for an entry in return fetch stack circuitry 230 associated with fetch group 235 b), fetch group 235 b is pulled from return fetch stack circuitry 230 and placed in execution order in instruction buffer circuitry 220. Thus, the instructions of fetch group 265 b are placed in instruction buffer circuitry 220 without having to re-fetch the instructions from instruction cache circuitry 110 after fetching the corresponding return instructions.

[0091] Note that method 700 includes elements 710 to 760. Method 700 may end in block 760, or some or all of the blocks of the method may be repeated. For example, method 700 may return to block 710 in response to a subsequent acquisition of a different call instruction. In some cases, method 700 may be performed in parallel with other instantiations of the method. In some embodiments, for example, a different call instruction may be acquired in block 750. In such cases, a second instantiation of method 700 (or a portion thereof) may be performed, for example, between the operations of blocks 750 and 760 of the first instantiation.

[0092] Move to Figure 8 , illustrates a flow chart of an embodiment of a method for changing the order of instructions fetched based on determining that a fetch group includes a backward branch instruction. In a manner similar to methods 600 and 700, method 800 can be used in conjunction with any of the computer circuit systems, systems, devices, elements, or components disclosed herein (such as systems 100 to 500). Figure 3 The method 800 is described with reference to the system 300 as an example. Figure 3 References to elements in are included as non-limiting examples.

[0093] As illustrated, method 800 begins at 810 by determining, by instruction fetch circuitry, that a fetch group includes a backward branch instruction having an associated target address within the fetch group. In a manner similar to method 700, method 800 begins after block 610 of method 600 has been executed, resulting in instruction fetch circuitry 101 having retrieved a fetch group 365. Instruction fetch circuitry 101 identifies the included control transfer instruction as being a backward branch instruction 370. As shown, backward branch instruction 370 includes a branch address 376 that directs program flow back to branch target instruction 375. In a manner similar to that described above with respect to block 710, in some embodiments, identification of backward branch instructions 370 in a fetch group 365 may be performed during a training operation that occurs when a fetch group 365 is first retrieved.

[0094] Method 800 may optionally continue by determining that the backward branch instruction has been taken more than a threshold number of consecutive times. In some embodiments, the operation of block 820 may be optional. In embodiments that include performing the operation of block 820, if the loop created by the backward branch instruction is repeated for more than a threshold number of consecutive times, the backward branch instruction may only be identified as one of a particular type of control transfer instruction. As described above with respect to Figure 3As described, adopting backward branch instruction 370 makes the instruction set from branch target instruction 375 until backward branch instruction 370 be repeated at least once.In some embodiments, backward branch instruction 370 can be a conditional branch instruction, and this conditional branch instruction continues to be adopted until the specified condition is invalid, causing to exit the loop.In other embodiments, backward branch instruction 370 can be an unconditional branch instruction, and different instructions in the loop can be conditional branch instructions, and this conditional branch instruction makes the loop exit when adopted, and otherwise allows program flow to remain in the loop.In some cases, the condition of exiting the loop can be that the value of the counter reaches a threshold value.When the threshold value is reached, exit the loop.If frame 820 is included, the observed number of loop iterations must reach the threshold number of times so that the method continues at 830.Otherwise, if the threshold value is not reached, method 800 can end.

[0095] Method 800 is performed at 830 by storing the first portion of the acquisition group followed by the second portion of the acquisition group in the instruction buffer, wherein the first portion and the second portion of the acquisition group each include at least the instruction at the associated target address and the backward branch instruction. In order to change the instructions of the acquisition group 365, the first portion of the acquisition group 365 (e.g., acquisition group 365a) includes instructions from the first instruction 368 to the backward branch instruction 370. It should be noted that the acquisition group 365a includes the full loop plus one or more instructions that are not included in the loop (e.g., the first instruction 368 that is not in the loop in this example). The second portion of the acquisition group 365 (e.g., acquisition group 365b) includes instructions that constitute the loop (e.g., from the branch target instruction 375 to the backward branch instruction 370).

[0096] By duplicating the instructions of the loop within instruction buffer circuit 220, accesses to other circuits used to determine the next fetch address (such as branch prediction circuits and / or next fetch predictor circuits) may be reduced because program flow continues to flow from fetch group 365a to fetch group 365b as long as the condition held in the loop remains true, so that such accesses may only be made at the end of fetch group 365b. Although mispredictions may occur when exiting the loop, the bandwidth and power saved due to the reduction in accesses to other circuits may offset the additional bandwidth and power consumed by the mispredictions, resulting in a net savings.

[0097] Please note that Figure 8The method of includes elements 810 to 830. Method 800 may end in block 830, or some or all of the blocks of the method may be repeated. For example, method 800 may return to block 810 in response to retrieving a backward branch instruction in a subsequent acquisition group. In some cases, method 800 may be performed in parallel with other instantiations of the method or other methods disclosed. For example, system 300 may include a multi-core processor and / or a multi-threaded processor core, in which case two processor cores or two threads in a single multi-threaded core may retrieve an acquisition group including a backward branch instruction in parallel. Therefore, two instances of method 800 may be executed by two cores (or multi-threaded cores) in an overlapping manner.

[0098] Go to Fig. 9 , illustrates a flow chart of an embodiment of a method for changing the order of instructions fetched based on determining that a fetch group includes a forward branch instruction. Similar to methods 600 to 800, method 900 can be performed by any of the computer circuit systems, systems, devices, elements, or components disclosed herein, such as systems 100 to 500. Figure 4 The method 900 is described with reference to the system 400 as an example. Figure 4 References to elements in are included as non-limiting examples.

[0099] As shown, method 900 begins at 910 by determining that a fetch group includes a forward branch instruction having an associated target address within the fetch group. As described for methods 700 and 800, method 900 begins after block 610 of method 600 has been executed, resulting in instruction fetch circuitry 101 having retrieved a fetch group 465. Instruction fetch circuitry 101 identifies the included control transfer instruction as being a forward branch instruction 470. As shown, forward branch instruction 470 includes a branch address 476 that directs program flow through one or more skipped instructions 477 to a branch target instruction 475. In a similar manner as described above for blocks 710 and 810, in some embodiments, identification of forward branch instructions 470 in a fetch group 465 may be performed during a training operation that occurs when a fetch group 465 is first retrieved.

[0100] Method 900 continues at 920 by storing, by instruction fetch circuitry, a first portion of the fetch group in instruction buffer circuitry, wherein the first portion of the fetch group includes instructions from the beginning of the fetch group to the forward branch instruction. To change the instructions of fetch group 465, a first portion of fetch group 465 (e.g., fetch group 465a) includes instructions from first instruction 468 to forward branch instruction 470. Fetch group 465a is written to instruction buffer circuitry 220 in execution order.

[0101] Method 900 continues at 930 by identifying, by the instruction fetch circuitry, a second portion of the fetch group, the second portion beginning with the instruction at the associated target address. The instruction fetch circuitry 101 determines that the target address for the forward branch instruction 470 is the branch address 476 at which the branch target instruction 475 is located. Beginning with the branch target instruction 475, the instruction fetch circuitry 101 identifies instructions to be included in the second portion of the fetch group 465 (e.g., fetch group 465b) up to and including the last instruction 478. However, in other embodiments, if the second taken control transfer instruction is located at or after the branch address 478 and before the address of the last instruction 478, the fetch group 465b may end before the last instruction 476.

[0102] The method further continues at 940 by storing, by the instruction fetch circuitry, the second portion of the fetch group in the instruction buffer circuitry following the first portion, omitting instructions between the forward branch instruction and the instruction at the associated target address. As illustrated, the fetch group is stored in the instruction buffer circuitry 220 by omitting the skipped instruction 477 between the forward branch instruction 470 and the branch target instruction 475 at the branch address 476. By omitting the skipped instruction 477, the instruction fetch circuitry 110 may be able to perform a next fetch operation and write the instructions retrieved from the next fetch operation into the remaining locations in the instruction buffer circuitry 220 that may have been occupied by the skipped instruction 477.

[0103] Note that method 900 includes elements 910 to 940. Method 900 may end in block 940, or may repeat some or all of the blocks of the method. For example, method 900 may return to block 910 in response to retrieving another forward branch instruction in a subsequent acquisition group. In the manner described above, any of the disclosed methods may be performed in parallel with other instantiations of the method or other disclosed methods.

[0104] Figures 1 to 9 Circuits and methods for a system (such as an integrated circuit) are illustrated, the system including an instruction fetch circuit configured to change the order of fetched instructions based on determining that a particular type of control transfer function is included in the fetched instructions. Any embodiments of the disclosed system may be included in one or more of a variety of computer systems, such as desktop computers, laptop computers, smart phones, tablet computers, and wearable devices. In some embodiments, the above circuits may be implemented on a system on a chip (SoC) or other type of integrated circuit. Fig.10A block diagram illustrating an embodiment of a computer system 1000 is illustrated in FIG. In some embodiments, computer system 1000 may include one or more of any of systems 100-500 disclosed.

[0105] In the illustrated embodiment, system 1000 includes at least one instance of a system on chip (SoC) 1006, which may include various types of processor circuits, such as a central processing unit (CPU), a graphics processing unit (GPU), or other communication structures, as well as interfaces to memory and input / output devices. The circuits included in SoC 1006 may be implemented using any suitable combination of sequential logic circuits and combinational logic circuits. In addition, registers and / or memory circuits (such as static random access memory (SRAM), data latches, and triggers, etc.) may be used in these circuits to temporarily hold information (such as instructions, addresses, and other such information). Some memories (such as cache circuits) may include content addressable memory (CAM) circuits. One or more of these processor circuits may correspond to an example of a system disclosed herein. In various embodiments, SoC 1006 is coupled to external memory circuit 1002, peripheral device 1004, and power source 1008.

[0106] A power source 1008 is also provided that supplies a supply voltage to the SoC 1006 and one or more supply voltages to the external memory circuit 1002 and / or the peripheral device 1004. In various embodiments, the power source 1008 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet computer, or other device). In some embodiments, more than one instance of the SoC 1006 is included (and more than one external memory circuit 1002 is also included).

[0107] The external memory circuit 1002 is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, etc., and / or low power versions of SDRAM, such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. In some embodiments, the external memory circuit 1002 may include non-volatile memory, such as flash memory (FRAM), ferroelectric random access memory (FRAM), or magnetoresistive RAM (MRAM). One or more memory devices may be coupled to a circuit board to form a memory module, such as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), etc. Alternatively, the device may be installed together with an SoC or an integrated circuit in a chip stacking configuration, a package stacking configuration, or a multi-chip module configuration.

[0108] Peripheral devices 1004 include any desired circuitry, depending on the type of system 1000. For example, in one embodiment, peripheral devices 1004 include devices for various types of wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, peripheral devices 1004 also include additional storage, including RAM storage, solid-state storage, or disk storage. Peripheral devices 1004 include user interface devices such as display screens, including touch screens or multi-touch screens, keyboards or other input devices, microphones, speakers, etc.

[0109] As illustrated, system 1000 is shown to have applications in a wide range of fields. For example, system 1000 can be used as a part of a chip, circuit system, component, etc. of a desktop computer 1010, a laptop computer 1020, a tablet computer 1030, a cellular or mobile phone 1040, or a TV 1050 (or a set-top box coupled to a TV). Smart watches and health monitoring devices 1060 are also illustrated. In some embodiments, smart watches may include various general computing related functions. For example, smart watches may provide access to email, mobile phone services, user calendars, etc. In various embodiments, health monitoring devices may be dedicated medical devices or otherwise include dedicated health-related functionality. In various embodiments, the above-mentioned smart watches may include or may not include some or any health monitoring related functions. Other wearable devices 1060 are also envisioned, such as devices worn around the neck, devices attached to a hat or other helmets, devices implantable in the human body, glasses designed to provide enhanced and / or virtual reality experience, etc.

[0110] The system 1000 may also be used as part of a cloud-based service 1070. For example, the previously mentioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Still further, the system 1000 may be used in one or more devices in a home 1080 other than those previously mentioned. For example, a home appliance may monitor and detect noteworthy conditions. Various devices in a home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device and provide an alert to the homeowner (or, for example, a maintenance agency) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in a home and may automatically adjust the heating / cooling system based on a history of responses by the homeowner to various conditions. Fig.10 1090. For example, the system 1000 may be used for control and / or entertainment systems for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), etc. In various cases, the system 1000 may be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc.

[0111] Note that various potential applications of system 1000 may include various performance, cost, and power consumption requirements. Therefore, it may be beneficial to enable a scalable solution that can use one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption. These and many other embodiments are possible and contemplated. Note that Fig.10 The illustrated devices and applications are merely illustrative and are not intended to be limiting. Other devices are possible and contemplated.

[0112] As about Fig.10 As disclosed, computer system 1000 may include one or more integrated circuits included in a personal computer, smart phone, tablet computer, or other type of computing device. Fig.11 A process for designing and producing an integrated circuit using design information is shown in .

[0113] Fig.11 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. Fig.11 Embodiments of the present invention may be used in the design and manufacture of integrated circuits (e.g., including Figures 1 to 5 In the illustrated embodiment, the semiconductor manufacturing system 1120 is configured to process the design information 1115 stored on the non-transitory computer readable storage medium 1110 and manufacture the integrated circuit 1130 based on the design information 1115.

[0114] The non-transitory computer-readable storage medium 1110 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1110 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1110 may include other types of non-transitory memory or a combination thereof. The non-transitory computer-readable storage medium 1110 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0115] The design information 1115 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, and the like. The design information 1115 may be used by the semiconductor manufacturing system 1120 to manufacture at least a portion of the integrated circuit 1130. The format of the design information 1115 may be recognizable by at least one semiconductor manufacturing system, such as, for example, the semiconductor manufacturing system 1120. In some embodiments, the design information 1115 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in the integrated circuit 1130 may also be included in the design information 1115. Such cell libraries may include information indicating device or transistor level netlists, mask design data, characterization data, and the like of cells included in the cell library.

[0116] In various embodiments, integrated circuit 1130 may include one or more custom macrocells, such as memory and analog or mixed signal circuits, etc. In this case, design information 1115 may include information related to the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0117] Semiconductor manufacturing system 1120 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1120 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0118] In various embodiments, the integrated circuit 1130 is configured to operate according to the circuit design specified by the design information 1115, which may include performing any of the functionality described herein. For example, the integrated circuit 1130 may include any of the various elements shown or described herein. In addition, the integrated circuit 1130 may be configured to perform various functions described herein in conjunction with other components.

[0119] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0120] ***

[0121] The present disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," and "a specific embodiment," etc. do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0122] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuit systems outside the scope of the present disclosure, which, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0123] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The embodiments disclosed by the present invention are intended to be illustrative and non-restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0124] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0125] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0126] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0127] ***

[0128] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0129] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a group of two or more items.

[0130] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0131] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0132] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0133] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0134] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0135] The phrase "based on" or is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0136] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0137] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0138] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0139] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform the particular function.

[0140] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0141] ***

[0142] Different "circuits" may be described in the present disclosure. These circuits or "circuitry" constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. The circuitry may be custom designed or taken from a standard library. In various specific implementations, the circuitry may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuitry.

[0143] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of the circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For a person skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0144] In various embodiments, as discussed in the previous paragraphs, circuits, units and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may subsequently be synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0145] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0146] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. A device, comprising: instruction cache circuit; and An instruction fetch circuit, the instruction fetch circuit being configured to: retrieving from the instruction cache circuitry a fetch group comprising a plurality of instructions for execution by the processing circuitry; determining that the fetch group includes a control transfer instruction predicted to be taken, wherein a target address associated with the control transfer instruction is directed to an instruction within the fetch group; as well as Instructions within the fetch group are altered based on the determination in a manner that is based on a type of the control transfer instruction.

2. The apparatus of claim 1 , wherein to change the instruction within the fetch group, the instruction fetch circuit is configured to: In response to determining that the control transfer instruction is a call instruction: identifying the address of the instruction following the call instruction as the associated target address; storing a first portion of the fetch group in an instruction buffer circuit, the first portion comprising instructions from the beginning of the fetch group to the call instruction; and storing a second portion of the fetch group in a return fetch stack circuit distinct from the instruction buffer circuit, the second portion beginning with the instruction at the associated target address; and The next fetch group is retrieved based on the target address of the call instruction.

3. The apparatus of claim 1 , wherein to change the instruction within the fetch group, the instruction fetch circuit is configured to: responsive to determining that the control transfer instruction is a backward branch instruction, storing a first portion of the fetch group followed by a second portion of the fetch group in an instruction buffer; and The first portion and the second portion of the fetch group each include at least the instruction at the associated target address and the backward branch instruction. 4 . The apparatus of claim 3 , wherein to determine that the control transfer instruction is a backward branch instruction, the instruction fetch circuit is configured to: determine that the backward branch instruction is taken more than a threshold number of consecutive times.

5. The apparatus of claim 1 , wherein to change the instruction within the fetch group, the instruction fetch circuit is configured to: In response to determining that the control transfer instruction is a forward branch instruction: storing a first portion of the fetch group in an instruction buffer circuit, wherein the first portion of the fetch group includes instructions from the beginning of the fetch group to the forward branch instruction; identifying a second portion of the fetch group, the second portion beginning with an instruction at the associated target address; as well as The second portion of the fetch group is stored in the instruction buffer circuit subsequent to the first portion, omitting instructions between the forward branch instruction and the instruction at the associated target address.

6. The apparatus of claim 1 , wherein to make the determination, the instruction fetch circuit is configured to: after an initial retrieval of the fetch group, marking a reference to a fetch address corresponding to the fetch group in response to determining that the control transfer instruction and the instruction at the associated target address are included in the fetch group; and Upon subsequent retrieval of the fetch group, the marked reference is used to determine that the fetch group includes the control transfer instruction and the instruction at the associated target address.

7. The apparatus according to claim 6, wherein the instruction fetch circuit is further configured to: After said initial retrieval of said get group, retrieving a next get group based on said associated target address; and After the subsequent retrieval of the get group, retrieval of the next get group is skipped based on the associated target address.

8. A method comprising: retrieving, by instruction fetch circuitry, a fetch group including a plurality of instructions for execution by the processing circuitry; determining, by the instruction fetch circuitry, that the fetch group includes a control transfer instruction predicted to be taken and that the control transfer instruction has an associated target address that leads to an instruction included in the fetch group; as well as An order of instructions within the fetch group is changed based on the determination in a manner that is based on a type of the control transfer instruction.

9. The method according to claim 8, wherein: In response to determining that the control transfer instruction is a call instruction, the changing includes: Using the address of the instruction subsequent to the call instruction as the associated target address; storing a first portion of the fetch group in an instruction buffer circuit, the first portion comprising instructions from the beginning of the fetch group to the call instruction; and A second portion of the fetch group is stored in a return fetch stack circuit distinct from the instruction buffer circuit, the second portion beginning with the instruction at the associated target address.

10. The method according to claim 9, further comprising: retrieving a next fetch group based on a target address of the call instruction; as well as The second portion is retrieved from the return fetch stack circuit in response to determining that the next fetch group includes a return instruction.

11. The method according to claim 8, wherein: In response to determining that the control transfer instruction is a backward branch instruction, the changing includes: A first portion of the fetch group followed by a second portion of the fetch group is stored in an instruction buffer, wherein the first portion and the second portion of the fetch group each include at least the instruction at the associated target address and the backward branch instruction.

12. The method according to claim 11, further comprising: The control transfer instruction is determined to be a backward branch instruction in response to determining that the backward branch instruction is taken more than a threshold number of consecutive times.

13. The method according to claim 8, wherein: In response to determining that the control transfer instruction is a forward branch instruction, the changing includes: The fetch group is stored in an instruction buffer circuit by omitting instructions between the forward branch instruction and the instruction at the associated target address.

14. A system, comprising: an instruction cache circuit configured to store a plurality of instructions; a next fetch predictor circuit configured to predict a target address of a control transfer instruction in a fetch group using the particular fetch address; and An instruction fetch circuit, the instruction fetch circuit being configured to: using the particular fetch address to retrieve the fetch group from the plurality of instructions in the instruction cache circuit; using the predicted target address from the next fetch predictor circuit to determine that the control transfer instruction is predicted to be taken and the destination of the associated target address is included in the fetch group; as well as A reference to the particular fetch address in the next fetch predictor circuit is marked in response to the determining.

15. The system of claim 14, wherein the instruction fetch circuit is further configured to: retrieving the fetch group from the instruction cache circuitry using the particular fetch address subsequent to the tag, including the control transfer instruction predicted to be taken; and The next fetch predictor circuit is bypassed in response to the marked reference to determine the target address of the control transfer instruction predicted to be taken.

16. The system of claim 15, wherein the instruction fetch circuit is further configured to: storing the first portion of the fetch group in an instruction buffer circuit in the order in which the first portion was fetched; and A second portion of the fetch group is stored in the instruction buffer circuit in an order different from the order in which the second portion was fetched relative to the first portion, wherein the second portion is based on the target address and a type of control transfer instruction predicted to be taken.

17. The system of claim 15, wherein: In response to determining that the control transfer instruction is a call instruction, the instruction fetch circuit is further configured to: An address subsequent to the address of the call instruction is identified as the associated target address.

18. The system of claim 15, wherein: In response to determining that the control transfer instruction is a backward branch instruction, the instruction fetch circuit is further configured to: The associated target address corresponding to the target address of the backward branch instruction is determined to be between the particular fetch address and the address of the backward branch instruction, inclusive.

19. The system of claim 18, wherein to mark the reference to the particular fetch address, the instruction fetch circuit is further configured to: determine that the backward branch instruction is taken more than a threshold number of consecutive times.

20. The system of claim 15, wherein: In response to determining that the control transfer instruction is a forward branch instruction, the instruction fetch circuit is further configured to: determining that the associated target address corresponding to the target address of the forward branch instruction is between the address of the forward branch instruction and a last address of the fetch group; and Wherein the next fetch predictor circuit is further configured to determine whether a second pass control instruction is included in the fetch group after the forward branch instruction.

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