Reception circuit, power storage group, reception method, reception program, and storage medium on which reception program is recorded

Abstract

A first resistor (R1) is connected to a non-inverting input terminal of the comparator (CP). A second resistor (R2) is connected to a feedback path between the output terminal and the non-inverting input terminal of the comparator (CP). A capacitor (C1) is connected between a connection point between the first resistor (R1) and the non-inverting input terminal of the comparator (CP) and a low-side fixed potential. A binary voltage representing information of a plurality of bits is input as an input signal to an inverting input terminal of a comparator (CP). An input signal of a binary voltage is input to a non-inverting input terminal of a comparator (CP) via a low-pass filter including a first resistor (R1) and a capacitor (C1).

Description

Technical Field

[0001] The present disclosure relates to a receiving circuit, a power storage pack, a receiving method, and a receiving program for receiving a binary voltage representing a plurality of bits of information. Background Art

[0002] In recent years, electric power-assisted bicycles have become popular. Electric power-assisted bicycles use portable battery packs that can be easily loaded and unloaded. In order to remove the terminals for communication lines from the connector of the battery pack, a system has been developed in which a wireless communication function is installed in the battery pack and the electric power-assisted bicycle, and a control signal is transmitted wirelessly.

[0003] If there are multiple electric-assisted bicycles within the range of wireless communication with the battery pack, the installed battery pack may be mistakenly controlled by other vehicles adjacent to the vehicle, and the safety and reliability of the entire system cannot be ensured. In particular, in rental services and sharing services, there are many cases where multiple electric-assisted bicycles are parked in a parking lot. In order to safely and reliably operate the entire system, each electric-assisted bicycle needs to accurately identify the installed battery pack.

[0004] It is possible to consider that the battery pack supplies power to the vehicle through the power line and superimposes the identification information on the power line through a binary current (other than zero) or a binary voltage (other than zero). On the receiving side, the measured value of the current or voltage is compared with a threshold value, and the measured value above the threshold value is set to 1, and the measured value below the threshold value is set to 0 to receive the identification information.

[0005] However, due to the deviation of component characteristics and the change of consumption current, the measured value of current or voltage may be offset, and it may not be possible to accurately receive identification information. The factors that cause the current or voltage to change superimposed on the power line are long-term and short-term fluctuation factors. Long-term fluctuation factors include individual differences in electronic components and changes over time. Long-term fluctuation factors are generally caused by fluctuations in DC components. Short-term fluctuation factors include unexpected changes in load current such as intermittent operation of microcontrollers. Short-term fluctuation factors are caused by changes in AC components, and current fluctuations or voltage fluctuations in one packet belong to this category.

[0006] Patent Document 1 discloses a method of switching a load resistance using a switch to switch a current threshold according to the magnitude of a communication current.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: International Publication No. 18 / 173173 Summary of the invention

[0010] In the method disclosed in Patent Document 1, the number of current thresholds that can be switched depends on the number of load resistors and switches. Therefore, in order to increase the number of current thresholds that can be switched, the circuit scale needs to be increased. In addition, the switching of the current threshold is switching between fixed values. In addition, it is difficult to cope with short-term fluctuation factors.

[0011] The present disclosure has been made in view of such circumstances, and an object of the present disclosure is to provide a technology for reducing bit errors when receiving a binary voltage representing a plurality of bits of information.

[0012] In order to solve the above problem, a receiving circuit of a certain mode of the present disclosure comprises: a comparator; a first resistor connected to the non-inverting input terminal of the comparator; a second resistor connected to the feedback path between the output terminal of the comparator and the non-inverting input terminal; and a capacitor connected between the connection point between the first resistor and the non-inverting input terminal of the comparator and a fixed potential on the low side. A binary voltage representing multiple bits of information is input as an input signal to the inverting input terminal of the comparator, and the input signal of the binary voltage is input to the non-inverting input terminal of the comparator via a low-pass filter including the first resistor and the capacitor.

[0013] Furthermore, optional combinations of the above-described constituent elements and modes in which the present disclosure is expressed in the form of devices, systems, methods, computer programs, recording media storing the computer programs, and the like may also be practiced as additional modes of the present disclosure.

[0014] According to the present disclosure, it is possible to reduce bit errors when receiving a binary voltage representing a plurality of bits of information. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The figure shows an electric assist bicycle equipped with a battery pack according to the embodiment.

[0016] Figure 2 This is a diagram for explaining an overview of a first example of an authentication process for a battery pack mounted on a vehicle.

[0017] Figure 3 It is a diagram showing a first configuration example of a battery pack and a vehicle according to an embodiment.

[0018] Figure 4 This is a diagram for explaining an overview of a second example of an authentication process for a battery pack mounted on a vehicle.

[0019] Figure 5 It is a diagram showing a second configuration example of a battery pack and a vehicle according to the embodiment.

[0020] Fig. 6A This is a diagram showing an example of a transmission current and a reception current superimposed on a power line.

[0021] Figure 6B This is a diagram showing an example of a transmission current and a reception current superimposed on a power line.

[0022] Figure 7 It is a diagram showing a configuration example of a first ID detection circuit.

[0023] Figure 8 It shows the direction Figure 7 FIG. 1 is a diagram showing an example of waveforms of the reception current I input to the first ID detection circuit and the threshold value Ith.

[0024] Fig. 9 It is shown Figure 7 A diagram showing a specific configuration example of a first ID detection circuit.

[0025] Fig.10 The graph shows the relationship between the input voltage Vin and the high-side threshold value VthH and the relationship between the input voltage Vin and the low-side threshold value Vth when the first resistor R1 = 18.0 kΩ and the second resistor R2 = 47.0 kΩ.

[0026] Fig.11A It is shown Fig. 9 FIG. 1 is a diagram of a simulation waveform of the first ID detection circuit shown.

[0027] Fig. 11B It is shown Fig. 9 FIG. 1 is a diagram of a simulation waveform of the first ID detection circuit shown.

[0028] Fig.12 : is a diagram showing simulation waveforms of the input voltage Vin and the threshold value Vth according to the comparative example. DETAILED DESCRIPTION

[0029] Figure 1 1 is a diagram showing an electric assist bicycle equipped with a battery pack according to an embodiment. The battery pack 10 is a portable / replaceable battery pack 10 that can be installed in a mounting slot of a vehicle 20 or a charger (not shown). In the following, an electric assist bicycle is assumed as the vehicle 20 in the embodiment.

[0030] The replaceable battery pack 10 is frequently attached and detached from the mounting slot of the vehicle 20 or the charger, so the connector portion of the battery pack 10 is prone to deterioration. Therefore, in this embodiment, a wireless communication function is installed in the battery pack 10, and control signals are transmitted by wireless communication. As a result, the terminals for the communication line can be removed from the connector of the battery pack 10, and only the terminals for the power line can be used.

[0031] The wireless communication between the vehicle 20 and the battery pack 10 uses short-range wireless communication. As short-range wireless communication, Bluetooth (registered trademark), Wi-Fi (registered trademark), infrared communication, etc. can be used. In the following, in this embodiment, it is assumed that BLE (Bluetooth Low Energy) is used as the short-range wireless communication.

[0032] BLE is one of the extended standards of Bluetooth and is a low-power short-range wireless communication standard using the 2.4 GHz frequency band. BLE has low power consumption to the extent that it can be driven by a button battery for several years, so it is suitable for battery driving and can minimize the impact on the remaining capacity of the battery pack 10. In addition, modules for BLE communication are available in large quantities on the market, so they can be obtained at a low cost.

[0033] When using a general level 2 device, the radio wave reach range of BLE is about 10m. Therefore, there may be a situation where multiple vehicles 20 and multiple battery packs 10 exist within one communication range of BLE. In this case, radio wave interference may occur between vehicle systems, making the operation unstable. In addition, the vehicle 20 may be mistakenly connected to a battery pack 10 other than the battery pack 10 installed on itself, in which case the uninstalled battery pack 10 may be mistakenly controlled.

[0034] Therefore, a mechanism is required to ensure that the battery pack 10 installed in the vehicle 20 and the battery pack 10 that is the communication object of the vehicle 20 are the same battery pack 10. In the present embodiment, identification information (ID) is used to confirm the identity of the battery pack 10 that is physically connected to the vehicle 20 by wire and the battery pack 10 that is connected to the vehicle 20 by wireless communication. The identification information (ID) may be identification information inherent to each vehicle 20 or each battery pack 10, or may be temporary identification information. As inherent identification information, for example, a BD (Bluetooth Device) address or a MAC (Medium Access Control) address may be used.

[0035] Figure 2 This is a diagram for explaining an overview of example 1 of the authentication process of the battery pack 10 mounted on the vehicle 20. When the connector of the battery pack 10 is connected to the connector of the mounting slot of the vehicle 20, the vehicle 20 transmits ID1 to the battery pack 10 via a wired method. When the battery pack 10 receives ID1 via a wired method, it transmits a broadcast data packet (beacon packet) including the received ID1 and its own battery pack ID via short-range wireless communication. The broadcast data packet is a signal for notifying the surroundings of its own presence via short-range wireless communication.

[0036] When the vehicle 20 receives a broadcast data packet, it compares the ID1 contained in the broadcast data packet with the ID1 sent to the battery pack 10 via a wired method. When the two are consistent, the vehicle 20 authenticates that the installed battery pack 10 is the same as the communication object of the short-range wireless communication. When the two are inconsistent, the vehicle 20 determines that the installed battery pack 10 is different from the communication object of the short-range wireless communication, and the battery pack 10 as the communication object has not passed the authentication. For example, when a broadcast data packet containing ID2 is received, it is inconsistent with the ID1 sent to the battery pack 10 via a wired method, so the battery pack 10 as the transmission target of the broadcast data packet containing ID2 has not passed the authentication.

[0037] Figure 3 1 is a diagram showing a first configuration example of a battery pack 10 and a vehicle 20 according to the embodiment. Figure 3 The structure example 1 shown corresponds to the authentication processing example 1. Figure 3 The components required for the authentication processing example 1 are depicted, and components irrelevant to the authentication processing example 1 are omitted as appropriate. Figure 3 It is assumed that the battery pack 10 is mounted on the vehicle 20 .

[0038] The battery pack 10 includes a storage battery 11, a first relay 12, a first current sensor 13, a first power supply circuit 14, a first control unit 15, a first wireless communication unit 16, a first antenna 17, a first ID detection circuit 19, and a power supply terminal T1. The vehicle 20 includes a motor 21, an inverter 22, a second relay 23, a second power supply circuit 24, a second control unit 25, a second wireless communication unit 26, a second antenna 27, a second ID superimposition circuit 28, and a power receiving terminal T2. When the battery pack 10 is mounted on the vehicle 20, the power supply terminal T1 and the power receiving terminal T2 are in physical contact, and the power line Lp1 in the battery pack 10 and the power line Lp2 in the vehicle 20 are connected.

[0039] The storage battery 11 includes a plurality of cells connected in series or in series-parallel. The cells can be lithium-ion cells, nickel-metal hydride cells, lead-acid cells, etc. In the following, in this specification, it is assumed that a lithium-ion cell (nominal voltage: 3.6V-3.7V) is used. The number of cells connected in series is determined according to the driving voltage of the motor 21 of the vehicle 20.

[0040] The first relay 12 is inserted into the power line Lp1 that connects the battery 11 and the power supply terminal T1. In addition, other types of switches such as semiconductor switches may be used instead of the relay.

[0041] The first current sensor 13 measures the current flowing in the power line Lp1 in the battery pack 10 and outputs the current to the first ID detection circuit 19. The first current sensor 13 is composed of, for example, a combination of a shunt resistor and an amplifier. The voltage across the shunt resistor inserted in the power line Lp1 is amplified by the amplifier, thereby outputting a voltage value corresponding to the current flowing in the power line Lp1 from the first current sensor 13. In addition, a Hall element or a CT sensor may be used instead of the shunt resistor.

[0042] The first power supply circuit 14 is a DC / DC converter that steps down the voltage of the battery 11 to generate a power supply voltage (for example, about 3.3V to 5V) for the first control unit 15 and a power supply voltage (5V in the specific example below) for the first ID detection circuit 19. The first power supply circuit 14 may be composed of a switching regulator or a linear regulator.

[0043] The first control unit 15 is a microcontroller that controls the entire battery pack 10. The first control unit 15 monitors the state of the storage battery 11 (specifically, the voltage, current, and temperature of each single cell included in the storage battery 11). The first control unit 15 estimates the SOC (State Of Charge), FCC (Full Charge Capacity), and SOH (State Of Health) of each single cell included in the storage battery 11 based on these monitoring data. In addition, when the single cell included in the storage battery 11 generates overvoltage, undervoltage, overcurrent, high temperature abnormality, or low temperature abnormality, the first control unit 15 disconnects the first relay 12 to protect the single cell.

[0044] The first wireless communication unit 16 performs short-range wireless communication processing. In this embodiment, the first wireless communication unit 16 is composed of a BLE module, and the first antenna 17 is composed of a patch antenna or a pattern antenna built into the BLE module. The first wireless communication unit 16 outputs the data received through short-range wireless communication to the first control unit 15, and transmits the data input from the first control unit 15 through short-range wireless communication.

[0045] In the present embodiment, the vehicle 20 includes a three-phase AC motor as a driving motor 21. The inverter 22 converts the DC power supplied from the battery pack 10 into AC power during power operation and supplies it to the motor 21. During regeneration, the AC power supplied from the motor 21 is converted into DC power and supplied to the battery pack 10. During power operation, the motor 21 rotates according to the AC power supplied from the inverter 22. During regeneration, the rotational energy based on deceleration is converted into AC power and supplied to the inverter 22.

[0046] The second relay 23 is inserted in the power line Lp2 that connects the inverter 22 and the power receiving terminal T2. In addition, other types of switches such as semiconductor switches may be used instead of the relay.

[0047] The second power supply circuit 24 is a DC / DC converter that generates a power supply voltage (for example, about 3.3V to 5V) for the second control unit 25 by stepping down the voltage supplied from the storage battery 11 in the battery pack 10 installed in the vehicle 20. The second power supply circuit 24 can be composed of a switching regulator or a linear regulator. In this embodiment, the vehicle 20 is not equipped with a self-contained battery (for example, a lead battery) for generating a control power supply. Therefore, it is necessary to generate a control power supply from the driving power supply supplied from the storage battery 11 in the installed battery pack 10.

[0048] The second control unit 25 is a microcontroller that controls the entire vehicle 20. The second wireless communication unit 26 performs short-range wireless communication processing. In this embodiment, the second wireless communication unit 26 is composed of a BLE module, and the second antenna 27 can be composed of a patch antenna or a pattern antenna built into the BLE module. The second wireless communication unit 26 outputs the data received through short-range wireless communication to the second control unit 25, and transmits the data input from the second control unit 25 through short-range wireless communication.

[0049] The second ID superimposing circuit 28 superimposes the ID on the current flowing in the power line Lp2. The ID is defined by a plurality of bits, and each bit is represented by a binary current. When the power supply of the second control unit 25 is not received from the self-contained battery built into the vehicle 20 but from the storage battery 11 of the battery pack 10, the power on and off of the current flowing from the storage battery 11 to the vehicle 20 cannot be allocated to the binary current representing each bit of the ID. Therefore, the binary current representing each bit needs to be set to two current values ​​other than zero.

[0050] The second ID superimposition circuit 28 includes two loads having different resistance values, and one or more switches for selecting one of the two loads or making the two loads non-conductive. Alternatively, the second ID superimposition circuit 28 may include a variable load that can be switched to two resistance values, and one or more switches for switching the resistance value of the variable load or making the variable load non-conductive.

[0051] When the second relay 23 is disconnected, the current flowing in the power line Lp2 depends roughly on the current consumption of the second control unit 25. When the second relay 23 is disconnected, the second control unit 25 sets the ID to the second ID superimposition circuit 28. The second ID superimposition circuit 28 superimposes the bit "1" of the ID on the current by turning on the load with the smaller resistance value of the two loads, and superimposes the bit "0" of the ID on the current by turning on the load with the larger resistance value. Thus, the value of the current introduced to the vehicle 20 side changes according to each bit of the ID.

[0052] The first current sensor 13 of the battery pack 10 measures the current flowing in the power line Lp1 and outputs the current to the first ID detection circuit 19. The first ID detection circuit 19 detects the ID superimposed on the current flowing in the power line Lp1 based on the voltage value corresponding to the current measured by the first current sensor 13, and outputs the detected ID to the first control unit 15. A specific configuration example of the first ID detection circuit 19 will be described later.

[0053] Figure 4 This is a diagram for explaining an overview of authentication processing example 2 of a battery pack 10 mounted on a vehicle 20. When the connector of the battery pack 10 is connected to the connector of the mounting slot of the vehicle 20, the battery pack 10 transmits ID1 to the vehicle 20 via a wired method. At the same time, the battery pack 10 transmits a broadcast packet including ID1 via short-range wireless communication.

[0054] When the vehicle 20 receives a broadcast data packet, it compares the ID1 contained in the broadcast data packet with the ID1 received via a wired method. When the two are consistent, the vehicle 20 authenticates that the installed battery pack 10 is the same as the communication object of the short-range wireless communication. When the two are inconsistent, the vehicle 20 determines that the installed battery pack 10 is different from the communication object of the short-range wireless communication, and the battery pack 10 as the communication object has not passed the authentication. For example, when a broadcast data packet containing ID2 is received, it is inconsistent with the ID1 received via a wired method, so the battery pack 10 as the transmission target of the broadcast data packet containing ID2 has not passed the authentication.

[0055] Figure 5 1 is a diagram showing a second configuration example of a battery pack 10 and a vehicle 20 according to the embodiment. Figure 5 The structural example 2 shown corresponds to the authentication processing example 2. Figure 5 Components required for authentication processing example 2 are depicted, and components irrelevant to authentication processing example 2 are omitted as appropriate. In configuration example 1, ID is superimposed on the current flowing in the power line. In configuration example 2, ID is superimposed on the voltage of the power line.

[0056] exist Figure 5In the structural example 2 shown, compared with Figure 3 In the configuration example 1 shown, a first ID superimposition circuit 18 is provided on the battery pack 10 side, and a second ID detection circuit 29 and a voltage detection circuit 210 are provided on the vehicle 20 side. The first ID superimposition circuit 18 is constituted by an adder circuit using an operational amplifier, for example. The operational amplifier uses the voltage of the battery 11 as a power supply voltage, adds a base voltage lower than the power supply voltage to the ID voltage supplied from the first control unit 15, and outputs the added voltage to the power line Lp1. As a result, the value of the voltage supplied to the vehicle 20 side changes according to each bit of the ID.

[0057] The voltage detection circuit 210 on the vehicle 20 side measures the voltage of the power line Lp2 and outputs the voltage to the second ID detection circuit 29. The voltage detection circuit 210 is composed of, for example, a resistor voltage divider circuit, and the divided voltage is input to the second ID detection circuit 29. The second ID detection circuit 29 detects the ID superimposed on the voltage flowing in the power line Lp2 based on the voltage value measured by the voltage detection circuit 210, and outputs the detected ID to the second control unit 25.

[0058] exist Figure 3 In the configuration example 1 shown, the ID is transmitted from the vehicle 20 to the battery pack 10, so the vehicle 20 becomes the identification information transmitting device and the battery pack 10 becomes the identification information receiving device. Figure 5 In the configuration example 2 shown, the ID is transmitted from the battery pack 10 to the vehicle 20, so the battery pack 10 becomes the identification information transmitting device and the vehicle 20 becomes the identification information receiving device. Next, the identification information receiving device will be described based on the configuration example 1 using the current superposition method.

[0059] Fig. 6A , 6B This is a diagram showing an example of a transmission current and a reception current superimposed on a power line. Fig. 6A An example of a transmission current superimposed by an identification information transmission device is shown. Figure 6B An example of the received current detected by the identification information receiving device is shown. The identification information receiving device determines that the current value I is equal to or greater than the threshold value Ith, and determines that the current value I is equal to or less than the threshold value Ith. As an example, the threshold value Ith may be set to 50mA, the assumed value of the low level side of the current value I may be set to 30mA, and the assumed value of the high level side may be set to 70mA.

[0060] At this time, due to the deviation of component characteristics and the change of consumption current, it is possible to add an offset to the current value I. The deviation of component characteristics is caused by at least one of individual differences, temperature fluctuations, and changes over time. The unexpected change of consumption current of the identification information sending device (vehicle 20) is caused, for example, by the second control unit 25 starting some background processing or event processing (such as software update processing) during the authentication process using the second control unit 25 (microcontroller). In addition, the change of consumption current of the identification information sending device (vehicle 20) may also be caused by structural changes such as the lighting of the light of the identification information sending device (vehicle 20).

[0061] When the current consumption of the identification information transmitting device increases due to such a change in the system state or system structure, the current flowing in the power line increases. In other words, an offset is added to the current flowing in the power line. Due to this offset, errors may occur in the bit determination of the ID superimposed on the current flowing in the power line. Fig. 6A , 6B In the example shown, the ID superimposed on the current by the identification information transmitting device is "00101011110000011101", while the ID detected by the identification information receiving device based on the current is "00101011110000011111", and a bit error occurs in the second bit from the bottom. Next, a method for preventing ID bit determination errors and achieving stable communication by eliminating the influence of the offset superimposed on the current is described.

[0062] Figure 7 1 is a diagram showing a configuration example of the first ID detection circuit 19. The first ID detection circuit 19 includes a hysteresis comparator 191 and an inverter circuit 192. The hysteresis comparator 191 includes a comparator CP, a first resistor R1, a second resistor R2, and a first capacitor C1.

[0063] The comparator CP is an open collector or open drain type comparator.

[0064] The non-inverting input terminal of the comparator CP is connected to the first resistor R1. The second resistor R2 is connected to the feedback path between the output terminal and the non-inverting input terminal of the comparator CP. The first capacitor C1 is connected between the connection point between the first resistor R1 and the non-inverting input terminal of the comparator CP and the fixed potential on the low side (set to the ground potential in this embodiment).

[0065] The hysteresis comparator 191 is an inverting hysteresis comparator having Schmitt trigger characteristics by applying positive feedback. An input signal obtained by obtaining the current flowing in the power line as a voltage value is input to the inverting input terminal of the comparator CP. The input signal includes a binary voltage representing information of multiple bits. The ID specified by multiple bits is superimposed on the current flowing in the power line, and the ID is input to the inverting input terminal of the comparator CP as a binary voltage.

[0066] The input signal is input to the non-inverting input terminal of the comparator CP via a low-pass filter composed of a first resistor R1 and a first capacitor C1. That is, the value obtained by integrating the input signal is input to the non-inverting input terminal of the comparator CP. In this embodiment, the value obtained by integrating is used as a threshold value Ith for determining whether the input signal is a high level or a low level.

[0067] The inverting hysteresis comparator 191 outputs a low level when the input signal exceeds the threshold value Ith, and outputs a high level when the input signal is lower than the threshold value Ith. In the hysteresis comparator 191, the threshold value when the output signal is high and the threshold value when the output signal is low are different values. The threshold value of the former becomes the low-side threshold value, and the threshold value of the latter becomes the high-side threshold value, and the low-side threshold value and the high-side threshold value become the dead zone where the output is not inverted. When the input signal in the high-level state is lower than the low-side threshold value IthL, the output signal of the hysteresis comparator 191 changes from a low level to a high level. When the input signal in the low-level state exceeds the high-level threshold value IthH, the output signal of the hysteresis comparator 191 changes from a high level to a low level.

[0068] The inverting circuit 192 inverts the logic of the signal input from the hysteresis comparator 191 and outputs it. Specifically, the inverting circuit 192 outputs a low level when a high level is input from the hysteresis comparator 191, and outputs a high level when a low level is input.

[0069] Alternatively, the output signal of the hysteresis comparator 191 may be directly input to the analog input port of the first control unit 15 (microcontroller) without providing the inverting circuit 192. In this case, the logic of the output signal of the hysteresis comparator 191 is inverted in the control unit 15.

[0070] Figure 8 It shows the direction Figure 7 FIG. 1 is a diagram showing an example of waveforms of the reception current I input to the first ID detection circuit 19 and the threshold value Ith. Figure 8 In the example shown, different from Fig. 6A , 6BIn the example shown, the threshold value Ith changes dynamically according to the change of the received current I. The threshold value Ith changes in a manner that basically maintains the center of the amplitude of the high level and the low level of the received current I. As shown in period a, during the period when the received current I frequently repeats the high level and the low level, the threshold value Ith is maintained near the center of the amplitude of the received current I by the action of the low-pass filter. As shown in period b, during the period when the received current I continues to be at a high level or a low level, the threshold value Ith is maintained near the center of the amplitude of the received current I by the action of the Schmidt trigger. As shown in period c, when the received current I changes, the threshold value Ith follows the change of the received current I and is maintained near the center of the amplitude of the received current I after the change by the action of the low-pass filter and the Schmidt trigger.

[0071] Fig. 9 It is shown Figure 7 The high-side power supply terminal of the comparator CP is connected to the high-side fixed potential (at Fig. 9 In the example shown, VCC = 5 V), the low-side power supply terminal of the comparator CP is connected to the low-side fixed potential (in Fig. 9 The second capacitor C2 is connected between the high-side fixed potential and the low-side fixed potential. The second capacitor C2 is a bypass capacitor for noise removal.

[0072] The inverting circuit 192 includes a PNP transistor Tr, a first pull-up resistor Ra, a second pull-up resistor Rb, and a third resistor R3. The PNP transistor Tr and the third resistor R3 are connected in series between the high-side fixed potential and the low-side fixed potential. The emitter terminal of the PNP transistor Tr is connected to the high-side fixed potential, the collector terminal is connected to the third resistor R3, and the base terminal is connected to the output terminal of the comparator CP. The connection point between the PNP transistor Tr and the third resistor R3 becomes the output of the first ID detection circuit 19.

[0073] The first pull-up resistor Ra and the second pull-up resistor Rb are connected in series between the high-side fixed potential and the output terminal of the comparator CP. Specifically, the first pull-up resistor Ra is connected between the emitter terminal and the base terminal of the PNP transistor Tr, and the second pull-up resistor Rb is connected between the output terminal of the comparator CP and the base terminal of the PNP transistor Tr. The first pull-up resistor Ra and the second pull-up resistor Rb use the bias resistor of the PNP transistor Tr.

[0074] As the PNP transistor Tr, a digital transistor with two bias resistors built in may also be used. In addition, the two bias resistors may also be external. In addition, other pull-up resistors may be connected between the high-side fixed potential and the output terminal of the comparator CP instead of the two bias resistors.

[0075] Alternatively, a P-channel FET (Field Effect Transistor) may be used instead of the PNP transistor Tr. In this case, the source terminal of the P-channel FET is connected to the high-side fixed potential, the drain terminal is connected to the third resistor R3, and the gate terminal is connected to the output terminal of the comparator CP and the first pull-up resistor Ra.

[0076] Generally, the high-side threshold value VthH and the low-side threshold value VthL of the hysteresis comparator are defined by the following (Formula 1) and (Formula 2).

[0077] VthH=a·(R2 / R1)·Vref+aVOH… (Formula 1)

[0078] VthL=a·(R2 / R1)·Vref+aVOL… (Formula 2)

[0079] a=1 / (1+(R2 / R1))

[0080] VOH: Output voltage level of the comparator when it is at high level

[0081] VOL: Output voltage level of the comparator at low level

[0082] In the present embodiment, the reference voltage Vref applied to the first resistor R1 is the input voltage Vin, so the above (Formula 1) and (Formula 2) can be rewritten as the following (Formula 3) and (Formula 4).

[0083] VthH=a·(R2 / R1)·Vin+aVOH… (Formula 3)

[0084] VthL=a·(R2 / R1)·Vin+aVOL… (Formula 4)

[0085] Therefore, the voltage of the non-inverting input terminal of the comparator CP, that is, the threshold value Vth is defined by the following (Formula 5).

[0086] Vth=a·(R2 / R1)·Vin+aVO… (Formula 5)

[0087] In this way, the threshold Vth changes depending on whether the input voltage Vin and the output voltage VO of the comparator CP are at a high level or a low level. When the input voltage Vin is at a low level, the threshold Vth shifts upward, and when the input voltage Vin is at a high level, the threshold Vth shifts downward, thereby maintaining the threshold Vth near the center of the amplitude of the input voltage Vin.

[0088] In the comparator CP with an open collector, when the output voltage VO of the comparator CP is at a high level, the PNP transistor Tr becomes cut-off, and the output voltage Vout output from the connection point between the collector terminal of the PNP transistor Tr and the third resistor R3 becomes a low level. In this state, current flows from the power supply Vcc through the path of the first pull-up resistor Ra, the second pull-up resistor Rb, the second resistor R2, and the first resistor R1.

[0089] The current equation when the output voltage Vout is at a low level is defined by the following (Equation 6).

[0090] (Vin-Vth) / R1=(Vcc-Vth) / (R2+Ra+Rb)… (Formula 6)

[0091] On the other hand, when the output voltage VO of the comparator CP is at a low level, the PNP transistor Tr becomes conductive, and the output voltage Vout output from the connection point between the collector terminal of the PNP transistor Tr and the third resistor R3 becomes high level. In this state, current flows from the base terminal of the PNP transistor Tr through the inside of the comparator CP to the fixed potential on the low side.

[0092] The current equation when the output voltage Vout is at a high level is defined by the following (Equation 7).

[0093] (Vin-Vth) / R1=(Vth-O) / R2… (Formula 7)

[0094] The increase voltage ΔV+ of the threshold value Vth when the PNP transistor Tr is turned on is defined by the following (Formula 8).

[0095] △V+=(Ton / C1)·((Vcc-Vth) / (R2+Ra+Rb))… (Equation 8)

[0096] Ton: The conduction time of the PNP transistor Tr

[0097] The reduction voltage ΔV- of the threshold value Vth when the PNP transistor Tr is turned off is defined by the following (Formula 9).

[0098] △V-=(Toff / C1)·V / R… (Formula 9)

[0099] Toff: turn-off time of PNP transistor Tr

[0100] Next, the relationship between the constants of each element will be described. In the following description, the following design elements are assumed.

[0101] Communication speed: 9600bps = 4800Hz

[0102] Input voltage Vin range: 0V~5.0V

[0103] High level of input voltage Vin: 3.0V

[0104] Low level of input voltage Vin: 1.5V

[0105] Change in input voltage Vin due to load change: ±0.5V

[0106] High level of output voltage Vout: 4.0V~5.0V

[0107] Low level of output voltage Vout: 0V~0.5V

[0108] In this embodiment, each parameter is set as follows based on the above-mentioned design factors.

[0109] Pull-up power supply (Vcc): 5.0V

[0110] The first pull-up resistor Ra: 10.0 kΩ

[0111] Second pull-up resistor Rb: 10.0kΩ

[0112] First resistor R1: 18.0kΩ

[0113] Second resistor R2: 47.0kΩ

[0114] a=1 / (1+(R2 / R1)):0.28

[0115] VOH:4.9V

[0116] VOL:0.1V

[0117] Fig.10 The relationship between the input voltage Vin and the high-side threshold value VthH and the relationship between the input voltage Vin and the low-side threshold value Vth are shown in the graph when the first resistor R1 = 18.0 kΩ and the second resistor R2 = 47.0 kΩ. In stable operation, it is required that the high-side threshold value VthH when the input voltage Vin is at a low level is smaller than the high level of the input voltage Vin, and the low-side threshold value VthL when the input voltage Vin is at a high level is larger than the low level of the input voltage Vin. In addition, it is desired that the high-side threshold value VthH when the input voltage Vin is at a low level and the low-side threshold value VthL when the input voltage Vin is at a high level are as close as possible.

[0118] exist Fig.10In the example shown, when the low level of the input voltage Vin is 1.5 V, the high-side threshold VthH becomes approximately 2.24 V. 2.24 V is a value smaller than 3.0 V when the input voltage Vin is at a high level. When the high level of the input voltage Vin is 3.0 V, the low-side threshold VthL becomes approximately 2.19 V. 2.19 V is a value larger than 1.5 V when the input voltage Vin is at a low level.

[0119] When the load changes, the input voltage Vin must not exceed the output voltage level VOH when the comparator CP is at a high level, and must not fall below the output voltage level VOL when the comparator CP is at a low level, depending on the size of the assumed load change.

[0120] exist Fig.10 In the example shown, when the low level of the input voltage Vin decreases by -0.5V of the assumed load variation to 1.0V, it does not fall below the output voltage level VOL of the comparator CP at the low level, that is, 0.1V. On the other hand, when the high level of the input voltage Vin increases by +0.5V of the assumed load variation to 3.5V, it does not exceed the output voltage level VOH of the comparator CP at the high level, that is, 4.9V.

[0121] Based on the above considerations, the ratio (R2 / R1) of the resistance value of the second resistor R2 to the resistance value of the first resistor R1 is set within a range of 2 to 3. Fig. 9 , Fig.10 In the example shown, the ratio is 2.61. When the ratio is set to a value significantly deviated from the range of 2 to 3, the threshold value Vth in stable operation significantly deviates from the center of the amplitude of the input voltage Vin, and thus erroneous detection is likely to occur during load fluctuations.

[0122] In addition, the total resistance value of the first resistor R1 and the resistance value of the second resistor R2 is set to be three times or more the resistance value of the pull-up resistor (in this embodiment, the combined resistance value of the first pull-up resistor Ra and the second pull-up resistor Rb). Fig. 9 , Fig.10 In the example shown, the total resistance value of the first resistor R1 and the second resistor R2 is 65 kΩ, the resistance value of the pull-up resistor is 20 kΩ, and the total resistance value of the first resistor R1 and the second resistor R2 is set to 3.3 times the resistance value of the pull-up resistor.

[0123] When the resistance value of the pull-up resistor is large relative to the sum of the resistance values ​​of the first resistor R1 and the second resistor R2, the output voltage VO of the comparator CP may decrease when the output voltage Vout is at a low level, and the PNP transistor Tr may not be turned off. By setting the resistance value of the pull-up resistor to be more than three times the sum of the resistance values ​​of the first resistor R1 and the second resistor R2, the PNP transistor Tr can be driven normally.

[0124] The resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 are set so that the cutoff frequency fc defined by the resistance value of the first resistor R1 and the capacitance value of the first capacitor C1 is within the range of 1 / 10 to 1 / 5 of the frequency of the input voltage Vin.

[0125] exist Fig. 9 , Fig.10 In the example shown, the cutoff frequency fc of the low-pass filter is approximately 884 Hz, which is within the range of 1 / 10 to 1 / 5 of the 4800 Hz of the input voltage Vin. By setting the cutoff frequency fc of the low-pass filter to approximately 1 / 5 of the frequency of the input signal, the influence of short-term current fluctuations in a packet can be fully removed.

[0126] However, if the cutoff frequency fc of the low-pass filter is set too low, the tracking performance of the threshold Vth decreases, and the determination accuracy of the input voltage Vin decreases. For this reason, it is desirable that the lower limit of the cutoff frequency fc be set to about 1 / 10 of the frequency of the input signal.

[0127] exist Fig. 9 , Fig.10 In the example shown, the capacitance value of the second capacitor C2 is set to 0.1 uF, and the constant of a general bypass capacitor connected to the power supply terminal of an IC is used.

[0128] The resistance value of the third resistor R3 is selected in consideration of the dark current flowing in the third resistor R3 when the time for the output voltage Vout to become a high level becomes longer. For example, the resistance value of the third resistor R3 is set in the range of 10k to 100kΩ. Fig. 9 , Fig.10 In the example shown, it is set to 47.0 kΩ.

[0129] Fig.11A , Fig. 11B It is shown Fig. 9 FIG. 1 is a diagram of a simulation waveform of the first ID detection circuit 19 shown. Fig.11A The analog waveforms of the input voltage Vin and the threshold Vth are shown. Fig. 11B A simulation waveform of the output voltage Vout is shown.

[0130] Immediately after the power supply of the comparator CP is turned on, the threshold Vth is located below 1.5 V, which is the low level of the input voltage Vin. Fig.10 Since the VthH (about 2.24 V) at the time of the low-level input shown is different, there is a possibility that the first bit of the ID as the input signal may be erroneously detected.

[0131] In this embodiment, the identification information transmitting device superimposes a preset signal Pp on the power line for making the threshold Vth close to the center of the amplitude of the binary voltage representing the ID before transmitting the ID. The identification information receiving device receives the preset signal Pp before receiving the ID as the target input signal. Fig.11A In the example shown, a preset pulse of high level and low level is superimposed as the preset signal Pp. In addition, the pattern of the preset signal Pp and the time width between the preset signal Pp and the ID signal can be set to the optimal value by the designer based on experiments and simulations.

[0132] exist Fig.11A In the example shown, the threshold value Vth shifts to the approximate center of the amplitude of the input voltage Vin, and whether the input voltage Vin is at a high level or a low level can be accurately detected based on the threshold value Vth.

[0133] Fig.12 The simulation waveforms of the input voltage Vin and the threshold value Vth according to the comparative example are shown.

[0134] The comparative example is an example using a comparator CP that does not have Schmitt trigger characteristics and does not apply positive feedback to the comparator CP. The threshold Vth is basically intended to be maintained near the center of the amplitude of the input voltage Vin by the action of the low-pass filter, but in the interval where the high level of the input voltage Vin continues, the threshold Vth is attracted to the high level side, and in the interval where the low level of the input voltage Vin continues, the threshold Vth is attracted to the low level side.

[0135] Therefore, when a large load change occurs in the interval where the input voltage Vin is continuously high or low, a bit error is likely to occur. Fig.11A In the embodiment shown, even in the interval where the input voltage Vin is continuously high or low, the threshold Vth is maintained near the center of the amplitude of the input voltage Vin by the action of the Schmitt trigger. Therefore, bit errors due to fluctuations in the threshold Vth are less likely to occur.

[0136] As described above, the first ID detection circuit 19 is operated by the power of the battery 11. Since the first ID detection circuit 19 is used only when the battery pack 10 is installed in the vehicle 20, it is desirable to set a structure that can cut off the power supply to the first ID detection circuit 19 within a certain time (for example, 10 seconds) from the installation of the battery pack 10 to the completion of authentication. In this case, the power consumption of the battery 11 can be reduced.

[0137] In the above description, an example is shown in which the ID superimposed on the current flowing in the power line is detected by hardware processing of the first ID detection circuit 19. In this regard, the ID can also be detected by software processing based on the first control unit 15 (microcontroller). In this case, the first ID detection circuit 19 is omitted, and the input signal (input voltage Vin) corresponding to the current measured by the first current sensor 13 is directly input to the analog input port of the first control unit 15 (microcontroller).

[0138] The A / D converter in the first control unit 15 (microcontroller) converts the input signal into a digital value at a sampling rate higher than the clock frequency corresponding to the communication speed of the ID (for example, a sampling rate of 10 to 100 times the clock frequency). In order to accurately observe the waveform transition within the unit cycle of the input signal, high-speed sampling is required. The CPU in the first control unit 15 (microcontroller) integrates the digital input signal obtained by high-speed sampling to calculate the threshold value Vth. The CPU compares the calculated threshold value Vth with the input signal through Schmitt trigger action, and judges it as 1 when the input signal is above the threshold value Vth, and judges it as 0 when it is less than the threshold value Vth.

[0139] The ID detection process by software processing is effective when the communication speed of the ID is low.

[0140] On the other hand, when the communication speed of the ID is high, a high-performance control unit needs to be used for the first control unit 15 (microcontroller). In addition, a heat countermeasure is required. In the ID detection process based on software processing, it is easier to change the time constant than in the ID detection process based on hardware processing.

[0141] As described above, in this embodiment, the integral signal of the input signal based on the current superimposed with ID is set to the threshold value Vth, and the threshold value Vth is compared with the input signal based on the current through the Schmidt trigger action, thereby automatically eliminating the current fluctuation. At this time, the current fluctuation that dynamically follows the actual current fluctuation can be eliminated. More specifically, a low-pass filter is used to extract the DC component from the input signal based on the measured current and set it as the threshold value Vth, thereby removing the influence of long-term current fluctuations based on individual differences and changes over the years of electronic components. In addition, the influence of short-term current fluctuations in a packet can be fully removed by setting the cutoff frequency fc of the low-pass filter within the range of 1 / 10 to 1 / 5 of the clock frequency corresponding to the communication speed of the ID. Therefore, even if an unexpected current fluctuation occurs during current communication, stable communication can be performed. As a result, it is possible to reduce erroneous judgments when detecting ID based on the input signal based on the current.

[0142] In addition, compared to the method of switching the load resistance by a switch to switch the current threshold according to the size of the communication current (refer to patent document 1), the detection value of the input signal based on the current can be flexibly corrected, and the correction response range is also wide. In contrast, in the above method, the current threshold cannot be switched finely, so it is difficult to optimize the correction amount used to remove the influence of current fluctuations. In addition, the influence of short-term current fluctuations cannot be removed. In addition, the detection and threshold change of the communication current based on the control of a microcontroller, etc. are required, and there is no guarantee that a judgment can be made after the threshold is changed. In addition, a circuit for changing the threshold is required. In addition, the ID detection method involved in this embodiment can be implemented by a simple circuit or simple software, and has great advantages in actual use. There is no need to carry a load resistor and a switch as in the above method. In addition, the ID detection method involved in this embodiment has high versatility and a wide range of applications.

[0143] The first control unit 15 and the second control unit 25 are composed of, for example, a microcomputer mainly composed of a CPU (Central Processing Unit) and a memory. In other words, the first control unit 15 and the second control unit 25 are implemented by a computer having a CPU and a memory, and the CPU executes a program stored in the memory, so that the computer functions as the first control unit 15 and the second control unit 25. The program is recorded in advance in the memory of the control unit 5, but it can also be provided through a telecommunication line such as the Internet, or by recording in a (non-transitory) recording medium such as a memory card.

[0144] In addition, the above-mentioned program can also be recorded on a recording medium. If the recording medium is used, the above-mentioned program can be installed in the above-mentioned computer, for example. Here, the recording medium on which the above-mentioned program is recorded can also be a non-transient recording medium. The non-transient recording medium is not particularly limited, and can be, for example, a recording medium such as a CD-ROM.

[0145] The present disclosure has been described above based on the embodiments. The embodiments are illustrative, and it is easy for a person skilled in the art to understand that various modifications can be made to the combination of these components and processing steps, and such modifications are also within the scope of the present disclosure.

[0146] In the above embodiment, an example is described in which authentication is performed when the battery pack 10 installed in the installation slot of the vehicle 20 is the same as the battery pack 10 that is the communication target of the vehicle 20. In this regard, the ID detection method involved in the above embodiment can also be used when authentication is performed when the battery pack 10 installed in the installation slot of the charger is the same as the battery pack 10 that is the communication target of the charger. In this case, the charger may be the identification information transmitting device and the battery pack 10 may be the identification information receiving device, or the battery pack 10 may be the identification information transmitting device and the charger may be the identification information receiving device.

[0147] In the above embodiment, an example of using the battery pack 10 with built-in storage battery 11 is described. In this regard, a capacitor pack with built-in capacitors including electric double layer capacitor cells, lithium ion capacitor cells, etc. may also be used. In this specification, battery packs and capacitor packs are collectively referred to as storage packs.

[0148] The present disclosure is suitable for application to a vehicle 20 that is not equipped with a self-contained power supply, but does not exclude application to a vehicle 20 that is equipped with a self-contained power supply. Therefore, the vehicle 20 is not limited to an electric power-assisted bicycle, but also includes an electric motorcycle (electric scooter), an electric kickboard, an electric car (including a golf cart, a shuttle bus and other low-speed electric cars), a railway vehicle, etc. In addition, the object to which the power storage group is installed is not limited to the vehicle 20, for example, it also includes electric mobile bodies such as electric ships and multi-rotor aircraft (drones).

[0149] In the above embodiment, an ID detection circuit is described which receives identification information defined by a plurality of bits superimposed on the current or voltage of the power line as a binary voltage. Figure 7 or above Fig. 9 The circuit structure shown can also be applied to the case of receiving a binary voltage representing a plurality of bits of information other than identification information. Figure 7 or above Fig. 9The circuit shown in the figure that receives the binary voltage representing multiple bits of information not limited to identification information is called a receiving circuit. The receiving circuit is a concept that includes an ID detection circuit. The binary voltage representing multiple bits of information received by the receiving circuit may not be a binary voltage transmitted via a power line, but a binary voltage transmitted via a signal line or a binary voltage transmitted wirelessly.

[0150] The receiving circuit of the present disclosure is effective for applications where the amplitude range of the received binary voltage (Vin) is different from the amplitude range of the output binary voltage (Vout). For example, it is effective for applications where the amplitude range of the received binary voltage (Vin) is away from zero. As such, the receiving circuit of the present disclosure can reduce bit errors when receiving a binary voltage representing multiple bits of information.

[0151] Furthermore, the embodiment can also be determined by the following items.

[0152] [Project 1]

[0153] A receiving circuit (19), characterized by comprising:

[0154] Comparator (CP);

[0155] a first resistor (R1) connected to a non-inverting input terminal of the comparator (CP);

[0156] a second resistor (R2) connected to a feedback path between an output terminal of the comparator (CP) and the non-inverting input terminal; and

[0157] a capacitor (C1) connected between a connection point between the first resistor (R1) and the non-inverting input terminal of the comparator (CP) and a fixed potential on the low side,

[0158] wherein a binary voltage representing a plurality of bits of information is input as an input signal to an inverting input terminal of the comparator (CP),

[0159] The binary voltage input signal is input to a non-inverting input terminal of the comparator (CP) via a low-pass filter including the first resistor (R1) and the capacitor (C1).

[0160] According to this, it is possible to reduce bit errors when receiving a binary voltage representing a plurality of bits of information.

[0161] [Project 2]

[0162] The receiving circuit (19) according to item 1 is characterized in that:

[0163] A ratio of a resistance value of the second resistor (R2) to a resistance value of the first resistor (R1) is set within a range of 2 to 3.

[0164] According to this, the voltage (threshold) of the non-inverting input terminal during the stable operation can be maintained near the center of the amplitude of the binary voltage input signal.

[0165] [Item 3]

[0166] The receiving circuit (19) according to item 1 is characterized in that:

[0167] The comparator (CP) is an open collector or open drain comparator (CP),

[0168] The receiving circuit (19) further comprises:

[0169] a pull-up resistor (Ra, Rb) connected between an output terminal of the comparator (CP) and a fixed potential on a high side;

[0170] a PNP transistor (Tr) or a P-channel FET, a base terminal of the PNP transistor (Tr) being connected to the output terminal of the comparator (CP) and an emitter terminal being connected to the fixed potential of the high side, and a gate terminal of the P-channel FET being connected to the output terminal of the comparator (CP) and a source terminal being connected to the fixed potential of the high side; and

[0171] A third resistor (R3) is connected between the fixed potential on the low side and the collector terminal of the PNP transistor (Tr) or the drain terminal of the P-channel FET.

[0172] According to this, the output voltage of the comparator (CP) can be logically inverted to restore the logic of the input voltage, and the high level and low level of the output voltage can be easily matched with the power supply voltage range of the subsequent circuit.

[0173] [Item 4]

[0174] The receiving circuit (19) according to item 3 is characterized in that:

[0175] The total of the resistance value of the first resistor (R1) and the resistance value of the second resistor (R2) is set to be three times or more the resistance value of the pull-up resistor (Ra, Rb).

[0176] According to this, the PNP transistor (Tr) or the P-channel FET can be driven normally.

[0177] [Item 5]

[0178] The receiving circuit (19) according to item 3 is characterized in that:

[0179] The ratio of the resistance value of the second resistor (R2) to the resistance value of the first resistor (R1) is set in the range of 2 to 3.

[0180] The total of the resistance value of the first resistor (R1) and the resistance value of the second resistor (R2) is set to be three times or more the resistance value of the pull-up resistor (Ra, Rb).

[0181] This allows the voltage (threshold) of the non-inverting input terminal to be maintained near the center of the amplitude of the binary voltage input signal during stable operation, and allows the PNP transistor (Tr) or the P-channel FET to be driven normally.

[0182] [Item 6]

[0183] The receiving circuit (19) according to item 1 is characterized in that:

[0184] The resistance value of the first resistor (R1) and the capacitance value of the capacitor (C1) are set in such a manner that a cutoff frequency defined by the resistance value of the first resistor (R1) and the capacitance value of the capacitor (C1) is within a range of 1 / 10 to 1 / 5 of the frequency of the input signal.

[0185] This makes it possible to sufficiently eliminate the influence of short-term current fluctuations.

[0186] [Item 7]

[0187] The receiving circuit (19) according to item 1 is characterized in that:

[0188] Before receiving a target input signal, a preset signal for bringing a voltage of a non-inverting input terminal of the comparator (CP) close to a center of an amplitude of the input signal is received.

[0189] This can prevent erroneous determination immediately after activation of the comparator (CP).

[0190] [Item 8]

[0191] The receiving circuit (19) according to any one of items 1 to 7 is characterized in that:

[0192] The receiving circuit (19) receives, as a binary voltage, identification information defined by a plurality of bits, which is superimposed on the current or voltage of the power line by an identification information transmitting device (20) connected via the power line.

[0193] This can reduce erroneous determination when detecting identification information superimposed on the current or voltage of the power line.

[0194] [Item 9]

[0195] A portable power storage pack (10) that can be attached and detached freely comprises the receiving circuit (19) described in item 8.

[0196] According to this, it is possible to realize a power storage group (10) that reduces erroneous determination when detecting identification information superimposed on a current or voltage of a power line.

[0197] [Item 10]

[0198] A receiving method, characterized in that it comprises the following steps:

[0199] integrating a binary voltage representing a plurality of bits of information as an input signal; and

[0200] The input signal after the integration is used as a threshold value, and the threshold value is compared with the input signal through a Schmitt trigger action. When the input signal is greater than the threshold value, it is determined to be 1, and when the input signal is less than the threshold value, it is determined to be 0.

[0201] According to this, it is possible to reduce bit errors when receiving a binary voltage representing a plurality of bits of information.

[0202] [Item 11]

[0203] A receiving program, characterized in that it causes a computer to execute the following processing:

[0204] integrating a binary voltage representing a plurality of bits of information as an input signal; and

[0205] The input signal after the integration is used as a threshold value, and the threshold value is compared with the input signal through a Schmitt trigger action. When the input signal is greater than the threshold value, it is determined to be 1, and when the input signal is less than the threshold value, it is determined to be 0.

[0206] According to this, it is possible to reduce bit errors when receiving a binary voltage representing a plurality of bits of information.

[0207] Description of Reference Numerals

[0208] 10: battery pack; 20: vehicle; 11: storage battery; 12: first relay; 13: first current sensor; 14: first power supply circuit; 15: first control unit; 16: first wireless communication unit; 17: first antenna; 18: first ID superposition circuit; 19: first ID detection circuit; 21: motor; 22: inverter; 23: second relay; 24: second power supply circuit; 25: second control unit; 26: second wireless communication unit; 27: second antenna; 28: second ID superposition circuit; 29: second ID detection circuit; 210: voltage detection circuit; T1: power supply terminal; T2: power receiving terminal; Lp: power line; 191: hysteresis comparator; 192: inverting circuit; R1: first resistor; R2: second resistor; R3: third resistor; Ra: first pull-up resistor; Rb: second pull-up resistor; C1: first capacitor; C2: second capacitor; CP: comparator; Tr: PNP transistor.

Claims

1. A receiving circuit, characterized in that: have: Comparator; a first resistor connected to a non-inverting input terminal of the comparator; a second resistor connected to a feedback path between the output terminal of the comparator and the non-inverting input terminal; as well as a capacitor connected between a connection point between the first resistor and the non-inverting input terminal of the comparator and a fixed potential on the low side, wherein a binary voltage representing a plurality of bits of information is input as an input signal to an inverting input terminal of the comparator, The binary voltage input signal is input to the non-inverting input terminal of the comparator via a low-pass filter including the first resistor and the capacitor.

2. The receiving circuit according to claim 1, characterized in that: A ratio of a resistance value of the second resistor to a resistance value of the first resistor is set within a range of 2 to 3.

3. The receiving circuit according to claim 1, characterized in that: The comparator is an open collector or open drain comparator. The receiving circuit also has: a pull-up resistor connected between the output terminal of the comparator and a fixed potential on the high side; A PNP transistor or a P-channel field effect transistor, wherein a base terminal of the PNP transistor is connected to the output terminal of the comparator and an emitter terminal is connected to the fixed potential of the high side, and a gate terminal of the P-channel field effect transistor is connected to the output terminal of the comparator and a source terminal is connected to the fixed potential of the high side; as well as A third resistor is connected between the fixed potential on the low side and the collector terminal of the PNP transistor or the drain terminal of the P-channel field effect transistor.

4. The receiving circuit according to claim 3, characterized in that: The total of the resistance value of the first resistor and the resistance value of the second resistor is set to be three times or more the resistance value of the pull-up resistor.

5. The receiving circuit according to claim 3, characterized in that: The ratio of the resistance value of the second resistor to the resistance value of the first resistor is set in the range of 2 to 3. The total of the resistance value of the first resistor and the resistance value of the second resistor is set to be three times or more the resistance value of the pull-up resistor.

6. The receiving circuit according to claim 1, characterized in that: The resistance value of the first resistor and the capacitance value of the capacitor are set so that a cutoff frequency defined by the resistance value of the first resistor and the capacitance value of the capacitor is within a range of 1 / 10 to 1 / 5 of the frequency of the input signal.

7. The receiving circuit according to claim 1, characterized in that: Before receiving a target input signal, a preset signal for bringing a voltage of a non-inverting input terminal of the comparator close to a center of an amplitude of the input signal is received.

8. The receiving circuit according to any one of claims 1 to 7, characterized in that: The receiving circuit receives, as a binary voltage, identification information defined by a plurality of bits, which is superimposed on the current or voltage of the power line by an identification information transmitting device connected via the power line. 9 . A portable power storage pack that is detachable and includes the receiving circuit according to claim 8 .

10. A receiving method, characterized in that: The following steps are involved: Integrate a binary voltage representing a plurality of bits of information as an input signal; as well as The input signal after the integration is used as a threshold value, and the threshold value is compared with the input signal through a Schmitt trigger action. When the input signal is greater than the threshold value, it is determined to be 1, and when the input signal is less than the threshold value, it is determined to be 0.

11. A receiving program, characterized in that: Causes the computer to perform the following processing: integrating a binary voltage representing a plurality of bits of information as an input signal; and The input signal after the integration is used as a threshold value, and the threshold value is compared with the input signal through a Schmitt trigger action. When the input signal is greater than the threshold value, it is determined to be 1, and when the input signal is less than the threshold value, it is determined to be 0.

12. A non-transitory recording medium having a receiving program recorded thereon, wherein the non-transitory recording medium causes a computer to execute the following processing: integrating a binary voltage representing a plurality of bits of information as an input signal; and The input signal after the integration is used as a threshold value, and the threshold value is compared with the input signal through a Schmitt trigger action. When the input signal is greater than the threshold value, it is determined to be 1, and when the input signal is less than the threshold value, it is determined to be 0.

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