Semiconductor device and electronic apparatus

Abstract

A semiconductor device having a fast access speed is provided. The semiconductor device includes a first memory layer, a second memory layer, and a circuit layer. The first memory layer includes a plurality of first memory circuits, the second memory layer includes a second memory circuit, and the circuit layer includes a selector. The selector comprises a plurality of input terminals and output terminals. The first storage layer is located below the circuit layer, and the second storage layer is located above the circuit layer. The plurality of first storage circuits are electrically connected to the plurality of input terminals, and the second storage circuit is electrically connected to the output terminal. The selector has a function of bringing one selected from the plurality of input terminals into a conductive state with an output terminal of the selector. In addition, the semiconductor device has a function of writing data read out from the second memory circuit to the first memory circuit through the selector.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] In addition, one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a working method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, camera devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, their driving methods, their manufacturing methods or their inspection methods can be cited. Background Art

[0003] In recent years, as the amount of data used increases, a storage device with a larger storage capacity is required. In order to increase the storage capacity per unit area, stacking storage cells like a 3D NAND storage device is effective (see Patent Documents 1 to 3). By stacking storage cells, the storage capacity per unit area can be increased according to the number of stacked storage cells. [Prior technical literature] [Patent Document]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2011 / 0065270 [Patent Document 2] U.S. Patent Application Publication No. 2016 / 0149004 [Patent Document 3] U.S. Patent Application Publication No. 2013 / 0069052 Summary of the invention Technical problem to be solved by the invention

[0005] Storage devices such as cache memory and main memory used in computers are required to have the following characteristics: the time required for access is short, in other words, for example, the writing speed and reading speed are fast. For example, SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are used as cache memory and main memory of computers because their access time (sometimes called delay time, latency, etc.) is about several nanoseconds to tens of nanoseconds.

[0006] The storage devices such as registers and cache memories located at the upper level of the storage hierarchy in a processor such as a CPU (Central Processing Unit) have a smaller storage capacity than the storage devices located at the lower level of the storage hierarchy, so sometimes the required data is not stored in the register or cache memory (sometimes referred to as a cache miss). When a cache miss occurs, the processor accesses the storage devices located at the lower level of the storage hierarchy to obtain the required data (sometimes referred to as a cache miss penalty). The processor exchanges data with the storage devices located at the lower level of the storage hierarchy through the bus. Note that the speed of accessing the storage devices located at the lower level of the storage hierarchy from the CPU through the bus is slow, which can easily affect the operating speed of the processor.

[0007] One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a fast access speed. Another purpose of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a small circuit area. Another purpose of one embodiment of the present invention is to provide an electronic device including the semiconductor device. Another purpose of one embodiment of the present invention is to provide a novel semiconductor device or a novel electronic device.

[0008] Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above-mentioned purposes do not prevent the existence of other purposes. In addition, other purposes are purposes that are not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the purposes not mentioned above from the description of the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the above-mentioned purposes and other purposes. In addition, one embodiment of the present invention does not need to achieve all of the above-mentioned purposes and other purposes. Solutions to technical problems (1) One embodiment of the present invention is a semiconductor device, comprising a first storage layer, a second storage layer and a circuit layer. The first storage layer comprises a plurality of first storage circuits, the second storage layer comprises a second storage circuit, and the circuit layer comprises a selector. The selector comprises a plurality of input terminals and an output terminal. The first storage layer is located below the circuit layer, and the second storage layer is located above the circuit layer. The plurality of first storage circuits are electrically connected to the plurality of input terminals, and the second storage circuit is electrically connected to the output terminal. The selector has a function of making one selected from the plurality of input terminals and the output terminal conductive. In addition, the semiconductor device has a function of writing data read from the second storage circuit to the first storage circuit through the selector. (2) In one embodiment of the present invention having the structure of (1) above, a semiconductor substrate containing silicon may also be further included. In particular, the first storage layer is preferably located on the semiconductor substrate, and the first storage circuit preferably includes a first transistor. Note that the first transistor contains silicon in the channel formation region. (3) In one embodiment of the present invention having the structure of (2) above, the second storage circuit may include a second transistor. In particular, the second transistor preferably includes a metal oxide in a channel formation region.

[0012] The metal oxide contains one or more selected from indium, zinc and element M. In addition, element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony. (4) In one embodiment of the present invention having the structure of (3) above, the data may be any one of 1 bit, 2 bits, 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, and 256 bits. (5) In one embodiment of the present invention having the above-described configuration (4), the first storage circuit and the second storage circuit may be connected to each other without being connected via a system bus. (6) One embodiment of the present invention is a semiconductor device, comprising a first storage layer, a second storage layer, and a circuit layer. The first storage layer comprises a plurality of first storage circuits, the second storage layer comprises a second storage circuit, and the circuit layer comprises a selector. The second storage circuit comprises a capacitor and a second transistor. The capacitor comprises a first conductor, a second conductor, a first insulator, and a second insulator, and the second transistor comprises a second conductor, a third conductor, a fourth conductor, a third insulator, a fourth insulator, and a metal oxide. The selector comprises a plurality of input terminals and an output terminal, the first storage layer is located below the circuit layer, and the second storage layer is located above the circuit layer.

[0016] The first insulator includes a first opening. The first conductor is located on the side and bottom surface of the first opening and on the top surface of the first insulator. The second insulator is located on the top surface of the first insulator and on the top surface of the first conductor. The second conductor is located in the region of the top surface of the second insulator that overlaps with the first conductor. The third insulator is located on the top surface of the second conductor, and the third conductor is located on the top surface of the third insulator. The third insulator and the third conductor include a second opening. The metal oxide is located on the side of the second opening, on the top surface of the second conductor, and on the top surface of the third conductor. The fourth insulator is located on the top surface of the metal oxide and on the top surface of the third conductor. The fourth conductor is located in the region of the top surface of the fourth insulator that overlaps with the metal oxide.

[0017] The plurality of first storage circuits are electrically connected to the plurality of input terminals, and the third conductor is electrically connected to the output terminal. The selector has a function of connecting one selected from the plurality of input terminals to the output terminal. In addition, the semiconductor device has a function of writing data read from the second storage circuit to the first storage circuit via the selector. (7) In one embodiment of the present invention having the structure (6) above, the metal oxide may contain one or more selected from indium, zinc and element M.

[0019] The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony. (8) In one embodiment of the present invention having the structure of (7) above, a semiconductor substrate containing silicon may also be included. In particular, the first storage layer is preferably located on the semiconductor substrate, and the first storage circuit preferably includes a first transistor. Note that the first transistor contains silicon in the channel formation region. (9) In one embodiment of the present invention having the structure (8) above, the second insulator may include an oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium and magnesium. (10) In one embodiment of the present invention having the structure of (9) above, the data may be any one of 1 bit, 2 bits, 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, and 256 bits. (11) In one embodiment of the present invention having the configuration of (10) above, the first storage circuit and the second storage circuit may be connected to each other not via a system bus. (12) Another embodiment of the present invention is an electronic device including any one of the semiconductor devices described in (1) to (11) above and a housing. Effects of the Invention

[0025] According to one embodiment of the present invention, a semiconductor device with a fast access speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a small circuit area can be provided. In addition, according to one embodiment of the present invention, an electronic device including the semiconductor device can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device or a novel electronic device can be provided.

[0026] Note that the effects of one embodiment of the present invention are not limited to the above effects. The effects listed above do not prevent the existence of other effects. In addition, other effects are effects that are not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the effects that are not mentioned above from the description of the specification or drawings, etc. In addition, one embodiment of the present invention has at least one of the above effects and other effects. Therefore, one embodiment of the present invention sometimes does not have the effects listed above depending on the circumstances. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1A is a perspective schematic diagram showing a structural example of a semiconductor device, Figure 1B is a block diagram showing a structural example of a semiconductor device. Figure 2 is a conceptual diagram illustrating a storage hierarchy associated with various storage devices included in a computer. Figure 3 It is a perspective schematic diagram showing a structural example of a semiconductor device. Figure 4 It is a perspective schematic diagram showing a structural example of a semiconductor device. Figure 5 is a block diagram showing a structural example of a semiconductor device. Figure 6 is a block diagram showing a structural example of a semiconductor device. Figure 7 is a circuit diagram showing a structural example of a semiconductor device. Fig. 8A and Figure 8B is a circuit diagram showing a structural example of a semiconductor device. Fig. 9 is a block diagram showing a structural example of a semiconductor device. Fig.10 is a circuit diagram showing a structural example of a semiconductor device. Fig.11 is a circuit diagram showing a structural example of a semiconductor device. Fig.12 is a block diagram showing a structural example of a semiconductor device. Fig.13 is a block diagram showing a structural example of a semiconductor device. Fig.14 is a circuit diagram showing a structural example of a semiconductor device. Fig.15 It is a perspective schematic diagram illustrating a structural example of a storage device. Fig.16 is a block diagram showing a structural example of a semiconductor device. Fig.17 is a block diagram showing a structural example of a memory circuit included in a semiconductor device. FIG. 18A to FIG. 18E is a circuit diagram showing a structural example of a memory cell included in a semiconductor device. FIG. 19A to FIG. 19C is a circuit diagram showing a structural example of a memory cell included in a semiconductor device. Fig. 20A and Fig. 20B is a circuit diagram showing a structural example of a memory cell included in a semiconductor device. Fig.21 is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Fig. 22 is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Fig.23A and Fig. 23B is a schematic cross-sectional view showing a structural example of a transistor included in a semiconductor device. Fig.24 is a schematic cross-sectional view showing a structural example of a transistor included in a semiconductor device. Fig.25 is a schematic cross-sectional view illustrating a structural example of a capacitor included in a semiconductor device. Fig.26 is a schematic cross-sectional view illustrating a structural example of a semiconductor device. FIG. 27A to FIG. 27C is a plan view showing a structural example of a transistor included in a semiconductor device, Fig.27D is a cross-sectional view showing a structural example of a transistor included in a semiconductor device. Fig.28A is a plan view showing a structural example of a transistor included in a semiconductor device, Fig.28B is a cross-sectional view showing a structural example of a transistor included in a semiconductor device. Fig.29A and Fig.29BThis is a diagram showing an example of an electronic component. Fig. 30A and Fig. 30B is a diagram showing an example of an electronic device, FIG. 30C to FIG. 30E This is a diagram showing an example of a large computer. Fig.31 is a diagram showing an example of space equipment. Fig.32 is a diagram showing an example of a storage system that can be used in a data center. Fig.33A is a perspective schematic diagram showing a structural example of a display device, Fig.33B is a block diagram showing a structural example of a display device. Fig.34 is a circuit diagram showing a structural example of a pixel circuit included in a display device. Fig.35 It is a perspective schematic diagram showing a structural example of a stacked structure included in the display device. FIG. 36A to FIG. 36I It is a perspective view showing an example of an electronic device. Modes for Carrying Out the Invention

[0028] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (e.g., a transistor, a diode, a photodiode), and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip having an integrated circuit, and an electronic component containing a chip in a package are all examples of a semiconductor device. In addition, for example, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device are sometimes semiconductor devices themselves, or sometimes include a semiconductor device.

[0029] In addition, in this specification, when it is described that "X is connected to Y", it means that the following cases are disclosed in this specification, etc.: a case where X is electrically connected to Y; a case where X is functionally connected to Y; and a case where X is directly connected to Y. Therefore, it is not limited to the connection relationship shown in the drawings or text, and other connection relationships are also within the scope described in the drawings or text. X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films or layers).

[0030] As an example of a case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitors, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) capable of electrically connecting X and Y may be connected between X and Y. In addition, the switch has a function of controlling on or off. In other words, whether or not current flows is controlled by placing the switch in a conducting state (on state) or a non-conducting state (off state).

[0031] In addition, when both sides of X and Y are provided with elements and power lines (for example, VDD (high power potential), VSS (low power potential), GND (ground potential) or wiring supplying a desired potential), it cannot be said that X and Y are electrically connected. In addition, when only power lines are provided between X and Y, there are no other elements between X and Y, so it can be said that X and Y are directly connected. Therefore, when only power lines are provided between X and Y, it can also be said that "X and Y are electrically connected". However, when both sides of X and Y are provided with elements and power lines, it can be said that X is electrically connected to the power line (through elements) and Y is electrically connected to the power line, but it cannot be said that X and Y are electrically connected. In addition, when the gate and source of the transistor are between X and Y, it cannot be said that X and Y are electrically connected. In addition, when the gate and drain of the transistor are between X and Y, it cannot be said that X and Y are electrically connected. That is, with respect to the transistor, when the drain and source of the transistor are between X and Y, it can be said that X and Y are electrically connected. Furthermore, when a capacitor is disposed between X and Y, it may be said that X and Y are electrically connected, but it may not be said that X and Y are electrically connected. For example, in the structure of a digital circuit or a logic circuit, when a capacitor is disposed between X and Y, it may not be said that X and Y are electrically connected. On the other hand, for example, in the structure of an analog circuit, when a capacitor is disposed between X and Y, it may be said that X and Y are electrically connected.

[0032] As an example of a case where X and Y are functionally connected, for example, one or more circuits capable of functionally connecting X and Y (for example, a logic circuit (for example, an inverter, a NAND circuit, a NOR circuit), a signal conversion circuit (for example, a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit such as a boost circuit and a buck circuit), a level shift circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifier circuit (for example, a circuit capable of increasing signal amplitude or current amount, an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit), a signal generation circuit, a storage circuit, a control circuit, etc.) may be connected between X and Y. Note that, for example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y can be said to be functionally connected.

[0033] Furthermore, when it is clearly stated that “X is electrically connected to Y”, the following cases are included: a case where X is electrically connected to Y (in other words, a case where X and Y are connected with another element or another circuit interposed therebetween); and a case where X and Y are directly connected (in other words, a case where X and Y are connected without another element or another circuit interposed therebetween).

[0034] In addition, for example, it can be expressed as "X, Y, the source of the transistor (sometimes referred to as one of the first terminal and the second terminal) and the drain of the transistor (sometimes referred to as the other of the first terminal and the second terminal) are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence." Or, it can be expressed as "the source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence." Or, it can be expressed as "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are connected to each other in sequence." By specifying the connection order in the circuit structure using the same expression method as these examples, the source and drain of the transistor can be distinguished to determine the technical scope. Note that this expression method is an example and is not limited to the above expression method. Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films or layers, etc.).

[0035] In addition, even if independent components are electrically connected to each other on a circuit diagram, one component may have the functions of multiple components. For example, when a part of a wiring is used as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the category of "electrically connected" in this specification also includes the case where one conductive film has the functions of multiple components.

[0036] In this specification, etc., a "resistor" may be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, etc., a "resistor" includes a wiring having a resistance value, a transistor, a diode, or a coil through which current flows between a source and a drain. Therefore, a "resistor" may sometimes be referred to as a "resistance", "load", or "region having a resistance value". In contrast, a "resistance", "load", or "region having a resistance value" may sometimes be referred to as a "resistor". As for the resistance value, for example, it is preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0037] In this specification, etc., "capacitor" can be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a wiring area having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, "capacitor", "parasitic capacitance" or "gate capacitance" etc. can sometimes be replaced by "capacitor". In contrast, "capacitor" can sometimes be replaced by "capacitor", "parasitic capacitance" or "gate capacitance". In addition, "capacitor" (a "capacitor" including three or more terminals) includes an insulator and a pair of conductors clamping the insulator. Thus, the "pair of conductors" of the "capacitor" can be replaced by "a pair of electrodes", "a pair of conductive areas", "a pair of areas" or "a pair of terminals". In addition, "one of a pair of terminals" and "the other of a pair of terminals" are sometimes referred to as the first terminal and the second terminal, respectively. In addition, the electrostatic capacitance value can be, for example, greater than 0.05fF and less than 10pF. In addition, for example, it can also be greater than 1pF and less than 10μF.

[0038] In this specification, etc., a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type or p-channel type) and the level of the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as the source and the other is used as the drain. Therefore, in this specification, etc., the source and the drain can be interchanged. In this specification, etc., when describing the connection relationship of the transistor, the expressions "one of the source and the drain" (first electrode or first terminal) and "the other of the source and the drain" (second electrode or second terminal) are used. In addition, depending on the structure of the transistor, a back gate is sometimes included in addition to the above three terminals. In this case, in this specification, etc., one of the gate and the back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and the back gate of the transistor is sometimes referred to as the second gate. In addition, in the same transistor, "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate may be referred to as a first gate, a second gate, a third gate, etc. in this specification and the like.

[0039] For example, in this specification, a multi-gate structure transistor having more than two gate electrodes can be used as an example of a transistor. When a multi-gate structure is used, since the channel forming regions are connected in series, a structure in which multiple transistors are connected in series is formed. Therefore, by adopting a multi-gate structure, the off-state current can be reduced, and the voltage resistance of the transistor can be improved (improving reliability). Alternatively, by utilizing a multi-gate structure, when the transistor operates in a saturation region, even if the voltage between the drain and the source changes, the change in the current between the drain and the source is not too large, so that a voltage-current characteristic with a flat tilt angle can be obtained. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with an extremely high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0040] In addition, a circuit diagram showing a circuit element sometimes includes a case where the circuit element has a plurality of circuit elements. For example, a circuit diagram showing a resistor includes a case where two or more resistors are connected in series. In addition, for example, a circuit diagram showing a capacitor includes a case where two or more capacitors are connected in parallel. In addition, for example, a circuit diagram showing a transistor includes a case where two or more transistors are connected in series and the gates of each transistor are electrically connected to each other. Similarly, for example, a circuit diagram showing a switch includes a case where the switch has two or more transistors, the two or more transistors are electrically connected in series or in parallel and the gates of each transistor are electrically connected to each other.

[0041] In this specification, etc., a node may be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region depending on the circuit structure and device structure. In addition, terminals, wiring, etc. may also be referred to as nodes.

[0042] In addition, in this specification, etc., a selector sometimes refers to, for example, a circuit that includes a plurality of input terminals and an output terminal, selects one from the plurality of input terminals and causes the selected input terminal and an output terminal to be in a conductive state. In other words, a selector sometimes refers to a circuit that selects one from the input signals input to each of the plurality of input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector sometimes refers to, for example, a circuit that includes a plurality of output terminals and an input terminal, selects one from the plurality of output terminals and causes the selected output terminal and an input terminal to be in a conductive state. In other words, a selector sometimes refers to a circuit that selects one from the plurality of output terminals and outputs the input signal input to the input terminal to the selected output terminal. That is, a selector sometimes refers to a multiplexer or a demultiplexer.

[0043] In addition, in this specification, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from the reference potential. For example, when the reference potential is the ground potential (ground potential), "voltage" can also be called "potential". The ground potential does not necessarily mean 0V. In addition, the potential is relative, and the potential supplied to the wiring, the potential applied to the circuit, the potential output from the circuit, etc., etc., also changes according to the change of the reference potential.

[0044] In addition, in this specification, "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both recorded as "wirings used to supply high-level potentials", the high-level potentials supplied by the two wirings may be different from each other. Similarly, when two wirings are both recorded as "wirings used to supply low-level potentials", the low-level potentials supplied by the two wirings may be different from each other.

[0045] In addition, "electric current" refers to the migration phenomenon (conduction) of electric charge. For example, the description of "conduction of a positively charged body" can be replaced by the description of "conduction of a negatively charged body in the opposite direction". Therefore, in this specification, etc., in the absence of special instructions, "electric current" refers to the migration phenomenon (conduction) of electric charge when carriers migrate. Here, as carriers, for example, electrons, holes, anions, cations, complex ions, etc. can be cited, and the carriers are different according to the system through which the current flows (for example, semiconductors, metals, electrolytes, and vacuum). In addition, the "direction of electric current" in wiring, etc. is the direction in which positively charged carriers migrate, and is recorded as a positive current amount. In other words, the direction in which negatively charged carriers migrate is opposite to the direction of electric current, and is recorded as a negative current amount. Therefore, in this specification, etc., in the absence of special instructions, regarding the positive and negative of the current (or the direction of the current), the description of "the current flows from element A to element B" can be replaced by the description of "the current flows from element B to element A". In addition, the description of "the current is input to element A" can be replaced by the description of "the current is output from element A".

[0046] In addition, in this specification, etc., ordinal numbers such as "first", "second", and "third" are added to avoid confusion among constituent elements. Therefore, the ordinal numbers do not limit the number of constituent elements. In addition, the ordinal numbers do not limit the order of the constituent elements. For example, in this specification, etc., the "first" constituent element in one embodiment may be referred to as the "second" constituent element in other embodiments or claims. In addition, for example, in this specification, etc., the constituent element referred to by "first" in one embodiment may be omitted in other embodiments or claims.

[0047] In this specification, etc., for the sake of convenience, words and phrases indicating configurations such as "upper" and "lower" are sometimes used to illustrate the positional relationship of constituent elements with reference to the drawings. In addition, the positional relationship of constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in the specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the situation. For example, if it is an expression of "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can be replaced with "an insulator located on the bottom surface of a conductor".

[0048] In addition, the terms "above" or "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, if it is an expression "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B above insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B below insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with below insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included.

[0049] In addition, in this specification, etc., words such as "row" and "column" are sometimes used to describe the components configured in a matrix and their positional relationship. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, etc., and the words can be appropriately replaced according to the situation. For example, by rotating the direction of the drawing by 90 degrees, the expression of "row direction" can sometimes be replaced by "column direction".

[0050] In addition, in this specification, etc., words such as "film" and "layer" can be interchanged with each other depending on the situation. For example, "conductive layer" can sometimes be replaced with "conductive film". In addition, "insulating film" can sometimes be replaced with "insulating layer". In addition, other words can be used instead of words such as "film" and "layer" depending on the situation or condition. For example, "conductive layer" or "conductive film" can sometimes be replaced with "conductive body". In addition, for example, "insulating layer" or "insulating film" can sometimes be replaced with "insulator".

[0051] Note that in this specification, etc., the words "electrode", "wiring" and "terminal" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, the words "electrode" or "wiring" also include the case where a plurality of "electrodes" or "wirings" are formed as one. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or "electrode", and vice versa. Furthermore, the word "terminal" also includes the case where one or more selected from "electrode", "wiring" and "terminal" are formed as one. Therefore, for example, an "electrode" can be a part of a "wiring" or a "terminal", and for example, a "terminal" can be a part of a "wiring" or an "electrode". In addition, the words "electrode", "wiring" or "terminal" are sometimes replaced by words such as "region" depending on the situation.

[0052] In this specification, etc., depending on the situation or conditions, the words "wiring", "signal line" or "power line" can be interchanged with each other. For example, "wiring" can sometimes be converted to "signal line". In addition, for example, "wiring" can sometimes be converted to "power line". Vice versa, "signal line" or "power line" can sometimes be converted to "wiring". "Power line" can sometimes be converted to "signal line". Vice versa, "signal line" can sometimes be converted to "power line". In addition, depending on the situation or conditions, "potential" applied to the wiring can sometimes be converted to "signal". Vice versa, "signal" can sometimes be converted to "potential".

[0053] In addition, in this specification, etc., the working method of the semiconductor device is sometimes described with reference to a timing diagram. In addition, the timing diagram used in this specification, etc. shows an ideal working example, and is not limited to the period, signal (for example, potential or current) and timing shown in the timing diagram unless otherwise specified. In the timing diagram of this specification, etc., the size and timing of the signal (for example, potential or current) of each wiring (including nodes) in the timing diagram can be changed according to the situation. For example, even if two periods with equal intervals are shown in the timing diagram, the lengths of the two periods are sometimes different. In addition, for example, even if one of the two periods is shown to be long and the other is short, the lengths of the two periods may sometimes be the same, or sometimes one of the two periods may be short and the other may be long.

[0054] In this specification, etc., metal oxide refers to the oxide of metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when the metal oxide can constitute the channel formation region of a transistor having at least one of an amplification function, a rectification function and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0055] In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0056] In addition, in this specification, etc., impurities of a semiconductor refer to substances other than the main components constituting the semiconductor film. For example, an element with a concentration of less than 0.1 at.% is an impurity. When impurities are contained, one or more selected from the group consisting of an increase in the defect state density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity sometimes occur. When the semiconductor is an oxide semiconductor, as impurities that change the semiconductor properties, there are, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, and in particular, there are, for example, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc.

[0057] In this specification, etc., a switch refers to an element that has a function of controlling whether to allow current to flow by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to an element that has a function of selecting and switching a current path. Therefore, a switch sometimes includes two or more terminals for allowing current to flow in addition to a control terminal. As an example of a switch, an electric switch or a mechanical switch can be used. In other words, a switch is not limited to a specific element as long as it can control the current.

[0058] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM: Metal Insulator Metal) diodes, metal-insulator-semiconductor (MIS: Metal Insulator Semiconductor) diodes, or diode-connected transistors), or logic circuits combining these elements. When a transistor is used as a switch, the "on state" of the transistor refers to, for example, a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited or a state in which current can flow between the source electrode and the drain electrode. In addition, the "non-conducting state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When the transistor is used only as a switch, there is no particular restriction on the polarity (conductivity type) of the transistor.

[0059] An example of a mechanical switch is a switch using MEMS (micro-electromechanical system) technology. This switch has a mechanically movable electrode and operates by controlling conduction and non-conduction by moving the electrode.

[0060] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, it also includes a state where the angle is greater than -5° and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, it also includes a state where the angle is greater than 85° and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0061] In this specification, etc., the structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one mode of the present invention. In addition, when a plurality of structural examples are described in one embodiment, these structural examples can be appropriately combined.

[0062] In addition, the content (or part thereof) described in a certain embodiment may be applied / combined / replaced with other content (or part thereof) described in the embodiment and at least one of the content (or part thereof) described in one or more other embodiments.

[0063] Note that the contents described in the embodiments refer to the contents described in each embodiment using various drawings or the contents described in the text described in the specification.

[0064] In addition, more figures may be formed by combining a figure (or a portion thereof) shown in a certain embodiment with other parts of the figure, other figures (or a portion thereof) shown in the embodiment, and at least one of the figures (or a portion thereof) shown in one or more other embodiments.

[0065] The embodiments described in this specification are described with reference to the accompanying drawings. However, a person skilled in the art can easily understand the fact that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to represent the same parts or parts with the same functions, and repeated descriptions are omitted. In stereograms or top views, for the sake of clarity, the illustrations of some constituent elements are sometimes omitted.

[0066] In this specification, etc., when the same symbol is used for multiple elements and it is necessary to distinguish them, a symbol such as "_1", "[n]", "[m, n]" is sometimes added to the symbol for identification. In addition, in the drawings, etc., when a symbol is added to a symbol for identification, such as "_1", "[n]", "[m, n]", etc., if it is not necessary to distinguish them in this specification, etc., a symbol such as "_1", "[n]", "[m, n]" is sometimes not added for identification.

[0067] In the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and the shapes or values ​​shown in the drawings are not limited. For example, the unevenness of signals, voltages or currents caused by noise or timing deviations may be included.

[0068] (Implementation Method 1) In this embodiment, a semiconductor device which is one embodiment of the present invention is described.

[0069] First, the concept of storage hierarchy associated with the various storage devices included in a computer. Figure 2 An example of the storage hierarchy is shown, Figure 2 The storage hierarchy 100 shown includes a register 101 , a first cache memory 102 , a second cache memory 103 , a main memory 104 , and an auxiliary storage device 105 .

[0070] The register 101 is a storage device included in a processor such as a CPU or a GPU (Graphics Processing Unit). The register 101 has a function of temporarily storing input data to an arithmetic circuit included in the processor and output data calculated by the arithmetic circuit. In addition, the register 101 can temporarily store data according to a control device included in the processor in addition to data related to the arithmetic circuit.

[0071] The register 101 includes, for example, a flip-flop circuit.

[0072] The first cache memory 102 is, for example, a storage device located between the register 101 and the main memory 104 in the storage hierarchy 100, and has a function of storing data with a high CPU access frequency. Generally, the first cache memory 102 is sometimes referred to as a primary cache memory.

[0073] The second cache memory 103 is a storage device located between the register 101 and the main memory 104 in the storage hierarchy 100, and has a function of storing data whose CPU access frequency is second only to the first cache memory 102. Generally speaking, the second cache memory 103 is sometimes called a secondary cache memory.

[0074] The first cache memory 102 and the second cache memory 103 include, for example, SRAM.

[0075] Note that the second cache memory 103 does not need to be provided in the storage hierarchy 100 depending on the computer. Alternatively, a cache memory (sometimes referred to as a third cache memory or a third-level cache memory) having a slower access speed and a larger storage capacity than the second cache memory 103 may be provided in the storage hierarchy 100. That is, the storage hierarchy 100 may include one or more cache memories.

[0076] The memory hierarchy 100 may have a configuration in which the first cache memory 102 and the second cache memory 103 are included in the processor. The memory hierarchy 100 may have a configuration in which the first cache memory 102 and the second cache memory 103 are included in the processor and the main memory 104 described later, respectively.

[0077] The main memory 104 is, for example, a storage device located between the first cache memory 102 and the second cache memory 103 and the auxiliary storage device 105 in the storage hierarchy 100 , and has a function of directly writing or reading data by receiving a command signal from a processor including a register 101 .

[0078] The main memory 104 includes, for example, a DRAM.

[0079] The auxiliary storage device 105 is a storage device with a large storage capacity, and a nonvolatile storage device is mainly used as the auxiliary storage device 105. Examples of the nonvolatile storage device include a magnetic storage medium (such as a HDD (Hard Disk Drive) or a magnetic tape) or a flash memory (such as an SSD (Solid State Drive) or a USB memory).

[0080] In addition, a storage device called a disk cache may be provided between the main memory 104 and the auxiliary storage device 105 in the storage hierarchy 100. By providing a disk cache between the main memory 104 and the auxiliary storage device 105, the data transmission speed between the main memory 104 and the auxiliary storage device 105 can be increased.

[0081] There is a tendency for a difference to occur between the operating speed of the processor and the operating speed (sometimes referred to as the access speed) of each storage device included in the storage hierarchy 100 (especially the storage devices located in the lower level of the first cache memory 102). Therefore, generally speaking, the higher the level of the storage device in the storage hierarchy 100, the faster the access speed is required. In addition, the higher the level of the storage device, the closer the distance to the calculation circuit or control circuit included in the processor is required.

[0082] In addition, in the storage hierarchy 100, the storage capacity of the storage device that is frequently accessed is preferably small. This is because when the storage capacity is small, the time required to search for data stored in the storage device is shorter, and the storage device operates faster. On the other hand, when a large amount of data is to be processed by a processor, the storage capacity of the storage hierarchy 100 as a whole is preferably large. Therefore, the lower the storage device, the larger the storage capacity is required. For example, the first cache memory 102 preferably has a larger storage capacity than the register 101, the second cache memory 103 preferably has a larger storage capacity than the first cache memory 102, the main memory 104 preferably has a larger storage capacity than the second cache memory 103, and the auxiliary storage device 105 preferably has a larger storage capacity than the main memory 104.

[0083] When the processor reads out the required data in the storage hierarchy from register 101 to main memory 104, it attempts to access the upper storage devices in the storage hierarchy 100 in sequence. When the required data is not stored in the storage device of the upper level (a cache miss occurs), the processor accesses the storage device located at a lower level than the storage device of the upper level. In particular, the lower the level of the storage device, the longer the distance from the processor (register 101), and therefore the longer the time required for access (a cache miss loss occurs). In addition, a bus (such as an internal bus or an external bus) is sometimes used when transferring data between storage devices of two different levels, and the greater the amount of data flowing through the bus, the greater the impact on the performance (operating speed) of the processor.

[0084] In view of this, Figure 1A and Figure 1B A semiconductor device according to one embodiment of the present invention that solves the above-mentioned problems will be described. Figure 1A is a perspective schematic diagram showing a structural example of a semiconductor device DEV as one embodiment of the present invention, Figure 1B is a block diagram of a semiconductor device DEV.

[0085] The semiconductor device DEV includes a memory layer MEML_L of a lower memory device in the memory hierarchy 100, a memory layer MEML_H of an upper memory device in the memory hierarchy 100, and a circuit layer SWCL. The memory layer MEML_H is located below the circuit layer SWCL, and the memory layer MEML_L is located above the circuit layer SWCL. That is, in the semiconductor device DEV, the memory layer MEML_H, the circuit layer SWCL, and the memory layer MEML_L are stacked in sequence from the bottom.

[0086] The memory layer MEML_L is, for example, a memory layer including the register 101 , the first cache memory 102 , the second cache memory 103 , or the main memory 104 in the memory hierarchy 100 .

[0087] The storage layer MEML_H is, for example, a storage layer in an upper level of the storage layer MEML_L included in the storage hierarchy 100. For example, when the first cache memory 102 is included in the storage layer MEML_L, the storage layer MEML_H preferably includes the register 101. In addition, for example, when the second cache memory 103 is included in the storage layer MEML_L, the first cache memory 102 is preferably included in the storage layer MEML_H. In addition, for example, when the main memory 104 is included in the storage layer MEML_L, the second cache memory 103 is preferably included in the storage layer MEML_H.

[0088] Note that Figure 1A and Figure 1BIn the embodiment, a plurality of memory circuits ME_L are included in the memory layer MEML_L, and a plurality of memory circuits ME_H are included in the memory layer MEML_H.

[0089] As an example, Figure 3 As shown, the memory circuit ME_L includes a memory cell array in which a plurality of memory cells MC_L are arranged in a matrix of more than one row. In addition, when the wiring WL_L extends in the row direction on the memory cell array as a read word line, the wiring BL_L preferably extends in the column direction on the memory cell array as a bit line for transmitting data read from the memory cell MC_L. In addition, the memory cell MC_L ( Figure 3 In the figure, the area MA_L) preferably holds one data. For example, when a memory cell MC_L has a storage capacity of 1 bit and the number of columns of the memory cell array is 8, the memory cell MC_L equivalent to one row of the memory cell array (the memory cell MC_L of the area MA_L) holds one data with a storage capacity of 8 bits. That is, 8 bits (1 byte) of data can be read out through a single read operation. In addition, for example, when a memory cell MC_L has a storage capacity of 1 bit and the number of columns of the memory cell array is 64, the memory cell MC_L of the area MA_L holds one data with a storage capacity of 64 bits. That is, 64 bits (8 bytes) of data can be read out through a single read operation. Note that the number of columns of the memory cell array is not limited to a multiple of 8, but can also be an integer greater than 1.

[0090] In other words, when the number of rows of the memory cell array of the memory circuit ME_L is m (where m is an integer greater than 1) and the number of columns is n (where n is an integer greater than 1), the memory circuit ME_L can store m n-bit data.

[0091] As an example, similar to the memory circuit ME_L, the memory circuit ME_H includes a memory cell array in which a plurality of memory cells MC_H are arranged in a matrix of more than one row. Note that the memory cells included in the memory circuit ME_H may have the same structure as or different structures from the memory cells included in the memory circuit ME_L. Furthermore, when the wiring WL_H extends in the row direction on the memory cell array as a write word line, the wiring BL_H preferably extends in the column direction on the memory cell array as a bit line for transmitting data written to the memory cell MC_H. In addition, the memory cell MC_H ( Figure 3In the figure, it is preferred to store 1 data. For example, when a memory cell MC_H has a storage capacity of 1 bit and the number of columns of the memory cell array is 8, 1 data with a storage capacity of 8 bits (1 byte) can be written to the memory cell MC_H in the area MA_H. In addition, for example, when a memory cell MC_H has a storage capacity of 1 bit and the number of columns of the memory cell array is 64, 1 data with a storage capacity of 64 bits (8 bytes) can be written to the memory cell MC_H in the area MA_H. Note that the number of columns of the memory cell array is not limited to a multiple of 8, and can also be an integer greater than 1.

[0092] Similar to the storage circuit ME_L, when the number of rows of the storage cell array of the storage circuit ME_H is m (here, m is an integer greater than 1) and the number of columns is n (here, n is an integer greater than 1), the storage circuit ME_H can store m n-bit data.

[0093] In particular, the storage capacity of data held in area MA_H is preferably the same as that held in area MA_L. In other words, the number of rows and columns of the memory cell array of memory circuit ME_H is preferably equal to the number of rows and columns of the memory cell array of memory circuit ME_L.

[0094] In addition, if Figure 1B and Figure 3 As shown, the semiconductor device DEV has a structure in which a storage circuit ME_L sends one bit or more bits of one data to the circuit layer SWCL. In addition, the semiconductor device DEV has a structure in which a storage circuit ME_H receives one bit or more bits of one data from the circuit layer SWCL. Therefore, as an example, the storage circuit ME_L and the storage circuit ME_H are both storage circuits for storing digital data.

[0095] For example, the storage circuit ME_L has a function of reading 8-bit (1-byte) data and sending the data to the circuit layer SWCL. In addition, the storage circuit ME_H has a function of writing 8-bit data sent from the storage circuit ME_L through the circuit layer SWCL. Note that the storage circuit ME_L and the storage circuit ME_H can also process data less than 8 bits, such as 1 bit, 2 bits, or 4 bits. In addition, for example, data greater than 8 bits, such as 16 bits, 32 bits, 64 bits, 128 bits, or 256 bits, can also be processed.

[0096] Therefore, when the read word line in the memory cell array included in the memory circuit ME_H extends in the row direction, the number of columns of the memory cell array is preferably equal to the number of columns of the memory cell array included in the memory circuit ME_L. For example, when the memory cell in each of the memory circuit ME_L and the memory circuit ME_H can hold 1-bit data, by setting the number of columns of the memory cell array of each of the memory circuit ME_L and the memory circuit ME_H to 8, each of the memory circuit ME_L and the memory circuit ME_H can be a memory circuit that processes 8-bit data. At this time, the number of wirings BL_L used to send data from the memory circuit ME_L to the circuit layer SWCL can be 8, and the number of wirings BL_H used to send data from the circuit layer SWCL to the memory circuit ME_H can also be 8. In addition, for example, by setting the number of columns of the memory cell array of each of the memory circuit ME_L and the memory circuit ME_H to 64, each of the memory circuit ME_L and the memory circuit ME_H can be a memory circuit that processes 64-bit data. In this case, the number of wirings BL_L for transmitting data from the memory circuit ME_L to the circuit layer SWCL may be 64, and the number of wirings BL_H for transmitting data from the circuit layer SWCL to the memory circuit ME_H may also be 64.

[0097] Furthermore, when the wiring WL_H used as a read word line in the memory cell array included in the memory circuit ME_H extends in the row direction, the number of rows of the memory cell array included in the memory circuit ME_H is preferably equal to the number of rows of the memory cell array included in the memory circuit ME_L.

[0098] Note that specific circuit structures of the storage circuit ME_L and the storage circuit ME_H will be described later.

[0099] Since the storage layer MEML_L overlaps the storage layer MEML_H via the circuit layer SWCL, for example, by forming a wiring used as a plug in each of the storage layer MEML_L, the circuit layer SWCL, and the storage layer MEML_H, the storage layer MEML_L and the circuit layer SWCL can be electrically connected, and the circuit layer SWCL and the storage layer MEML_H can also be electrically connected. That is, the electrical connection between the storage layer MEML_L and the circuit layer SWCL and the electrical connection between the circuit layer SWCL and the storage layer MEML_H can be achieved by wiring in the stacking direction. In this case, compared with the case where wiring is formed on a plane, the wiring length can be shortened and the number of wirings can be increased. Therefore, by stacking the storage layer MEML_L, the circuit layer SWCL, and the storage layer MEML_H and forming wiring in the stacking direction, the amount of data exchanged between the storage layer MEML_L and the storage layer MEML_H can be increased. In addition, the data transmission speed between the storage layer MEML_L and the storage layer MEML_H can be improved.

[0100] In addition, the storage layer MEML_L and the storage layer MEML_H are electrically connected through the circuit layer SWCL, so for example, there is no need to set up a system bus between the storage layer MEML_L and the storage layer MEML_H. The system bus is a data transmission channel (wiring) that connects the various devices that constitute the computer and the processor, and is divided into an external bus that connects the processor to external devices (such as a main memory, an auxiliary storage device, or an optical drive) and an internal bus that connects the circuits in the processor (such as a cache memory, a control device, or an arithmetic circuit). In particular, when the processor is a CPU, the system bus is sometimes referred to as a CPU bus. The system bus is connected to each device and has a tendency to have a longer transmission channel (wiring), so sometimes the time required for data transmission is longer, and sometimes the power consumption required for data transmission is higher.

[0101] By directly exchanging data between the memory layer MEML_L and the memory layer MEML_H without passing through the system bus like the semiconductor device DEV, the access speed of the processor including the semiconductor device DEV is improved, and power consumption can be reduced.

[0102] The circuit layer SWCL has a function of selecting one of the multiple storage circuits ME_L included in the storage layer MEML_L and one of the multiple storage circuits ME_H included in the storage layer MEML_H and making the selected storage circuit ME_L and the storage circuit ME_H conductive. In addition, each of the multiple storage circuits ME_L that are not selected is not conductive with the multiple storage circuits ME_H included in the storage layer MEML_H.

[0103] That is, by using the circuit layer SWCL to select one of the multiple storage circuits ME_L included in the storage layer MEML_L and one of the multiple storage circuits ME_H included in the storage layer MEML_H, the data held in the area MA_L of the storage cell array of the selected storage circuit ME_L in the storage layer MEML_L can be read out and written to the area MA_H of the storage cell array of the selected storage circuit ME_H in the storage layer MEML_H.

[0104] Note that although the above shows a structural example of reading one data in the area MA_L of the memory cell array in the memory circuit ME_L and writing it to the area MA_H of the memory cell array in the memory circuit ME_H, one embodiment of the present invention is not limited to this, and the structure of the data may be changed. Figure 3 The structure of the semiconductor device DEV adopts a structure in which not one data is read from the memory circuit ME_L but a plurality of data are read and written into the memory circuit ME_H.

[0105] For example, in Figure 4In the semiconductor device DEV shown in FIG. 1 , a plurality of memory cells MC_L arranged in a memory cell array of a memory circuit ME_L are electrically connected to a plurality of wirings BLUT_L, respectively, and the plurality of wirings BLUT_L are electrically connected to a circuit layer SWCL. Figure 4 In the semiconductor device DEV shown, a plurality of memory cells MC_H arranged in a memory cell array of a memory circuit ME_H are respectively electrically connected to a plurality of wirings BLUT_H, and the plurality of wirings BLUT_H are electrically connected to a circuit layer SWCL.

[0106] That is, the number of wirings of the wiring BLUT_L is equal to the number of memory cells MC_L configured in the memory cell array of the memory circuit ME_L. In addition, the number of wirings of the wiring BLUT_H is equal to the number of memory cells MC_H configured in the memory cell array of the memory circuit ME_H. Furthermore, the number of rows of the memory cell array of the memory circuit ME_L is preferably equal to the number of rows of the memory cell array of the memory circuit ME_H, and the number of columns of the memory cell array of the memory circuit ME_L is preferably equal to the number of columns of the memory cell array of the memory circuit ME_H.

[0107] The wiring BLUT_L is equivalent to Figure 3 The wiring BL_L in the memory circuit ME_L is electrically connected to one of the plurality of memory cells MC_L included in the memory circuit ME_L. Figure 3 Similarly, the wiring BLUT_H is equivalent to Figure 3 The wiring BL_H in the memory circuit ME_H is electrically connected to one of the plurality of memory cells MC_H included in the memory circuit ME_H. Figure 3 The wiring BL_H in is different.

[0108] like Figure 4 As in the semiconductor device DEV of the present invention, by electrically connecting each of the wirings BLUT_L to each of the plurality of memory cells MC_L in the memory circuit ME_L, in the memory cell array of the memory circuit ME_L, a plurality of data held by the memory cells MC_L arranged in a plurality of rows (all rows) can be simultaneously transmitted to the circuit layer SWCL without transmitting the data held by the memory cells MC_L arranged in one row. In addition, by electrically connecting each of the wirings BLUT_H to each of the plurality of memory cells MC_H in the memory circuit ME_H, in the memory cell array of the memory circuit ME_H, the data transmitted by the circuit layer SWCL can be simultaneously written to the memory cells MC_H arranged in a plurality of rows (all rows) without writing to the memory cells MC_H arranged in one row.

[0109] Note that the memory circuit ME_L and the memory circuit ME_H described above may also be memory circuits for storing analog data instead of digital data. In this case, the data exchanged between the memory circuit ME_L and the memory circuit ME_H through the circuit layer SWCL may be analog data instead of digital data. In the case of analog data, the number of wirings connected between the memory circuit ME_L and the memory circuit ME_H may be less than the number of wirings in the case of processing digital data, so the circuit area of ​​the semiconductor device DEV may be further reduced.

[0110] <Structural Example of Circuit Layer SWCL> Next, a configuration example of the circuit layer SWCL will be described.

[0111] <<Direct Mapping Method>> First, a case where a direct mapping method is adopted as the storage structure of the storage layer MEML_L and the storage layer MEML_H will be described.

[0112] The direct mapping method is a method in which, when data held by a memory circuit ME_L included in a memory layer MEML_L is written to a memory circuit ME_H in a memory layer MEML_H, the address of the memory circuit ME_H to which the data is written depends on the address of the memory circuit ME_L holding the data.

[0113] Figure 5 An example of a direct mapping method applied to the storage layer MEML_L and the storage layer MEML_H is shown. As an example, Figure 5 In the semiconductor device DEV, the memory layer MEML_L includes 2 5 =32 blocks of storage capacity, and the storage layer MEML_H includes 2 3 = 8 blocks of storage capacity. Note that in the storage layer MEML_L, 1 block is 1 storage circuit ME_L, and in the storage layer MEML_H, 1 block is 1 storage circuit ME_H. That is, the storage layer MEML_L includes 32 storage circuits ME_L, and the storage layer MEML_H includes 8 storage circuits ME_H.

[0114] Furthermore, memory addresses of “00000” to “11111” are assigned to the 32 memory circuits ME_L of the memory layer MEML_L, respectively. Similarly, memory addresses of “000” to “111” are assigned to the 8 memory circuits ME_H of the memory layer MEML_H, respectively.

[0115] Note that, for the sake of simplicity, it is assumed that both the memory circuit ME_L and the memory circuit ME_H include a matrix memory cell array of one row. In other words, it is assumed that when data is read from the memory circuit ME_L, the memory circuit ME_L uniquely reads the data of the one row. Furthermore, it is assumed that when data is written to the memory circuit ME_H, the data is uniquely written to the one row of the memory circuit ME_H.

[0116] Here, among the 32 memory circuits ME_L in the memory layer MEML_L, attention is paid to the memory circuits ME_L of the block whose last three bits of the memory address are "000" (although Figure 5 Not shown, but Figure 5 There are 4 memory circuits ME_L in the memory layer MEML_L. Figure 5 In the semiconductor device DEV, data of any one of the memory circuits ME_L of the block whose last three bits of the memory address are "000" is sent to the memory circuit ME_H whose memory address is "000" in the memory layer MEML_H.

[0117] Similarly, among the three memory circuits ME_L in the memory layer MEML_L, the memory circuit ME_L in the block whose last three bits of the memory address are "100" is focused. Figure 5 In the semiconductor device DEV, data of any one of the memory circuits ME_L in the block whose last three bits of the memory address are "100" is sent to the memory circuit ME_H whose memory address is "100" in the memory layer MEML_H.

[0118] Similarly, among the 32 memory circuits ME_L in the memory layer MEML_L, attention is paid to the memory circuits ME_L in the block whose last three bits of the memory address are "111". Figure 5 In the semiconductor device DEV, data of any one of the memory circuits ME_L of the block whose last three bits of the memory address are "111" is sent to the memory circuit ME_H whose memory address is "111" in the memory layer MEML_H.

[0119] In short, when data read from the memory layer MEML_L is written to the memory layer MEML_H, the address of the memory circuit ME_H in the memory layer MEML_H to which the data is written is limited to the same value as the last three bits of the memory address of the memory layer MEML_L from which the data is read.

[0120] As described above, in the direct mapping method, when data read from the storage layer MEML_L is written to the storage layer MEML_H, the memory address of the storage circuit ME_H in the storage layer MEML_H, which is the object of data writing, depends on the memory address of the storage circuit ME_L in the storage layer MEML_L from which the data is read. That is, in the direct mapping method, the data written to the storage circuit ME_H is limited to the data read from the storage circuit ME_L of the specific memory address. Therefore, for example, when searching for data of a certain storage circuit ME_L in the storage layer MEML_L from among the plurality of storage circuits ME_H in the storage layer MEML_H, the specified storage circuit ME_H can be found from the storage layer MEML_H using the memory address of the storage circuit ME_L holding the desired data, so the data reading speed can be improved by adopting the direct mapping method.

[0121] A configuration example of the circuit layer SWCL in the case where the direct mapping method is applied to the semiconductor device DEV will be described. Figure 6 Yes Figure 5 FIG. 1 is a circuit diagram showing an example of a circuit structure of an additional circuit layer SWCL in a semiconductor device DEV. Figure 6 In Figure 1A and Figure 1B The circuit layer SWCL is shown schematically as circuit layer SWCLA.

[0122] The circuit layer SWCLA includes switches SW

[00000] to SW

[11111] . Note that Figure 6 The summary shows switch SW

[00000] , switch SW

[00100] , switch SW

[00111] , switch SW

[01000] , switch SW

[01100] , switch

[01111] , switch SW

[10000] , switch SW

[10100] , switch SW

[10111] , and switch SW

[11111] .

[0123] The first terminal of the switch SW

[00000] is electrically connected to the memory circuit ME_L whose memory address is “00000” in the memory layer MEML_L. In addition, the first terminal of the switch SW

[01000] is electrically connected to the memory circuit ME_L whose memory address is “01000” in the memory layer MEML_L. In addition, the first terminal of the switch SW

[10000] is electrically connected to the memory circuit ME_L whose memory address is “10000” in the memory layer MEML_L. In addition, although not shown in the figure, the first terminal of the switch SW

[11000] is electrically connected to the memory circuit ME_L whose memory address is “11000” in the memory layer MEML_L. In addition, each second terminal of the switch SW

[00000] , the switch SW

[01000] , the switch SW

[10000] , and the switch SW

[11000] is electrically connected to the memory circuit ME_H whose memory address is “000” in the memory layer MEML_H.

[0124] One of the switches SW

[00000] , SW

[01000] , SW

[10000] , and SW

[11000] is turned on, and the others are turned off, thereby selecting one of the memory addresses "00000", "01000", "10000", and "11000" in the memory layer MEML_L. Then, the data held by the memory circuit ME_L of the selected memory address is read out, and the data is sent to the memory circuit ME_H of the memory address "000" in the memory layer MEML_H, and the data is stored in the memory circuit ME_H of the memory address "000".

[0125] Similarly, the first terminal of the switch SW

[00100] is electrically connected to the memory circuit ME_L whose memory address is “00100” in the memory layer MEML_L. In addition, the first terminal of the switch SW

[01100] is electrically connected to the memory circuit ME_L whose memory address is “01100” in the memory layer MEML_L. In addition, the first terminal of the switch SW

[10100] is electrically connected to the memory circuit ME_L whose memory address is “10100” in the memory layer MEML_L. In addition, although not shown, the first terminal of the switch SW

[11100] is electrically connected to the memory circuit ME_L whose memory address is “11100” in the memory layer MEML_L. In addition, each second terminal of the switch SW

[00100] , the switch SW

[01100] , the switch SW

[10100] , and the switch SW

[11100] is electrically connected to the memory circuit ME_H whose memory address is “100” in the memory layer MEML_H.

[0126] One of the switches SW

[00100] , SW

[01100] , SW

[10100] , and SW

[11100] is turned on and the others are turned off, thereby selecting one of the memory addresses "00100", "01100", "10100", and "11100" in the memory layer MEML_L. Then, the data held by the memory circuit ME_L of the selected memory address is read out, thereby the data is sent to the memory circuit ME_H of the memory address "100" in the memory layer MEML_H, and the data is stored in the memory circuit ME_H of the memory address "100".

[0127] Similarly, the first terminal of the switch SW

[00111] is electrically connected to the memory circuit ME_L whose memory address is “00111” in the memory layer MEML_L. In addition, the first terminal of the switch SW

[01111] is electrically connected to the memory circuit ME_L whose memory address is “01111” in the memory layer MEML_L. In addition, the first terminal of the switch SW

[10111] is electrically connected to the memory circuit ME_L whose memory address is “10111” in the memory layer MEML_L. In addition, the first terminal of the switch SW

[11111] is electrically connected to the memory circuit ME_L whose memory address is “11111” in the memory layer MEML_L. In addition, each second terminal of the switch SW

[00111] , the switch SW

[01111] , the switch SW

[10111] , and the switch SW

[11111] is electrically connected to the memory circuit ME_H whose memory address is “111” in the memory layer MEML_H.

[0128] One of the switches SW

[00111] , SW

[01111] , SW

[10111] , and SW

[11111] is turned on and the others are turned off, thereby selecting one of the memory addresses "00111", "01111", "10111", and "11111" in the memory layer MEML_L. Then, the data held by the memory circuit ME_L of the selected memory address is read out, thereby the data is sent to the memory circuit ME_H of the memory address "111" in the memory layer MEML_H, and the data is stored in the memory circuit ME_H of the memory address "111".

[0129] To simply explain Figure 6 The circuit layer SWCLA, Figure 7 Show Figure 6 An example of a structure of a portion of a semiconductor device DEV. Note that Figure 7 The circuit layer SWCLA shown is Figure 6The circuit SWCLA shown is different in that a selector MPX is shown in the former. In addition, Figure 7 The summary shows the memory circuits ME_L having the memory addresses “00000”, “01000”, “10000”, and “11000” in the memory layer MEML_L and the memory circuit ME_H having the memory address “000” in the memory layer MEML_H.

[0130] As an example, the selector MPX includes a plurality of input terminals IT and one output terminal OT.

[0131] The plurality of input terminals IT of the selector MPX are electrically connected to the plurality of memory circuits ME_L in the memory layer MEML_L, respectively. The predetermined last few bits of the memory addresses of the plurality of memory circuits ME_L electrically connected to the plurality of input terminals IT of the selector MPX are equal to each other (in Figure 7 In addition, the output terminal OT of the selector MPX is electrically connected to the storage circuit ME_H (in Figure 7 , the memory address of the storage circuit ME_H is "000").

[0132] The selector MPX has, for example, a function of making one of the multiple input terminals IT of the selector MPX and the output terminal OT of the selector MPX conductive according to the signal SSIG input to the selector MPX. In addition, the selector MPX has, for example, a function of selecting one of the input signals input to the multiple input terminals IT of the selector MPX and outputting the selected input signal to the output terminal OT of the selector MPX according to the signal SSIG input to the selector MPX. In addition, the selector MPX has, for example, a function of making the remaining of the multiple input terminals IT of the selector MPX and the output terminal OT of the selector MPX non-conductive.

[0133] For this reason, the selector MPX is sometimes called a multiplexer.

[0134] In addition, a sampling and holding circuit may be provided between the output terminal OT of the selector MPX and the storage circuit ME_H. In the semiconductor device DEV, by providing a sampling and holding circuit between the output terminal OT of the selector MPX and the storage circuit ME_H, data at the output terminal OT of the selector MPX can be temporarily held. That is, data to be written to the storage circuit ME_H can be prepared in advance, thereby increasing the operating speed of the semiconductor device DEV.

[0135] Fig. 8A and Figure 8BEach of them is a circuit diagram showing a specific structural example of the selector MPX.

[0136] and Figure 6 The circuit layer SWCLA shown is similar, Fig. 8A In the selector MPX shown, each first terminal of the switches SW1 to SW4 is electrically connected to the corresponding storage circuit ME_L, and each second terminal of the switches SW1 to SW4 is electrically connected to the storage circuit ME_H. In addition, the control terminal of the switch SW1 is electrically connected to the wiring SL1, the control terminal of the switch SW2 is electrically connected to the wiring SL2, the control terminal of the switch SW3 is electrically connected to the wiring SL3, and the control terminal of the switch SW4 is electrically connected to the wiring SL4.

[0137] As switches SW1 to SW4, for example, electric switches (such as analog switches or transistors) can be used. Note that when, for example, transistors are used as switches SW1 to SW4, the transistors can be transistors (OS transistors) containing oxide semiconductors (metal oxides) in the channel formation region. The metal oxides will be described in detail in Embodiments 2 and 3. In addition, the transistor can also be a transistor (Si transistor) containing silicon in the channel formation region. As silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. can be used. In addition, in addition to electric switches, mechanical switches can also be used.

[0138] It is assumed in this specification and the like that each of the switches SW1 to SW4 is turned on when a high-level potential is input to the control terminal, and is turned off when a low-level potential is input to the control terminal.

[0139] Each of the wirings SL1 to SL4 is used, for example, as a wiring for transmitting a signal (variable potential) for switching the conductive state or non-conductive state of the switches SW1 to SW4. The signals transmitted to the wirings SL1 to SL4 are equivalent to Figure 7 Note that each of the wirings SL1 to SL4 may be used as a wiring for supplying a constant potential (eg, a high-level potential, a low-level potential, a ground potential, or a negative potential) instead of being used as a wiring for supplying a signal (variable potential).

[0140] exist Fig. 8AIn the selector MPX shown in the figure, for example, by supplying a high-level potential to one selected from the wirings SL1 to SL4 and supplying a low-level potential to the rest, it is possible to make a conduction state between one of the plurality of input terminals IT of the selector MPX and the output terminal OT of the selector MPX. Note that when it is desired to make a non-conduction state between all of the plurality of input terminals IT of the selector MPX and the output terminal OT of the selector MPX, for example, a low-level potential may be supplied to each of the wirings SL1 to SL4.

[0141] Figure 8B The selector MPX shown is constructed using a Cetu method using multiple switches. Note that Figure 8B The selector MPX includes a switch SWa1, a switch SWa2, a switch SWb1, a switch SWb2, a switch SWb3 and a switch SWb4. For details about each switch, refer to Fig. 8A Description of switches SW1 to SW4 are shown.

[0142] Each first terminal of the switches SWb1 to SWb4 is electrically connected to the corresponding storage circuit ME_L. In addition, the first terminal of the switch SWa1 is electrically connected to the second terminal of the switch SWb1 and the second terminal of the switch SWb2. In addition, the first terminal of the switch SWa2 is electrically connected to the second terminal of the switch SWb3 and the second terminal of the switch SWb4. The second terminal of the switch SWa1 and the second terminal of the switch SWa2 are electrically connected to the storage circuit ME_H. In addition, the control terminal of the switch SWb1 and the control terminal of the switch SWb3 are electrically connected to the wiring SLb1, the control terminal of the switch SWb2 and the control terminal of the switch SWb4 are electrically connected to the wiring SLb2, the control terminal of the switch SWa1 is electrically connected to the wiring SLa1, and the control terminal of the switch SWa2 is electrically connected to the wiring SLa2.

[0143] For details about the wiring SLa1, the wiring SLa2, the wiring SLb1, and the wiring SLb2, refer to Fig. 8A Description of the wiring SL1 to the wiring SL4 shown.

[0144] In particular, the signal supplied to the wiring SLa1 is preferably a signal that is a logical inversion of the signal supplied to the wiring SLa2. In addition, the signal supplied to the wiring SLb1 is preferably a signal that is a logical inversion of the signal supplied to the wiring SLb2. Thus, one of the switches SWa1 and SWa2 can be turned on and the other can be turned off. In addition, one of the switches SWb1 and SWb2 can be turned on and the other can be turned off. In addition, one of the switches SWb3 and SWb4 can be turned on and the other can be turned off.

[0145] As described above, by supplying a predetermined signal to each of the wiring SLa1, the wiring SLa2, the wiring SLb1, and the wiring SLb2, a conductive state can be established between one of the plurality of input terminals IT of the selector MPX and the output terminal OT of the selector MPX. Note that, when it is desired to make a non-conductive state between all of the plurality of input terminals IT of the selector MPX and the output terminal OT of the selector MPX, for example, a low-level potential can be supplied to each of the wiring SLa1 and the wiring SLa2.

[0146] Note that one embodiment of the present invention is not limited to the structure of the semiconductor device DEV described above. One embodiment of the present invention may have a structure obtained by modifying the semiconductor device described above.

[0147] For example, although the semiconductor device DEV in the above description has a structure in which the storage layer MEML_L includes 32 storage circuits ME_L and the storage layer MEML_H includes 8 storage circuits ME_H, there is no particular limitation on the number of storage circuits ME_L included in the storage layer MEML_L and the number of storage circuits ME_H included in the storage layer MEML_H.

[0148] Furthermore, for example, although the block of the storage circuit ME_H to be stored is set with reference to the last three bits of the memory address of the storage layer MEML_L in the semiconductor device DEV, the memory address referenced by the storage layer MEML_L may be the last 1 bit, the last 2 bits, or the last 4 bits or more. Furthermore, the number of storage circuits ME_L included in the storage layer MEML_L and the number of storage circuits ME_H included in the storage layer MEML_H may also be determined based on the range of the referenced memory address.

[0149] <<Group Associative Mode>> Next, a case where a set associative method is adopted as the storage structure of the storage layer MEML_L and the storage layer MEML_H, which is different from the direct mapping method, is described.

[0150] The set associative method is a method in which, when data held by the storage circuit ME_L included in the storage layer MEML_L is written to the storage circuit ME_H of the storage layer MEML_H, the data held by the storage circuit ME_L included in the storage layer MEML_L is held in one of a plurality of storage circuits ME_H specified based on the address of the storage circuit ME_L.

[0151] Fig. 9 FIG. 2 shows an example of a set associative method applied to the storage layer MEML_L and the storage layer MEML_H. Figure 5 The semiconductor device DEV also has Fig. 9In the semiconductor device DEV, the memory layer MEML_L includes 32 memory circuits ME_L, and the memory layer MEML_H includes 8 memory circuits ME_H. Figure 5 The semiconductor device DEV is similarly Fig. 9 The memory address is also shown in the semiconductor device DEV.

[0152] Note that Fig. 9 In the memory layer MEML_H of the semiconductor device DEV, the block (memory circuit ME_H) with the memory address "000" or "001" is grouped as ST_1. In addition, the block (memory circuit ME_H) with the memory address "010" or "011" is grouped as ST_2. The block (memory circuit ME_H) with the memory address "100" or "101" is grouped as ST_3. The block (memory circuit ME_H) with the memory address "110" or "111" is grouped as ST_4.

[0153] In addition, Figure 5 The semiconductor device DEV also has Fig. 9 In the semiconductor device DEV, it is assumed that the memory circuit ME_L and the memory circuit ME_H both include a matrix memory cell array of one row. In other words, it is assumed that when data is read from the memory circuit ME_L, the memory circuit ME_L uniquely reads the data of the one row. In addition, it is assumed that when data is written to the memory circuit ME_H, the data is uniquely written to the one row of the memory circuit ME_H.

[0154] Here, among the 32 memory circuits ME_L in the memory layer MEML_L, attention is paid to the memory circuits ME_L of the block whose last three bits of the memory address are "000" (although Fig. 9 Not shown, but Fig. 9 There are 4 memory circuits ME_L in the memory layer MEML_L. Fig. 9 In the semiconductor device DEV, data of any one of the memory circuits ME_L of the block whose last three bits of the memory address are "000" is sent to any one of the memory circuits ME_H included in the group ST_1 in the memory layer MEML_H.

[0155] Similarly, among the 32 memory circuits ME_L in the memory layer MEML_L, the memory circuit ME_L of the block whose last three bits of the memory address are "100" is focused on (although Fig. 9 Not shown, but Fig. 9 There are 4 memory circuits ME_L in the memory layer MEML_L. Fig. 9In the semiconductor device DEV, data of any one of the memory circuits ME_L of the block whose last three bits of the memory address are "100" is sent to any one of the memory circuits ME_H included in the group ST_3 in the memory layer MEML_H.

[0156] That is, when the data read from the storage layer MEML_L is written to the storage layer MEML_H, as in the direct mapping method, the memory address of the storage circuit ME_H in the storage layer MEML_H that is the object of data writing depends on the memory address of the storage circuit ME_L of the storage layer MEML_L from which the data is read, but in the group associative method, the storage circuit ME_H that is the object of data writing can be selected from multiple blocks included in the specified group.

[0157] In particular, Fig. 9 The method of selecting the writing object of the data read from the storage layer MEML_L from the two storage circuits ME_H is sometimes called a 2-way set associative method. In addition, the method of selecting the writing object of the data read from the storage layer MEML_L from N (N is an integer greater than 2) storage circuits ME_H is sometimes called an N-way set associative method.

[0158] As in the direct mapping method, in the set associative method, the memory address of the storage circuit ME_H in the storage layer MEML_H as the object of data writing depends on the memory address of the storage circuit ME_L in the storage layer MEML_L from which the data is read. That is, in the set associative method, the data written to the storage circuit ME_H is limited to the data read from the storage circuit ME_L at a specific memory address. Therefore, for example, when searching for data of a certain storage circuit ME_L in the storage layer MEML_L based on a plurality of storage circuits ME_H in the storage layer MEML_H, the memory address of the storage circuit ME_L holding the desired data can be used to find the specified storage circuit ME_H from the storage layer MEML_H, so the data reading speed can be improved by adopting the set associative method. Note that unlike the direct mapping method, there are a plurality of storage circuits ME_H (the number of blocks included in the group) as candidates for the writing object of the data read from the storage layer MEML_L, so the time required to search for the desired data (the time required for reading) is sometimes longer than that of the direct mapping method.

[0159] Fig.10 Show Fig. 9 An example of the structure of the circuit layer SWCL in the semiconductor device DEV. Fig.10 In FIG. 1 , the circuit layer SWCLB is shown as the circuit layer SWCL. In addition, as an example, Fig.10 The storage layer MEML_L and the storage layer MEML_H are also shown. Fig.10The summary shows the memory circuits ME_L having memory addresses “00000”, “01000”, “10000” and “11000” in the memory layer MEML_L and the memory circuits ME_H having memory addresses “000” and “001” in the memory layer MEML_H (group ST_1 ).

[0160] The circuit layer SWCLB includes a selector MPX and a selector DMPX. As an example, the selector MPX includes a plurality of input terminals IT1 and an output terminal OT1. In addition, as an example, the selector DMPX includes an input terminal IT2 and a plurality of output terminals OT2. For details about the selector MPX, please refer to Figure 7 Description of the selector MPX.

[0161] The multiple input terminals IT1 of the selector MPX are electrically connected to the multiple storage circuits ME_L in the storage layer MEML_L, respectively. The specified last few bits of the memory addresses of the multiple storage circuits ME_L, respectively electrically connected to the multiple input terminals IT1 of the selector MPX, are equal to each other. In addition, the output terminal OT1 of the selector MPX is electrically connected to the input terminal IT2 of the selector DMPX. In addition, the multiple output terminals OT2 of the selector DMPX are electrically connected to the storage circuits ME_H of the specified memory addresses, respectively.

[0162] The selector DMPX has, for example, a function of making the input terminal IT2 of the selector DMPX and one of the multiple output terminals OT2 of the selector DMPX conductive according to the signal DSIG input to the selector DMPX. In addition, the selector DMPX has, for example, a function of making the input terminal IT2 of the selector DMPX and the remaining multiple output terminals OT2 of the selector DMPX non-conductive.

[0163] For this reason, the selector DMPX is sometimes called a demultiplexer.

[0164] Fig.11 It is shown Fig.10 A circuit diagram showing a specific structural example of the selector MPX and the selector DMPX.

[0165] Similar to the circuit layer SWCLA shown in FIG8 , Fig.11In the selector DMPX shown, each first terminal of the switches SW1 to SW4 is electrically connected to the corresponding storage circuit ME_L, each second terminal of the switches SW1 to SW4 is electrically connected to each first terminal of the switches SW5 and SW6, and each second terminal of the switches SW5 and SW6 is electrically connected to the corresponding storage circuit ME_H. In addition, the control terminal of the switch SW1 is electrically connected to the wiring SL1, the control terminal of the switch SW2 is electrically connected to the wiring SL2, the control terminal of the switch SW3 is electrically connected to the wiring SL3, and the control terminal of the switch SW4 is electrically connected to the wiring SL4. In addition, the control terminal of the switch SW5 is electrically connected to the wiring SL5, and the control terminal of the switch SW5 is electrically connected to the wiring SL5.

[0166] For details about the wirings SL1 to SL4, refer to Fig. 8A Description of the wiring SL1 to the wiring SL4 shown.

[0167] The wiring SL5 and the wiring SL6 are each used as a wiring for transmitting a signal (variable potential) for switching the conductive state or non-conductive state of the switch SW1 to the switch SW6. The signals transmitted to the wiring SL5 and the wiring SL6 are equivalent to Fig.10 Note that the wiring SL5 and the wiring SL6 may each be used as a wiring for supplying a constant potential (eg, a high-level potential, a low-level potential, a ground potential, or a negative potential) instead of being used as a wiring for supplying a signal (variable potential).

[0168] exist Fig.11 In the selector MPX shown in the figure, for example, by supplying a high level potential to one selected from the wirings SL1 to SL4 and supplying a low level potential to the rest, one of the plurality of input terminals IT1 of the selector MPX and the output terminal OT1 of the selector MPX can be brought into conduction. That is, the memory circuit ME_L included in the memory layer MEML_L can be selected by the above operation. In addition, for example, when one of the wirings SL5 and SL6 is supplied with a high level potential and the other is supplied with a low level potential, Fig.11 The selector DMPX shown can make the input terminal IT2 of the selector DMPX and one of the multiple output terminals OT2 of the selector MPX into a conductive state. That is, the memory circuit ME_H included in the memory layer MEML_H can be selected through the above operation. As a result, the memory circuit ME_L from which data is read and the memory circuit ME_H to which the data is written become conductive.

[0169] also, Fig.11 One or both of the selector MPX and the selector DMPX in the embodiment may also have the following features: Figure 8BThe circuit structure of the Seto method is similar to the selector MPX (not shown).

[0170] Alternatively, a sampling and holding circuit may be provided between one of the plurality of output terminals OT2 of the selector DMPX and one of the plurality of storage circuits ME_H. In the semiconductor device DEV, by providing a sampling and holding circuit between the output terminal OT2 of the selector DMPX and the storage circuit ME_H, data of the output terminal OT2 of the selector DMPX may be temporarily held. Fig.11 In the semiconductor device DEV, by providing a sampling and holding circuit between the output terminal OT2 of the selector DMPX and the storage circuit ME_H, the data written to each storage circuit ME_H having the memory addresses "000" and "001" can be temporarily held in advance. In addition, by making the sampling and holding circuits output the write data at the same time, the write data can be sent to each storage circuit ME_H having the memory addresses "000" and "001" at the same time. In other words, the writing operation to each storage circuit ME_H having the memory addresses "000" and "001" can be synchronized. Therefore, it is not necessary to operate each of the plurality of storage circuits ME_H separately, thereby increasing the operating speed of the semiconductor device DEV.

[0171] Note that one embodiment of the present invention is not limited to the structure of the semiconductor device DEV described above. One embodiment of the present invention may have a structure obtained by modifying the semiconductor device DEV described above.

[0172] For example, although the semiconductor device DEV in the above description has a structure in which the storage layer MEML_L includes 32 storage circuits ME_L and the storage layer MEML_H includes 8 storage circuits ME_H, there is no particular limitation on the number of storage circuits ME_L included in the storage layer MEML_L and the number of storage circuits ME_H included in the storage layer MEML_H.

[0173] In addition, for example, although the group in the storage layer MEML_H as the storage object is set with reference to the last 3 bits of the memory address of the storage layer MEML_L in the above-mentioned semiconductor device DEV, the memory address referenced by the storage layer MEML_L may also be the last 1 bit, the last 2 bits, or the last 4 bits or more. Alternatively, although the number of blocks in the group is set to two as a 2-way group associative method above, the number of blocks in the group may also be set to three or more. In addition, the number of storage circuits ME_L included in the storage layer MEML_L and the number of storage circuits ME_H included in the storage layer MEML_H may also be determined based on the range of the referenced memory address and the number of blocks in the group.

[0174] <<Fully Associative Mode>> Next, a description will be given of a case where a fully associative method is adopted as a storage structure of the storage layer MEML_L and the storage layer MEML_H, which is different from the direct mapping method and the set associative method.

[0175] The fully associative method is a method in which data read out from one selected from a plurality of memory circuits ME_L included in the memory layer MEML_L is held in one selected from a plurality of memory circuits ME_H in the memory layer MEML_H, the selected memory circuit ME_H being independent of the memory address of the selected memory circuit ME_L. That is, in the fully associative method, there is no particular restriction on data written to the memory circuit ME_H in the memory layer MEML_H.

[0176] Fig.12 An example of a fully associative method applied to the storage layer MEML_L and the storage layer MEML_H is shown. Figure 5 The semiconductor device DEV also has Fig.12 In the semiconductor device DEV, the memory layer MEML_L includes 32 memory circuits ME_L, and the memory layer MEML_H includes 8 memory circuits ME_H. Figure 5 The semiconductor device DEV is similarly Fig.12 The memory address is also shown in the semiconductor device DEV.

[0177] Note that, as described in the direct mapping method and the set associative method, in the semiconductor device DEV, the number of memory circuits ME_L included in the memory layer MEML_L may not be 32. Similarly, the number of memory circuits ME_H included in the memory layer MEML_H may not be eight.

[0178] In addition, Fig.12 The semiconductor device DEV also has Figure 5 In the semiconductor device DEV, it is assumed that the memory circuit ME_L and the memory circuit ME_H both include a matrix memory cell array of one row. In other words, it is assumed that when data is read from the memory circuit ME_L, the memory circuit ME_L uniquely reads the data of the one row. In addition, it is assumed that when data is written to the memory circuit ME_H, the data is uniquely written to the one row of the memory circuit ME_H.

[0179] The data written to one of the plurality of memory circuits ME_H selected from the memory layer MEML_H is the data read from one of the plurality of memory circuits ME_L selected from the memory layer MEML_L. Fig.12In the semiconductor device DEV, an example is shown in which data read from one of the memory circuits ME_L with memory addresses “00000” to “11111” in the memory layer MEML_L is written to the memory circuit ME_H with memory address “001” in the memory layer MEML_H.

[0180] like Fig.12 As shown, each memory circuit ME_H in the memory layer MEML_H of the semiconductor device DEV may store one of the data held by the memory circuit ME_L in the memory layer MEML_L with the memory address of “00000” to “11111”. Fig.13 A specific example will be described. The data held by the storage circuit ME_L with the memory address “00000” in the storage layer MEML_L is written to the storage circuit ME_H with the memory address “000” in the storage layer MEML_H. The data held by the storage circuit ME_L with the memory address “00100” in the storage layer MEML_L is written to the storage circuit ME_H with the memory address “001” in the storage layer MEML_H. The data held by the storage circuit ME_L with the memory address “01000” in the storage layer MEML_L is written to the storage circuit ME_H with the memory address “010” in the storage layer MEML_H. The data held by the storage circuit ME_L with the memory address “10100” in the storage layer MEML_L is written to the storage circuit ME_H with the memory address “011” in the storage layer MEML_H. The data held by the storage circuit ME_L with the memory address “10010” in the storage layer MEML_L is written to the storage circuit ME_H with the memory address “100” in the storage layer MEML_H. The data held by the storage circuit ME_L with the memory address “10100” in the storage layer MEML_L is written to the storage circuit ME_H with the memory address “101” in the storage layer MEML_H. The data held by the storage circuit ME_L with the memory address “00111” in the storage layer MEML_L is written to the storage circuit ME_H with the memory address “110” in the storage layer MEML_H. The data held by the storage circuit ME_L with the memory address “01101” in the storage layer MEML_L is written to the storage circuit ME_H with the memory address “111” in the storage layer MEML_H.

[0181] In the fully associative method, for example, when there is an empty block (memory circuit ME_H that does not hold data) in the memory layer MEML_H, data held by one of the memory circuits ME_L with memory addresses "00000" to "11111" in the memory layer MEML_L can be stored in the empty block. Therefore, by adopting the fully associative method, data can be written preferentially to the memory circuit ME_H of the empty block, so the number of memory circuits ME_H of the empty block (memory circuits ME_H in an idle state) can be reduced.

[0182] Fig.14 Show Fig.13 An example of the structure of the circuit layer SWCL in the semiconductor device DEV. Fig.14 In FIG. 1 , the circuit layer SWCLC is shown as the circuit layer SWCL. In addition, Fig.14 Also shown are the storage layer MEML_L and the storage layer MEML_H.

[0183] The circuit layer SWCLC includes a selector MPX and a selector DMPX. As an example, the selector MPX includes a plurality of input terminals IT1 and an output terminal OT1. In addition, as an example, the selector DMPX includes an input terminal IT2 and a plurality of output terminals OT2. For details about the selector MPX, please refer to Figure 7 For more information about selector DMPX, refer to Fig.10 Description of the selector DMPX.

[0184] The multiple input terminals IT1 of the selector MPX are electrically connected to all the memory circuits ME_L in the memory layer MEML_L. In addition, the output terminal OT2 of the selector MPX is electrically connected to the input terminal IT2 of the selector DMPX. In addition, the multiple output terminals OT2 of the selector DMPX are electrically connected to all the memory circuits ME_H in the memory layer MEML_H.

[0185] For the structure of the selector MPX, please refer to Fig. 8A and Figure 8B For details about the structure of the selector DMPX, refer to Fig.11 Description of the selector DMPX is shown.

[0186] In addition, the group association method used in the description Fig.11 The semiconductor device DEV also has Fig.14 In the semiconductor device DEV shown in the figure, a sample-and-hold circuit may be provided between one of the plurality of output terminals OT2 of the selector DMPX and one of the plurality of storage circuits ME_H.

[0187] Note that one embodiment of the present invention is not limited to the structure of the above-mentioned semiconductor device. One embodiment of the present invention may have a structure obtained by modifying the above-mentioned semiconductor device.

[0188] For example, in the description of the direct mapping method, the set associative method, and the full associative method, the case where the storage circuit ME_L and the storage circuit ME_H each include one row of a matrix storage cell array is taken as an example for description, but the storage circuit ME_L and the storage circuit ME_H may each include multiple rows of a matrix storage cell array. In this case, data read from the i-th row (here, i is an integer greater than 1) of the storage cell array in the storage circuit ME_L is preferably written to the i-th row of the storage cell array in the storage circuit ME_H.

[0189] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0190] (Implementation Method 2) In this embodiment, a configuration example of a memory circuit included in the semiconductor device DEV and the memory layers MEML_L and MEML_H described in the above embodiment will be described.

[0191] Fig.15 It is a perspective schematic diagram showing a structural example of a semiconductor device DEV. Fig.16 1 is a block diagram of a structure example of a semiconductor device DEV. The semiconductor device DEV includes a drive circuit region 50, a control processing region 80, a circuit layer 90, and N layers (N is an integer greater than 1) of cell array layers 60. In addition, one layer of the cell array layer 60 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns.

[0192] Fig.16 An example is shown in which a cell array layer 60_k is configured with a memory cell 10[1,1], a memory cell 10[m,1] (here, m is an integer greater than 1), a memory cell 10[1,n] (here, n is an integer greater than 1), a memory cell 10[m,n], and a memory cell 10[i,j] (here, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n).

[0193] also, Fig.16 The example in which the control processing region 80 includes a cell array 70 , a drive circuit 71 , a drive circuit 72 , an ALU (arithmetic logic unit) 81 , an ALU controller 82 , an instruction decoder 83 , an interrupt controller 84 , and a timing controller 85 is shown.

[0194] Note that the cell array layers 60_1 to 60_N correspond to the memory layer MEML_L described in Embodiment 1. The circuit layer 90 corresponds to the circuit layer SWCL described in Embodiment 1. The cell array 70 corresponds to the memory layer MEML_H described in Embodiment 1.

[0195] The driving circuit region 50 has a function of driving the memory cells 10 included in the cell array layers 60_1 to 60_N. For example, the driving circuit region 50 may perform a work of writing data to the memory cells 10 or a work of reading data from the memory cells 10.

[0196] The control processing area 80 corresponds to, for example, a processor that can be used in a computer. Note that the cell array 70, the drive circuit 71, and the drive circuit 72 are used as a cache memory or a register included in the processor. Specifically, for example, the drive circuit 71 is used as a column driver for the cell array 70, and the drive circuit 72 is used as a row driver for the cell array 70. In addition, Fig.16 In the embodiment, the cell array 70 includes a plurality of memory cells 75 arranged in an array.

[0197] The N-layer cell array layer 60 is, for example, disposed on the circuit layer 90. The circuit layer 90 is, for example, disposed on the drive circuit region 50 and the control processing region 80. In particular, by disposing the N-layer cell array layer 60 on the drive circuit region 50 and the control processing region 80, the occupied area of ​​the semiconductor device DEV can be reduced. In addition, the storage capacity per unit area in the cell array layer 60 can be increased.

[0198] Note that the driver circuit region 50 and the control processing region 80 may be arranged on the same substrate. For example, the driver circuit region 50 and the control processing region 80 may be formed on a semiconductor substrate (for example, a single crystal substrate containing silicon). Note that the structure of the semiconductor device DEV is not limited to Fig.15 For example, the driving circuit region 50 may also be disposed on the control processing region 80. In this case, the driving circuit region 50 and the control processing region 80 may be disposed on different substrates and the driving circuit region 50 may be disposed on the control processing region 80 using Cu-Cu (copper-copper) direct bonding technology or the like.

[0199] In the present embodiment, the first cell array layer 60 is represented as cell array layer 60_1, the second cell array layer 60 is represented as cell array layer 60_2, and the third cell array layer 60 is represented as cell array layer 60_3. In addition, the k-th cell array layer 60 (k is an integer greater than 1 and less than N) is represented as cell array layer 60_k, and the N-th cell array layer 60 is represented as cell array layer 60_N. In the present embodiment, when explaining matters related to the entire N-layer cell array layer 60 or showing matters common to each layer of the N-layer cell array layer 60, it is sometimes simply represented as "cell array layer 60".

[0200] <Configuration Example of Control Processing Region 80> exist Fig.16 In the embodiment, the control processing area 80 includes, for example, an ALU 81, an ALU controller 82, an instruction decoder 83, an interrupt controller 84, and a timing controller 85. Note that Fig.16 The control processing area 80 shown is only an example of a simplified structure, and the control processing area 80 included in the actual processor has various structures depending on its purpose. Fig.16 The structure of the CPU or arithmetic circuit shown is a core, and multiple cores are set up and made to work simultaneously, that is, a structure like a GPU can also be used. In addition, the number of bits that can be processed in the internal arithmetic circuit of the CPU, the system bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, or 256 bits or more.

[0201] The instruction input to the control processing area 80 is input to the instruction decoder 83 and decoded. After being decoded, the instruction is input to the ALU controller 82, the interrupt controller 84 and the timing controller 85. In addition, the instruction can also be input to the drive circuit 71 and the drive circuit 72 of the storage circuit included in the control processing area 80.

[0202] The ALU controller 82, the interrupt controller 84, and the timing controller 85 can perform various controls according to the decoded instructions. Specifically, the ALU controller 82 generates a signal for controlling the operation of the ALU 81. In addition, when the program is executed in the driver circuit area 50, the interrupt controller 84 judges the interrupt request from the external input / output device or the peripheral circuit according to its priority or the state of the mask, etc. and processes the request. In addition, the storage circuit included in the control processing area 80 can generate the address of the storage cell included in the cell array 70 according to the decoded instruction and read data from the cell array 70 or write data to the cell array 70 according to the status of the driver circuit area 50.

[0203] In addition, the timing controller 85 generates a signal for controlling the operation timing of the ALU 81, the ALU controller 82, the instruction decoder 83, the interrupt controller 84, and the storage circuit included in the control processing area 80. For example, the timing controller 85 has an internal clock generator that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the above-mentioned various circuits. Note that the clock signal generated by the timing controller 85 may also be the above-mentioned signal CLK.

[0204] The storage circuit included in the control processing area 80 selects the holding operation in the storage cell 75 of the cell array 70 according to the instruction from the ALU 81. In other words, it is selected whether the data is held by the flip-flop or by the capacitor in the storage cell of the cell array 70. In the case where the data is held by the flip-flop, the power supply voltage is supplied to the storage cell 75 in the cell array 70. In the case where the data is held by the capacitor, the data is rewritten to the capacitor, and the supply of the power supply voltage to the storage cell 75 in the cell array 70 may be stopped.

[0205] <Structural Example of Driving Circuit Region 50> exist Fig.16 In the embodiment, the driving circuit area 50 includes a PSW 22 (power switch), a PSW 23 and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32 and a voltage generating circuit 33.

[0206] In the driving circuit area 50, the above-mentioned circuits, signals and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal. Fig.16 An example is shown in which the signal BW, the signal CE, the signal GW, the signal CLK, the signal WAKE, the signal PON1 , and the signal PON2 are generated in the control processing region 80 and transmitted from the control processing region 80 to the drive circuit region 50 .

[0207] In addition, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signal PON1 and the signal PON2 are power gating control signals. In addition, the signal PON1 and the signal PON2 may be generated in the control circuit 32 instead of in the control processing area 80.

[0208] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the driving circuit region 50 and the cell array layer 60. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the driving circuit region 50 and the cell array layer 60. In addition, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above-mentioned operation mode.

[0209] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0210] The peripheral circuit 41 is a circuit for writing and reading data from the memory cell 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0211] The row decoder 42 and the column decoder 44 have a function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed.

[0212] The row driver 43 has a function of selecting a write and read word line (for example, a word line described later) specified by the row decoder 42. Fig.17 The function of any one of the wiring WL[1] to the wiring WL[m] shown.

[0213] The column driver 45 has the following functions: writing data to the memory cell 10; reading data from the memory cell 10; and holding the read data. The column driver 45 has the function of selecting the write and read bit lines (for example, the bit lines described later) specified by the column decoder 44. Fig.17 The functions of the wiring BL[1] to the wiring BL[n]) shown.

[0214] The input circuit 47 has a function of holding the signal WDA. The data (first data in the above embodiment) held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. In the above embodiment, the read data (Dout) is processed as the data of the operation result. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the drive circuit area 50. The data output from the output circuit 48 is the signal RDA.

[0215] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the driver circuit area 50 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high level, which is higher than VDD. The on and off states of PSW22 are switched by the signal PON1, and the on and off states of PSW23 are switched by the signal PON2. Fig.16 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0216] Next, the electrical connection between the peripheral circuit 41 and the cell array layer 60 will be described.

[0217] Fig.17 4 is a block diagram showing a structural example of the peripheral circuit 41 and the cell array layer 60_k. Fig.17 In the embodiment, the row decoder 42 and the row driver 43 are electrically connected to each of the wirings WL[1] to WL[m], and the column decoder 44, the column driver 45 and the read amplifier 46 are electrically connected to each of the wirings BL[1] to BL[n].

[0218] Wiring WL[1] to wiring WL[m] are used as word lines. In addition, each of wiring WL[1] to wiring WL[m] may be a plurality of wirings instead of one wiring. For example, wiring WL may also have a write word line and a read word line.

[0219] Wiring BL[1] to wiring BL[n] are used as bit lines. In addition, each of wiring BL[1] to wiring BL[n] may be a plurality of wirings instead of one wiring. For example, wiring BL may also have a write bit line and a read bit line.

[0220] The memory cell 10 [i, j] arranged in the i-th row and the j-th column is electrically connected to the wiring WL [i] and the wiring BL [j].

[0221] like Fig.17 As shown, by electrically connecting the cell array layer 60 — k and the peripheral circuit 41 , data can be written to the cell array layer 60 — k and data can be read from the cell array layer 60 — k.

[0222] <Structural Example of Cell Array Layer 60 and Cell Array 70> Next, a circuit structure applicable to the cell array layer 60 or the cell array 70 will be described.

[0223] <<Structure Example 1>> Fig.18AFIG. 2 shows a structural example in which DRAM is used as the cell array layer 60 or the cell array 70 (hereinafter collectively referred to as a memory cell array MCA). DRAM can be used, for example, for Figure 2 In the storage hierarchy 100, at least one selected from the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104. In particular, DRAM is preferably used for the main memory 104, for example.

[0224] Fig.18A A memory cell array MCA with m rows and n columns is shown, wherein only the memory cells MC located at the 1st row and 1st column, the 1st row and the nth column, the mth row and the 1st column, and the mth row and the nth column are shown. Fig.18A , the 1st row wiring WL is illustrated as wiring WL[1], the mth row wiring WL is illustrated as wiring WL[m], the 1st column wiring BL is illustrated as wiring BL[1], and the nth row wiring BL is illustrated as wiring BL[n].

[0225] Note that the memory cell MC corresponds to the memory cell 10 when the memory cell array MCA is the cell array layer 60 , and corresponds to the memory cell 75 when the memory cell array MCA is the cell array 70 .

[0226] exist Fig.18A In the memory cell array MCA, the memory cell MC includes a transistor M1 and a capacitor C1.

[0227] In the memory cell MC in the i-th row and j-th column (i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n), the first terminal of the transistor M1 is electrically connected to the wiring BL[j], the second terminal of the transistor M1 is electrically connected to the first terminal of the capacitor C1, and the gate of the transistor M1 is electrically connected to the wiring WL[i]. The second terminal of the capacitor C1 is electrically connected to the wiring CL.

[0228] The wiring CL is used as a wiring for supplying a constant potential, for example. The constant potential may be a high level potential, a low level potential, a ground potential, or a negative potential. Note that the wiring CL may also be used as a wiring for supplying a variable potential (for example, a pulse potential).

[0229] Note that although Fig.18A In the memory cell array MCA, the transistor M1 is an n-channel transistor, but the transistor M1 may also be a p-channel transistor. Fig.18A The transistors in the memory cell array MCA may be replaced by p-channel transistors in some cases, and vice versa, the p-channel transistors in some cases, as shown in this specification.

[0230] In addition, the transistors shown in this specification and the like are Fig.18A The transistor M1 and the like included in the memory cell array MCA may be a Si transistor containing silicon in the channel formation region. As silicon, for example, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon or single crystal silicon may be cited. In addition, the transistors shown in this specification and the like may be OS transistors. The OS transistors will be described in this embodiment and embodiment 3. In addition, as transistors other than OS transistors and Si transistors, for example, transistors containing germanium (Ge) and the like in the channel formation region, transistors containing compound semiconductors such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) or silicon germanium (SiGe) in the channel formation region, transistors containing carbon nanotubes in the channel formation region, or transistors containing organic semiconductors in the channel formation region may be used.

[0231] In particular, the metal oxide contained in the channel formation region of the OS transistor is preferably an oxide selected from one or more of indium, element M (element M may include aluminum, gallium, yttrium, tin, copper, vanadium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt or antimony) and zinc. In addition, the off-state current of the OS transistor containing the metal oxide in the channel formation region can be 10aA (1×10 -17 A) or less, preferably 1aA (1×10 -18 A) or less, more preferably 10zA (1×10 -20 A) or less, more preferably 1zA (1×10 -21 A) or less, more preferably 100 μA (1×10 -22 A) or less. In addition, in the OS transistor, the carrier concentration of the metal oxide is low, so even if the temperature of the OS transistor changes, the off-state current is kept low. For example, even if the temperature of the OS transistor is 150°C, the off-state current per channel width of 1μm can be 100zA.

[0232] In particular, a DRAM using an OS transistor as the transistor M1 is sometimes referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).

[0233] Furthermore, the capacitor C1 may be a ferroelectric capacitor including a pair of electrodes and a ferroelectric material interposed between the pair of electrodes. In this case, the memory cell array MCA is sometimes referred to as FeRAM (Ferroelectric Random Access Memory).

[0234] At this time, the wiring CL is used as a plate line for polarizing the ferroelectric film of the ferroelectric capacitor or inverting the polarization of the ferroelectric film and is not used as a wiring for supplying a constant potential.

[0235] For example, the transistor M1 is turned on, a voltage corresponding to the data is supplied to the wiring BL, and a predetermined potential is supplied to the wiring CL to polarize the ferroelectric film included in the capacitor C1, thereby performing a data writing operation on the capacitor C1 as a ferroelectric capacitor. In addition, after the transistor M1 is turned on, a pulse potential is supplied to the wiring CL, thereby performing an operation of reading the written data from the capacitor C1. Note that the magnitude of the pulse potential supplied to the wiring CL may also be the same as the potential supplied to the wiring CL during writing. When the data held by the capacitor C1 is read out, it is determined whether the held data is "0" or "1" based on whether the pulse potential from the wiring CL causes polarization reversal. When the polarization reversal occurs in the ferroelectric film in the capacitor C1, current flows through the wiring BL via the transistor M1. That is, by obtaining the amount of current flowing through the wiring BL using, for example, a readout circuit having a structure of an integration circuit (or a current-charge (IQ) conversion circuit) and a current-voltage conversion circuit, the data held by the capacitor C1 can be read out.

[0236] <<Structure Example 2>> The memory cell array MCA is not limited to Fig.18A The structure of the circuit diagram shown may also be appropriately changed Fig.18A For example, Fig.18B As shown, in Fig.18A The transistor M1 in the memory cell array MCA may also be provided with a back gate.

[0237] Although Fig.18B The electrical connection relationship of the back gate of transistor M1 is not shown in the figure, but the connection object of the back gate of transistor M1 can be determined according to the desired operation or characteristics of transistor M1. For example, the electrical connection object of the back gate of transistor M1 can be the gate of transistor M1. By electrically connecting the gate and the back gate of transistor M1, the current flowing when transistor M1 is in the on state can be increased. In addition, for example, the back gate of transistor M1 can be provided with a wiring for electrically connecting to an external circuit to supply a potential to the back gate of transistor M1 through the external circuit, so as to increase the threshold voltage. By adopting this structure, the off-state current of transistor M1 can be reduced by the external circuit.

[0238] exist Fig.18B In the memory cell array MCA, the above-mentioned OS transistor can be used as the transistor M1 including a back gate, for example.

[0239] Note that although this structure example shows Fig.18AThe transistor M1 in the memory cell array MCA is provided with a back gate structure, but transistors included in other structures may also be provided with a back gate. That is, the transistors shown in this specification and the like may be transistors including a back gate.

[0240] <<Structure Example 3>> Fig.18C The following is a structural example of using ReRAM (Resistive Random Access Memory) as the memory cell array MCA. ReRAM can be used, for example, Figure 2 In the storage hierarchy 100, at least one selected from the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104. In particular, ReRAM is preferably used for the main memory 104, for example.

[0241] exist Fig.18C In the memory cell array MCA, the memory cell MC includes a transistor M1 and a variable resistance element VR. Fig.18C The memory cell MC shown uses a variable resistance element VR instead of Fig.18A The capacitor C1 in the memory cell MC.

[0242] <<Structure Example 4>> Fig.18D The following is a structural example of using MRAM (Magnetic Random Access Memory) as the memory cell array MCA. MRAM can be used, for example, Figure 2 In the storage hierarchy 100, at least one selected from the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104. In particular, MRAM is preferably used for the main memory 104, for example.

[0243] exist Fig.18D In the memory cell array MCA, the memory cell MC includes a transistor M1 and an MTJ (Magnetic Tunnel Junction) element MR. Fig.18D The memory cell MC shown uses an MTJ element MR instead of Fig.18A The capacitor C1 in the memory cell MC.

[0244] <<Structure Example 5>> Fig.18E The following is a configuration example in which a PRAM (Phase change Random Access Memory) is used as the memory cell array MCA. PRAM can be used, for example, Figure 2In the storage hierarchy 100, one or more selected from the register 101, the first cache memory 102, the second cache memory 103, and the main memory 104. In particular, a PRAM is preferably used for the main memory 104, for example.

[0245] exist Fig.18E In the memory cell array MCA, the memory cell MC includes a transistor M1 and a phase change memory PCM. Fig.18E The memory cell MC shown uses a phase change memory PCM instead of Fig.18A The capacitor C1 in the memory cell MC.

[0246] By changing the ferroelectric material of the capacitor C1 used for DRAM to a phase change material in a manufacturing process, a phase change memory PCM included in a PRAM can be manufactured. That is, by using a manufacturing device for DRAM, a PRAM can be manufactured.

[0247] <<Structure Example 6>> Fig.19A An example of a memory cell array MCA including memory cells having a structure of two transistors and one capacitor is shown. Fig.19A The memory cell array MCA shown can be used, for example, for Figure 2 One or more of the storage hierarchy 100 is selected from the register 101, the first cache memory 102, the second cache memory 103 and the main memory 104.

[0248] Fig.19A A memory cell array MCA with m rows and n columns is shown, wherein only the memory cells MC located at the 1st row and 1st column, the 1st row and the nth column, the mth row and the 1st column, and the mth row and the nth column are shown. Fig.19A In the diagram, the wiring located in the 1st column is illustrated as wiring RBL[1], wiring WBL[1], and wiring SL[1], the wiring located in the mth column is illustrated as wiring RBL[n], wiring WBL[n], and wiring SL[n], the wiring located in the 1st row is illustrated as wiring WL[1] and wiring RWL[1], and the wiring located in the mth row is illustrated as wiring WL[m] and wiring RWL[m].

[0249] The memory cell MC includes a transistor M2 , a transistor M3 , and a capacitor C2 .

[0250] As the transistor M2 and the transistor M3 , for example, transistors that can be used as the transistor M1 can be used.

[0251] In particular, when an OS transistor is used as the transistor M2, Fig.19AThe semiconductor device including the memory cell MC shown is called a NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory).

[0252] In the memory cell MC in the i-th row and j-th column, the first terminal of the transistor M2 is electrically connected to the first terminal of the capacitor C2, the second terminal of the transistor M2 is electrically connected to the wiring WBL[j], and the gate of the transistor M2 is electrically connected to the wiring WWL[i]. The second terminal of the capacitor C2 is electrically connected to the wiring RWL[i]. The first terminal of the transistor M3 is electrically connected to the wiring RBL[j], the second terminal of the transistor M3 is electrically connected to the wiring SL[j], and the gate of the transistor M3 is electrically connected to the first terminal of the capacitor C2. Note that Fig.19A In the figure, the wiring WWL[i], the wiring RWL[i], the wiring RBL[j], the wiring WBL[j], and the wiring SL[j] are omitted.

[0253] The wiring WBL[j] is used as a write bit line, and the wiring RBL[j] is used as a read bit line. The wiring WBL[j] and the wiring RBL[j] are each equivalent to Fig.17 The wiring BL shown in FIG. 1 is used as a write word line, and the wiring RWL[i] is used as a read word line. The wiring WWL[i] and the wiring RWL[i] are each equivalent to Fig.17 The wiring WL shown.

[0254] In addition, when writing or reading data, it is preferable that a constant potential such as a high level potential is supplied to the wiring RWL[i]. In addition, when retaining data, it is preferable that a constant potential such as a low level potential is supplied to the wiring RWL[i].

[0255] The wiring SL[j] is used as a wiring for supplying a predetermined potential when reading data from the memory cell MC.

[0256] A high level potential is supplied to the wiring WWL[i] to turn on the transistor M2. In other words, the wiring WBL[j] and the first terminal of the capacitor C2 of each memory cell MC are turned on, thereby writing data to the memory cell MC of the i-th row and j-th column. At this time, it is preferred to supply a high level potential to the wiring RWL[i]. Specifically, when the transistor M2 is in the on state, a potential corresponding to the information to be recorded is supplied to the wiring WBL[j] to write the potential to the first terminal of the capacitor C2 and the gate of the transistor M3. Then, a low level potential is supplied to the wiring WL[i] to turn off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor C2 and the potential of the gate of the transistor M3. In addition, the potential of the wiring RWL[i] is changed from a high level potential to a low level potential, and the gate potential of the transistor M3 is reduced by the capacitive coupling of the capacitor C2, so that the transistor M3 is turned off.

[0257] A high-level potential is supplied to the wiring RWL[i], and a predetermined potential is supplied to the wiring SL[j], thereby reading data from the memory cell MC in the i-th row and j-th column. Since the current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, the potential held by the first terminal of the capacitor C2 (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL[j] connected to the first terminal of the transistor M3. In other words, the information written in the memory cell can be read from the potential held by the first terminal of the capacitor C2 (or the gate of the transistor M3).

[0258] in addition, Fig.17 The memory cell MC shown is not limited to Fig.19A The memory cell MC shown. Fig.19A In the memory cell MC shown, circuit selection and circuit connection can be changed according to the situation. For example, transistors provided with back gates can be used as the transistors M2 and M3.

[0259] In addition, Fig.19A In the memory cell array MCA, the wiring WBL[j] and the wiring RBL[j] may be used as one wiring. Fig.19B The memory cell array MCA shown has a Fig.19A The structure in which the wiring WBL[j] and the wiring RBL[j] in the memory cell array MCA are always used as the wiring BL[j]. By always using a plurality of wirings as one wiring, the circuit area of ​​the memory cell array MCA can be reduced.

[0260] Alternatively, you can Fig.19A The circuit structure of the memory cell MC shown is changed to Fig.19CThe memory cell MC is shown. Fig.19C The memory cell MC shown includes a transistor M6. Fig.19A The memory cells MC shown are different.

[0261] In the memory cell MC in the i-th row and j-th column, the first terminal of the transistor M2 is electrically connected to the first terminal of the capacitor C2, the second terminal of the transistor M2 is electrically connected to the wiring WBL[j], and the gate of the transistor M2 is electrically connected to the wiring WWL[i]. The second terminal of the capacitor C2 is electrically connected to the wiring CL[i]. The first terminal of the transistor M3 is electrically connected to the first terminal of the transistor M6, the second terminal of the transistor M3 is electrically connected to the wiring SL[j], and the gate of the transistor M3 is electrically connected to the first terminal of the capacitor C2. In addition, the second terminal of the transistor M6 is electrically connected to the wiring RBL[j], and the gate of the transistor M6 is electrically connected to the wiring RWL[j]. Note that in Fig.19C In the figure, the wiring WWL[i], the wiring RWL[i], the wiring CL[j], the wiring RBL[j], the wiring WBL[j], and the wiring SL[j] are omitted.

[0262] The wiring CL[i] is used as a wiring for supplying a constant potential, for example. The constant potential may be a high level potential, a low level potential, a ground potential, or a negative potential. Note that the wiring CL[i] may also be used as a wiring for supplying a variable potential (for example, a pulse potential).

[0263] exist Fig.19C In the memory cell MC, the transistor M6 is used as a read transistor. As the transistor M6, a transistor that can be used as the transistor M2 or the transistor M3 can be used.

[0264] exist Fig.19A In the memory cell MC, the wiring RWL[i] used as the read word line is electrically connected to the second terminal of the capacitor C2, and Fig.19C In the memory cell MC, the wiring CL[i] is electrically connected to the second terminal of the capacitor C2 as a wiring for supplying a constant potential.

[0265] exist Fig.19A In the memory cell MC, since the gate potential of the transistor M3 is changed by the capacitive coupling of the capacitor C2 to perform the read operation, a read error may occur when the gate potential of the transistor M3 is incorrectly changed due to parasitic capacitance or the like. Fig.19C In the memory cell MC, the gate potential of the transistor M3 is not changed due to the capacitive coupling through the capacitor C2, so the above-mentioned read error does not occur.

[0266] <<Structure Example 7>> Fig. 20AAn example of an SRAM that can be used for a memory cell MC in a memory cell array MCA is shown. For example, an SRAM can be used for Figure 2 In the storage hierarchy 100, at least one selected from the register 101, the first cache memory 102, the second cache memory 103 and the main memory 104. In particular, SRAM can be used for the register 101, the first cache memory 102 and the second cache memory 103, for example.

[0267] The memory cell MC includes a transistor M4, a transistor M4r, a logic circuit INV1, and a logic circuit INV2.

[0268] As the transistor M4 and the transistor M4r, for example, a transistor that can be used as the transistor M1 can be used.

[0269] The logic circuit INV1 and the logic circuit INV2 have a function of generating and outputting an inverted signal for a signal input to the circuit. As the logic circuit INV1 and the logic circuit INV2, for example, an inverter circuit can be used. In addition to the inverter circuit, for example, a NAND circuit, a NOR circuit, an XOR circuit, or a logic circuit combining the above circuits can also be used.

[0270] The first terminal of the transistor M4 is electrically connected to the wiring BL, the second terminal of the transistor M4 is electrically connected to the input terminal of the logic circuit INV1 and the output terminal of the logic circuit INV2, and the gate of the transistor M4 is electrically connected to the wiring WL. The first terminal of the transistor M4r is electrically connected to the wiring BLB, the second terminal of the transistor M4r is electrically connected to the output terminal of the logic circuit INV1 and the input terminal of the logic circuit INV2, and the gate of the transistor M4r is electrically connected to the wiring WL.

[0271] The high power input terminals of the logic circuit INV1 and the logic circuit INV2 are electrically connected to the wiring C1L, and the low power input terminals of the logic circuit INV1 and the logic circuit INV2 are electrically connected to the wiring C2L. The wiring C1L is used as a wiring for supplying a high level potential, and the wiring C2L is used as a wiring for supplying a low level potential. The wiring C1L and the wiring C2L may be wirings that supply a variable potential instead of a constant potential.

[0272] A high-level potential is supplied to the wiring WL, turning on the transistor M4 and conducting the wiring BL with the input terminal of the logic circuit INV1 and the output terminal of the logic circuit INV2, thereby writing data. At this time, the transistor M4r is also turned on, and the wiring BLB with the output terminal of the logic circuit INV1 and the input terminal of the logic circuit INV2 is conducted. Therefore, when writing data to the memory cell MC, a data signal for writing can be sent from each of the wiring BL and the wiring BLB. Note that the data signal for writing input to the wiring BL is preferably an inverted signal of the signal input to the wiring BLB. In addition, the wiring BL and the wiring BLB are equivalent to Fig.17 The wiring BL and the wiring WL shown are equivalent to Fig.17 The wiring WL shown.

[0273] in addition, Fig.17 The memory cell MC shown is not limited to Fig. 20A The memory cell MC shown. Fig. 20A In the memory cell MC shown in FIG. 1 , circuit selection and circuit connection changes can be made according to the situation. Fig. 20B As shown, it can also be Fig. 20A A transistor M5, a transistor M5r, a capacitor C3, and a capacitor C3r are provided in the memory cell MC.

[0274] As the transistor M5 and the transistor M5r, for example, transistors that can be used as the transistor M1 can be used.

[0275] The first terminal of the transistor M5 is electrically connected to the second terminal of the transistor M4, the input terminal of the logic circuit INV1, and the output terminal of the logic circuit INV2, the second terminal of the transistor M5 is electrically connected to the first terminal of the capacitor C3, and the gate of the transistor M5 is electrically connected to the wiring W2L. The first terminal of the transistor M5r is electrically connected to the second terminal of the transistor M4, the input terminal of the logic circuit INV1, and the output terminal of the logic circuit INV2, the second terminal of the transistor M5r is electrically connected to the first terminal of the capacitor C3r, and the gate of the transistor M5r is electrically connected to the wiring W2L. Each second terminal of the capacitor C3 and the capacitor C3r is electrically connected to the wiring CL.

[0276] Fig. 20B The wiring W1L in the memory cell MC is equivalent to Fig. 20A The wiring W2L is used as a second word line to switch the on and off states of each of the transistors M5 and M5r. In addition, the wiring W1L and the wiring W2L are equivalent to Fig.17 The wiring WL shown.

[0277] The wiring CL is used as a wiring for supplying a constant potential to each second terminal of the capacitor C3 and the capacitor C3r. The constant potential can be a high level potential, a low level potential, a ground potential, or a negative potential. Note that the wiring CL can also be used as a wiring for supplying a variable potential (e.g., a pulse potential).

[0278] Each of transistor M5 and transistor M5r is turned on by wiring W2L, thereby the second terminal of transistor M4 and the first terminal of capacitor C3 are turned on, and the second terminal of transistor M4r and the first terminal of capacitor C3r are turned on. Thus, the potential of each of the input terminal of logic circuit INV1 and the output terminal of logic circuit INV2 is written to the first terminal of capacitor C3, and the potential of each of the output terminal of logic circuit INV1 and the input terminal of logic circuit INV2 is written to the first terminal of capacitor C3r. Then, transistor M5 and transistor M5r are turned off by wiring W2L, thereby each first terminal of capacitor C3 and capacitor C3r can be made floating, and the potential written to each first terminal of capacitor C3 and capacitor C3r can be maintained. At this time, even if the supply of voltage from wiring C1L and wiring C2L is temporarily stopped to stop driving logic circuit INV1 and logic circuit INV2, transistor M5, transistor M5r, capacitor C3 and capacitor C3r can be used to maintain data.

[0279] <Structural Example 1 of Semiconductor Device DEV> then, Fig.21 An example of a cross-sectional structure of a semiconductor device DEV according to one embodiment of the present invention is shown. Fig.21 The semiconductor device DEV shown includes a circuit layer 90 and a multi-layer cell array layer 60 (equivalent to the memory layer MEML_L in FIG. 1 described in Embodiment 1) above a driver circuit region 50 and a control processing region 80 . The multi-layer cell array layer 60 is located above the circuit layer 90 .

[0280] Fig.21 4 shows a transistor 400 included in the driver circuit region 50. The transistor 400 is provided on a substrate 311 and includes a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 including a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 400 may be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a semiconductor substrate (particularly, a single crystal substrate made of silicon) may be used.

[0281] In addition, a single crystal substrate made of germanium can also be used as the substrate 311. In addition, in addition to the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate including a stainless steel foil, a tungsten substrate, a substrate including a tungsten foil, a flexible substrate, a bonding film, a paper or a substrate film including a fibrous material can also be used. As an example of a glass substrate, barium borosilicate glass, aluminum borosilicate glass or soda lime glass can be cited. As an example of a flexible substrate, a bonding film or a substrate film, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Alternatively, as another example, a synthetic resin such as an acrylic resin can be cited. Alternatively, as another example, polypropylene, polyester, polyvinyl fluoride or polyvinyl chloride can be cited. Alternatively, other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper. When the manufacturing process of the semiconductor device DEV includes heat treatment, a material having high heat resistance is preferably selected as the substrate.

[0282] Here, in Fig.21 In the transistor 400 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, the conductor 316 can use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 400 is also referred to as a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the upper surface of the convex portion may also be provided. In addition, although a portion of the semiconductor substrate is processed to form a convex portion is shown here, an SOI (Silicon On Insulator) substrate may also be processed to form a semiconductor film having a convex shape.

[0283] Notice, Fig.21 The structure of the transistor 400 shown is just an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0284] A wiring layer including an interlayer film, wiring, and plugs may also be provided between each structure. In addition, the wiring layer may be provided in multiple layers according to the design. In addition, in this specification, wiring and plugs may also be one component. That is, a part of the conductor is sometimes used as wiring, and a part of the conductor is sometimes used as a plug.

[0285] For example, an insulator 320, an insulator 301, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 400. In addition, a conductor 328 and the like are embedded in the insulator 320 and the insulator 301. In addition, a conductor 330 and the like are embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0286] As the material of each plug and wiring (conductor 328 and conductor 330), a single layer or a laminate of one or more conductive materials selected from metal materials, alloy materials, metal nitride materials and metal oxide materials can be used. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, for example, tungsten is particularly preferred. In addition, as the material, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0287] In addition, the insulator used as the interlayer film can also be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 301, planarization can also be achieved by planarization treatment using a chemical mechanical polishing (CMP) method or the like.

[0288] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig. 22 In the embodiment, insulator 350, insulator 357, and insulator 352 are sequentially stacked on insulator 326 and conductor 330. Conductor 356 is formed between insulator 350, insulator 357, and insulator 352. Conductor 356 is used as a contact plug or wiring. In addition, the material that can be used for conductor 328 or conductor 330 can also be used for conductor 356.

[0289] The circuit layer 90 includes, for example, a transistor MN. As an example, the transistor MN may be a transistor included in the circuit layer SWCL described in Embodiment 1. For example, the transistor included in the circuit layer SWCL may be a transistor included in a switch included in the circuit layer SWCL.

[0290] As the transistor MN, for example, a transistor that can be used as the transistor M1 can be used.

[0291] In addition, Fig.21In the semiconductor device DEV shown, a conductor 361 and the like are provided on the conductor 356. In addition, a conductor 362 is embedded in the circuit layer 90, and a conductor 540a and a conductor 540b are provided on each of a pair of low resistance regions of the transistor MN in the circuit layer 90. In addition, a conductor 363a and a conductor 363b are provided above the transistor MN. The conductors 361, 362, 363a, and 363b are used as contact plugs or wirings.

[0292] The plurality of cell array layers 60 include a plurality of memory cells MC, respectively. Note that, as an example, Fig.21 The memory cell MC shown is Fig.18B The memory cell MC shown. Fig.21 Each memory cell MC shown includes a transistor M1 and a capacitor C1.

[0293] In addition, a conductor 502 is embedded in the interlayer film between the circuit layer 90 and the cell array layer 60_1. In addition, in each of the plurality of cell array layers 60, a conductor 503 is embedded in the insulator 514, the insulator 516, and the insulator 520 described later. Note that the conductor 503 may also be embedded in a portion of the conductor 502. The conductor 502 and the conductor 503 are used as contact plugs or wiring. In addition, in the plurality of cell array layers 60, a conductor used as a contact plug or wiring electrically connected to the memory cell MC in the cell array layer 60 of the upper layer is embedded. In addition, in each of the plurality of cell array layers 60, a conductor 504 is embedded in the insulator 520, the insulator 522, the conductor 542b, the insulator 554, the insulator 580, and the insulator 574 described later. Note that the insulator 574 may also use an insulating film made of the same material as the insulator 514. The conductor 502 , the conductor 503 , and the conductor 504 are used as contact plugs or wirings.

[0294] As an example, in Fig.21 In the semiconductor device DEV shown, the transistor MN in the circuit layer 90 is electrically connected to the transistor M1 in the memory cell MC of the cell array layer 60_1 through the conductor 540a, the conductor 363b, the conductor 502, and the conductor 503. In particular, the transistor MN is electrically connected to the transistor M1 through the conductor 503 being in contact with the conductor 542a or the conductor 542b described later.

[0295] Note that although Fig.21 In the embodiment, one transistor MN is provided on the electrical path between the transistor 400 included in the driving circuit region 50 and the control processing region 80 and the transistor M1 included in the memory cell MC of the cell array layer 60_1, but a plurality of transistors MN may be provided on the electrical path depending on the situation.

[0296] In addition, although Fig.21 The semiconductor device DEV has a structure in which a plurality of cell array layers 60 are stacked in sequence from below. However, the cell array in the semiconductor device DEV may also be as follows. Fig. 22 The diagram is formed in the stacking direction.

[0297] exist Fig. 22 In the semiconductor device DEV, a conductor 502 is embedded in the interlayer film between the circuit layer 90 and the cell array layer 60_1. In addition, in each of the plurality of cell array layers 60, a conductor 503 is embedded in an insulator 514 and an insulator 516 described later. Note that the conductor 503 may be embedded in a portion of the conductor 502. In addition, in each of the plurality of cell array layers 60, a conductor 504 is embedded in an insulator 520, an insulator 522, a conductor 542b, an insulator 554, an insulator 580, and an insulator 574 described later. Note that the insulator 574 may also be an insulating film made of the same material as the insulator 514. The conductors 502, 503, and 504 are used as contact plugs or wirings.

[0298] As an example, in Fig. 22 In the semiconductor device DEV shown, the transistor MN in the circuit layer 90 is electrically connected to the transistor M1 in each memory cell MC of the plurality of cell array layers 60 via the conductor 540a, the conductor 363b, the conductor 502, the conductor 503, and the conductor 504. In particular, the transistor MN is electrically connected to the transistor M1 via the conductor 504 in contact with the conductor 542b described later.

[0299] <<Structure example of transistor>> Next, explain Fig.21 and Fig. 22 The structure examples of transistor M1 and transistor MN are shown.

[0300] Fig.23A and Fig. 23B The transistor 500 shown is a transistor that can be used for the transistor M1 and the transistor MN in the semiconductor device DEV, in particular, Fig.23A is a schematic cross-sectional view of the transistor 500 in the channel length direction, Fig. 23B is a schematic cross-sectional view of the channel width direction of the transistor 500. Note that Fig.23A and Fig. 23B The structure of transistor 500 is shown disposed on insulator 512 .

[0301] In addition, the transistor MN in the semiconductor device DEV may be, for example, Fig.23A and Fig. 23BThe structure of the transistor 500 is shown in FIG. 1 . In addition, the transistor M1 of the semiconductor device DEV may be, for example, a Fig.23A The following is a modification example of Fig.25 In particular, in order to be electrically connected to the conductor 504, the transistor M1 in the cell array layer 60 is preferably Fig.25 Structure of transistor 500.

[0302] like Fig.23A and Fig. 23B As shown, for example, transistor 500 includes metal oxide 531a, metal oxide 531b, conductor 505, conductor 542a, conductor 542b, insulator 580, conductor 560, insulator 514, insulator 516, insulator 520, insulator 522, insulator 524, insulator 550, insulator 554, insulator 574, insulator 580, and insulator 581. Note that transistor 500 may not include all of the above components. For example, transistor 500 may not include insulator 520.

[0303] The conductor 505 (conductor 505a and conductor 505b) and the insulator 516 are arranged above the substrate (not shown). In particular, the conductor 505 is preferably provided in a manner embedded in the insulator 516. Specifically, the conductor 505a is in contact with the bottom surface and side walls of the opening provided in the insulator 516. In addition, the conductor 505b is provided in a manner embedded in the recess formed in the conductor 505a. Fig.23A and Fig. 23B In the transistor 500 shown in the figure, the height of the top surface of the conductor 505 b is substantially equal to the height of the top surface of the conductor 505 a and the height of the top surface of the insulator 516 .

[0304] In addition, the metal oxide 531 and the conductor 560 are arranged in a region overlapping with the conductor 505. In addition, the metal oxide 531b is arranged on the metal oxide 531a. In addition, the conductor 542a and the conductor 542b are arranged on the metal oxide 531b separately from each other. In addition, the insulator 580 is arranged on the conductor 542a and the conductor 542b. In particular, the insulator 580 has an opening formed in a region between the conductor 542a and the conductor 542b. In addition, the conductor 560 is arranged in the opening. In addition, the insulator 550 is arranged between the metal oxide 531b, the conductor 542a, the conductor 542b, and the insulator 580 and the conductor 560. Here, as Fig.23A and Fig. 23BAs shown, the top surface of the conductor 560 is preferably substantially consistent with the top surfaces of the insulators 550 and 580. Note that the conductors 505a and 505b are sometimes collectively referred to as the conductor 505 below. In addition, the metal oxide 531a and the metal oxide 531b are sometimes collectively referred to as the metal oxide 531. In addition, the conductors 542a and 542b are sometimes collectively referred to as the conductor 542.

[0305] In addition, if Fig.23A As shown, sometimes a region 543a is formed as a low resistance region at the interface between the metal oxide 531b and the conductor 542a and its vicinity. Similarly, sometimes a region 543b is formed as a low resistance region at the interface between the metal oxide 531b and the conductor 542b and its vicinity. In this case, the region 543a is used as one of the source region and the drain region, and the region 543b is used as the other of the source region and the drain region. In addition, the channel formation region is formed in the region sandwiched between the region 543a and the region 543b.

[0306] The oxygen concentration of the region 543a (region 543b) may be reduced by providing the above-mentioned conductor 542a (conductor 542b) in contact with the metal oxide 531. In addition, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the metal oxide 531 may be formed in the region 543a (region 543b). In this case, the carrier concentration of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.

[0307] exist Fig.23A and Fig. 23B In the transistor 500 shown in the figure, the side surfaces of the conductors 542a and 542b located on the side of the conductor 560 have a substantially vertical shape. Fig.23A and Fig. 23B The transistor 500 shown is not limited thereto, and a structure in which the angle formed by the side and bottom surfaces of the conductor 542a and the conductor 542b is greater than 10° and less than 80°, preferably greater than 30° and less than 60° may be adopted. In addition, the opposing side surfaces of the conductor 542a and the conductor 542b may also have a plurality of faces.

[0308] Note that in the transistor 500, two layers of the metal oxide 531a and the metal oxide 531b are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and its vicinity, but the present invention is not limited to this. For example, a single-layer structure of the metal oxide 531b or a stacked structure of three or more layers may be adopted. In addition, the metal oxide 531a and the metal oxide 531b may both have a stacked structure of two or more layers.

[0309] Here, the conductor 560 is used as the first gate electrode of the transistor (sometimes referred to as the gate electrode, the top gate electrode or the front gate electrode), and the conductor 542a and the conductor 542b are used as the source electrode or the drain electrode, respectively. As described above, the conductor 560 is embedded in the opening of the insulator 580 and in the region between the conductor 542a and the conductor 542b. Here, the configuration of the conductor 560, the conductor 542a and the conductor 542b is selected to be self-aligned with respect to the opening of the insulator 580. In other words, in the transistor 500, the first gate electrode can be configured to be self-aligned between the source electrode and the drain electrode. Thus, the conductor 560 can be formed in a manner without providing room for alignment, so that the occupied area of ​​the transistor 500 can be reduced. Thus, the high definition of the display device can be achieved. In addition, a display device with a narrow frame can be realized.

[0310] In addition, the conductor 505 is sometimes used as a second gate electrode (sometimes referred to as a bottom gate electrode or a back gate electrode). In this case, the threshold voltage V of the transistor 500 can be controlled by independently changing the potential applied to the conductor 505 without linking it with the potential applied to the conductor 560. th In particular, by applying a negative potential to the conductor 505, the V of the transistor 500 can be further increased. th Therefore, when a negative potential is applied to the conductor 505 , the drain current when the potential applied to the conductor 560 is 0 V can be reduced compared to when no negative potential is applied to the conductor 505 .

[0311] The conductor 505 is preferably larger than the channel formation region in the metal oxide 531. In particular, Fig. 23B As shown, it is preferred that the conductor 505 extends as a wiring to the region outside the end portion intersecting the metal oxide 531 in the channel width direction. That is, it is preferred that the conductor 505 and the conductor 560 overlap with the insulator on the outside of the side surface of the metal oxide 531 in the channel width direction.

[0312] like Fig.23A As shown in FIG. 5 , the conductor 560 preferably includes a conductor 560a disposed inside the insulator 550 and a conductor 560b embedded inside the conductor 560a. Fig.23A and Fig. 23B The conductor 560 is shown as a two-layer stacked structure, but the present invention is not limited thereto. For example, the conductor 560 may also have a single-layer structure or a stacked structure of three or more layers.

[0313] like Fig.23A and Fig. 23BAs shown, the transistor 500 preferably includes an insulator 512 disposed on a substrate (not shown), an insulator 514 disposed on the insulator 512, an insulator 516 disposed on the insulator 514, a conductor 505 disposed in a manner embedded in the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 505, an insulator 522 disposed on the insulator 520, and an insulator 524 disposed on the insulator 522. A metal oxide 531a is preferably disposed on the insulator 524.

[0314] In addition, if Fig.23A and Fig. 23B As shown in FIG. 5 , it is preferable to arrange an insulator 554 between the insulator 522, the insulator 524, the metal oxide 531a, the metal oxide 531b, the conductor 542a, the conductor 542b, and the insulator 580. Fig.23A and Fig. 23B As shown, insulator 554 is preferably in contact with the side surface of insulator 550, the top surface and side surface of conductor 542a, the top surface and side surface of conductor 542b, metal oxide 531a, metal oxide 531b, the side surface and top surface of insulator 524, and the top surface of insulator 522.

[0315] An insulator 574 and an insulator 581 serving as an interlayer film are preferably disposed over the transistor 500. Here, the insulator 574 is preferably in contact with the top surfaces of the conductor 560, the insulator 550, and the insulator 580. In this case, the top surface of the insulator 580 is preferably planarized.

[0316] In addition, it is preferable to provide a conductor 540 (conductor 540a and conductor 540b) which is electrically connected to the transistor 500 and serves as a plug. Therefore, the conductor 540 is provided in a manner in contact with the inner wall of the opening of the insulator 554, the insulator 580, the insulator 574, and the insulator 581. In particular, the following structure may be adopted: a first conductor of the conductor 540 is provided in a manner in contact with the inner wall, and a second conductor of the conductor 540 is provided on the side of the first conductor. Here, the height of the top surface of the conductor 540 and the height of the top surface of the insulator 581 may be substantially the same.

[0317] Specifically, for example, the first conductor of the conductor 540a is provided in contact with the inner wall of one of the two openings of the insulator 581, the insulator 574, the insulator 580, and the insulator 554, and the second conductor of the conductor 540a is formed in contact with the side thereof. The conductor 542a is located at least a portion of the bottom of the opening, and the conductor 540a is in contact with the conductor 542a. Similarly, the first conductor of the conductor 540b is provided in contact with the inner wall of the other of the two openings of the insulator 581, the insulator 574, the insulator 580, and the insulator 554, and the second conductor of the conductor 540b is formed in contact with the side thereof. The conductor 542b is located at least a portion of the bottom of the opening, and the conductor 540b is in contact with the conductor 542b.

[0318] In addition, in the transistor 500, the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, but the present invention is not limited to this. For example, the conductor 540 may also have a single-layer structure or a stacked structure of three or more layers. In the case where the structure has a stacked structure, sometimes an ordinal number is given in the order of formation to distinguish.

[0319] like Fig. 23B As shown, in the region of the metal oxide 531b that does not overlap with the conductor 542, that is, the channel formation region of the metal oxide 531, the side surface of the metal oxide 531 is covered by the conductor 560. Thus, the electric field of the conductor 560 serving as the first gate electrode easily acts on the side surface of the metal oxide 531, and as a result, the channel formation region of the metal oxide 531 can be electrically surrounded by the electric field of the conductor 560. Thus, the on-state current and frequency characteristics of the transistor 500 can be improved.

[0320] Note that the structure of the transistor of the semiconductor device according to one embodiment of the present invention is not limited to Fig.23A The transistor 500 is shown. For example, in Fig.23A In the embodiment, the transistor included in the semiconductor device DEV may have a structure in which the conductor 542a and the conductor 542b are formed on the side surface of the metal oxide 531a, the side surface of the insulator 524, and the top surface of the insulator 522 in addition to the metal oxide 531b (see Fig.25 ).

[0321] <<Materials Constituting Transistors>> Hereinafter, constituent materials that can be used for the transistor 500 will be described.

[0322] [Metal Oxide (Oxide Semiconductor)] A metal oxide used as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 531 (metal oxide 531a and metal oxide 531b) including a channel formation region in the transistor 500. For example, as the metal oxide to be the channel formation region of the metal oxide 531, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more is preferably used.

[0323] As the above-mentioned metal oxide, it is preferred to contain at least indium or zinc. In particular, it is preferred to contain indium and zinc. In addition, it is preferred to further contain element M. As element M, one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt and antimony can be used. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium and tin. In addition, element M more preferably contains one or both of gallium and tin.

[0324] As described above, the metal oxide 531 includes the metal oxide 531a and the metal oxide 531b on the metal oxide 531a. When the metal oxide 531a is provided under the metal oxide 531b, diffusion of impurities from a structure formed under the metal oxide 531a to the metal oxide 531b can be suppressed.

[0325] In addition, the metal oxide 531 preferably has a stacked structure of multiple oxide layers in which the atomic number ratios of each metal atom are different from each other. For example, when the metal oxide 531 contains at least indium (In) and element M, the atomic number ratio of element M among all constituent elements of the metal oxide 531a is preferably greater than the atomic number ratio of element M among all constituent elements of the metal oxide 531b. In addition, the atomic number ratio of element M in the metal oxide 531a relative to In is preferably greater than the atomic number ratio of element M in the metal oxide 531b relative to In.

[0326] It is preferable that the energy of the conduction band bottom of the metal oxide 531a be higher than the energy of the conduction band bottom of the metal oxide 531b. In other words, the electron affinity of the metal oxide 531a is preferably lower than the electron affinity of the metal oxide 531b.

[0327] Here, in the junction of the metal oxide 531a and the metal oxide 531b, the energy level of the conduction band bottom changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom of the junction of the metal oxide 531a and the metal oxide 531b continuously changes or continuously joins. For this reason, it is preferred to reduce the defect state density of the mixed layer formed at the interface of the metal oxide 531a and the metal oxide 531b.

[0328] Specifically, by making the metal oxide 531a and the metal oxide 531b contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the metal oxide 531b is In-Ga-Zn oxide (indium-gallium-zinc oxide), In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide can be used as the metal oxide 531a.

[0329] Specifically, the metal oxide 531a may have an atomic ratio of In:Ga:Zn=1:3:4, 1:3:2, or 1:1:0.5, and the metal oxide 531b may have an atomic ratio of In:Ga:Zn=1:1:1, 4:2:3, or 3:1:2.

[0330] At this time, the main path of the carrier is the metal oxide 531b. By adopting the above structure of the metal oxide 531a, the defect state density at the interface between the metal oxide 531a and the metal oxide 531b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, so that the transistor 500 can obtain a large on-state current and high frequency characteristics.

[0331] In addition, by forming the above-mentioned conductor 542 in contact with the metal oxide 531, the oxygen concentration near the conductor 542 in the metal oxide 531 may be reduced. In addition, a metal compound layer containing a metal contained in the conductor 542 and a component of the metal oxide 531 may be formed near the conductor 542 in the metal oxide 531. In this case, the carrier concentration in the region near the conductor 542 of the metal oxide 531 increases, and the region becomes a low resistance region.

[0332] In addition, the thickness of the region of the metal oxide 531b that does not overlap with the conductor 542 is sometimes thinner than the thickness of the region that overlaps with the conductor 542. This occurs because a portion of the top surface of the metal oxide 531b is removed when the conductor 542a and the conductor 542b are formed. When a conductive film that will become the conductor 542 is deposited on the top surface of the metal oxide 531b, a low resistance region is sometimes formed near the interface with the conductive film. In this way, by removing the low resistance region between the conductor 542a and the conductor 542b on the top surface of the metal oxide 531b, the formation of a channel in this region can be suppressed.

[0333] [Conductor] As the conductor, for example, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, or an alloy containing two or more of the above metal elements. As the conductor, for example, it is preferred to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that absorb oxygen and maintain conductivity, so they are preferred. Alternatively, as the conductor, for example, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element (such as phosphorus), or a silicide (such as nickel silicide) may be used.

[0334] In addition, a plurality of conductors formed of the above materials may be stacked. For example, a laminated structure may be formed by combining a material containing the above metal element and a conductive material containing oxygen. In addition, a laminated structure may be formed by combining a material containing the above metal element and a conductive material containing nitrogen. In addition, a laminated structure may be formed by combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0335] As the conductor 505a used as the second gate electrode, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N2O, NO, or NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules).

[0336] By using a conductive material having a function of inhibiting the diffusion of hydrogen as the conductor 505a, it is possible to inhibit impurities such as hydrogen contained in the conductor 505b from diffusing to the metal oxide 531 through the insulator 524. In addition, by using a conductive material having a function of inhibiting the diffusion of oxygen as the conductor 505a, it is possible to inhibit the conductor 505b from being oxidized and the conductivity from decreasing. As the conductive material having a function of inhibiting the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium or ruthenium oxide can be cited. Thus, the conductor 505a can be a single layer or a stack of the above conductive materials. For example, titanium nitride can be used as the conductor 505a.

[0337] As the conductor 505b, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used. For example, tungsten can be used for the conductor 505b.

[0338] As the conductor 542 (conductor 542a and conductor 542b) used as the source electrode or the drain electrode, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, or an alloy containing two or more of the above metal elements. As the conductor 542, for example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are preferably used. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred.

[0339] As the conductor 560a used as the first gate electrode, it is preferable to use the above-mentioned conductor having the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N2O, NO or NO2) and copper atoms. Alternatively, it is preferable to use a conductive material having the function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules).

[0340] By making the conductor 560a have the function of inhibiting the diffusion of oxygen, it is possible to inhibit the conductivity from decreasing due to oxidation of the conductor 560b caused by oxygen contained in the insulator 550. As the conductive material having the function of inhibiting the diffusion of oxygen, for example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide can be cited. By providing a conductive material containing oxygen as the conductor 560a, oxygen separated from the conductive material can be easily supplied to the channel formation region.

[0341] As the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper or aluminum. In addition, since the conductor 560 is also used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper or aluminum can be used. The conductor 560b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials can be used.

[0342] Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon can be used as the conductor 560. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from an external insulator or the like can sometimes be captured.

[0343] Note that Fig.23A and Fig. 23BIn the figure, the conductor 560 has a two-layer structure, but may also have a single-layer structure or a stacked-layer structure of three or more layers.

[0344] The conductors 540a and 540b used as the plugs are preferably made of a conductive material containing tungsten, copper or aluminum as a main component. The conductors 540a and 540b may have a laminated structure.

[0345] When a laminated structure is used as the conductor 540, it is preferable to use the above-mentioned conductor having the function of suppressing the diffusion of impurities such as water and hydrogen as the conductor in contact with the conductor 542, the insulator 554, the insulator 580, the insulator 574 and the insulator 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium or ruthenium oxide is preferably used. In addition, a conductive material having the function of suppressing the diffusion of impurities such as water and hydrogen can also be used in a single layer or a laminated layer. By using this conductive material, it is possible to prevent oxygen added to the insulator 580 from being absorbed by the conductor 540a and the conductor 540b. In addition, it is possible to prevent impurities such as water and hydrogen from being mixed into the metal oxide 531 through the conductor 540a and the conductor 540b from the layer above the insulator 581.

[0346] Similarly, each of the conductors 361, 362, 363a, 363b, 502, 503, and 504 used as contact plugs or wirings can use a material that can be used for the conductor 540a or 540b.

[0347] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0348] The insulator 514 is preferably used as a blocking insulating film that suppresses impurities such as water and hydrogen from being mixed into the transistor 500 from the substrate side. Therefore, the insulator 514 is preferably an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N2O, NO, or NO2), or copper atoms (not allowing the above impurities to pass through). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules) (not allowing the above oxygen to pass through).

[0349] As an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen and oxygen, for example, a single layer or a stack of insulators containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium and tantalum can be used. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide can be cited. In addition, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen and oxygen, for example, an oxide containing aluminum and hafnium (hafnium aluminate) can be cited. In addition, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen and oxygen, for example, metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride and silicon nitride can be cited.

[0350] It is particularly preferable to use aluminum oxide or silicon nitride as the insulator 514. This can suppress impurities such as water and hydrogen from diffusing from the side closer to the substrate than the insulator 514 to the side of the transistor 500. Alternatively, for example, diffusion of oxygen contained in the insulator 524 or the like to the side closer to the substrate than the insulator 514 can be suppressed.

[0351] Insulator 520 , insulator 522 , and insulator 524 are used as a second gate insulator.

[0352] Here, in the second gate insulator in contact with the metal oxide 531, oxygen is preferably removed by heating. In this specification, etc., oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately provided in the insulator 524 used as the second gate insulator. By providing an insulator containing oxygen in contact with the metal oxide 531, oxygen vacancies in the metal oxide 531 can be reduced, thereby improving the reliability of the transistor 500.

[0353] Specifically, an oxide material from which a part of oxygen is released by heating is preferably used as the insulator 524. The oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in thermal desorption spectroscopy (TDS) is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3Furthermore, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0354] Similar to the insulator 514 and the like, the insulator 522 is preferably used as a block insulating film for suppressing impurities such as water and hydrogen from entering the transistor 500 from the substrate side. For example, the insulator 522 preferably has lower hydrogen permeability than the insulator 524.

[0355] Furthermore, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules) (making it difficult for the oxygen to pass through). For example, the oxygen permeability of the insulator 522 is preferably lower than that of the insulator 524. By making the insulator 522 have a function of suppressing the diffusion of oxygen, it is preferable because the diffusion of oxygen contained in the metal oxide 531 to the substrate side can be reduced. In addition, the conductor 505 can be suppressed from reacting with oxygen contained in the insulator 524 and the metal oxide 531.

[0356] The insulator 522 preferably uses an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material. Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 is used as a layer that suppresses the release of oxygen from the metal oxide 531 and the mixing of impurities such as hydrogen into the metal oxide 531 from the surrounding portion of the transistor 500.

[0357] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide or zirconium oxide may be added to the above-mentioned insulator. In addition, these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be stacked on the above-mentioned insulator for use.

[0358] As the insulator 522, for example, an insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) can be used in a single layer or a stacked layer. Alternatively, the insulator 522 can also use an insulator with a high relative dielectric constant such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium. As the miniaturization or high integration of transistors progresses, problems such as leakage current caused by the thin filmization of the gate insulator sometimes occur. By using a high-k material as an insulator used as a gate insulator, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0359] The insulator 520 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure with thermal stability and a high relative dielectric constant can be formed. In addition, the insulator 520 can also use a material that can be applied to the insulator 524.

[0360] In addition, the insulator 520, the insulator 522, and the insulator 524 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to being formed of the same material, and may be a stacked structure formed of different materials.

[0361] The dielectric constants of the insulators 512, 516, 580, and 581 used as interlayer films are preferably lower than that of the insulator 514. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. In addition, the concentration of impurities such as water and hydrogen in the films of the insulators 516, 580, and 581 is preferably reduced.

[0362] As the insulator 512, the insulator 516, the insulator 580, and the insulator 581, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used. In addition, as the insulator 512, the insulator 516, the insulator 580, and the insulator 581, for example, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferred because they easily form regions containing oxygen that is released by heating. In addition, as the insulator 512, the insulator 516, the insulator 580, and the insulator 581, a resin can be used. In addition, as materials that can be used for the insulator 512, the insulator 516, the insulator 580, and the insulator 581, the above materials can also be appropriately combined.

[0363] As with the insulator 514 and the insulator 522, the insulator 554 and the insulator 574 preferably have a function of suppressing the diffusion of impurities such as water and hydrogen (for example, one or both of hydrogen atoms and hydrogen molecules). In other words, the insulator 554 and the insulator 574 are preferably used as a blocking insulating film that suppresses the impurities from being mixed into the transistor 500. Alternatively, the insulator 554 and the insulator 574 preferably have a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules). For example, the oxygen permeability of the insulator 554 and the insulator 574 is preferably lower than that of the insulator 524, the insulator 550, and the insulator 580. In other words, the insulator 554 and the insulator 574 preferably have a function of suppressing oxygen from detaching from the metal oxide 531 and diffusing to the outside of the insulator 554 or above the insulator 580. Therefore, as the insulator 554 and the insulator 574, a material that can be used for the insulator 514 or the insulator 524 can be used.

[0364] In this manner, by surrounding the insulator 524, the metal oxide 531, and the insulator 550 with the insulator 522, the insulator 554, and the insulator 574, impurities such as water and hydrogen can be suppressed from entering the transistor 500 from the outside. In addition, diffusion of oxygen from the inside of the transistor 500 to the outside can be suppressed.

[0365] The insulator 550 is used as a first gate insulator. The insulator 550 is preferably arranged in contact with the top surface of the metal oxide 531b. The insulator 550 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes. In particular, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred.

[0366] The concentration of impurities such as water and hydrogen in the insulator 550 is preferably reduced, similarly to the insulator 524. The thickness of the insulator 550 is preferably not less than 1 nm and not more than 20 nm.

[0367] In addition, an insulator may be provided between the insulator 580, the insulator 554, the conductor 542, and the metal oxide 531b and the insulator 550. As the insulator, aluminum oxide or hafnium oxide is preferably used, for example. By providing the insulator, oxygen can be prevented from being separated from the metal oxide 531b. 、 Oxygen is excessively supplied to the metal oxide 531 b and the conductor 542 is oxidized.

[0368] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses diffusion of oxygen from the insulator 550 to the conductor 560. Thus, oxidation of the conductor 560 due to oxygen in the insulator 550 can be suppressed.

[0369] In addition, the metal oxide is sometimes used as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 550, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant as the metal oxide. By making the gate insulator have a stacked structure of the insulator 550 and the metal oxide, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0370] Specifically, as the metal oxide, one or more metal oxides selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, as the metal oxide, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium oxides, is preferably used.

[0371] In addition, a blocking insulating film for impurities such as water, hydrogen, and oxygen may be provided between the conductor 540 and the insulator 580, the insulator 574, and the insulator 581. This can prevent water and impurities such as water from entering the metal oxide 531 through the conductors 540a and 540b from the insulator 580. In addition, it can prevent oxygen in the insulator 580 from being absorbed by the conductors 540a and 540b.

[0372] Although not shown, the conductor used as wiring may be arranged in contact with the top surface of the conductor 540a and the top surface of the conductor 540b. The conductor used as wiring preferably uses a conductive material with tungsten, copper or aluminum as a main component. In addition, the conductor may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material. The conductor may also be formed in a manner embedded in an opening in an insulator.

[0373] <<Capacitor Structure Example>> Next, explain Fig.21 and Fig. 22 An example of the structure of capacitor C1 is shown.

[0374] Fig.25 1 shows a structural example of a capacitor 600 as capacitor C1. Note that Fig.25 A structural example of a transistor 500 is shown in addition to the capacitor 600 .

[0375] exist Fig.25In the example, the opening of the insulator 580 is provided on a region on the insulator 554 that overlaps with the conductor 542a that functions as a source electrode or a drain electrode of the transistor 500. This region may overlap with a portion of each of the insulator 524 and the metal oxide 531.

[0376] An insulator 552 is formed on the insulator 580 on the side surface of the opening and on the insulator 554 on the bottom surface of the opening. In addition, a conductor 561a and a conductor 561b are sequentially formed on the insulator 552. Note that in this specification and the like, the conductor 561a and the conductor 561b may be collectively referred to as the conductor 561.

[0377] The conductor 542a is used as one of a pair of electrodes of the capacitor 600. In addition, the conductor 561 is used as the other of a pair of electrodes of the capacitor 600. In addition, the insulator 552 is used as a dielectric of the capacitor 600.

[0378] The conductor 561 preferably extends in the channel width direction as a wiring. That is, the conductor 561 may have a region that does not overlap with the conductor 542a but overlaps with the insulator 554 and the insulator 522 in the channel width direction.

[0379] For example, the material that can be used for the conductor 560a can be used as the conductor 561a. Also, for example, the material that can be used for the conductor 560b can be used as the conductor 561b.

[0380] A material having a high relative dielectric constant is preferably used as the insulator 552. For example, an insulator including a high-k material that can be used for the insulator 522 may be used as the insulator 552 in a single layer or in a stacked layer. The insulator 552 may also include thermally stable silicon oxide or silicon oxynitride.

[0381] <<Modification Example of Transistor 500>> Note that the structure of the transistor of the semiconductor device according to one embodiment of the present invention is not limited to Fig.23A and Fig. 23B For example, as a transistor of a semiconductor device according to one embodiment of the present invention, a transistor 500 may be used. Fig.24 Transistor 500 is shown. Fig.24 The transistor 500 shown is Fig.23A and Fig. 23B The transistor 500 shown in FIG. Fig.23A and Fig. 23B The transistor 500 shown is different in that an insulator 551 is included, and the conductor 542a (conductor 542a1 and conductor 542a2) and the conductor 542b (conductor 542b1 and conductor 542b2) both have a stacked-layer structure.

[0382] The conductor 542a has a laminated structure of a conductor 542a1 and a conductor 542a2 on the conductor 542a1, and the conductor 542b has a laminated structure of a conductor 542b1 and a conductor 542b2 on the conductor 542b1. The conductors 542a1 and 542b1 in contact with the metal oxide 531b are preferably conductors that are not easily oxidized, such as metal nitrides. Thus, it is possible to prevent the conductors 542a and 542b from being excessively oxidized due to oxygen in the metal oxide 531b. In addition, the conductors 542a2 and 542b2 are preferably conductors whose conductivity is higher than that of the metal layer of the conductors 542a1 and 542b1. Thus, the conductors 542a and 542b can be used as wiring or electrodes with high conductivity. In this manner, a semiconductor device can be provided in which the conductors 542a and 542b serving as wiring or electrodes are provided in contact with the top surface of the metal oxide 531 serving as an active layer.

[0383] As the conductor 542a1 and the conductor 542b1, metal nitrides are preferably used, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if oxygen is absorbed, so they are preferred.

[0384] In addition, the electrical conductivity of the conductor 542a2 and the conductor 542b2 is preferably higher than that of the conductor 542a1 and the conductor 542b1. For example, the thickness of the conductor 542a2 and the conductor 542b2 is preferably greater than that of the conductor 542a1 and the conductor 542b1. As the conductor 542a2 and the conductor 542b2, the conductor that can be used for the conductor 560b described above can be used. By adopting the above structure, the resistance of the conductor 542a2 and the conductor 542b2 can be reduced.

[0385] Therefore, tantalum nitride or titanium nitride can be used as the conductor 542a1 and the conductor 542b1, and tungsten can be used as the conductor 542a2 and the conductor 542b2.

[0386] like Fig.24As shown, when the channel length direction of the transistor 500 is viewed from the cross section, the distance between the conductor 542a1 and the conductor 542b1 is preferably smaller than the distance between the conductor 542a2 and the conductor 542b2. By adopting the above structure, the distance between the source and the drain can be further reduced and the channel length can be correspondingly reduced. Therefore, the frequency characteristics of the transistor 500 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0387] The insulator 551 is preferably an insulator that is not easily oxidized, such as a nitride. The insulator 551 is in contact with the side surface of the conductor 542a2 and the side surface of the conductor 542b2 and has the function of protecting the conductor 542a2 and the conductor 542b2. Since the insulator 551 is exposed to an oxidizing atmosphere, it is preferable to use an inorganic insulator that is not easily oxidized. In addition, since the insulator 551 is in contact with the conductor 542a2 and the conductor 542b2, it is preferable to use an inorganic insulator that is not easily oxidized by the conductor 542a2 and the conductor 542b2. Therefore, as the insulator 551, it is preferable to use an insulating material having oxygen barrier properties. For example, silicon nitride can be used as the insulator 551.

[0388] Fig.24 In the transistor 500 shown, in order to form the conductor 542a2 and the conductor 542b2, an opening is formed in the insulator 554, the insulator 580, the insulator 574, and the insulator 581 using a first mask. In addition, the insulator 551 is formed in a manner in contact with the side wall of the opening. Then, the conductor 542a1 and the conductor 542b1 are also formed using a second mask to form the transistor 500. Here, the above-mentioned opening overlaps with the area between the conductor 542a2 and the conductor 542b2. In addition, a portion of the conductor 542a1 and the conductor 542b1 is formed in a manner protruding into the above-mentioned opening. Therefore, the insulator 551 is in contact with the top surface of the conductor 542a1, the top surface of the conductor 542b1, the side surface of the conductor 542a2, and the side surface of the conductor 542b2 in the above-mentioned opening. In addition, the insulator 550 is in contact with the top surface of the metal oxide 531 in the region between the conductor 542 a 1 and the conductor 542 b 1 .

[0389] Preferably, heat treatment is performed in an oxygen-containing atmosphere after forming the conductor 542a1 and the conductor 542b1 and before depositing the insulator 550. Thus, oxygen is supplied to the metal oxide 531a and the metal oxide 531b, thereby reducing oxygen vacancies. In addition, by forming the insulator 551 in contact with the side of the conductor 542a2 and the side of the conductor 542b2, the conductor 542a2 and the conductor 542b2 can be prevented from being excessively oxidized. Thus, the electrical characteristics and reliability of the transistor can be improved. In addition, the electrical characteristics of multiple transistors formed on the same substrate can be suppressed from being uneven.

[0390] In addition, if Fig.24 As shown, in the transistor 500 , the insulator 524 may be formed in an island shape. Here, the side end of the insulator 524 may be formed so as to be substantially aligned with the side end of the metal oxide 531 .

[0391] In addition, if Fig.24 As shown in FIG. 5 , in the transistor 500, the insulator 522 may be in contact with the insulator 516 and the conductor 505. In other words, it is also possible not to set Fig.23A and Fig. 23B Insulator 520 is shown.

[0392] <Structural Example 2 of Semiconductor Device DEV> then, Fig.26 Shown with Fig.21 and Fig. 22 A different example of a cross-sectional structure of a semiconductor device DEV according to one embodiment of the present invention. Fig.26 The semiconductor device DEV shown is Fig. 22 In a modified example of the semiconductor device DEV, in the memory cells MC in the plurality of cell array layers 60, the capacitor C1 is provided below the transistor M1, which is similar to Fig. 22 The semiconductor device DEV is different.

[0393] Note that in order to avoid duplication of description, the description of the substrate 311, the driver circuit region 50, the control processing region 80, and the circuit layer 90 is omitted in this structural example.

[0394] exist Fig.26 In the embodiment, the plurality of unit array layers 60 respectively include Fig. 22 The memory cell MC shown is different from a plurality of memory cells MC. Note that, as an example, Fig.26 The memory cell MC shown is Fig.18A The memory cell MC shown. Fig.26 Each memory cell MC shown includes a transistor M1 and a capacitor C1.

[0395] In addition, a conductor 364 is embedded in the interlayer film between the circuit layer 90 and the cell array layer 60_1. In addition, in each of the plurality of cell array layers 60, a conductor 365 is embedded in an insulator 592 described later. In addition, in each of the plurality of cell array layers 60, a conductor 366 is embedded in an insulator 593, an insulator 594, an insulator 553, and an insulator 595 described later. In addition, in each of the plurality of cell array layers 60, a conductor 367 is embedded in an insulator 596, an insulator 583, a conductor 545, an insulator 555, and an insulator 597 described later. The conductors 364, 365, 366, and 367 are used as contact plugs or wirings.

[0396] For the conductors 364 , 365 , 366 , and 367 , for example, the materials that can be used for the conductor 502 , 503 , or 504 can be used.

[0397] As an example, in Fig.26 In the semiconductor device DEV shown, the transistor MN in the circuit layer 90 is electrically connected to the transistor M1 in each memory cell MC of the plurality of cell array layers 60 via the conductor 540a, the conductor 363b, the conductor 364, the conductor 365, the conductor 366, and the conductor 367. In particular, the transistor MN is electrically connected to the transistor M1 via the conductor 504 in contact with the conductor 542b described later.

[0398] Note that although Fig.26 In the embodiment, one transistor MN is provided on the electrical path between the transistor 400 included in the driving circuit region 50 and the control processing region 80 and the transistor M1 included in the memory cell MC of the cell array layer 60_1, but a plurality of transistors MN may be provided on the electrical path depending on the situation.

[0399] <<Structural Example of Memory Cell MC>> Next, the description includes Fig.26 FIG. 1 is a structural example of memory cells MC in a plurality of cell array layers 60 of a semiconductor device DEV.

[0400] Fig.27A 1 is a plan view showing a structural example of a memory cell MC and its surroundings included in each of the plurality of cell array layers 60 of the semiconductor device DEV. FIG. 27A to FIG. 27D In the example, transistor 500A is equivalent to Fig.26 The transistor M1 and capacitor 600A are equivalent to Fig.26 The capacitor in is 600A. Fig.27D It is along Fig.27A The cross-sectional view is shown along the dotted line A1-A2. Fig.27AIn the above diagram, for example, a part of the components of the transistor M1 such as an insulator is omitted. In addition, a part of the components such as an insulator is also omitted in the plan view of the transistor in the following.

[0401] As an example, the capacitor 600A includes an insulator 592 , an insulator 593 , an insulator 594 , an insulator 553 , an insulator 595 , a conductor 563 , a conductor 564 , and a conductor 544 .

[0402] The conductor 563 is embedded in the insulator 592. The conductor 563 can be used as, for example, a wiring CL extending in the Y direction.

[0403] The insulator 592 can use, for example, the materials described above for the insulator 512, the insulator 516, the insulator 580, or the insulator 581. In particular, the insulator 592 is preferably made of a material having a low relative dielectric constant, and for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride is more preferably used.

[0404] In addition, the conductor 563 can use, for example, the material that can be used for the conductor 505 or the conductor 365 .

[0405] As an example, an insulator 593 and an insulator 594 are sequentially formed on the insulator 592 and the conductor 563. In addition, an opening is provided in the region where the insulator 593 and the insulator 594 overlap with the conductor 563. The conductor 564 is formed on the bottom surface (on the conductor 563) and the side surface of the opening. Note that in FIG. 27 , the conductor 564 is also formed on the top surface of the insulator 594. In addition, an insulator 553 is formed on the insulator 594 and the conductor 564. In addition, a conductor 544 is formed in a manner covering the region where the insulator 553 overlaps with the conductor 564. In addition, an insulator 595 is formed on the conductor 544 and the insulator 553. Note that the top surface height of the insulator 595 is preferably substantially consistent with the top surface height of the conductor 544. Therefore, for example, it is preferable to flatten the insulator 595 and the conductor 544 by a flattening treatment using a chemical mechanical polishing (CMP) method or the like.

[0406] The conductor 564 corresponds to, for example, one of a pair of terminals of the capacitor 600A. In addition, the conductor 544 corresponds to, for example, the other of a pair of terminals of the capacitor 600A.

[0407] The conductor 564 and the conductor 544 are preferably used, for example, FIG. 23A to FIG. 25 The transistor 500 shown or Fig.25The conductor of the capacitor 600 shown in FIG. 5 is preferably made of tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. The above-mentioned materials are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, and therefore are preferred.

[0408] The insulator 553 is used as a dielectric sandwiched between a pair of terminals in the capacitor 600A, for example. Therefore, the insulator 553 is preferably made of the material that can be used for the insulator 552 described above.

[0409] The insulator 594 and the insulator 595 can use, for example, the materials that can be used for the insulator 512, the insulator 516, the insulator 580, or the insulator 581. In particular, the insulator 594 and the insulator 595 are preferably made of a material having a low relative dielectric constant, and for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride is more preferably used.

[0410] The transistor 500A is provided above the conductor 544 and the insulator 595 of the capacitor 600A.

[0411] The transistor 500A has a structure in which the direction of the channel length is not substantially parallel to the substrate 311 but is along the side surface of an opening provided in an insulator 583 to be described later.

[0412] As an example, the transistor 500A includes a conductor 544 serving as one of a source electrode and a drain electrode, a conductor 545 serving as the other of the source electrode and the drain electrode, a metal oxide 533 , an insulator 555 , and a conductor 565 serving as a gate electrode. Fig.27A The example in which the conductor 545 extends in a direction perpendicular to the conductor 544 and the conductor 565 is shown. As described above, the conductor 544 is also used as the other of the pair of electrodes of the capacitor 600A.

[0413] For example, the conductor 544 and the conductor 545 can use a material that can be used for the conductor 542 in the transistor 500. Also, for example, the conductor 565 can use a material that can be used for the conductor 560 in the transistor 500.

[0414] For example, a material that can be used for the metal oxide 531 in the transistor 500 can be used as the metal oxide 533 .

[0415] exist Fig.27A and Fig.27D, the direction in which the conductor 545 extends is recorded as the X direction. In addition, the direction perpendicular to the X direction and, for example, parallel to the top surface of the conductor 563 is recorded as the Y direction, and the direction perpendicular to the top surface of the conductor 563 is recorded as the Z direction. In the following drawings, the definitions of the X direction, the Y direction, and the Z direction are sometimes the same as those described above and sometimes different. The X direction, the Y direction, and the Z direction may be perpendicular to each other. In addition, in the description of the plan view in this specification, etc., the X direction is sometimes referred to as the right side or the left side and the Y direction is sometimes referred to as the upper side or the lower side. In addition, the right side and the left side may sometimes be referred to as the X direction and the -X direction, respectively, and the upper side and the lower side may sometimes be referred to as the Y direction and the -Y direction, respectively.

[0416] The conductor 544 is used as one of the source electrode and the drain electrode of the transistor 500A. The conductor 545 is used as the other of the source electrode and the drain electrode of the transistor 500A. The insulator 555 is used as a gate insulating layer of the transistor 500A. The conductor 565 is used as a gate electrode of the transistor 500A.

[0417] In the metal oxide 533, the entire region overlapping the gate electrode with the gate insulating layer between the source electrode and the drain electrode is used as a channel formation region. In addition, in the metal oxide 533, the region in contact with the source electrode is used as a source region, and the region in contact with the drain electrode is used as a drain region.

[0418] An insulator 596 is provided on the insulator 595 and the conductor 544. The insulator 596 may function as an interlayer insulating layer. Here, the interlayer insulating layer may be a blocking insulating film that suppresses the diffusion of impurities such as water and hydrogen (for example, one or both of hydrogen atoms and hydrogen molecules). Therefore, the insulator 596 may use the above-mentioned materials that can be used for the insulator 514 or the insulator 522.

[0419] An insulator 583 (insulator 583a and insulator 583b) is provided on the insulator 596, and a conductor 545 is provided on the insulator 583. The insulator 583 can be used as an interlayer insulating layer. Here, the interlayer insulating layer can be an interlayer film for separating the source electrode and the gate electrode in the transistor 500A. In addition, the insulator 597 can be used as an interlayer film for providing a circuit element or wiring above the transistor 500A.

[0420] For example, as the insulator 583 , a material that can be used for the insulator 514 , the insulator 516 , the insulator 522 , the insulator 524 , the insulator 550 , the insulator 554 , the insulator 574 , the insulator 580 , and the insulator 581 in the transistor 500 can be used.

[0421] Specifically, as the insulator 583a, for example, an oxide or an oxynitride is preferably used. In addition, as the insulator 583a, a film that releases oxygen by heating is preferably used. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulator 583a. When the insulator 583a releases oxygen, oxygen can be supplied from the insulator 583a to the metal oxide 533. By supplying oxygen from the insulator 583a to the metal oxide 533, especially by supplying oxygen from the insulator 583a to the channel formation region of the metal oxide 533, oxygen vacancies in the metal oxide 533 and hydrogen entering the oxygen vacancies can be reduced. Therefore, the transistor 500A can be a transistor with good electrical characteristics and high reliability.

[0422] In addition, specifically, as the insulator 583b, for example, silicon nitride, silicon oxynitride, or aluminum oxide can be appropriately used. The insulator 583b, for example, preferably has a region whose nitrogen content is higher than that of the insulator 583a. The insulator 583b, for example, can use a material whose nitrogen content is higher than that of the insulator 583a. The insulator 583b preferably uses a nitride or a nitride oxide. The insulator 583b, for example, can appropriately use silicon nitride or silicon oxynitride. By using silicon nitride or silicon oxynitride as the insulator 583b, the insulator 583b can be used as a barrier layer for inhibiting oxygen from detaching from the insulator 583a. In addition, by using silicon nitride or silicon oxynitride as the insulator 583b, the insulator 583b can be used as a barrier layer for inhibiting hydrogen from diffusing through the insulator 583 to the metal oxide 533.

[0423] The insulator 596 and the insulator 583 have an opening 601 that reaches the conductor 544. The conductor 545 has an opening 603 that reaches the opening 601. In other words, the opening 603 has a region that overlaps with the opening 601.

[0424] exist Fig.27A In FIG. 5 , a conductor 544, a conductor 545, a metal oxide 533, a conductor 565, an opening 601, and an opening 603 are shown as components of the transistor 500A. Fig. 23B Show omitted Fig.27A The structure example of the conductor 565 in the constituent elements shown. In other words, Fig.27B The conductor 544, the conductor 545, the metal oxide 533, the opening 601, and the opening 603 are shown. Fig.27C Show omitted Fig.27B The structure example of the metal oxide 533 in the constituent elements shown. In other words, Fig.27C Conductor 544 , conductor 545 , opening 601 , and opening 603 are shown.

[0425] like Fig.27C and Fig.27DAs shown, the conductor 545 has an opening 603 in the area overlapping with the conductor 544. Fig.27C As shown in FIG. 1 , the conductor 545 may cover the entire periphery of the opening 601 in a plan view. Here, the conductor 545 is preferably not provided inside the opening 601. In other words, the conductor 545 is preferably not disposed on the side surface of the insulator 583 on the opening 601 side.

[0426] FIG. 27A to FIG. 27C An example is shown in which the shapes of the opening 601 and the opening 603 are both circular when viewed from above. When the planar shapes of the opening 601 and the opening 603 are circular, the processing accuracy when forming the opening 601 and the opening 603 can be improved, and a small opening 601 and the opening 603 can be formed. Note that in this specification, etc., a circle is not limited to a perfect circle. For example, the planar shapes of the opening 601 and the opening 603 can be either elliptical or curved. Alternatively, they can be polygonal.

[0427] Fig.27D An example is shown in which the end of the conductor 545 on the side of the opening 603 is consistent with or substantially consistent with the end of the insulator 583 on the side of the opening 601. It can also be said that the planar shape of the opening 603 is consistent with or substantially consistent with the planar shape of the opening 601. In addition, in this embodiment, the end of the conductor 545 on the side of the opening 603 refers to the bottom surface end of the conductor 545 on the side of the opening 603. The bottom surface of the conductor 545 refers to the surface on the side of the insulator 583. The end of the insulator 583 on the side of the opening 601 refers to the top surface end of the insulator 583 on the side of the opening 601. The top surface of the insulator 583 refers to the surface on the side of the conductor 545. In addition, the planar shape of the opening 603 refers to the planar shape of the bottom surface end of the conductor 545 on the side of the opening 603. The planar shape of the opening 601 refers to the planar shape of the top surface end of the insulator 583 on the side of the opening 601.

[0428] Note that the ends are consistent or roughly consistent, which can also be said to be aligned or roughly aligned. In the case where the ends are aligned or roughly aligned or the plane shapes are consistent or roughly consistent, it can be said that at least a part of their outlines overlap each other between the stacked layers when viewed from above. For example, this includes the case where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. However, in reality, there are cases where the outlines do not overlap, and sometimes the upper layer is located on the inner side of the lower layer or the upper layer is located on the outer side of the lower layer. In this case, it can also be said that the ends are roughly aligned or the plane shapes are roughly consistent.

[0429] The opening 601 can be formed, for example, using a resist mask for forming the opening 603. Specifically, first, the insulator 596 on the conductor 544 and the insulator 595, the insulator 583 on the insulator 596, the conductive film to be the conductor 545 on the insulator 583, and the resist mask on the conductive film are formed. Next, after the opening 603 is formed in the conductive film using the resist mask, the opening 601 is formed in the insulator 596 and the insulator 583 using the resist mask, thereby making the end of the opening 601 coincide with or approximately coincide with the end of the opening 603. By adopting such a structure, the process can be simplified.

[0430] The metal oxide 533 is provided so as to cover the opening 601 and the opening 603 and to have a region located inside the opening 601 and the opening 603. The metal oxide 533 has a shape along the top surface and the side surface of the conductor 545, the side surface of the insulator 583, the side surface of the insulator 596, and the top surface of the conductor 544. For example, the metal oxide 533 has a region in contact with the top surface and the side surface of the conductor 545, the side surface of the insulator 583, and the top surface of the conductor 544.

[0431] The metal oxide 533 preferably covers the end of the conductor 545 on the side of the opening 603. For example, Fig.27D The structure in which the end of the metal oxide 533 is located on the conductor 545 is shown. It can be said that the end of the metal oxide 533 is in contact with the top surface of the conductor 545.

[0432] For example, Fig.27D Although the metal oxide 533 has a single-layer structure, one embodiment of the present invention is not limited thereto and the metal oxide 533 may have a stacked-layer structure of two or more layers.

[0433] The insulator 555 serving as the gate insulating layer of the transistor 500A is provided so as to cover the opening 601 and the opening 603 and to have a region located inside the opening 601 and the opening 603. The insulator 555 is provided on the metal oxide 533, the conductor 545, and the insulator 583. The insulator 555 may have a region in contact with the top surface and side surfaces of the metal oxide 533, the top surface and side surfaces of the conductor 545, the top surface of the insulator 583, and the top surface of the insulator 596. The insulator 555 has a shape along the top surface of the insulator 596, the top surface of the insulator 583, the top surface and side surfaces of the conductor 545, and the top surface and side surfaces of the metal oxide 533.

[0434] The conductor 565 serving as the gate electrode of the transistor 500A is provided on the insulator 555 and may have a region in contact with the top surface of the insulator 555. The conductor 565 has a region overlapping with the metal oxide 533 via the insulator 555. The conductor 565 has a shape along the top surface of the insulator 555.

[0435] For example, Fig.27D As shown in FIG. 5 , in the openings 601 and 603 , the conductor 565 has a region overlapping with the metal oxide 533 via the insulator 555 . Fig.27D In the example shown, the conductor 565 has a region overlapping with the conductor 544 and the conductor 545 via the insulator 555 and the metal oxide 533. In addition, the conductor 565 covers the entire metal oxide 533. With the above structure, a gate electric field can be applied to the entire metal oxide 533, so that the electrical characteristics of the transistor 500A can be improved, for example, the on-state current of the transistor can be increased.

[0436] The transistor 500A is a so-called top-gate transistor having a gate electrode above the metal oxide 533. Since the bottom surface of the metal oxide 533 has a region in contact with the source electrode and the drain electrode, it can be said to be a TGBC (Top Gate Bottom Contact) type transistor.

[0437] The transistor 500A may be used as, for example, one or more transistors selected from the transistors included in the circuit layer 90 , the transistors included in the driver circuit region 50 , and the transistors included in the control processing region 80 in addition to the transistors included in the memory cell MC.

[0438] Here, refer to Fig.28A and Fig.28B The channel length and channel width of the transistor 500A are described. Fig.28A It is shown Fig.27A An enlarged plan view of a structural example of transistor 500A and its vicinity is shown. Fig.28B It is shown Fig.27D An enlarged cross-sectional view of a structural example of a transistor 500A and its vicinity is shown.

[0439] In the metal oxide 533, the region in contact with the conductor 544 is used as one of the source region and the drain region, the region in contact with the conductor 545 is used as the other of the source region and the drain region, and the region between the source region and the drain region is used as a channel formation region.

[0440] The channel length of transistor 500A is the distance between the source region and the drain region. Fig.28BThe dotted double arrow in FIG. 5 represents a channel length L500 of the transistor 500A. The channel length L500 is a distance between an end of a region where the metal oxide 533 and the conductor 544 are in contact with each other and an end of a region where the metal oxide 533 and the conductor 545 are in contact with each other when viewed in cross section.

[0441] Here, the channel length L500 of the transistor 500A is equivalent to the length of the side surface of the opening 601 side of the insulator 583 when viewed from the XZ plane. In other words, the channel length L500 is determined by the thickness T583 of the insulator 583 and the angle θ583 formed by the side surface of the opening 601 side of the insulator 583 and the formed surface of the insulator 583 (here, the top surface of the conductor 544), and is not affected by the performance of the exposure device used when manufacturing the transistor. Therefore, the channel length L500 can be made smaller than the limiting resolution of the exposure device, so that a micro transistor can be realized. For example, the channel length L500 is preferably 0.010 μm or more and less than 3.0 μm, more preferably 0.050 μm or more and less than 3.0 μm, more preferably 0.10 μm or more and less than 3.0 μm, more preferably 0.15 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 3.0 μm, more preferably 0.20 μm or more and less than 2.5 μm, more preferably 0.20 μm or more and less than 2.0 μm, more preferably 0.20 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.5 μm, more preferably 0.30 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.2 μm, more preferably 0.40 μm or more and less than 1.0 μm, more preferably 0.50 μm or more and less than 1.0 μm. Fig.28B In FIG. 5 , the thickness T583 of the insulator 583 is indicated by a double-dash arrow.

[0442] By applying the transistor 500A to a transistor in a memory cell MC of the semiconductor device DEV, the transistor in the memory cell MC can be miniaturized, so the memory cell MC can be miniaturized. Thus, the miniaturization of the semiconductor device DEV can be achieved. In addition, by reducing the channel length L500, the on-state current of the transistor 500A can be increased. Therefore, by applying the transistor 500A to a transistor in the semiconductor device DEV, such as a transistor in the memory cell MC, the semiconductor device DEV can be driven at high speed.

[0443] By adjusting the thickness T583 and the angle θ583 of the insulator 596 and the insulator 583 , the channel length L500 can be controlled.

[0444] The thickness T583 of the insulator 596 and the insulator 583 is preferably greater than 0.010 μm and less than 3.0 μm, more preferably greater than 0.050 μm and less than 3.0 μm, more preferably greater than 0.10 μm and less than 3.0 μm, more preferably greater than 0.15 μm and less than 3.0 μm, more preferably greater than 0.20 μm and less than 3.0 μm, more preferably greater than 0.20 μm and less than 2.5 μm, more preferably greater than 0.20 μm and less than 2.0 μm, more preferably greater than 0.20 μm and less than 1.5 μm, more preferably greater than 0.30 μm and less than 1.5 μm, more preferably greater than 0.30 μm and less than 1.2 μm, more preferably greater than 0.40 μm and less than 1.2 μm, more preferably greater than 0.40 μm and less than 1.0 μm, more preferably greater than 0.50 μm and less than 1.0 μm.

[0445] The side surfaces of the insulator 596 and the opening 601 of the insulator 583 preferably have a tapered shape. The angle θ583 formed by the side surfaces of the insulator 596 and the opening 601 of the insulator 583 and the formed surface of the insulator 596 (here, the top surface of the conductor 544) is preferably less than 90 degrees. By reducing the angle θ583, the coverage of the layer (for example, the metal oxide 533) provided on the insulator 583 can be improved. However, when the angle θ583 is reduced, the contact area between the metal oxide 533 and the conductor 544 is sometimes reduced, and the contact resistance between the metal oxide 533 and the conductor 544 is increased. The angle θ583 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and less than 90 degrees, more preferably 55 degrees or more and less than 90 degrees, more preferably 60 degrees or more and less than 90 degrees, more preferably 60 degrees or more and less than 85 degrees, more preferably 65 degrees or more and less than 85 degrees, more preferably 65 degrees or more and less than 80 degrees, more preferably 70 degrees or more and less than 80 degrees. By setting the angle θ583 within the above range, the coverage of the layer (e.g., metal oxide 533) formed on the conductor 544 and the insulator 583 can be improved, thereby suppressing the generation of defects such as disconnection or voids in the layer. In addition, the contact resistance between the metal oxide 533 and the conductor 544 can be reduced.

[0446] In this specification and the like, disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of a formed surface (for example, a step, etc.).

[0447] Note that, for example, Fig.28B2 shows a structure in which the shape of the side surface of the insulator 596 and the opening 601 side of the insulator 583 is a straight line when viewed from a cross section, but one embodiment of the present invention is not limited to this. When viewed from a cross section, the shape of the side surface of the insulator 596 and the opening 601 side of the insulator 583 may be a curve, or the side surface may have both a straight line region and a curved region.

[0448] The channel width of the transistor 500A is the width of the source region or the width of the drain region in the direction perpendicular to the channel length direction. In other words, the channel width is the width of the region where the metal oxide 533 contacts the conductor 544 or the width of the region where the metal oxide 533 contacts the conductor 545 in the direction perpendicular to the channel length direction. Here, the width of the region where the metal oxide 533 contacts the conductor 545 in the direction perpendicular to the channel length direction is described as the channel width of the transistor 500A. Fig.28A and Fig.28B A solid double-ended arrow indicates a channel width W500 of the transistor 500A. The channel width W500 is the length of the bottom end of the conductor 545 on the opening 603 side in a plan view.

[0449] The channel width W500 is determined by the planar shape of the opening 603. Fig.28A and Fig.28B In FIG. 6 , a double-pointed double arrow indicates a width D500 of the opening 603. The width D500 refers to the short side of the smallest rectangle circumscribing the opening 603 in a plan view. When the opening 603 is formed by photolithography, the width D500 of the opening 603 is greater than the limiting resolution of the exposure device. Furthermore, the width D500 is, for example, preferably greater than or equal to 0.20 μm and less than 5.0 μm, more preferably greater than or equal to 0.20 μm and less than 4.5 μm, more preferably greater than or equal to 0.20 μm and less than 4.0 μm, more preferably greater than or equal to 0.20 μm and less than 3.5 μm, more preferably greater than or equal to 0.20 μm and less than 3.0 μm, more preferably greater than or equal to 0.20 μm and less than 2.5 μm, more preferably greater than or equal to 0.20 μm and less than 2.0 μm, more preferably greater than or equal to 0.20 μm and less than 1.5 μm, more preferably greater than or equal to 0.30 μm and less than 1.5 μm, more preferably greater than or equal to 0.30 μm and less than 1.2 μm, more preferably greater than or equal to 0.40 μm and less than 1.2 μm, more preferably greater than or equal to 0.40 μm and less than 1.0 μm, more preferably greater than or equal to 0.50 μm and less than 1.0 μm. When the planar shape of the opening 603 is circular, the width D500 corresponds to the diameter of the opening 603 , and the channel width W500 may be equal to the length of the outer periphery of the opening 603 in a plan view, and may be calculated as “D500×π”.

[0450] Since the size of transistor 500A is small, by using transistor 500A in cell array layer 60, a semiconductor device with high storage density can be provided. In addition, since transistor 500A operates faster, by using transistor 500A in a semiconductor device, a semiconductor device with high driving speed can be provided. In addition, since the electrical characteristics of transistor 500A are stable, by using transistor 500A in a semiconductor device, a semiconductor device with high reliability can be provided. In addition, since the off-state current of transistor 500A is small, by using transistor 500A in a semiconductor device, a semiconductor device with low power consumption can be provided.

[0451] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0452] (Implementation 3) In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. In the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) is briefly described.

[0453] [OS Transistor] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0454] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0455] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0456] In an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), electrons that become carriers may be generated. In addition, when V O When the voltage is lowered to 0.1 V, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor is often turned on (a state in which a channel exists even when a voltage is not applied to the gate electrode and current flows in the transistor). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H.

[0457] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called off-state leakage current or Ioff) of the transistor can be reduced.

[0458] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0459] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0460] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0461] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0462] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junctionless transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n + Type area.

[0463] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of short channel effects. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is also the width of the bottom surface of the gate electrode when looking down at the transistor.

[0464] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0465] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0466] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0467] (Implementation 4) In this embodiment, electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DC) that can use the semiconductor device described in the above embodiment are described. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device in one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0468] [Electronic components] Fig.29A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Fig.29A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Fig.29A700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0469] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0470] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0471] In addition, it is preferred that multiple memory cell arrays in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. When Si transistors are used in the storage layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0472] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon chip.

[0473] then, Fig.29B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0474] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0475] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0476] The plug board 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit disposed on the plug board 731 to the electrode disposed on the package substrate 732. Therefore, the plug board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon plug board, TSV can also be used as a through electrode.

[0477] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0478] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0479] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0480] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0481] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig.29B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0482] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0483] [Electronic equipment] then, Fig. 30A A perspective view of electronic device 6500 is shown. Fig. 30AThe electronic device 6500 shown is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a frame 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be used for the display unit 6502, the control device 6509, and the like.

[0484] Fig. 30B The electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a frame 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for the display unit 6615, the control device 6616, and the like. In addition, by using a semiconductor device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616, power consumption can be reduced, so it is preferred.

[0485] [Mainframe computer] then, Fig. 30C A perspective view of a mainframe computer 5600 is shown. Fig. 30C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0486] Computer 5620 may have, for example, Fig.30D The structure of the stereogram is shown. Fig.30D In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0487] Fig.30E The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.30ESemiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0488] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0489] Each of the connection terminals 5623, 5624, and 5625 can be used as an interface for supplying power to the personal computer card 5621 or inputting a signal, for example. In addition, for example, they can be used as an interface for outputting a signal calculated by the personal computer card 5621, for example. As the specifications of each of the connection terminals 5623, 5624, and 5625, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. can be cited. In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as each specification.

[0490] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0491] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0492] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0493] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0494] [Space Equipment] The semiconductor device of one embodiment of the present invention can be applied to space equipment such as equipment for processing and storing information.

[0495] A semiconductor device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space.

[0496] exist Fig.31 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.31 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0497] In addition, although Fig.31 Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0498] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0499] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0500] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0501] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, it is preferable to use an OS transistor of one embodiment of the present invention for the control device 6807. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change less. That is, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0502] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0503] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0504] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and having high radiation resistance.

[0505] [Data Center] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to manage data over a long period of time by ensuring data invariance. When managing data over a long period of time, it is necessary to enlarge facilities, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0506] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the scale of cooling equipment. As a result, it is possible to save space in the data center.

[0507] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0508] Fig.32 A storage system that may be used in a data center is shown. Fig.32 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as storage 7003 (shown as storage). The host 7001 and the storage 7003 are shown to be connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0509] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0510] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for DRAM which can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally provided in the storage to shorten the time required for data storage and output.

[0511] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0512] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0513] Note that by using a semiconductor device of one embodiment of the present invention for any one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, it is expected that the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for high performance or high integration of semiconductor devices increases, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a semiconductor device of one embodiment of the present invention. In addition, a semiconductor device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0514] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0515] (Implementation method 5) In this embodiment, a structural example in which the stacked-layer structure described in the above embodiment is applied to a display device and an electronic device using the display device will be described.

[0516] <Configuration Example of Display Device> Fig.33A is a perspective schematic diagram showing a structural example of a display device DSP using the stacked structure, Fig.33B It is a block diagram of the DSP of the display device.

[0517] The display device DSP includes a storage circuit area MEMA, a driving circuit area DRVA, a circuit layer SWCL, and a display area EMA. The storage circuit area MEMA and the driving circuit area DRVA are located below the circuit layer SWCL, and the display area EMA is located above the circuit layer SWCL. In other words, in the display device DSP, the storage circuit area MEMA and the driving circuit area DRVA, the circuit layer SWCL, and the display area EMA are stacked in sequence from the bottom.

[0518] The memory circuit area MEMA includes, for example, a plurality of memory circuits ME. The memory circuit ME may refer to the memory circuit ME in Embodiment 1. Therefore, the memory circuit area MEMA may include, for example, a memory circuit ME including DRAM, DOSRAM (registered trademark), NOSRAM (registered trademark), SRAM, FeRAM, ReRAM, MRAM, or PRAM. Fig.33B In the embodiment, the memory circuit ME is a memory circuit for storing digital data, and the memory circuit ME sends 1-bit or plural-bit data to the circuit layer SWCL. The memory circuit ME stores image data to be sent to the pixel circuit PX described later.

[0519] For example, the memory circuit ME has a function of reading out 8-bit (1-byte) image data and sending the image data to the drive circuit area DRVA described later. Note that the data that the memory circuit ME can process is not limited to 8 bits, and for example, it can also process data less than 8 bits such as 1 bit, 2 bits, or 4 bits. In addition, for example, it can also process data greater than 8 bits such as 16 bits, 32 bits, 64 bits, 128 bits, or 256 bits.

[0520] The driving circuit area DRVA includes, for example, a plurality of digital-to-analog conversion circuits DAC. The digital-to-analog conversion circuit DAC has a function of converting image data of digital data read from the storage circuit ME into analog data. In addition, the driving circuit area DRVA has a function of transmitting the converted analog data to the circuit layer SWCL.

[0521] As an example, the circuit layer SWCL includes a selector MPX. For the selector MPX, the description of the selector MPX described in Embodiment 1 can be referred to.

[0522] As an example, the display area EMA includes a plurality of pixel circuits PX. In particular, the pixel circuits PX are preferably arranged in an array in the display area EMA.

[0523] The plurality of input terminals IT of the selector MPX are electrically connected to the plurality of digital analog conversion circuits DAC of the drive circuit area DRVA, respectively. In addition, the output terminal OT of the selector MPX is electrically connected to one of the plurality of pixel circuits PX included in the display area EMA.

[0524] The selector MPX has, for example, a function of making one of the multiple input terminals IT of the selector MPX and the output terminal OT of the selector MPX conductive according to a signal PSIG input to the selector MPX. In addition, the selector MPX has, for example, a function of making the remaining of the other multiple input terminals IT of the selector MPX and the output terminal OT of the selector MPX non-conductive.

[0525] By configuring the display device DSP as described above, the display device DSP can select image data from the image data held by each of the plurality of memory circuits ME in the memory circuit area MEMA and display the selected image data on one of the plurality of pixel circuits PX in the display area EMA.

[0526] Next, a configuration example of the pixel circuit PX will be described.

[0527] exist Fig.34 2 shows a circuit layer OSL that may be included in the pixel circuit PX and a light emitting layer LE connected to the circuit layer OSL. Fig.34 In the embodiment, the light emitting layer LE includes a light emitting device 130. In addition, Fig.34 The diagram shows the connection between the circuit elements included in the circuit layer OSL in the pixel circuit PX.

[0528] The circuit layer OSL includes a transistor 500A, a transistor 500B, a transistor 500C, and a capacitor 600. As each of the transistor 500A, the transistor 500B, and the transistor 500C, for example, the transistor that can be used as the transistor M1 described in Embodiment 1 can be used. In particular, each of the transistor 500A, the transistor 500B, and the transistor 500C is preferably an OS transistor. Fig.34 In FIG. 1 , each of transistor 500A, transistor 500B, and transistor 500C is shown as an OS transistor including a back gate electrode. In this case, a structure in which the same signal as the gate electrode is supplied to the back gate electrode, or a structure in which a signal different from the gate electrode is supplied to the back gate electrode can be realized. Note that Fig.34 Although the transistor 500A, the transistor 500B, and the transistor 500C include back-gate electrodes, the transistor 500A, the transistor 500B, and the transistor 500C may not include back-gate electrodes.

[0529] The transistor 500B includes a gate electrode electrically connected to the transistor 500A, a first electrode electrically connected to the light emitting device 130 , and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring of a potential for supplying a current to the light emitting device 130 .

[0530] The transistor 500A includes a first terminal electrically connected to the gate electrode of the transistor 500B, a second terminal electrically connected to the wiring SL serving as a source line, and a gate electrode having a function of controlling switching between an on state and an off state according to the potential of the wiring G1 serving as a gate line.

[0531] The wiring SL is used as a source line in the pixel circuit PX, and therefore the image data sent to the wiring SL is image data output from the selector MPX of the above-mentioned circuit layer SWCL.

[0532] The transistor 500C includes a first terminal electrically connected to the wiring V0, a ​​second terminal electrically connected to the light emitting device 130, and a gate electrode having a function of controlling switching between an on state and an off state according to the potential of the wiring G2 used as a gate line. The wiring V0 is a wiring for supplying a reference potential and is also a wiring for outputting a current flowing through the circuit layer OSL to the driving circuit area DRVA.

[0533] The capacitor 600 includes a conductive film electrically connected to the gate electrode of the transistor 500B and a conductive film electrically connected to the second electrode of the transistor 500C.

[0534] The light emitting device 130 includes a first electrode electrically connected to the first electrode of the transistor 500B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for supplying a potential for supplying current to the light emitting device 130.

[0535] Thus, the intensity of light emitted by the light emitting device 130 can be controlled according to the image signal supplied to the gate electrode of the transistor 500B. In addition, the variation in gate-source voltage of the transistor 500B can be suppressed by the reference potential of the wiring V0 supplied through the transistor 500C.

[0536] In addition, a current value that can be used when setting pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can be used as a monitoring line that outputs the current flowing through the transistor 500B or the current flowing through the light-emitting device 130 to the outside. The current output to the wiring V0 is converted into a voltage by, for example, a source follower circuit and output to the outside. Alternatively, the current can be converted into a digital signal by, for example, an analog-to-digital conversion circuit and output to a circuit that performs dimming and color adjustment processing. The above-mentioned source follower circuit, analog-to-digital conversion circuit, and circuit that performs dimming and color adjustment processing can each be included in the drive circuit area DRVA, for example.

[0537] Fig.35 Schematically shows the upper and lower relationship of the driving circuit area DRVA, the memory circuit area MEMA, the circuit layer SWCL, and the circuit layer OSL having a plurality of transistors and the light emitting layer LE having the light emitting device 130 included in the pixel circuit PX. As an example, Fig.35 The display area EMA of the display device DSP shown includes a circuit layer OSL and a light emitting layer LE.

[0538] In addition, Fig.35In the structure shown as an example, the wiring used to electrically connect the circuit layer OSL to the driving circuit area DRVA can be shortened, so the wiring resistance of the wiring can be reduced. Therefore, data can be written at high speed, so the display device DSP can be driven at high speed. As a result, even if the number of pixel circuits PX included in the display device DSP is large, sufficient frame periods can be ensured, so the pixel density of the display device DSP can be improved. In addition, by increasing the pixel density of the display device DSP, the clarity of the image displayed by the display device DSP can be improved. For example, the pixel density of the display device DSP can be 500ppi or more, preferably 1000ppi or more, more preferably 3000ppi or more, further preferably 5000ppi or more, and further preferably 6000ppi or more. Therefore, it can be said that the display device DSP can be, for example, a display device for XR (Extended Reality or Cross Reality) such as AR (Augmented Reality) and VR (Virtual Reality), and is suitable for use in electronic devices such as HMD (Head-Mounted Display) where the display unit is close to the user.

[0539] <Structure Example of Electronic Equipment> Next, an example of electronic equipment that can use the above-mentioned display device DSP is described.

[0540] The electronic device includes, for example, a display device and one or more selected from an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

[0541] Furthermore, the electronic device may include a secondary battery, and the secondary battery is preferably charged by contactless power transmission.

[0542] Examples of secondary batteries include lithium ion secondary batteries (e.g., lithium polymer batteries using a gel electrolyte (lithium ion polymer batteries)), nickel hydrogen batteries, nickel cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel zinc batteries, and silver zinc batteries.

[0543] Furthermore, the electronic device may include an antenna. By using the antenna to receive a signal, an image, information, etc. may be displayed on the display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0544] For example, images with full HD, 4K2K, 8K4K, 16K8K or higher resolution can be displayed on the display area of ​​the electronic device.

[0545] Examples of electronic devices include electronic devices with large screens such as televisions, notebook personal computers, display devices, digital signage, pinball machines, and game consoles. In addition, examples of electronic devices include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0546] The electronic device can be assembled along a plane or curved surface of an inner wall or outer wall of a building such as a house or a high-rise building, etc. In addition, the electronic device can be assembled along a plane or curved surface of an interior decoration or exterior decoration of a car or the like.

[0547] [Mobile phone] Fig.36A The information terminal 5500 shown is a mobile phone (smartphone) which is one of the information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511 . The display portion 5511 has a touch panel as an input interface, and the housing 5510 is provided with buttons.

[0548] [Wearable terminal] Fig.36B 59 is an external view of an information terminal 5900 which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901 , a display portion 5902 , operation buttons 5903 , a crown 5904 , and a band 5905 .

[0549] [Information Terminal] in addition, Fig.36C A notebook information terminal 5300 is shown. As an example, Fig.36C In the illustrated notebook information terminal 5300 , a housing 5330 a includes a display portion 5331 , and a housing 5330 b includes a keyboard portion 5350 .

[0550] Note that in the above example, FIG. 36A to FIG. 36C Smartphones, wearable terminals, and notebook information terminals are shown as examples of electronic devices, but the present invention can also be applied to information terminals other than smart phones, wearable terminals, and notebook information terminals. Examples of information terminals other than smart phones, wearable terminals, and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0551] [camera] Fig.36D8100 is an external view of a camera 8000 equipped with a viewfinder 8100. The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, and a shutter button 8004. In addition, the camera 8000 is equipped with a detachable lens 8006. The viewfinder 8100 includes a housing 8101, a display unit 8102, and buttons 8103.

[0552] In the camera 8000, the lens 8006 and the housing may be formed as one body.

[0553] The camera 8000 can take a picture by pressing a shutter button 8004 or touching a display portion 8002 serving as a touch panel.

[0554] The housing 8001 includes an embedder having electrodes, and can be connected to a flash device in addition to the viewfinder 8100 .

[0555] The housing 8101 is attached to the camera 8000 via an inserter that is fitted into the inserter of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on the display portion 8102.

[0556] Button 8103 is used as a power button.

[0557] The display device according to one embodiment of the present invention can be used for the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100. Alternatively, the camera 8000 may include a built-in viewfinder.

[0558] [Game console] Fig.36E 1 is an external view showing a portable game machine 5200 as an example of a game machine. The portable game machine 5200 includes a housing 5201 , a display portion 5202 , and buttons 5203 .

[0559] In addition, the images of the portable game console 5200 can be output by a display device such as a television device, a personal computer monitor, a game monitor, or a head-mounted display.

[0560] By using the display device described in the above embodiment mode for the portable game machine 5200, a low-power portable game machine 5200 can be realized. In addition, low power consumption can reduce heat generated by the circuit, thereby reducing negative effects on the circuit itself, peripheral circuits, and modules caused by heat.

[0561] exist Fig.36EIn the embodiment of the present invention, a portable game console is shown as an example of a game console, but the electronic device of one embodiment of the present invention is not limited thereto. As an electronic device of one embodiment of the present invention, for example, a fixed game console, an arcade game console installed in an entertainment facility (for example, a game center, an amusement park, etc.), and a pitching machine for batting practice installed in a sports facility can be cited.

[0562] [TV device] Fig.36F 9000 includes a frame 9002, a display unit 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, and a sensor 9007 (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, number of rotations, distance, light (including infrared), liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration or smell), etc. Alternatively, the sensor has the function of detecting or measuring smell or light (including infrared). A display device of one embodiment of the present invention can be assembled in a television device. A display unit 9001 of, for example, 50 inches or more or 100 inches or more can be assembled in a television device.

[0563] By applying the display device described in the above embodiment to the television set 9000, low power consumption television set 9000 can be realized. In addition, low power consumption can reduce heat generated by the circuit, thereby reducing negative effects on the circuit itself, peripheral circuits, and modules caused by heat.

[0564] [Mobile body] A display device according to one embodiment of the present invention can be applied near a driver's seat of a car as a moving object.

[0565] Figure 36G This is a diagram showing the vicinity of the front windshield in the interior of a vehicle. Figure 36G Display panel 5701, display panel 5702, display panel 5703 installed on the instrument panel, and display panel 5704 installed on the pillar are shown.

[0566] Display panels 5701 to 5703 can display various information such as navigation information, speedometer, tachometer, driving distance, fuel level, gear status, air conditioning settings, etc. In addition, users can appropriately change the display content and layout displayed on the display panel according to their preferences, which can improve the design. Display panels 5701 to 5703 can also be used as lighting devices.

[0567] By displaying the image captured by the camera unit installed on the vehicle body on the display panel 5704, the field of view (blind spot) blocked by the pillar can be supplemented. In other words, by displaying the image captured by the camera unit installed on the outside of the car, the blind spot can be supplemented, thereby improving safety. In addition, by displaying the image that supplements the invisible part, safety can be confirmed more naturally and comfortably. The display panel 5704 can be used as a lighting device.

[0568] The display device of one embodiment of the present invention can be applied to, for example, the display panels 5701 to 5704 .

[0569] Although a car is described as an example of a mobile body in the above examples, the mobile body is not limited to a car. For example, a tram, a monorail, a ship, a flying object (for example, a helicopter, an unmanned aircraft (drone), an airplane, a rocket), etc. can also be cited as a mobile body, and a display device according to one embodiment of the present invention can be applied to these mobile bodies.

[0570] [Digital Signage] Fig.36H Shows an example of a digital sign that can be mounted on a wall. Fig.36H An example of a digital signage 6200 hung on a wall 6201 is shown. The display device according to one embodiment of the present invention can be applied to, for example, a display unit of the digital signage 6200. In addition, the digital signage 6200 can be provided with an interface such as a touch panel.

[0571] Note that an electronic device that can be hung on a wall is shown as an example of a digital signage above, but the types of digital signage are not limited to this. For example, digital signage can be: a digital signage mounted on a pole; a digital signage placed on the ground; or a digital signage installed on the roof or side wall of a building.

[0572] [Head-mounted display] Fig.36I 8300 is an external view showing an electronic device 8300 as a head mounted display. The electronic device 8300 includes a housing 8301 , a display portion 8302 , a belt-shaped fixing member 8304 , a head mounted fixing member 8304 a , and a pair of lenses 8305 .

[0573] In addition, although Fig.36I Although not shown in the figure, the electronic device 8300 may also be equipped with interfaces such as operation buttons or power buttons.

[0574] The user can see the display on the display unit 8302 through the lens 8305. Preferably, the display unit 8302 is arranged in a curved manner. This is because the user can experience a high sense of reality. In addition, different images displayed on different areas of the display unit 8302 can be seen through the lens 8305, and three-dimensional display using parallax can be performed. In addition, one embodiment of the present invention is not limited to a structure in which one display unit 8302 is provided, and two display units 8302 can also be provided in a manner in which one display unit is provided for each eye of the user.

[0575] In addition, for example, a very high-definition d...

Claims

1. A semiconductor device comprising: First storage layer; Second storage layer; as well as Circuit layer, Wherein, the first storage layer includes a plurality of first storage circuits, The second storage layer includes a second storage circuit, The circuit layer includes a selector, The selector includes a plurality of input terminals and an output terminal. The first storage layer is located below the circuit layer. The second storage layer is located above the circuit layer, The plurality of first storage circuits are all electrically connected to the plurality of input terminals, The second storage circuit is electrically connected to the output terminal, The selector has a function of bringing one selected from the plurality of input terminals into conduction with the output terminal. Furthermore, the semiconductor device has a function of writing the data read from the second storage circuit into the first storage circuit via the selector.

2. The semiconductor device according to claim 1, further comprising: a semiconductor substrate comprising silicon, The first storage layer is located on the semiconductor substrate. The first storage circuit includes a first transistor, And the first transistor contains the silicon in a channel formation region.

3. The semiconductor device according to claim 2, wherein the second storage circuit comprises a second transistor, the second transistor includes a metal oxide in a channel formation region, The metal oxide comprises one or more selected from indium, zinc and element M, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony.

4. The semiconductor device according to claim 3, The data is any one of 1 bit, 2 bits, 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits and 256 bits.

5. The semiconductor device according to claim 4, The first storage circuit and the second storage circuit are not connected via a system bus.

6. A semiconductor device comprising: First storage layer; Second storage layer; as well as Circuit layer, Wherein, the first storage layer includes a plurality of first storage circuits, The second storage layer includes a second storage circuit, The second storage circuit includes a capacitor and a second transistor. The capacitor includes a first conductor, a second conductor, a first insulator and a second insulator. The second transistor includes the second conductor, a third conductor, a fourth conductor, a third insulator, a fourth insulator and a metal oxide. The circuit layer includes a selector, The selector includes a plurality of input terminals and an output terminal. The first storage layer is located below the circuit layer. The second storage layer is located above the circuit layer, The first insulator comprises a first opening, The first conductor is located on the side and bottom surfaces of the first opening and the top surface of the first insulator. The second insulator is located on the top surface of the first insulator and the top surface of the first conductor, The second conductor is located in a region of the top surface of the second insulator that overlaps with the first conductor. The third insulator is located on the top surface of the second conductor, The third conductor is located on the top surface of the third insulator, The third insulator and the third conductor include a second opening, The metal oxide is located on the side surface of the second opening, the top surface of the second conductor, and the top surface of the third conductor. The fourth insulator is located on the top surface of the metal oxide and the top surface of the third conductor, The fourth conductor is located in a region of the top surface of the fourth insulator that overlaps with the metal oxide. The plurality of first storage circuits are all electrically connected to the plurality of input terminals, The third conductor is electrically connected to the output terminal, The selector has a function of bringing one selected from the plurality of input terminals into conduction with the output terminal. Furthermore, the semiconductor device has a function of writing the data read from the second storage circuit into the first storage circuit via the selector.

7. The semiconductor device according to claim 6, The metal oxide comprises one or more selected from indium, zinc and element M, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony.

8. The semiconductor device according to claim 7, further comprising: a semiconductor substrate comprising silicon, The first storage layer is located on the semiconductor substrate. The first storage circuit includes a first transistor, And the first transistor contains the silicon in a channel formation region.

9. The semiconductor device according to claim 8, The second insulator comprises an oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium and magnesium.

10. The semiconductor device according to claim 9, The data is any one of 1 bit, 2 bits, 4 bits, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits and 256 bits.

11. The semiconductor device according to claim 10, The first storage circuit and the second storage circuit are not connected via a system bus.

12. An electronic device comprising: The semiconductor device according to any one of claims 1 to 11; as well as Frame.

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