3D memory cell with double-sided contacts and method of manufacture

Abstract

Disclosed herein is a memory device including a stacked structure. The stacked structure has a plurality of first layers and a plurality of dielectric layers alternating. The stack structure has a first surface and a second surface opposite the first surface. The plurality of first contact structures includes a conductive material. A plurality of first contact structures penetrate from the first surface into the stack structure to contact first portions of the plurality of first layers, respectively. The plurality of second contact structures includes a conductive material. Each of the plurality of second contact structures penetrates from the second surface into the stack structure to respectively contact a remaining portion of the conductive layer other than the first portion of the plurality of first layers.

Description

Technical Field

[0001] The present disclosure relates to three-dimensional (3D) memory devices and methods of manufacturing the same. Background Art

[0002] Planar memory cells are shrunk to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit. 3D memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the invention

[0003] The present disclosure describes a three-dimensional (3D) memory device and a method for manufacturing the same. For example, in one aspect, a method includes providing a stacked structure, the stacked structure including a plurality of alternating first layers and a plurality of dielectric layers, wherein the stacked structure has a first surface and a second surface opposite to the first surface. The method includes forming a plurality of first contact structures penetrating from the first surface into the stacked structure to contact first portions of the plurality of first layers, respectively. In addition, the method includes forming a plurality of second contact structures penetrating from the second surface into the stacked structure to contact remaining portions of the plurality of first layers, respectively, except for the first portions of the plurality of first layers.

[0004] On the other hand, the present disclosure describes a memory device, including a stacked structure having a plurality of first layers and a plurality of dielectric layers alternating. The stacked structure has a first surface and a second surface opposite to the first surface. The memory device includes a plurality of first contact structures having a conductive material. The plurality of first contact structures penetrate into the stacked structure from the first surface to contact with first portions of the plurality of first layers, respectively. The memory device also includes a plurality of second contact structures having a conductive material, wherein each of the plurality of second contact structures penetrates into the stacked structure from the second surface to contact with the remaining portions of the plurality of conductive layers, respectively, except for the first portions of the plurality of first layers.

[0005] On the other hand, the present disclosure also describes a system, including a memory device configured to store data. The memory device includes a stacked structure having a plurality of first layers and a plurality of dielectric layers alternating. The stacked structure has a first surface and a second surface opposite to the first surface. The memory device includes a plurality of first contact structures having a conductive material. Each of the plurality of first contact structures penetrates into the stacked structure from the first surface to contact with a first portion of the plurality of first layers, respectively. A plurality of second contact structures of the memory device have a conductive material. Each of the plurality of second contact structures penetrates into the stacked structure from the second surface to contact with the remaining portions of the plurality of conductive layers, respectively, except for the first portions of the plurality of first layers. A memory controller is electrically connected to the memory device and controls the memory device.

[0006] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims.

[0007] Some embodiments provide one or more of the following advantages. For example, in some embodiments, forming a contact structure extending through the top surface and the bottom surface increases the overall density of the 3D memory device because both the first surface and the second surface have contact structures extending through the 3D memory device toward the center of the 3D memory device. A higher density 3D memory device increases the storage capacity of a given vertical space, so that a larger memory capacity can be achieved without increasing the vertical space.

[0008] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable one skilled in the relevant art to make and use the present disclosure.

[0010] Figure 1 A plan view of a 3D memory device with contact structures according to some aspects of the present disclosure is shown.

[0011] Figure 2 A top perspective view of a 3D memory device with contact structures according to some aspects of the present disclosure is shown.

[0012] Figure 3 Shows the formation Figure 1 and Figure 2A flow chart of a method for a 3D memory device is shown.

[0013] Figure 4 A side view of a stacked structure 400 with staggered layers is shown.

[0014] Figure 5A-Figure 8 Shown in Figure 3 Stack structure 400 is shown at various processing stages during method 300 .

[0015] Fig. 9 A block diagram of a system having a 3D memory device is shown.

[0016] The present disclosure will be described with reference to the accompanying drawings. Like reference numerals and names in the various drawings indicate like elements. DETAILED DESCRIPTION

[0017] Although specific configurations and arrangements have been discussed, it should be understood that this is done only for the purpose of illustration. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. The present disclosure may also be used in various other applications. The functions and structural features described in the present disclosure may be combined, adjusted and modified with each other and in a manner not specifically depicted in the accompanying drawings, so that these combinations, adjustments and modifications are within the scope of the present disclosure.

[0018] Typically, a term can be understood at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a", "an" or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood to not necessarily be intended to express an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0019] The meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “over” means not only the meaning of “above something” or “on something,” but also includes the meaning of “it is over something” or “it is over something” without intervening features or layers therebetween (i.e., directly on something).

[0020] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or feature as shown in the figures to another element or features. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0021] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0022] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire lower or upper structure, or may have a range that is less than the range of the lower or upper structure. In addition, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors (wherein interconnect lines and / or vertical contacts are formed) and one or more dielectric layers.

[0023] In some 3D memory devices (such as 3D NAND memory devices), memory cells for storing data are stacked vertically by a stacked structure (e.g., a memory stack) in a vertical channel structure. The 3D memory device typically includes a contact region formed on one or more sides (edges) or at the center of the stacked memory structure for purposes such as word line pick-up / fan-out using electrical / physical contacts landing on different steps / levels of the contact region. Sometimes a dummy channel structure is formed through the memory stack in an area outside of a core array region where a channel structure of a 3D NAND memory device is formed to provide mechanical support to the stack structure, particularly during a gate replacement process that temporarily removes some layers of the stack structure by opening a gap across the core array region and the contact region of the stack structure.

[0024] As the memory cell density of 3D NAND memory devices continues to increase, the integration of various structures (such as dummy channel structures, contact structures, contact regions, seam openings, etc.) becomes increasingly challenging from both a device design perspective and a manufacturing process perspective.

[0025] In order to solve one or more of the above problems, the embodiments described herein are directed to forming contact structures on both sides of the stacked structure. The channel length of the contact structure also needs to be at substantially the same length in order to reach the conductive layer (e.g., word line) in the 3D memory device. There may be, for example, 400 or more channels in a 3D memory device. Each channel may require a specific aspect ratio, critical dimension (CD), and spacing between channels of the contact structure. For example, the CD of a channel that penetrates less than 300 layers may be between 1 mm and 2 mm.

[0026] A combination of isotropic and anisotropic etching can be used to form a channel so that the correct depth of the vertical channel is reached for each conductive layer of the stacked structure and the correct horizontal length is achieved. At a depth of more than, for example, 300 layers into the stacked structure, etching accuracy and selectivity are reduced. To address this challenge, the method disclosed herein forms a plurality of contact structures on a first side of the stacked structure, flips the stacked structure, and continues by forming a second plurality of contact structures on a second side of the stacked structure. Advantageously, the disclosed method can achieve a narrower 3D memory structure in some cases. And the overall density of the 3D memory structure can be increased because both the first surface and the second surface of the stacked structure have contact structures extending therethrough. Therefore, more 3D memory structures can be arranged horizontally in the controller, thereby achieving a denser array of 3D memory structures.

[0027] Figure 1 1 shows a plan view of a 3D memory device 100 having a contact structure 106 according to some aspects of the present disclosure. In some embodiments, the 3D memory device 100 is a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings. It should be noted that Figure 1 100 includes an x-axis and a y-axis to illustrate two orthogonal (perpendicular) directions in the wafer plane. The x-direction is the stacking layer (eg, word line) direction of the 3D memory device 100 , and the y-direction is the bit line direction of the 3D memory device 100 .

[0028] like Figure 1As shown, the 3D memory device 100 may include one or more blocks 102 arranged in the y direction (bit line direction) and separated by a gap structure 108 (e.g., a gate line gap (GLS)). In some embodiments where the 3D memory device 100 is a NAND flash memory device, each block 102 is the minimum erasable unit of the NAND flash memory device. Each block 102 may also include a plurality of fingers 104 separated by a gap structure 108 having an "H" cut 109 in the y direction.

[0029] like Figure 1 As shown, the 3D memory device 100 can be divided into at least a core array region 101 (also referred to as a core region), in which an array of channel structures 110 is formed, and a contact region 103, in which a contact structure 106 is formed. According to some embodiments, the core array region 101 and the contact region 103 are arranged in the x-direction (stacked layer direction). Although Figure 1 One core array region 101 and one contact region 103 are shown in the figure, but in other examples, the 3D memory device 100 may include multiple core array regions 101 and / or multiple contact regions 103, for example, one contact region 103 between two core array regions 101 in the x direction. Figure 1 Only the portion of the core array region 101 adjacent to the contact region 103 is shown.

[0030] As described in detail below, the contact region 103 may include a conductive portion 105 and a dielectric portion 107 arranged in the y-direction. Figure 1 As shown, according to some embodiments, the contact structure 106 is disposed in the dielectric portion 107, and the dummy channel structure 112 is disposed in the conductive portion 105 of the contact region 103 to provide mechanical support and / or load balancing. Figure 1 As shown in FIG. 1 , the dummy channel structure 112 is also disposed in the dielectric portion 107 of the contact region 103, for example, between the contact structures 106 in the x-direction. In some embodiments, the dummy channel structure 112 is not disposed in the dielectric portion 107 of the contact region 103, that is, it is disposed only in the conductive portion 105 of the contact region 103. Figure 1 As shown, each finger 104 of the 3D memory device 100 may include a row of contact structures 106 disposed in a dielectric portion 107 of the contact region 103. The layout and arrangement of the contact structures 106 and the shape of each contact structure 106 may vary in different examples.

[0031] Figure 2 1 shows a top perspective view of a 3D memory device 100 having a contact structure 106 according to some aspects of the present disclosure. Figure 1 and Figure 2 As shown, stacked structure 201 can be formed on substrate 203, which can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. In some embodiments, substrate 203 includes single crystal silicon, which is a portion of a wafer on which 3D memory device 100 is manufactured, whether in its native thickness or after being thinned. In some embodiments, substrate 203 includes, for example, polycrystalline silicon, which is a semiconductor layer that replaces a portion of a wafer on which 3D memory device 100 is manufactured. It should be noted that Figure 1 and Figure 2 , includes x, y, and z axes to further illustrate the spatial relationship of components in the 3D memory device 100. The substrate 203 of the 3D memory device 100 includes two lateral surfaces extending laterally in the xy plane: a top surface on the front side of the wafer on which the stacked structure 201 can be formed, and a bottom surface on the back side opposite to the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when the substrate 203 is located in the lowest plane of the 3D memory device 100 in the z-direction (a vertical direction perpendicular to the xy plane), it is determined whether a component (e.g., a layer or device) is "on", "above", or "below" another component (e.g., a layer or device) of the 3D memory device 100 relative to the substrate 203 of the 3D memory device 100 in the z-direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0032] Figure 3 Shows the manufacturing Figure 1 Flowchart of an example method of stacking a structure as shown in FIG. Method 300 begins at operation 302, wherein a 3D stacking structure 400 is provided, such as Figure 4 shown. Figure 4 A side view of a stacked structure 400 having a plurality of staggered layers is shown. The 3D stacked structure 400 includes a contact region 404 and a core region 406 that meet at an interface 408. The 3D stacked structure 400 is disposed on a first substrate 402 with a first insulating layer 410 disposed therebetween. The 3D stacked structure 400 has a first surface 424 and a second surface 426 opposite to the first surface 424. The 3D stacked structure 400 is disposed between the first surface 424 and the second surface 426.

[0033] The contact region 404 includes a first dielectric layer 412 and a second dielectric layer 414 interlaced through the stacked structure 400. One or more second insulating layers in the second insulating layer 416 are disposed above the topmost first dielectric layer 412. The first dielectric layer 412 and the second dielectric layer 414 may include one or more dielectric materials. For example, the first dielectric layer 412 may include an oxide, such as silicon oxide. The second dielectric layer 414 may include a nitride, such as SiN or TiN. The insulating layer 416 may be an oxide layer, or a layer having one or more other types of one or more dielectric materials.

[0034] The core region 406 includes a first conductive layer 418 interleaved with a first dielectric layer 412. A high-k dielectric layer 420 circumscribes the first conductive layer 418. The high-k dielectric layer 420 and the first dielectric layer 412 contact each other at the interface 408. Because in some examples, the lengths of the first dielectric layer 412 and the first conductive layer 418 can be different in each vertical row of the 3D stacked structure 400, the horizontal position of the interface 408 will depend on a given row of the stacked structure 400.

[0035] Each of the first substrate 402, the first insulating layer 410, the first dielectric layer 412, the second dielectric layer 414, the second insulating layer 416, the first conductive layer 418, and the high-k dielectric layer 420 has a first surface parallel to the first surface 424 and a second surface parallel to the second surface 426 of the 3D stacked structure 400. In one example, the high-k dielectric layer 420 is made of an oxide material. In some examples, the high-k dielectric layer 420 is made of any one of aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), or a combination thereof. In some embodiments, the first conductive layer 418 may be made of tungsten (W) or cobalt (Co). In this article, high-k refers to a material with a high dielectric constant k.

[0036] A conductive channel structure 422 is formed in the core region 406 of the 3D stacked structure 400. The conductive channel structure 422 extends through the first dielectric layer 412 and the second dielectric layer 414 in the contact region 404. A dummy channel (not shown) mechanically supports the 3D stacked structure 400 during manufacturing. In at least one example, the conductive channel structure 422 may have a cylindrical shape (e.g., a column). However, other shapes are possible without departing from the scope of the present disclosure.

[0037] To form the conductive channel structure 422, a channel hole extending vertically through the stacked structure is formed. In some embodiments, a memory layer and a channel layer are sequentially formed on the sidewalls of the channel hole. The memory layer (including a barrier layer, a storage layer, and a tunneling layer) and the channel layer are sequentially formed in this order along the sidewalls and bottom surface of the hole. In some embodiments, the memory layer is first deposited along the sidewalls and bottom surface of the channel hole, and then the semiconductor channel is deposited on the memory layer. One or more thin film deposition processes can be used to continuously deposit a barrier layer, a storage layer, and a tunneling layer in this order to form a memory layer. The channel layer can then be formed by depositing a semiconductor material (such as polysilicon) on the tunneling layer of the memory layer using one or more thin film deposition processes.

[0038] Figure 4 An example of a manufacturing process for forming a hole for the conductive channel structure 422 is shown including wet etching and / or dry etching, such as deep reactive ion etching (DRIE). Film layers such as the first dielectric layer 412 and the second dielectric layer 414 and the first insulating layer 410 and the second insulating layer 416 can be formed by one or more film deposition processes including atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), any other suitable process, or any combination thereof. In addition, conductive layers such as the first conductive layer 418 and the conductive channel structure 422 can be deposited using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0039] The first insulating layer 410 extends horizontally between the 3D stacked structure 400 and the first substrate 402. In some examples, the first insulating layer 410 surrounds the conductive channel structure 422 so that a first terminal of the conductive channel structure 422 is exposed through the top of the second insulating layer 416. A second terminal of the conductive channel structure 422, opposite to the first terminal, extends into the first substrate 402 below the top surface of the first substrate 402. The first insulating layer 410 and the second insulating layer 416 can be made of, for example, SiO2 and have a thickness of from 5 nm to 50 nm.

[0040] At operation 304, a first contact structure 500 is formed in the 3D memory device. The first contact structure 500 is formed through the first insulating layer. Figures 5A-5E As shown, the stacked structure has a first contact structure 500 that passes through a plurality of staggered layers. The first contact structure 500 extends through the first insulating layer 410 and a portion of the 3D stacked structure 400. The first contact structure 500 is substantially isotropically formed so that the sidewalls of the first contact structure 500 are relatively symmetrical about an imaginary center 516 extending through the center of the contact structure 500.

[0041] After forming the first contact structure 500 in whole or in part, a horizontal trench (not shown) is formed in the 3D stacked structure 400 at the terminal of the contact structure 500. In one example, the horizontal trench is substantially symmetrical about the imaginary center 516, such as Figure 5A As shown. Therefore, the length in the vertical direction and the height in the vertical direction are substantially symmetrical about the center of the vertical channel. The symmetrically formed horizontal channel is formed by dry etching (e.g., by DRIE). Therefore, the height of the horizontal channel can decrease in the direction away from the center.

[0042] The first dielectric layer 412 is removed by etching along the length of the horizontal channel. After removing the first dielectric layer 412, the high-k dielectric layer 420 is removed from a portion of the first conductive layer 418 at the interface 408. Thus, the first conductive layer 418 near the interface 408 is exposed to the surrounding environment within the 3D stacked structure 400. In some examples, the length of the horizontal channel extends laterally into the contact region 404 and the core region 406.

[0043] The high-k dielectric layer 420 is removed from the first conductive layer 418 in a portion of the core region 406, so that the horizontal channel extends to the first insulating layer 410 surrounding the conductive channel structure 422. When the high-k dielectric layer 420 is removed, the first conductive layer 418 is thereby exposed to the environment. The height of the horizontal channel is substantially uniform in a direction away from or toward the center.

[0044] In this example, a wet etchant is used to form the horizontal channels. A dry etchant is used to form the contact structure 500. Phosphoric acid is an example of a wet etchant, however other wet etchants are suitable as long as the height of the resulting horizontal channels is substantially uniform. Advantageously, the wet etchant removes the first dielectric layer 412 and does not etch the second dielectric layer 414 (orange, dark and light yellow). In addition, the high-k dielectric layer 420 is etched during operation 304. In one example, phosphoric acid is a wet etchant.

[0045] Proceeding to operation 306, one or more metals are formed in the first contact structure. Figure 5A and Figure 5B First contact structures 500 and 502 are shown extending through the 3D stacked structure 400. Figure 5A As shown in FIG. 4 , one or more conductive layers, such as a second conductive layer 504 (i.e., a lateral contact) and a conductive shell 508 (i.e., a first portion), are deposited in the first contact structure 500 and the horizontal trench. A dielectric filler 506 is enclosed within the conductive shell 508. The dielectric filler 506 also provides structural support for the conductive shell 508 and the surrounding layers (i.e., the first dielectric layer 412, the second dielectric layer 414, and the insulating layer 416) in the contact region 404 of the 3D stacked structure 400.

[0046] The second conductive layer 504 is disposed in the horizontal channel. The second conductive layer 504 covers and contacts the sidewall of the first contact structure 500, so that the second conductive layer 504 disposed in the first contact structure 500 contacts and is electrically coupled to the first conductive layer 418. The dielectric filler 506 is formed on the second conductive layer 504. The conductive shell 508 has a flat surface 510 parallel to the first surface 424. In one example, the periphery of the conductive shell 508 has a circular shape and can form a ring around the dielectric filler 506. Therefore, the flat surface 510 of the conductive shell 508 has a corresponding circular shape, thereby forming a circular or elliptical shape. In another example, the conductive shell 508 has a rectangular shape, and therefore, the flat surface 510 has a corresponding rectangular shape, such as a square or a rectangle.

[0047] The conductive shell 508 is deposited over the second conductive layer 504, thereby creating a signal path between the first conductive layer 418, the second conductive layer 504, and the conductive shell 508. One advantage of this embodiment is the increased integrity of the conductive layer extending from the write line leading out of the 3D stacked structure 400. The height of the horizontal channel and therefore the height of the first conductive layer 418 (e.g., word line) can have a thickness in the range of, for example, from 10 nm to 100 nm.

[0048] The second conductive layer 504 surrounded by the high-k dielectric layer 420 fills the entirety of the horizontal trench between the contact region 404 and the core region 406. In this way, the second conductive layer 504 is physically and electrically coupled to the first conductive layer 418. On the opposite side of the 3D stacked structure 400 is the interface 408 in the contact region 404, where the second conductive layer 504 contacts and terminates at the vertical sidewalls of the first dielectric layer 412. The upper and lower sides (shown but not numbered) of the second conductive layer 504 in the horizontal trench contact the first dielectric layer 412. In this way, the second conductive layer 504 is insulated on the upper and lower sides of the second conductive layer 504. In some embodiments, the second conductive layer 504 is composed of tungsten, cobalt, or a combination of both.

[0049] Figure 5BA top perspective view of the 3D stacked structure 400 is shown. The first contact structures 500, 502 and the conductive channel structure 422 are exposed through the first surface 424 of the 3D stacked structure 400. The diameter 512 of the first contact structure 500 is greater than the diameter 514 of the first contact structure 502. The diameter 512 of the first contact structure 500 and the diameter 514 of the first contact structure 502 correspond to the depth of each conductive structure (e.g., word line) within the 3D stacked structure 400. Therefore, because the first contact structure 500 extends to a greater depth below the first surface 424 than the first contact structure 502, the diameter 512 is greater than the diameter 514. In some examples, the depth of the first contact structure 500 can be equal to or less than 300 interleaved layers (e.g., the first dielectric layer 412 and the second dielectric layer 414, the first conductive layer 418, and the high-k dielectric layer 420).

[0050] like Figure 5C As shown, the first semiconductor layer 520 is disposed on top of and in contact with the second substrate 522 relative to the first surface 424 of the 3D stacked structure 400. The first semiconductor layer 520 and the second substrate 522 are rotated 518 (i.e., flipped) 180 degrees so that the first semiconductor layer 520 faces downward toward the first surface 424. In some embodiments, the 3D stacked structure 400 can be part of a non-monolithic 3D memory device, in which components such as the first semiconductor layer 520 and the stacked structure 400 are formed on different substrates and then bonded in a face-to-face manner. In other embodiments, the 3D stacked structure 400 is rotated 518 180 degrees to reorient the first surface 424 of the 3D stacked structure and the first semiconductor layer 520 for hybrid bonding.

[0051] At operation 308, Figure 5D As shown, the first semiconductor layer 520 is bonded to the stacked structure 400 (i.e., the memory cell array) to form an additional frame of the 3D stacked structure 400. For example, the first semiconductor layer 520 is hybrid bonded to the first surface 424 of the 3D stacked structure 400. The first semiconductor layer 520 has a first surface 604 and a second surface 606 opposite to the first surface 604. One or more interconnect structures can be formed, which provide electrical signals between the stacked structure 400 and one or more peripheral devices. The first semiconductor layer 520 includes a substrate, a peripheral circuit layer disposed on the substrate, and an interconnect layer disposed on the contact layer. Other structures such as through-silicon vias (TSVs) electrically couple the first semiconductor layer 520 to the stacked structure 400. Continuous etching and deposition may be required to form interconnects and TSVs (not shown). In one example, the first semiconductor layer 520 is a complementary metal oxide semiconductor (CMOS).

[0052] Peripheral devices may be formed on the substrate of the first semiconductor layer 520. For example, all or part of the peripheral devices are formed below the surface of the substrate, and / or directly on the surface of the substrate. One or more peripheral devices may include transistors and doped regions to form source / drain regions of transistors formed on the substrate of the first semiconductor layer 520. Some examples of peripheral devices include any suitable digital, analog, and / or mixed-signal peripheral circuits for facilitating the operation of the 3D stacked structure 400. In addition, the peripheral devices may include one or more of the following: power bus and metal wiring, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors).

[0053] At operation 310 , the position of the first surface may be flipped 180 degrees relative to the second surface of the film structure. Figure 5E The 3D stacked structure 400 is shown flipped so that the first surface 424 and the second surface 426 have the same Figures 5A-5D The insulating layer 416 and the 3D stacked structure 400 are etched through the first surface 424 to form a trench in which the first contact structures 500, 502 are formed. The first substrate 402 is removed by etching so that the first surface 424 is exposed to the surrounding processing environment. In one example, the first substrate 402 is removed by using an acid.

[0054] continue Figure 6 After rotating the 3D stacked structure 400 at operation 310, the first substrate 402 is removed from the 3D stacked structure 400. An additional protective layer is formed, for example, by oxide deposition on top of and in contact with the second surface 426. In some embodiments, the protective layer may be composed of a material having the same composition as the insulating layer 416 and may be formed on top of the first insulating layer 410.

[0055] At operation 312, a second contact structure is formed on a second surface of the stacked structure. Fig. 7A As shown, second contact structures 700 and 702 are formed through second surface 426. Second insulating layer 416 and stacked structure 400 are etched through second surface 426 to form channels into which second contact structures 700, 702 are formed. The vertical channels and horizontal channels in second contact structures 700, 702 are formed in a process similar to the vertical channels and horizontal channels formed in first contact structures 500, 502, as described above with respect to operations 304-306. Therefore, operation 312 is not repeated in its entirety.

[0056] The 3D stacked structure 400 has first contact structures 500, 502 that penetrate into the stacked structure 400 from the first surface 424 to respectively contact the first portion of the first dielectric layer 412. The stacked structure 400 has the remaining portion of the layer (i.e., the plurality of first dielectric layers 412) that is not in contact with any of the first contact structures 500, 502 that penetrate into the first surface 424. However, the second contact structures 700, 702 are in contact with the remaining portion of the first dielectric layer 412. Therefore, the second contact structures 700, 702 penetrate into the 3D stacked structure 400 from the second surface 426 to respectively contact the remaining portion of the first dielectric layer 412.

[0057] The second semiconductor layer 800 is disposed on top of and in contact with the third substrate 802 relative to the second surface 426. Figure 7B 426. The second semiconductor layer 800 and the third substrate 802 are rotated 518 180 degrees relative to the second surface 426 so that the second semiconductor layer 800 faces downward toward the second surface 426. As described above with respect to the first semiconductor layer 520, in some embodiments, the second semiconductor layer 800 and the third substrate 802 are formed on different substrates and then bonded in a face-to-face manner. In other embodiments, the 3D stacked structure 400 is rotated 518 180 degrees to reorient the first surface 426 of the 3D stacked structure 400 and the second semiconductor layer 800. In some embodiments, the second semiconductor layer 800 is a CMOS.

[0058] At operation 314, one or more second metals are deposited in the second contact structure. Operation 314 includes a similar process to operation 306, and thus operation 314 is not repeated in its entirety. Thus, the second conductive layer 504 and the dielectric filler 506 are deposited in their respective trenches in a similar manner as described in operation 306.

[0059] At operation 316, the second semiconductor layer 800 is bonded to the second surface 426 of the stacked structure 400. A third substrate 802 is formed over and in contact with the second semiconductor layer 800. Figure 8 A 3D memory device 100 is shown formed of a 3D stacked structure 400 having a plurality of interleaved layers (i.e., first and second dielectric layers 412, 414, first conductive layer 418, and high-k dielectric layer 420) disposed between semiconductor layers 520, 800 surrounded by substrates 402, 802. In some examples, first substrate 402 and third substrate 802 form a housing 808.

[0060] The second semiconductor layer 800 has a first surface 804 and a second surface 806 opposite to the first surface 604. The first substrate 402 and the second substrate 802 may be any suitable semiconductor material, such as silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any suitable combination thereof.

[0061] Fig. 9 A block diagram of a system 900 having a 3D memory device according to some aspects of the present disclosure is shown. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory bank therein. Fig. 9 As shown in , the system 900 may include a host 908 and a memory system 902, the memory system 902 having one or more 3D memory devices 904 and a memory controller 906. The host 908 may be a processor of an electronic device such as a central processing unit (CPU), or a system on a chip (SoC) such as an application processor (AP). The host 908 may be configured to send data to the 3D memory device 904 or receive data from the 3D memory device 904.

[0062] 3D memory device 904 may be any 3D memory device disclosed herein, such as Figure 1 -5, 6A and 6B. In some embodiments, each 3D memory device 904 includes a NAND flash memory. Consistent with the scope of the present disclosure, the contact structure can replace the contact region and the word line contact to achieve the word line pick-up / fan-out function, thereby reducing manufacturing costs and simplifying the manufacturing process.

[0063] According to some embodiments, the memory controller 906 (also referred to as a controller circuit) is coupled to the 3D memory device 904 and the host 908, and is configured to control the 3D memory device 904. For example, the memory controller 906 can be configured to operate a plurality of channel structures via word lines. The memory controller 906 can manage data stored in the 3D memory device 904 and communicate with the host 908. In some embodiments, the memory controller 906 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 906 is designed to operate in a high duty cycle environment SSD or an embedded multimedia card (eMMC), which is used as a data storage body for mobile devices (such as smart phones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 906 may be configured to control operations of the 3D memory device 904, such as read, erase, and program operations. The memory controller 906 may also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 904, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 906 is also configured to process error correction code (ECC) with respect to data read from or written to the 3D memory device 904. Any other suitable functions may also be performed by the memory controller 906, such as formatting the 3D memory device 904.

[0064] The memory controller 906 may communicate with an external device (e.g., the host 908) according to a specific communication protocol. For example, the memory controller 906 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0065] The memory controller 906 and one or more 3D memory devices 904 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 902 can be implemented and packaged into different types of terminal electronic products. In one example, the memory controller 906 and a single 3D memory device 904 can be integrated into a memory card (not shown). The memory card can be a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCMicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may include a memory card connector that electrically couples the memory card to the host 908.

[0066] For example, in one aspect, a method includes providing a stacked structure, the stacked structure including a plurality of first layers and a plurality of dielectric layers alternating, wherein the stacked structure has a first surface and a second surface opposite to the first surface. The method includes forming a plurality of first contact structures penetrating from the first surface into the stacked structure to contact with first portions of the plurality of first layers, respectively. In addition, the method includes forming a plurality of second contact structures penetrating from the second surface into the stacked structure to contact with remaining portions of the plurality of first layers, respectively, except for the first portions of the plurality of first layers.

[0067] In another example, the memory controller 906 and the plurality of 3D memory devices 904 may be integrated into a solid-state device (SSD) (not shown). The SSD may include an SSD connector that electrically couples the SSD to a host 908. In some implementations, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of a memory card.

[0068] In some embodiments of the method, the stack structure has a core region and a contact region adjacent to the core region, and wherein the first contact structure and the second contact structure are in the contact region.

[0069] In some embodiments of the method, forming the first contact structure includes forming a first vertical groove penetrating from the first surface into the contact region to contact the first portion of the first layer, respectively. The method further includes depositing a dielectric layer in each of the first vertical grooves. The method includes penetrating (i.e., forming an opening by a process such as etching) the dielectric layer to form first lateral grooves connected to the first vertical grooves, respectively. Each of the first lateral grooves extends in a corresponding one of the first layers in the first portion of the first layer. In addition, the method includes filling the first vertical groove and the first lateral groove with a conductive material. Forming the second contact structure includes forming a second vertical groove penetrating from the second surface into the contact region to contact the remaining portion of the first layer except the first portion of the first layer, respectively. In addition, the method includes depositing a dielectric layer in each of the second vertical grooves. The method also includes penetrating the dielectric layer to form a second lateral groove connected to the second vertical groove, respectively, wherein each of the second lateral grooves extends in a corresponding one of the first layers in the remaining portion of the first layer. The method includes filling the second vertical groove and the second lateral groove with a conductive material.

[0070] In some embodiments, the method includes etching the first layer in the core region to produce a recess. The method further includes forming a second layer by filling the recess in the core region with a conductive material to contact the first contact structure and the second contact structure, respectively.

[0071] In some embodiments, the first layer is a sacrificial layer and the second layer is a conductive layer.

[0072] In some embodiments, the method includes electrically connecting a first peripheral circuit to the first contact structure, and electrically connecting a second peripheral circuit to the second contact structure.

[0073] In some embodiments, the method includes removing the substrate of the stacked structure after electrically connecting the first peripheral circuit to the first contact structure.

[0074] In some embodiments, after removing the substrate, the method includes forming a protection layer outside the second surface before forming the second contact structure.

[0075] On the other hand, the present disclosure describes a memory device, including a stacked structure having a plurality of first layers and a plurality of dielectric layers alternating. The stacked structure has a first surface and a second surface opposite to the first surface. The memory device includes a plurality of first contact structures having a conductive material. The plurality of first contact structures penetrate into the stacked structure from the first surface to contact with the first portions of the plurality of first layers, respectively. The memory device also includes a plurality of second contact structures having a conductive material, wherein each of the plurality of second contact structures penetrates into the stacked structure from the second surface to contact with the remaining portions of the plurality of conductive layers, respectively, except for the first portions of the plurality of first layers.

[0076] In some embodiments, the stack structure has a core region and a contact region adjacent to the core region, a first layer in the core region is a conductive layer, and a first layer in the contact region is a sacrificial layer.

[0077] In some embodiments, each of the first contact structure and the second contact structure has a vertical contact and a lateral contact connected to the vertical contact.

[0078] In some embodiments, each vertical contact of the first contact structure penetrates from the first surface into the contact region to connect with the corresponding lateral contact. Each vertical contact of the second contact structure penetrates from the second surface into the contact region to connect with the corresponding lateral contact.

[0079] In some embodiments, the vertical contact of each of the first contact structure and the second contact structure is at least partially surrounded by a dielectric layer.

[0080] In some embodiments, the lateral contact of each of the first and second contact structures extends in a respective one of the sacrificial layers in the contact region and is electrically connected to a respective one of the conductive layers in the core region.

[0081] In some embodiments, a vertical contact connected to a lateral contact at a greater depth from a first surface or a second surface has a larger cross-sectional area at the respective first surface or second surface.

[0082] In some embodiments, a cross-sectional area of ​​a vertical contact of a first contact structure at the first surface at least partially overlaps a cross-sectional area of ​​a corresponding vertical contact of a second contact structure at the second surface.

[0083] In some implementations, a memory device has a first peripheral circuit electrically connected to a first contact structure and a second peripheral circuit electrically connected to a second contact structure.

[0084] In some implementations, the first peripheral circuit and the second peripheral circuit are located on opposite sides of the stack structure.

[0085] In some implementations, a memory device includes a first substrate bonded to a first surface and a second substrate bonded to a second surface, and wherein the first substrate and the second substrate include silicon.

[0086] In another aspect, the present disclosure also describes a system including a memory device configured to store data. The memory device includes a stacked structure having a plurality of first layers and a plurality of dielectric layers alternating. The stacked structure has a first surface and a second surface opposite to the first surface. The memory device includes a plurality of first contact structures having a conductive material. Each of the plurality of first contact structures penetrates into the stacked structure from the first surface to contact with a first portion of the plurality of first layers, respectively. A plurality of second contact structures of the memory device have a conductive material. Each of the plurality of second contact structures penetrates into the stacked structure from the second surface to contact with the remaining portions of the plurality of conductive layers, respectively, except for the first portions of the plurality of first layers. A memory controller is electrically connected to the memory device and controls the memory device.

[0087] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of the claimed protection defined by the claims themselves, but rather as descriptions of features that may be specific to a particular implementation of a particular disclosure. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as functioning in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and claims may be directed to sub-combinations or variations of sub-combinations.

[0088] Similarly, although operations are shown in the drawings and described in a particular order in the claims, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0089] Specific implementations of the subject matter have been described. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In some cases, multitasking and parallel processing of the disclosed operations may be advantageous.

[0090] Therefore, the foregoing description of specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments. The breadth and scope of the present disclosure should not be limited by any of the above examples of the disclosed embodiments, but should only be limited according to the attached claims and their equivalents. Other embodiments are also within the scope of the attached claims.

Claims

1. A method of forming a memory device, comprising: Providing a stacked structure, the stacked structure comprising a plurality of first layers and a plurality of dielectric layers alternatingly, wherein the stacked structure has a first surface and a second surface opposite to the first surface; forming a plurality of first contact structures penetrating from the first surface into the stack structure to respectively contact the first portions of the plurality of first layers; and A plurality of second contact structures are formed penetrating from the second surface into the stack structure to respectively contact remaining portions of the plurality of first layers excluding the first portions of the plurality of first layers.

2. The method according to claim 1, wherein: The stack structure includes a core region and a contact region adjacent to the core region, and wherein the first contact structure and the second contact structure are in the contact region.

3. The method according to claim 2, wherein: Forming the first contact structure includes: forming first vertical grooves penetrating from the first surface into the contact areas to respectively contact the first portions of the first layer; depositing a dielectric layer in each of the first vertical grooves; penetrating the dielectric layer to form first lateral grooves connected to the first vertical grooves, respectively, wherein each of the first lateral grooves extends in a corresponding one of the first layers in the first portion of the first layer; and filling the first vertical groove and the first lateral groove with a conductive material; and Wherein, forming the second contact structure comprises: forming second vertical grooves penetrating from the second surface into the contact region to respectively contact remaining portions of the first layer except the first portion of the first layer; depositing a dielectric layer in each of the second vertical grooves; penetrating the dielectric layer to form second lateral grooves connected to the second vertical grooves, respectively, wherein each of the second lateral grooves extends in a corresponding one of the remaining portions of the first layer; and The second vertical recess and the second lateral recess are filled with the conductive material.

4. The method according to any one of claims 2 or 3, further comprising: etching the first layer in the core region to produce a recess; as well as A second layer is formed by filling the recesses in the core region with a conductive material to contact the first contact structure and the second contact structure, respectively.

5. The method according to claim 4, wherein: The first layer is a sacrificial layer, and the second layer is a conductive layer.

6. The method according to any one of claims 1 to 5, further comprising: A first peripheral circuit is electrically connected to the first contact structure, and a second peripheral circuit is electrically connected to the second contact structure.

7. The method according to claim 6, further comprising: The substrate of the stacked structure is removed after electrically connecting the first peripheral circuit to the first contact structure.

8. The method according to claim 7, further comprising: After removing the substrate, a protection layer is formed outside the second surface before forming the second contact structure.

9. A memory device comprising: A stack structure comprising a plurality of first layers and a plurality of dielectric layers alternatingly, wherein the stack structure has a first surface and a second surface opposite to the first surface; a plurality of first contact structures including a conductive material, wherein the plurality of first contact structures penetrate from the first surface into the stack structure to respectively contact with first portions of the plurality of first layers; and A plurality of second contact structures including conductive materials, wherein each of the plurality of second contact structures penetrates into the stack structure from the second surface to respectively contact remaining portions of the plurality of conductive layers except the first portions of the plurality of first layers.

10. The memory device according to claim 9, wherein: The stack structure includes a core region and a contact region adjacent to the core region, wherein the first layer in the core region is a conductive layer, and wherein the first layer in the contact region is a sacrificial layer.

11. The memory device according to any one of claims 9 and 10, wherein: Each of the first contact structure and the second contact structure includes a vertical contact and a lateral contact connected to the vertical contact.

12. The memory device according to claim 11, wherein: The vertical contact of each first contact structure in the first contact structure penetrates from the first surface into the contact area to connect with the corresponding lateral contact, and wherein the vertical contact of each second contact structure in the second contact structure penetrates from the second surface into the contact area to connect with the corresponding lateral contact.

13. The memory device according to any one of claims 11 and 12, wherein: The vertical contact of each of the first contact structure and the second contact structure is at least partially surrounded by a dielectric layer.

14. The memory device according to any one of claims 11 to 13, wherein: The lateral contact of each of the first and second contact structures extends in a respective one of the sacrificial layers in the contact region and is electrically connected to a respective one of the conductive layers in the core region.

15. The memory device according to any one of claims 11 to 14, wherein: A vertical contact connected to a lateral contact at a greater depth from the first surface or the second surface has a larger cross-sectional area at the respective first surface or the second surface.

16. The memory device according to any one of claims 11 to 15, wherein: A cross-sectional area of ​​a vertical contact of a first contact structure at the first surface at least partially overlaps a cross-sectional area of ​​a corresponding vertical contact of a second contact structure at the second surface.

17. The memory device according to any one of claims 9 to 16, wherein: The memory device also includes a first peripheral circuit electrically connected to the first contact structure and a second peripheral circuit electrically connected to the second contact structure.

18. The memory device of claim 17, wherein: The first peripheral circuit and the second peripheral circuit are located on opposite sides of the stack structure.

19. The memory device according to any one of claims 9 to 18, wherein: The memory device also includes a first substrate bonded to the first surface and a second substrate bonded to the second surface, and wherein the first substrate and the second substrate include silicon.

20. A system comprising: A memory device configured to store data, the memory device comprising: A stack structure comprising a plurality of first layers and a plurality of dielectric layers alternatingly, wherein the stack structure has a first surface and a second surface opposite to the first surface; a plurality of first contact structures including a conductive material, wherein each of the plurality of first contact structures penetrates into the stacked structure from the first surface to contact first portions of the plurality of first layers, respectively; and a plurality of second contact structures including a conductive material, wherein each of the plurality of second contact structures penetrates from the second surface into the stack structure to respectively contact remaining portions of the plurality of conductive layers excluding first portions of the plurality of first layers; and A memory controller is electrically connected to the memory device and controls the memory device.

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