Insulated gate bipolar transistor

Abstract

An IE effect is obtained and latch-up is suppressed in an IGBT. An insulated gate bipolar transistor has a first active region (31), a second active region (32), and a non-active region (34) disposed between the first active region and the second active region and in which a plurality of dummy trenches are disposed. In a hole accumulation region (36), which is a region between a first boundary gate trench (14gx1) and a second boundary gate trench (14gx2), inter-trench regions are disposed so as to satisfy the following conditions: a plurality of non-contact inter-trench regions are disposed in a non-active region; at least one inter-contact trench region is arranged in the non-active region; the non-contact inter-trench regions are not adjacent to each other in the hole accumulation region.

Description

Technical Field

[0001] (Cross-reference of related applications)

[0002] This application is a related application of Japanese patent application No. 2022-125751 filed on August 5, 2022, and claims the priority based on the Japanese patent application. All the contents described in the Japanese patent application are incorporated herein by reference as the contents constituting the present specification.

[0003] The technology disclosed in this specification relates to an insulated gate bipolar transistor. Background Art

[0004] In the international publication No. WO2017 / 033315, an insulated gate transistor (hereinafter referred to as IGBT: insulated gate bipolar transistor) is disclosed. In the IGBT, a plurality of grooves are provided on the surface of a semiconductor substrate. A gate electrode and a dummy electrode are provided in each groove. The gate electrode has a potential independent of the emitter electrode. The dummy electrode has a potential independent of the gate electrode. In an area where a gate electrode is provided (hereinafter referred to as an active area), a channel is formed in a base layer when a prescribed potential is applied to the gate electrode. Thus, the active area functions as an IGBT. In an area where a dummy electrode is provided (hereinafter referred to as an inactive area), a channel is not formed in the base layer. Thus, the inactive area does not function as an IGBT. In the inactive area, the base layer is not connected to the emitter electrode.

[0005] When the IGBT is turned on, holes flow from the collector layer into the drift layer. The holes flowing into the drift layer flow to the emitter electrode via the base layer. In the non-active region, since the base layer is not connected to the emitter electrode, the holes do not flow to the emitter electrode in the non-active region. Therefore, in this IGBT, holes are easily accumulated in the drift layer. Therefore, due to the so-called IE (injection enhanced) effect, the resistance of the drift layer is reduced. Therefore, the on-voltage of this IGBT is low. Summary of the invention

[0006] When the IGBT is turned on, the holes accumulated in the drift layer flow to the emitter electrode via the base layer when the IGBT is turned off. As mentioned above, in the IGBT of International Publication No. WO2017 / 033315, the base layer in the non-active region is not connected to the emitter electrode. Therefore, when the IGBT is turned off, the holes in the drift layer in the non-active region flow to the emitter electrode via the base layer adjacent to the non-active region in the active region (i.e., the base layer at the boundary). Therefore, the hole current is concentrated in the base layer at the boundary, and latch-up is likely to occur. In this specification, an IGBT that can obtain the IE effect and is not prone to latch-up is proposed.

[0007] The insulated gate bipolar transistor disclosed in this specification comprises: a semiconductor substrate having a plurality of trenches arranged at intervals on the upper surface; an emitter electrode arranged on the upper surface of the semiconductor substrate; a collector electrode arranged on the lower surface of the semiconductor substrate; a gate insulating film covering the inner surface of each of the trenches; and a trench electrode arranged in each of the trenches and insulated from the semiconductor substrate by the gate insulating film. The plurality of trenches comprises gate trenches and dummy trenches. The trench electrode in the gate trench is a gate electrode having an independent potential from the emitter electrode. The trench electrode in the dummy trench is a dummy electrode having an independent potential from the gate electrode. The semiconductor substrate comprises: a first active region having a plurality of the gate trenches; a second active region having a plurality of the gate trenches; and an inactive region arranged between the first active region and the second active region and having a plurality of the dummy trenches. The semiconductor substrate comprises a collector layer, a drift layer, a base layer and a plurality of emitter layers. The collector layer is distributed across the first active region, the second active region, and the inactive region, and is a p-type layer in contact with the collector electrode. The drift layer is distributed across the first active region, the second active region, and the inactive region, and is an n-type layer disposed on the upper portion of the collector layer. The base layer is distributed across the first active region, the second active region, and the inactive region, and is a p-type layer disposed on the upper portion of the drift layer and disposed in the inter-trench region between the respective trenches. The plurality of emitter layers are disposed in the plurality of inter-trench regions in the first active region and the second active region, and are n-type layers in contact with the gate insulating film and the emitter electrode and separated from the drift layer by the base layer. In each of the inter-trench regions in the first active region and the second active region, the base layer is in contact with the emitter electrode. In the hole accumulation region, the inter-trench region is arranged in a manner satisfying the following conditions in a region between a first boundary gate trench closest to the inactive region among the gate trenches in the first active region and a second boundary gate trench closest to the inactive region among the gate trenches in the second active region, i.e., a region where:

[0008] a plurality of non-contact inter-trench regions are arranged in the inactive region, the non-contact inter-trench regions being the inter-trench regions where the base layer is insulated from the emitter electrode;

[0009] At least one contact inter-trench region is arranged in the inactive region, the contact inter-trench region being the inter-trench region where the base layer and the emitter electrode are in contact;

[0010] In the hole accumulation region, the non-contact inter-groove regions are not adjacent to each other.

[0011] In addition, the above-mentioned "non-contact inter-groove regions are adjacent to each other" means that a plurality of contact inter-groove regions are adjacent to each other with the grooves between them. In other words, the above-mentioned "in the above-mentioned hole accumulation region, the above-mentioned non-contact inter-groove regions are not adjacent to each other" means that there are no portions in the hole accumulation region where a plurality of contact inter-groove regions are adjacent to each other with the grooves between them.

[0012] When the IGBT is turned on, the non-contact inter-groove region arranged in the non-active region suppresses the flow of holes in the drift layer to the emitter electrode. Therefore, due to the IE effect, the resistance of the drift layer is reduced. In addition, in the non-active region, at least one contact inter-groove region is arranged in a manner that the non-contact inter-groove regions are not adjacent to each other. Therefore, when the IGBT is turned off, the holes accumulated in the drift layer flow to the emitter electrode through the base layer of the contact inter-groove region in the non-active region. Therefore, the concentration of hole current in the base layer of the contact inter-groove region around the non-contact inter-groove region is suppressed. Therefore, latch-up is suppressed. As described above, the IGBT can obtain the IE effect and is not prone to latch-up. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a cross-sectional view of the IGBT of the embodiment.

[0014] Figure 2 It is a cross-sectional view of an IGBT of a comparative example.

[0015] Figure 3 It is a graph showing the hole current density distribution of the IGBT of the embodiment.

[0016] Figure 4 It is a graph showing the hole current density distribution of the IGBT of the comparative example.

[0017] Figure 5 is a graph showing the peak hole current density according to the number n of contact inter-trench regions.

[0018] Figure 6 It is a cross-sectional view of an IGBT according to a first modification.

[0019] Figure 7 It is a cross-sectional view of an IGBT according to a second modification.

[0020] Figure 8 It is a cross-sectional view of an IGBT according to a third modified example.

[0021] Fig. 9 It is a cross-sectional view of an IGBT according to a fourth modification. DETAILED DESCRIPTION

[0022] Alternatively, in the above-mentioned IGBT, when the dummy trench next to the first boundary gate trench is set as the first boundary dummy trench, the inter-trench region between the first boundary gate trench and the first boundary dummy trench is the contact inter-trench region, and the inter-trench region between the first boundary dummy trench and the dummy trench next to it is the contact inter-trench region. Furthermore, when the dummy trench next to the second boundary gate trench is set as the second boundary dummy trench, the inter-trench region between the second boundary gate trench and the second boundary dummy trench is the contact inter-trench region, and the inter-trench region between the second boundary dummy trench and the dummy trench next to it is the contact inter-trench region.

[0023] In the inter-groove region between the gate trench and the dummy trench, the hole current density tends to become high. In contrast, as described above, by setting the inter-groove region between the first boundary dummy trench and the dummy trench next to it and the inter-groove region between the second boundary dummy trench and the dummy trench next to it as the contact inter-groove region, the concentration of hole current in the inter-groove region between the gate trench and the dummy trench can be suppressed.

[0024] Alternatively, in the above-mentioned IGBT, the above-mentioned semiconductor substrate has a barrier layer and a lower base layer. Alternatively, the above-mentioned barrier layer is an n-type layer, distributed across the above-mentioned first active region, the above-mentioned second active region and the above-mentioned inactive region, arranged at the bottom of the above-mentioned base layer, and arranged in each of the above-mentioned inter-trench regions. Alternatively, the above-mentioned lower base layer is a p-type layer, distributed across the above-mentioned first active region, the above-mentioned second active region and the above-mentioned inactive region, arranged between the above-mentioned barrier layer and the above-mentioned drift layer, and arranged in each of the above-mentioned inter-trench regions.

[0025] In the above-mentioned IGBT, the semiconductor substrate may include a plurality of n-type pillar layers extending from a position in contact with the emitter electrode to the barrier layer and making Schottky contact with the emitter electrode.

[0026] In the above-mentioned IGBT, the semiconductor substrate may include an n-type cathode layer in contact with the collector electrode at a position adjacent to the collector layer.

[0027] Example

[0028] Figure 1 The IGBT of the embodiment shown has a semiconductor substrate 12. In the present embodiment, the semiconductor substrate 12 is made of a single crystal of silicon. However, the semiconductor substrate 12 may also be made of other semiconductor materials (e.g., SiC, GaN, etc.). A plurality of grooves 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each groove 14 is formed along the y direction (relative to the upper surface 12a). Figure 1 The trenches 14 extend in a straight line (in a direction perpendicular to the paper surface). That is, the trenches 14 extend parallel to each other. The plurality of trenches 14 are arranged at intervals in the x direction perpendicular to the y direction on the upper surface 12a. Hereinafter, each semiconductor region located between a pair of trenches 14 is referred to as an inter-trench region 16.

[0029] The inner surface of each trench 14 is covered with a gate insulating film 18. A trench electrode 20 is disposed in each trench 14. Each trench electrode 20 is insulated from the semiconductor substrate 12 by the gate insulating film 18.

[0030] An interlayer insulating film 22 and an emitter electrode 24 are provided on the upper portion of the semiconductor substrate 12. The interlayer insulating film 22 covers the upper surface of each trench electrode 20. The emitter electrode 24 covers the upper surface 12a of the semiconductor substrate 12 and the interlayer insulating film 22. A collector electrode 26 is provided on the lower portion of the semiconductor substrate 12. The collector electrode 26 covers the lower surface 12b of the semiconductor substrate 12.

[0031] The plurality of trench electrodes 20 include a gate electrode 20g and a dummy electrode 20d. The gate electrode 20g is insulated from the emitter electrode 24. Therefore, the potential of the gate electrode 20g is independent from the potential of the emitter electrode 24. The gate electrode 20g is connected to a gate pad at a position not shown in the figure. The dummy electrode 20d is insulated from the gate electrode 20g. Therefore, the potential of the dummy electrode 20d is independent from the potential of the gate electrode 20g. The dummy electrode 20d is electrically connected to the emitter electrode 24 at a position not shown in the figure (for example, the end of the dummy electrode 20d). Therefore, the dummy electrode 20d has the same potential as the emitter electrode 24 (i.e., 0V). Hereinafter, the trench 14 having the gate electrode 20g therein is referred to as a gate trench 14g. In addition, hereafter, the trench 14 having the dummy electrode 20d therein is referred to as a dummy trench 14d.

[0032] The semiconductor substrate 12 has a first active region 31, a second active region 32, and an inactive region 34. A plurality of gate trenches 14g are arranged in the first active region 31. A plurality of gate trenches 14g are arranged in the second active region 32. No dummy trenches 14d are arranged in the first active region 31 and the second active region 32. Therefore, each inter-trench region 16 in the first active region 31 and the second active region 32 is arranged between a pair of gate trenches 14g. The inactive region 34 is arranged between the first active region 31 and the second active region 32 in the x direction. A plurality of dummy trenches 14d are arranged in the inactive region 34. No gate trench 14g is arranged in the inactive region 34. Therefore, each inter-trench region 16 in the inactive region 34 is arranged between a pair of dummy trenches 14d. Each inter-trench region 16 at the boundary portion of each active region 31, 32 and the inactive region 34 is arranged between the gate trench 14g and the dummy trench 14d. Hereinafter, the gate trench 14g arranged at the position closest to the inactive region 34 among the gate trenches 14g in the first active region 31 is referred to as the first boundary gate trench 14gx1. In addition, the gate trench 14g arranged at the position closest to the inactive region 34 among the gate trenches 14g in the second active region 32 is referred to as the second boundary gate trench 14gx2. In addition, the region between the first boundary gate trench 14gx1 and the second boundary gate trench 14gx2 is referred to as the hole accumulation region 36. The inactive region 34 is included in the hole accumulation region 36. In addition, the dummy trench 14d next to the first boundary gate trench 14gx1 is referred to as the first boundary dummy trench 14dx1. In addition, the dummy trench 14d next to the second boundary gate trench 14gx2 is referred to as a second boundary dummy trench 14dx2.

[0033] The semiconductor substrate 12 includes a collector layer 40 , a buffer layer 42 , a drift layer 44 , a base layer 46 , and a plurality of emitter layers 48 .

[0034] The collector layer 40 is a p-type layer and is distributed in a range including the lower surface 12b of the semiconductor substrate 12. The collector layer 40 is distributed across the first active region 31, the second active region 32, and the hole accumulation region 36. The collector layer 40 is in ohmic contact with the collector electrode 26 on the lower surface 12b.

[0035] The buffer layer 42 is an n-type layer, and is disposed on the upper portion of the collector layer 40. The buffer layer 42 is distributed over the first active region 31, the second active region 32, and the hole accumulation region 36. The buffer layer 42 is in contact with the collector layer 40 from the upper side.

[0036] The drift layer 44 is an n-type layer having a lower n-type impurity concentration than the buffer layer 42. The drift layer 44 is distributed across the first active region 31, the second active region 32, and the hole accumulation region 36. The drift layer 44 is disposed on the upper portion of the collector layer 40 and the buffer layer 42. The drift layer 44 is in contact with the buffer layer 42 from the upper side. The drift layer 44 is distributed from a position in contact with the buffer layer 42 to a position in contact with the lower end of each trench 14. The drift layer 44 is in contact with the gate insulating film 18 at the bottom and side surfaces of each trench 14. The upper end portion of the drift layer 44 is located in each inter-trench region 16.

[0037] The base layer 46 is a p-type layer and is disposed on the upper part of the drift layer 44. The base layer 46 is distributed across the first active region 31, the second active region 32, and the hole accumulation region 36. The base layer 46 is disposed in each inter-trench region 16. The base layer 46 is in contact with the drift layer 44 from the upper side. The base layer 46 is in contact with the gate insulating film 18 on the side of the trench 14 above the drift layer 44.

[0038] Each emitter layer 48 is an n-type layer and is arranged in the corresponding inter-trench region 16. Two emitter layers 48 are arranged in each inter-trench region 16. Each emitter layer 48 is in contact with the gate insulating film 18 at the upper end of each trench 14. Each emitter layer 48 is in contact with the gate insulating film 18 on the upper side of the base layer 46. Each emitter layer 48 is in contact with the base layer 46. Each emitter layer 48 is separated from the drift layer 44 by the base layer 46. Each emitter layer 48 is arranged in a range that partially includes the upper surface 12a. The base layer 46 is distributed in the region between the two emitter layers 48 in each inter-trench region 16.

[0039] The plurality of inter-trench regions 16 include non-contact inter-trench regions whose upper surfaces are covered by the interlayer insulating film 22 and contact inter-trench regions whose upper surfaces are not covered by the interlayer insulating film 22. In the non-contact inter-trench regions, the base layer 46 and the emitter layer 48 are insulated from the emitter electrode 24 by the interlayer insulating film 22. In the contact inter-trench regions, the base layer 46 and the emitter layer 48 are in ohmic contact with the emitter electrode 24.

[0040] All the inter-trench regions 16 in the first active region 31 and the second active region 32 are contact inter-trench regions. Inter-trench regions 16a to 16g exist in the hole accumulation region 36. The inter-trench region 16a between the first boundary gate trench 14gx1 and the first boundary dummy trench 14dx1 is a contact inter-trench region. In addition, the inter-trench region 16g between the second boundary gate trench 14gx2 and the second boundary dummy trench 14dx2 is a contact inter-trench region. The inter-trench regions 16b to 16f in the non-active region 34 include contact inter-trench regions and non-contact inter-trench regions. The inter-trench region 16b between the first boundary dummy trench 14dx1 and the dummy trench 14d next to it is a contact inter-trench region. The inter-trench region 16c next to the inter-trench region 16b is a non-contact inter-trench region. The inter-trench region 16d next to the inter-trench region 16c is a contact inter-trench region. The inter-groove region 16e next to the inter-groove region 16d is a non-contact inter-groove region. The inter-groove region 16f next to the inter-groove region 16e (i.e., the inter-groove region 16f between the second boundary dummy groove 14dx2 and the dummy groove 14d next to it) is a contact inter-groove region. In this way, the non-contact inter-groove regions and the contact inter-groove regions are alternately arranged in the non-active region 34. Therefore, in the hole accumulation region 36, the non-contact inter-groove regions are not adjacent to each other.

[0041] Next, the operation of the IGBT 10 will be described. When the IGBT 10 is in operation, a higher potential than that of the emitter electrode 24 is applied to the collector electrode 26. In addition, the potential of the gate electrode 20g is controlled by a gate control circuit outside the IGBT 10. The potential of the gate electrode 20g is controlled between 0V (i.e., the same potential as the emitter electrode 24) and a higher potential. If the potential of the gate electrode 20g is controlled to be a potential higher than the gate threshold, a channel is formed in the range of the base layer 46 that is opposite to the gate electrode 20g. Since the gate electrode 20g is arranged in the first active region 31 and the second active region 32, a channel is formed in the base layer 46 in the first active region 31 and the second active region 32. The emitter layer 48 is connected to the drift layer 44 through the channel. Since the dummy electrode 20d in the inactive region 34 is electrically connected to the emitter electrode 24, the potential of the dummy electrode 20d is maintained at the potential of the emitter electrode 24. Therefore, no channel is formed in the inactive region 34. If a channel is formed in the first active region 31 and the second active region 32, electrons flow from the emitter layer 48 in the first active region 31 and the second active region 32 into the drift layer 44 through the channel. Then, holes flow from the collector layer 40 into the drift layer 44 through the buffer layer 42. As a result, the resistance of the drift layer 44 decreases, and electrons flow in the drift layer 44 with low loss. The electrons in the drift layer 44 flow to the collector layer via the buffer layer 42. By such electron flow, the IGBT is turned on. In addition, the holes that flow into the drift layer 44 flow to the emitter electrode 24 via the base layer 46. However, since the inter-groove regions 16c and 16e are non-contact inter-groove regions, holes do not flow from the base layer 46 to the emitter electrode 24 in the inter-groove regions 16c and 16e. Therefore, in the inactive region 34, holes are difficult to flow toward the emitter electrode 24, and holes are easily accumulated in the drift layer 44. Thus, by providing the non-contact inter-trench region in the inactive region 34, holes are easily accumulated in the drift layer 44, and the resistance of the drift layer 44 can be reduced by the IE effect. Therefore, the on-voltage of the IGBT is low.

[0042] Then, if the potential of the gate electrode 20g is lowered to 0V, the channel disappears. Then, the flow of electrons stops, and the IGBT 10 is turned off. When the IGBT 10 is turned off, the holes existing in the drift layer 44 are discharged to the emitter electrode 24 via the base layer 46. If the hole current flowing at this time is concentrated in a specific inter-trench region 16, latch-up occurs.

[0043] For example, Figure 2As a comparative example, the case where the inter-trench regions 16c to 16e are non-contact inter-trench regions is shown. In this case, the holes accumulated in the drift layer 44 below the inter-trench regions 16c to 16e flow toward the contact inter-trench regions closest to the inter-trench regions 16c to 16e, i.e., the inter-trench regions 16b and 16f, as shown by arrows 102. That is, the hole current is concentrated in the inter-trench regions 16b and 16f. As a result, the potential of the base layer 46 in the inter-trench regions 16b and 16f rises, so that the holes in the inter-trench regions 16b and 16f easily flow from the base layer 46 to the emitter layer 48. When the holes flow from the base layer 46 to the emitter layer 48, latch-up occurs and a high current flows in the IGBT 10, and a high load acts on the IGBT 10.

[0044] In contrast, Figure 1 In the IGBT 10 of the embodiment, in the hole accumulation region 36 including the non-active region 34, a plurality of non-contact inter-groove regions are arranged non-adjacently. Therefore, holes accumulated in the drift layer 44 in the non-active region 34 can flow to the emitter electrode 24 via the contact inter-groove regions (i.e., inter-groove regions 16b, 16d, 16f) adjacent to the non-contact inter-groove regions (i.e., inter-groove regions 16c, 16e) as indicated by arrows 100. Thus, in the IGBT 10 of the embodiment, the hole current flows dispersedly when turned off. Therefore, it is possible to suppress the hole current from concentrating on a specific inter-groove region 16, and it is possible to suppress latch-up.

[0045] Figure 3 Indicated in Figure 1 The density distribution of the hole current flowing when the IGBT10 of the embodiment shown is turned off. Figure 4 Indicated in Figure 2 The density distribution of hole current flowing when the IGBT of the comparative example shown in FIG. Figure 3 , Figure 4 By comparison, it can be seen that in the IGBT 10 of the embodiment, the hole current flows through the inter-trench region 16 d , so that the hole current density in the inter-trench regions 16 b and 16 f can be reduced. Thus, the peak value of the hole current can be reduced.

[0046] In addition, if Figure 3As shown, in the inter-trench regions 16a and 16g, the hole current density becomes higher than that in other inter-trench regions 16. The inter-trench regions 16a and 16g are located between the gate electrode 20g and the dummy electrode 20d. The dummy electrode 20d is fixed to the potential of the emitter electrode 24. On the other hand, at the time of shutdown, the potential of the gate electrode 20g has a potential close to the gate threshold. Therefore, at the time of shutdown, the potential of the dummy electrode 20d is lower than the potential of the gate electrode 20g. Therefore, in the inter-trench regions 16a and 16g, the hole current biasedly flows to the area closer to the dummy electrode 20d, and the density of the hole current tends to become higher. Therefore, if the holes accumulated in the drift layer 44 in the inactive region 34 flow into the inter-trench regions 16a and 16g, the hole current density of the inter-trench regions 16a and 16g becomes very high. In contrast, Figure 1 As shown, in the IGBT of the embodiment, the inter-trench regions 16b and 16f adjacent to the inter-trench regions 16a and 16g on the non-active region 34 side become contact inter-trench regions. Therefore, most of the holes accumulated in the drift layer 44 in the non-active region 34 flow into the inter-trench regions 16b and 16f, and the hole current is suppressed from concentrating in the inter-trench regions 16a and 16g. As a result, latch-up in the inter-trench regions 16a and 16g is suppressed.

[0047] Figure 5 2 shows the results of simulation of the peak value of the hole current density when the number n of contact inter-trench regions in the inter-trench regions 16 b to 16 f is changed. Figure 5 In the example, n=0 indicates that all the inter-groove regions 16b to 16f are non-contact inter-groove regions. n=2 indicates Figure 2 n=3 means Figure 1 n = 4 means that the inter-groove regions 16b, 16c, 16e, and 16f are contact inter-groove regions, and the inter-groove region 16d is a non-contact inter-groove region. n = 5 means that all the inter-groove regions 16b to 16f are contact inter-groove regions. Figure 5 As shown, in the case of n=3, the peak value of the hole current density is lowered to the same extent as in the case of n=5. In addition, in the case of n=2, the peak value of the hole current density is higher than in the case of n=3.

[0048] As described above, according to the IGBT 10 of the embodiment, a low on-voltage can be achieved by the IE effect, and latch-up can be suppressed.

[0049] In addition, in the above-mentioned embodiment, five inter-trench regions 16 are arranged in the non-active region 34, but the number of inter-trench regions 16 in the non-active region 34 may be more or less than 5. In addition, in the above-mentioned embodiment, the inter-trench regions 16a and 16g between the gate trench 14g and the dummy trench 14d are contact inter-trench regions. However, the inter-trench regions 16a and 16g between the gate trench 14g and the dummy trench 14d may be non-contact inter-trench regions. In this case, latch-up can be suppressed by making the non-contact inter-trench regions non-adjacent in the hole accumulation region 36.

[0050] Furthermore, in the above-described embodiment, the emitter layer 48 is provided in the inactive region 34 , but the emitter layer 48 may not be provided in the inactive region 34 .

[0051] In the above-described embodiment, the dummy electrode 20d is electrically connected to the emitter electrode 24. However, as long as the potential of the dummy electrode 20d is independent of the potential of the gate electrode 20g, the dummy electrode 20d may be electrically connected to the emitter electrode 24. Fig. 9 As shown, the dummy electrode 20d is electrically connected to a pad other than the emitter electrode 24.

[0052] In addition, you can Figure 6 As shown, an n-type barrier layer 50 is provided in the base layer 46, and the base layer 46 is divided into an upper base layer 46a and a lower base layer 46b by the barrier layer 50. The upper base layer 46a is distributed across the first active region 31, the second active region 32, and the hole accumulation region 36. The upper base layer 46a is arranged in each inter-trench region 16. The barrier layer 50 is distributed across the first active region 31, the second active region 32, and the hole accumulation region 36. The barrier layer 50 is arranged at the lower part of the upper base layer 46a. The barrier layer 50 is arranged in each inter-trench region 16. The lower base layer 46b is distributed across the first active region 31, the second active region 32, and the hole accumulation region 36. The lower base layer 46b is arranged between the barrier layer 50 and the drift layer 44. The lower base layer 46b is disposed in each inter-trench region 16. In this structure, when the IGBT is turned on, holes in the drift layer 44 flow toward the emitter electrode 24 via the lower base layer 46b, the barrier layer 50, and the upper base layer 46a. In this structure, since the flow of holes is suppressed by the barrier layer 50, holes are more easily accumulated in the drift layer 44. Therefore, according to this structure, the on-voltage of the IGBT can be further reduced.

[0053] In addition, when the barrier layer 50 is provided, Figure 7As shown, multiple n-type column layers 52 may also be provided. Each column layer 52 is arranged in the corresponding inter-groove region 16. Each column layer 52 extends from a position in contact with the emitter electrode 24 to the barrier layer 50. Each column layer 52 makes Schottky contact with the emitter electrode 24. According to this structure, the on-voltage of the IGBT can be more effectively reduced.

[0054] In addition, if Figure 8 As shown, an n-type cathode layer 60 may also be provided in the semiconductor substrate 12. The cathode layer 60 is disposed at the lower portion of the buffer layer 42. The n-type impurity concentration of the cathode layer 60 is higher than the n-type impurity concentration of the buffer layer 42. The cathode layer 60 is in ohmic contact with the collector electrode 26 at a position adjacent to the collector layer 40. According to this structure, a pn diode is formed between the emitter electrode 24 and the collector electrode 26 by the base layer 46, the drift layer 44, the buffer layer 42, and the cathode layer 60. The pn diode can function as a so-called freewheeling diode, and is turned on when a higher potential than the collector electrode 26 is applied to the emitter electrode 24.

[0055] The above detailed description of the implementation methods is provided, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various forms of deformation and modification of the specific examples illustrated above. The technical elements described in this specification or the drawings exert technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or the drawings achieves multiple purposes at the same time, and achieving one of the purposes itself has technical usefulness.

Claims

1. An insulated gate bipolar transistor, characterized in that: have: A semiconductor substrate (12) having a plurality of grooves (14) arranged at intervals on its upper surface; An emitter electrode (24) is provided on the upper surface of the semiconductor substrate; A collector electrode (26) is provided on the lower surface of the semiconductor substrate; A gate insulating film (18) covers the inner surface of each of the above-mentioned grooves; as well as A trench electrode (20) is disposed in each of the trenches and insulated from the semiconductor substrate by the gate insulating film; The plurality of trenches include gate trenches (14g) and dummy trenches (14d); The trench electrode in the gate trench is a gate electrode (20g) having a potential independent of the emitter electrode; The trench electrode in the dummy trench is a dummy electrode (20d) having a potential independent of the gate electrode; The semiconductor substrate has: The first active region (31) is provided with a plurality of the above-mentioned gate trenches; The second active region (32) is provided with a plurality of the gate trenches; and A non-active region (34) is arranged between the first active region and the second active region, and is provided with a plurality of the dummy trenches; The semiconductor substrate has: A p-type collector layer (40) is distributed across the first active region, the second active region and the inactive region and is in contact with the collector electrode; An n-type drift layer (44) is distributed across the first active region, the second active region and the inactive region, and is disposed on the upper portion of the collector layer; A p-type base layer (46) is distributed across the first active region, the second active region and the inactive region, and is disposed on the upper portion of the drift layer and in an inter-trench region (16) between each of the trenches; and A plurality of n-type emitter layers (48) are arranged in the plurality of inter-trench regions in the first active region and the second active region, are in contact with the gate insulating film, are in contact with the emitter electrode, and are separated from the drift layer by the base layer; In each of the inter-trench regions in the first active region and the second active region, the base layer is in contact with the emitter electrode; The inter-trench region is arranged in a hole accumulation region (36) between a first boundary gate trench (14gx1) closest to the inactive region in the gate trench in the first active region and a second boundary gate trench (14gx2) closest to the inactive region in the gate trench in the second active region, in a manner satisfying the following conditions: a plurality of non-contact inter-trench regions are arranged in the inactive region, the non-contact inter-trench regions being the inter-trench regions where the base layer is insulated from the emitter electrode; At least one contact inter-trench region is arranged in the inactive region, the contact inter-trench region being the inter-trench region where the base layer and the emitter electrode are in contact; In the hole accumulation region, the non-contact inter-groove regions are not adjacent to each other.

2. The insulated gate bipolar transistor according to claim 1, wherein: When the dummy trench next to the first boundary gate trench is defined as the first boundary dummy trench (14dx1), the inter-trench region between the first boundary gate trench and the first boundary dummy trench is the contact inter-trench region, and the inter-trench region between the first boundary dummy trench and the dummy trench next to it is the contact inter-trench region; When the above-mentioned dummy trench next to the above-mentioned second boundary gate trench is set as the second boundary dummy trench (14dx2), the above-mentioned inter-trench region between the above-mentioned second boundary gate trench and the above-mentioned second boundary dummy trench is the above-mentioned contact inter-trench region, and the above-mentioned inter-trench region between the above-mentioned second boundary dummy trench and the above-mentioned dummy trench next to it is the above-mentioned contact inter-trench region.

3. The insulated gate bipolar transistor according to claim 1 or 2, characterized in that: The semiconductor substrate has: An n-type barrier layer (50) is distributed across the first active region, the second active region and the inactive region, and is disposed at the bottom of the base layer and in each of the inter-trench regions; and The p-type lower base layer (46b) is distributed across the first active region, the second active region and the inactive region, and is disposed between the barrier layer and the drift layer and in each of the inter-trench regions.

4. The insulated gate bipolar transistor according to claim 3, wherein: The semiconductor substrate has a plurality of n-type pillar layers (52) extending from a position in contact with the emitter electrode to the barrier layer and making Schottky contact with the emitter electrode.

5. The insulated gate bipolar transistor according to claim 1 or 2, wherein: The semiconductor substrate includes an n-type cathode layer (60) in contact with the collector electrode at a position adjacent to the collector layer.

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