Low-dropout linear voltage regulator, chip and electronic device

Abstract

The application discloses a low-dropout linear voltage stabilizing circuit, a chip and electronic equipment, and belongs to the field of semiconductor integrated circuits. The circuit comprises a voltage detection module, a first adjusting module and a second adjusting module. The voltage detection module is connected with a target output end of the circuit, and is used for outputting a first control voltage according to an output voltage of the target output end; the first adjusting module is connected with the voltage detection module and the target output end respectively, and is used for providing a first current to the target output end according to the first control voltage; the second adjusting module is connected with the voltage detection module and the target output end respectively, and is used for providing a second current to the target output end according to the first control voltage; wherein the first current and the second current are both used for stabilizing the output voltage. In the case that the output voltage changes, the output voltage can be recovered faster through the first current and the second current, the transient response of the circuit is improved, and the circuit performance is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor integrated circuits, and in particular to a low-dropout linear voltage regulator, a chip and an electronic device. BACKGROUND

[0002] An LDO (Low Dropout Linear Regulator) is a kind of voltage regulator circuit, which can ensure stable output voltage within the range of load current variation, so as to supply power to other chips.

[0003] In related technologies, if the load current changes, the output voltage of the LDO will change accordingly. The LDO itself can adjust the output voltage to maintain the stability of the output voltage. The process of restoring the stability of the output voltage is called transient response, and how to improve the transient response of the LDO becomes a problem to be solved. SUMMARY

[0004] The present application provides a low-dropout linear voltage regulator, a chip and an electronic device, which can be used to solve the problems in related technologies. The technical solution includes the following contents.

[0005] In a first aspect, a low-dropout linear voltage regulator is provided, characterized in that the circuit comprises a voltage detection module, a first adjustment module and a second adjustment module.

[0006] The voltage detection module is connected to the target output terminal of the low-dropout linear voltage regulator, and is configured to output a first control voltage according to the output voltage of the target output terminal.

[0007] The first adjustment module is connected to the voltage detection module and the target output terminal respectively, and is configured to receive the first control voltage and provide a first current to the target output terminal according to the first control voltage.

[0008] The second adjustment module is connected to the voltage detection module and the target output terminal respectively, and is configured to receive the first control voltage and provide a second current to the target output terminal according to the first control voltage.

[0009] The first current and the second current are both used to stabilize the output voltage.

[0010] In a possible implementation, the first adjustment module comprises a first adjustment unit, a first current source and a first transistor.

[0011] The first adjustment unit is connected to the voltage detection module and the gate of the first transistor respectively, and is configured to receive the first control voltage and provide a first target current to the gate of the first transistor according to the first control voltage.

[0012] The first current source is connected with the gate of the first transistor, and is configured to provide a first reference current to the gate of the first transistor.

[0013] The source of the first transistor is connected with a first input terminal, and the drain of the first transistor is connected with the target output terminal, configured to provide the first current to the target output terminal according to a second control voltage, the first input terminal is configured to provide a supply voltage, and the second control voltage is determined according to the first target current and the first reference current.

[0014] In a possible implementation, the first adjusting unit includes a second transistor and a first mirror component.

[0015] The source of the second transistor is connected with the first input terminal, the drain of the second transistor is connected with the first mirror component, and the gate of the second transistor is connected with the voltage detection module and configured to receive the first control voltage and provide a first source current to the first mirror component according to the first control voltage.

[0016] The first mirror component is connected with the gate of the first transistor, configured to receive the first source current and output the first target current to the gate of the first transistor, and the first target current is a mirror current of the first source current.

[0017] In a possible implementation, the first mirror component includes a third transistor and a fourth transistor.

[0018] The source of the third transistor is grounded, the drain of the third transistor is connected with the drain of the second transistor, and the gate of the third transistor is connected with the drain of the second transistor and the gate of the fourth transistor, configured to receive the first source current and provide a first gate current to the fourth transistor.

[0019] The source of the fourth transistor is grounded, and the drain of the fourth transistor is connected with the gate of the first transistor, configured to receive the first gate current and output the first target current to the gate of the first transistor.

[0020] In a possible implementation, the first adjusting module includes a second adjusting unit, a first comparator, a fifth transistor and a first resistor, one end of the first resistor is connected with the first input terminal.

[0021] The second adjusting unit is connected with the voltage detection module and the first comparator respectively, configured to receive the first control voltage and provide a first target voltage to the first comparator according to the first control voltage.

[0022] The first comparator is connected with the gate of the fifth transistor and a second input end, and is configured to receive a first reference voltage and the first target voltage, output a third control voltage to the gate of the fifth transistor according to the first reference voltage and the first target voltage, and the second input end is configured to provide the first reference voltage.

[0023] The source of the fifth transistor is connected with another end of the first resistor, the drain of the fifth transistor is connected with the target output end, and the fifth transistor is configured to provide the first current to the target output end according to the third control voltage, and the first input end is configured to provide a supply voltage.

[0024] In a possible implementation, the second adjusting unit comprises a sixth transistor and a second resistor, and the second resistor is connected with the ground and the drain of the sixth transistor.

[0025] The source of the sixth transistor is connected with the first input end, and the gate of the sixth transistor is connected with the voltage detection module and configured to receive the first control voltage and provide the first target voltage to the first comparator according to the first control voltage.

[0026] In a possible implementation, the circuit further comprises a third adjusting module.

[0027] The third adjusting module is connected with the voltage detection module, the target output end and a ground end respectively, and is configured to receive the first control voltage and output a third current according to the first control voltage.

[0028] The third current is a current from the target output end to the ground end, and the third current is configured to stabilize the output voltage.

[0029] In a possible implementation, the voltage detection module comprises a sampling module and an error amplifier.

[0030] The sampling module is connected with the target output end and the error amplifier respectively, and is configured to receive the output voltage and output the feedback voltage to the error amplifier according to the output voltage.

[0031] The error amplifier is connected with a third input end, and is configured to receive the feedback voltage and a second reference voltage, and output the first control voltage according to the feedback voltage and the second reference voltage, and the third input end is configured to provide the second reference voltage.

[0032] In a possible implementation, the second adjusting module comprises a target transistor.

[0033] The source of the target transistor is connected with the first input end, the drain of the target transistor is connected with the target output end, the gate of the target transistor is connected with the voltage detection module, and the first control voltage is received, and the second current is provided to the target output end according to the first control voltage, and the first input end is used for providing a power supply voltage.

[0034] In a second aspect, a chip is provided, and the chip comprises the low-dropout linear voltage regulator circuit in the first aspect and any possible implementation manner.

[0035] In a third aspect, an electronic device is provided, and the electronic device comprises the low-dropout linear voltage regulator circuit in the first aspect and any possible implementation manner.

[0036] The technical scheme provided in the application at least brings the following beneficial effects:

[0037] In the technical scheme provided in the application, the voltage detection module can determine the first control voltage according to the output voltage of the target output end, the first adjusting module can determine the first current provided to the target output end according to the first control voltage, and the second adjusting module can determine the second current provided to the target output end according to the first control voltage. Since the first current and the second current are both used to stabilize the output voltage, in the case that the output voltage changes, the output voltage can be recovered faster through the first current and the second current, the recovery speed of the output voltage is improved, the transient response of the circuit is improved, and the circuit performance is improved. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0039] Figure 1 is a schematic diagram of a low-dropout linear voltage regulator circuit provided by the related art;

[0040] Figure 2 is a waveform schematic diagram provided by the related art;

[0041] Figure 3 is a schematic diagram of a low-dropout linear voltage regulator circuit provided by the embodiments of the application;

[0042] Figure 4 is a schematic diagram of another low-dropout linear voltage regulator circuit provided by the embodiments of the application;

[0043] Figure 5is a schematic diagram of another low-dropout linear regulator circuit provided by an embodiment of the present application.

[0044] Figure 6 is a schematic diagram of another low-dropout linear regulator circuit provided by an embodiment of the present application.

[0045] Figure 7 is a schematic diagram of another low-dropout linear regulator circuit provided by an embodiment of the present application.

[0046] Figure 8 is a schematic diagram of another low-dropout linear regulator circuit provided by an embodiment of the present application.

[0047] Figure 9 is a waveform diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the drawings.

[0049] It should be noted that the terms "first", "second", and the like in the present application are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] In the field of semiconductor integrated circuits, LDO (Low Dropout Linear Regulator, low-dropout linear regulator) is a common voltage stabilizing circuit that can ensure stable output voltage within the range of load current variation to supply power to other chips.

[0051] As shown in Figure 1 , a schematic diagram of a low-dropout linear regulator circuit provided by the related art is shown. Figure 1 The low-dropout linear regulator circuit includes an error amplifier (EA), a transistor (also referred to as a power transistor) MP, a resistor R1, a resistor R2, and a capacitor COUT. The capacitor COUT is connected to the output end of the low-dropout linear regulator circuit. The output voltage VOUT of the output end is used to supply power to the load Rload.

[0052] In Figure 1In this example, transistor MP is a PMOS (P-channel Metal Oxide Semiconductor), which has the characteristic of conducting at low voltage levels. In practical applications, low-dropout linear regulator circuits can also be designed based on NMOS (N-channel Metal Oxide Semiconductor), which has the characteristic of conducting at high voltage levels. This will not be elaborated upon here. The following explanation uses a PMOS transistor as an example to illustrate the operating principle of a low-dropout linear regulator circuit.

[0053] like Figure 1 As shown, when transistor MP is a PMOS, the output terminal of error amplifier EA is connected to the gate of transistor MP. The source voltage of transistor MP is the supply voltage VIN. The drain of transistor MP is connected to the output terminal of the low-dropout linear regulator circuit and is used to provide the output voltage VOUT. One end of resistor R1 is connected to the drain of transistor MP, and the other end of resistor R1 is connected to one end of resistor R2. The other end of resistor R2 is grounded. Resistors R1 and R2 form a sampling module used to sample the output voltage VOUT and obtain the feedback voltage VFB. The positive input terminal (i.e., the non-inverting input terminal, or simply the positive terminal) of error amplifier EA is connected to the connection node between resistors R1 and R2 and is used to receive the feedback voltage VFB. The negative input terminal (i.e., the inverting input terminal, or simply the negative terminal) of error amplifier EA receives the reference voltage VREF. In addition, the voltage at the power supply terminal of error amplifier EA is the supply voltage VIN. One end of capacitor COUT is connected to resistor R1 and the drain of transistor MP, i.e., the voltage at this end is the output voltage VOUT. The other end of capacitor COUT is connected to the ground terminal GND. One end of the load Rload is connected to the resistor R1, the drain of the transistor MP, and the capacitor COUT, meaning that the voltage at this end is the output voltage VOUT. The other end of the load Rload is connected to the ground terminal GND.

[0054] When the low-dropout linear regulator circuit is in steady state, the load current of the load Rload remains unchanged. At this time, the capacitor COUT no longer charges or discharges, and the output voltage VOUT is stable. After sampling the output voltage VOUT through resistors R1 and R2, a feedback voltage VFB is obtained and input to the error amplifier EA. The error amplifier EA generates a control voltage Vgs based on the error between the feedback voltage VFB and the reference voltage VREF. The control voltage Vgs controls the conduction current of the transistor MP. Since the circuit is in steady state, the value of the control voltage Vgs remains unchanged, keeping the conduction current of the transistor MP constant, thus preventing any change in the output voltage VOUT. In this state, the low-dropout linear regulator circuit can provide a stable output voltage VOUT to power the load Rload.

[0055] Optionally, when the low-dropout linear regulator circuit is in steady state, since capacitor COUT no longer charges or discharges, the circuit mainly provides the load current to the load Rload through the conduction current of transistor MP. In this case, the feedback voltage VFB is equal to (or approximately equal to) the reference voltage VREF. At this time, the value of the control voltage Vgs remains unchanged, the conduction current of transistor MP remains unchanged, and thus the output voltage VOUT also remains unchanged. In this case, the output voltage VOUT satisfies: VOUT = (VREF / R2) × (R1 + R2). Since the reference voltage VREF, resistor R1, and resistor R2 all remain unchanged, the output voltage VOUT also remains unchanged.

[0056] In the field of semiconductor integrated circuits, a transient increase in the load current of a load Rload is often referred to as a change from a light load to a heavy load. Conversely, a transient decrease in the load current of a load Rload is referred to as a change from a heavy load to a light load.

[0057] When the load Rload changes from light to heavy, meaning the load current increases transiently, the low-dropout linear regulator circuit cannot respond quickly enough—that is, the transistor MP's on-state current cannot increase quickly enough. Therefore, capacitor COUT needs to discharge to provide the increased current from the load Rload. The discharge of capacitor COUT causes a sharp drop in the output voltage VOUT. Figure 2 As shown, Figure 2 Figure (1) shows the waveform of the output voltage VOUT. Figure 2 Figure (2) shows the waveform of the load current, where the negative sign "-" in "-80.0mA" indicates the direction of the load current, and the value "80.0mA" indicates the magnitude of the load current. Figure 2 It can be seen that when the load current increases from 0 to 80mA, the output voltage VOUT will drop sharply from 3.30658V to 3.30025V, a drop of about 6.33mV.

[0058] Understandably, the output voltage VOUT will decrease due to the load current. However, the low-dropout linear regulator has adjustment capabilities and can return to a steady state after a period of adjustment. As the name suggests, steady state refers to a stable condition; when the low-dropout linear regulator is in a steady state, the output voltage VOUT remains constant. In this example, the process of the low-dropout linear regulator transitioning from one steady state to another is called a transient state. When the low-dropout linear regulator is in a transient state, the output voltage VOUT will change.

[0059] When the low-dropout linear regulator is in transient state, due to the load Rload changing from light load to heavy load (i.e. the load current transiently increases), the capacitor COUT discharges, causing the output voltage VOUT to drop, causing the feedback voltage VFB to drop, causing the control voltage Vgs to drop, thereby causing the on-current of the transistor MP to increase. By continuously increasing the on-current of the transistor MP, the current compensation for the increase of the load Rload is achieved, and the capacitor COUT is charged, causing the output voltage VOUT to gradually increase, and eventually the low-dropout linear regulator returns to steady state, and the output voltage VOUT remains unchanged.

[0060] It should be noted that the load current is different, the working point of the low-dropout linear regulator is different, so that the output voltage VOUT in steady state is also different. Alternatively, for the case of load current transiently increasing, the output voltage of the circuit in steady state before the load current transiently increases is higher than the output voltage of the circuit in steady state after the load current transiently increases. As shown in (1) of Figure 2 , the output voltage VOUT of the circuit in steady state before the load current transiently increases is 3.30658V (volts), and the output voltage VOUT of the circuit in steady state after the load current transiently increases is 3.30468V, and the output voltage VOUT decreases.

[0061] For the case of the load Rload changing from heavy load to light load, i.e. the load current transiently decreases. Since the low-dropout linear regulator cannot respond in time, i.e. the on-current of the transistor MP cannot decrease in time, therefore the capacitor COUT needs to be charged to extract the current decreased by the load Rload. Charging the capacitor COUT will cause the output voltage VOUT to rise sharply. As shown in Figure 2 , when the load current decreases from 80mA to 0, the output voltage VOUT will rise sharply, with an increase of about 6.26mV.

[0062] When the low-dropout linear regulator is in transient state, due to the load Rload changing from heavy load to light load (i.e. the load current transiently decreases), the capacitor COUT charges, causing the output voltage VOUT to rise, causing the feedback voltage VFB to rise, causing the control voltage Vgs to increase, thereby causing the on-current of the transistor MP to decrease. By continuously decreasing the on-current of the transistor MP, a smaller current is provided to the load Rload, and the capacitor COUT is discharged, causing the output voltage VOUT to gradually decrease, and eventually the low-dropout linear regulator returns to steady state, and the output voltage VOUT remains unchanged.

[0063] Alternatively, for the case of load current transiently decreasing, the output voltage of the circuit in steady state before the load current transiently decreases is lower than the output voltage of the circuit in steady state after the load current transiently decreases. As shown in Figure 2As shown in (1) of FIG. 1, the output voltage VOUT of the circuit at the steady state before the load current transient reduction is 3.30468V, which is lower than the output voltage VOUT of the circuit at the steady state after the load current transient reduction.

[0064] The low-dropout linear regulator in the related art has poor transient response. As shown in (1) of FIG. 1, the output voltage VOUT of the circuit at the steady state before the load current transient reduction is 3.30468V, which is lower than the output voltage VOUT of the circuit at the steady state after the load current transient reduction. Figure 2 As shown in (1) of FIG. 1, the output voltage VOUT of the circuit at the steady state before the load current transient reduction is 3.30468V, which is lower than the output voltage VOUT of the circuit at the steady state after the load current transient reduction.

[0065] As shown in (1) of FIG. 1, the output voltage VOUT of the circuit at the steady state before the load current transient reduction is 3.30468V, which is lower than the output voltage VOUT of the circuit at the steady state after the load current transient reduction. Figure 3 As shown in (1) of FIG. 1, the output voltage VOUT of the circuit at the steady state before the load current transient reduction is 3.30468V, which is lower than the output voltage VOUT of the circuit at the steady state after the load current transient reduction. Figure 3 FIG. 1 is a schematic diagram of a low-dropout linear regulator provided by an embodiment of the present application. The low-dropout linear regulator includes a voltage detection module 10, a first regulating module 20 and a second regulating module 30. Wherein, Figure 3 The black circle in (1) of FIG. 1 represents the output end, and the white circle represents the input end.

[0066] In an exemplary embodiment, the voltage detection module 10 is connected to the target output end of the low-dropout linear regulator, and is configured to output a first control voltage according to the output voltage of the target output end; the first regulating module 20 is connected to the voltage detection module 10 and the target output end respectively, and is configured to receive the first control voltage and provide a first current to the target output end according to the first control voltage; the second regulating module 30 is connected to the voltage detection module 10 and the target output end respectively, and is configured to receive the first control voltage and provide a second current to the target output end according to the first control voltage; wherein the first current and the second current are both used to stabilize the output voltage.

[0067] That is, as shown in (1) of FIG. 1, the output voltage VOUT of the circuit at the steady state before the load current transient reduction is 3.30468V, which is lower than the output voltage VOUT of the circuit at the steady state after the load current transient reduction. Figure 4As shown, the low-dropout linear voltage regulator comprises a target output end for providing an output voltage VOUT. The voltage detection module 10 is connected to the target output end for receiving the output voltage VOUT of the target output end and outputting a first control voltage Vgs1 according to the output voltage VOUT. The first control voltage Vgs1 is positively correlated with the output voltage VOUT. That is, when the output voltage VOUT increases, the first control voltage Vgs1 increases, and when the output voltage VOUT decreases, the first control voltage Vgs1 decreases. The first adjustment module 20 is connected to the voltage detection module 10 for receiving the first control voltage Vgs1 output by the voltage detection module 10. The first adjustment module 20 is also connected to the target output end for providing a first current I1 to the target output end. The first current I1 is negatively correlated with the first control voltage Vgs1. That is, when the first control voltage Vgs1 increases, the first current I1 decreases, and when the first control voltage Vgs1 decreases, the first current I1 increases. The second adjustment module 30 is connected to the voltage detection module 10 for receiving the first control voltage Vgs1 output by the voltage detection module 10. The second adjustment module 30 is also connected to the target output end for providing a second current I2 to the target output end. The second current I2 is negatively correlated with the first control voltage Vgs1. That is, when the first control voltage Vgs1 increases, the second current I2 decreases, and when the first control voltage Vgs1 decreases, the second current I2 increases.

[0068] The low-dropout linear voltage regulator further comprises a first input end for providing a supply voltage VIN. The voltage detection module 10, the first adjustment module 20, and the second adjustment module 30 are all connected to the first input end for receiving the supply voltage VIN provided by the first input end so that the modules can operate normally.

[0069] The low-dropout linear voltage regulator further comprises a capacitor COUT, one end of which is connected to the target output end so that the voltage at this end is the output voltage VOUT. The other end of the capacitor COUT can be grounded or connected to other circuits or other components, which include but are not limited to at least one of resistors, amplifiers, power tubes, power supplies, switches, etc. In actual applications, the low-dropout linear voltage regulator can also include other components, which will not be described here.

[0070] The output voltage VOUT is used to power a load Rload. Alternatively, one end of the load Rload is connected to the target output end so that the voltage at this end is the output voltage VOUT. The other end of the load Rload can be grounded or connected to other circuits or other components.

[0071] In the present example, when the low-dropout linear regulator is in steady state, the capacitor COUT is no longer charged or discharged. At this time, the output voltage VOUT does not change, and the output current formed by the combination of the first current I1 and the second current I2 is used to provide the load current of the load Rload.

[0072] When the load Rload changes from light load to heavy load, i.e., the load current transiently increases, since the low-dropout linear regulator fails to respond in time, i.e., the first current I1 and the second current I2 fail to increase in time, the capacitor COUT needs to be discharged to provide the increased load current of the load Rload. The discharge of the capacitor COUT causes the output voltage VOUT to sharply decrease, in which case the low-dropout linear regulator changes from steady state to transient state. Since both the first current I1 and the second current I2 are used to stabilize the output voltage VOUT, in the case where the output voltage VOUT decreases, both the first current I1 and the second current I2 increase. By continuously increasing the first current I1 and the second current I2, the increased load current of the load Rload is provided by the two currents, and the capacitor COUT is charged, so that the output voltage VOUT gradually increases, and finally the low-dropout linear regulator reenters steady state, and the output voltage VOUT remains unchanged.

[0073] Conversely, when the load Rload changes from heavy load to light load, i.e., the load current of the load Rload transiently decreases, since the low-dropout linear regulator fails to respond in time, i.e., the first current I1 and the second current I2 fail to decrease in time, the capacitor COUT needs to be charged to draw the load current of the load Rload. The charge of the capacitor COUT causes the output voltage VOUT to sharply increase, in which case the low-dropout linear regulator changes from steady state to transient state. Since both the first current I1 and the second current I2 are used to stabilize the output voltage VOUT, in the case where the output voltage VOUT increases, both the first current I1 and the second current I2 decrease. By continuously decreasing the first current I1 and the second current I2, a smaller load current is provided to the load Rload, and the capacitor COUT is discharged, so that the output voltage VOUT gradually decreases, and finally the low-dropout linear regulator reenters steady state, and the output voltage VOUT remains unchanged.

[0074] In a possible implementation manner, as Figure 5As shown, the voltage detection module 10 comprises a sampling module 101 and an error amplifier EA; the sampling module 101 is connected with the target output end and the error amplifier EA respectively, for receiving the output voltage VOUT, and outputting a feedback voltage VFB1 to the error amplifier EA according to the output voltage VOUT; the error amplifier EA is connected with a third input end, for receiving the feedback voltage VFB1 and a second reference voltage VREF1, and outputting a first control voltage Vgs1 according to the feedback voltage VFB1 and the second reference voltage VREF1, the third input end being used for providing the second reference voltage VREF1.

[0075] One end of the sampling module 101 is connected with the target output end, for receiving the output voltage VOUT provided by the target output end. The other end of the sampling module 101 is connected with the positive end of the error amplifier EA, for outputting the feedback voltage VFB1 to the positive end of the error amplifier EA. The embodiment of the present application does not limit the structure of the sampling module 101. Exemplarily, the sampling module 101 is a capacitive voltage division assembly, which comprises a capacitor and a resistor, and the capacitor is connected with the resistor in series. The output voltage VOUT can act on the capacitor, and the capacitor can store electric charge, thereby generating a voltage division effect to obtain the feedback voltage VFB1.

[0076] Alternatively, the sampling module 101 is a resistive voltage division assembly, which comprises a plurality of sampling resistors connected in series. The output voltage VOUT passes through at least one sampling resistor to obtain the feedback voltage VFB1, and the feedback voltage VFB1 is less than the output voltage VOUT. For example, Figure 5 As shown, the sampling module 101 comprises a sampling resistor R1 and a sampling resistor R2 connected in series. One end of the sampling resistor R1 is connected with the target output end, so that the voltage at this end is the output voltage VOUT. The other end of the sampling resistor R1 is connected with one end of the sampling resistor R2. The other end of the sampling resistor R2 is connected with the ground end GND, so that the voltage at this end is 0. The output voltage VOUT is divided by the sampling resistor R1 to obtain the feedback voltage VFB1. And, the feedback voltage VFB1 satisfies: In actual application, the other end of the sampling resistor R2 can also not be connected with the ground, but be connected with other circuits or other components, which is not limited herein.

[0077] The positive terminal of the error amplifier EA is connected with the sampling module 101, for example, connected with the series node between the sampling resistor R1 and the sampling resistor R2, for receiving the feedback voltage VFB1. The negative terminal of the error amplifier EA is connected with the third input terminal, for receiving the second reference voltage VREF1 provided by the third input terminal. Optionally, the third input terminal is one end of the output voltage of the power supply circuit or one end of the output voltage of the component, for example, one end of the capacitor or the output voltage of the power supply, for providing the second reference voltage VREF1. The error amplifier EA detects the error voltage between the actual output voltage and the expected output voltage by comparing the feedback voltage VFB1 (i.e. the voltage obtained by sampling the actual output voltage VOUT) with the second reference voltage VREF1. The first control voltage Vgs1 is output by amplifying the error voltage. Therefore, the first control voltage Vgs1 is positively correlated with the error voltage.

[0078] Optionally, the power terminal of the error amplifier EA is connected with the first input terminal, for receiving the supply voltage VIN provided by the first input terminal, so that the error amplifier EA can operate normally. The first input terminal is one end of the output voltage of the power supply circuit or one end of the output voltage of the component, for example, one end of the output voltage of the switching power supply circuit, for providing the supply voltage VIN.

[0079] In this example, when the load Rload changes from light load to heavy load, i.e. the load current transiently increases, the capacitor COUT is discharged, so that the output voltage VOUT decreases. Due to the decrease of the output voltage VOUT, the feedback voltage VFB1 decreases, so that the first control voltage Vgs1 decreases. Conversely, when the load Rload changes from heavy load to light load, i.e. the load current transiently decreases, the capacitor COUT is charged, so that the output voltage VOUT increases. Due to the increase of the output voltage VOUT, the feedback voltage VFB1 increases, so that the first control voltage Vgs1 increases.

[0080] The first regulating module 20 can receive the first control voltage Vgs1 and provide the first current I1 to the target output terminal according to the first control voltage Vgs1. Wherein, the first regulating module 20 satisfies: when the first control voltage Vgs1 decreases, output a higher first current I1; when the first control voltage Vgs1 increases, output a lower first current I1. Based on this, in actual application, any circuit satisfying this function can be used as the first regulating module 20. The following shows several possible implementation manners, which are shown as implementation manner A and implementation manner B respectively.

[0081] In the implementation manner A, as shown in Figure 5As shown, the first adjusting module 20 comprises a first adjusting unit 201, a first current source IREF1 and a first transistor M4. The first adjusting unit 201 is connected with the voltage detection module 10 and the gate of the first transistor M4 respectively, for receiving the first control voltage Vgs1, providing the first target current I3 to the gate of the first transistor M4 according to the first control voltage Vgs1; the first current source IREF1 is connected with the gate of the first transistor M4, for providing the first reference current I4 to the gate of the first transistor M4; the source of the first transistor M4 is connected with the first input end, and the drain of the first transistor M4 is connected with the target output end, for providing the first current I1 to the target output end according to the second control voltage Vgs2, and the first input end is used for providing the power supply voltage VIN, and the second control voltage Vgs2 is determined according to the first target current I3 and the first reference current I4.

[0082] One end of the first adjusting unit 201 is connected with the voltage detection module 10, for receiving the first control voltage Vgs1 provided by the voltage detection module 10. The other end of the first adjusting unit 201 is connected with the gate of the first transistor M4, for providing the first target current I3 to the gate of the first transistor M4. In addition, the first adjusting unit 201 is also connected with the first input end, for receiving the power supply voltage VIN provided by the first input end. The first adjusting unit 201 is also connected with the ground end GND, so that the voltage of this end is 0. By being connected with the first input end and the ground end GND, the first adjusting unit 201 can normally work.

[0083] The embodiment of the present application does not limit the structure of the first adjusting unit 201. Exemplarily, as shown in the figure, Figure 5 The first adjusting unit 201 comprises a second transistor M1 and a first mirror component 202.

[0084] The source of the second transistor M1 is connected with the first input end, the drain of the second transistor M1 is connected with the first mirror component 202, the gate of the second transistor M1 is connected with the voltage detection module 10, for receiving the first control voltage Vgs1, and providing the first source current I5 to the first mirror component 202 according to the first control voltage Vgs1; the first mirror component 202 is connected with the gate of the first transistor M4, for receiving the first source current I5 and outputting the first target current I3 to the gate of the first transistor M4, and the first target current I3 is the mirror current of the first source current I5.

[0085] In this example, the second transistor M1 is a PMOS transistor. When the actual voltage of the gate of the PMOS transistor is lower than its threshold voltage, a current path can be formed between the source and the drain of the PMOS transistor, through which the source outputs a conduction current to the drain. The lower the actual voltage of the gate of the PMOS transistor, the greater the conduction current; the higher the actual voltage of the gate of the PMOS transistor, the smaller the conduction current.

[0086] Based on this, the source of the second transistor M1 is connected with the first input end, for receiving the supply voltage VIN provided by the first input end, so that when the second transistor M1 is turned on (i.e. a current path is formed between the source and the drain), a conduction current is provided. The drain of the second transistor M1 is connected with the first mirroring component 202, for providing the first source current I5 to the first mirroring component 202, the first source current I5 being the conduction current of the source to the drain of the second transistor M1. The gate of the second transistor M1 is connected with the voltage detection module 10, for receiving the first control voltage Vgs1 provided by the voltage detection module 10, the first control voltage Vgs1 being used to control the size of the first source current I5. Based on the working characteristics of the PMOS transistor, if the first control voltage Vgs1 decreases (equivalent to the absolute value of the first control voltage Vgs1 increasing), the first source current I5 increases; if the first control voltage Vgs1 rises (equivalent to the absolute value of the first control voltage Vgs1 decreasing), the first source current I5 decreases.

[0087] The first mirroring component 202 is connected with the drain of the second transistor M1, for receiving the first source current I5 provided by the drain of the second transistor M1. The first mirroring component 202 is also connected with the gate of the first transistor M4, for outputting the first target current I3 to the gate of the first transistor M4. The first target current I3 is a mirror current of the first source current I5.

[0088] It should be noted that the first mirroring component 202 is a kind of mirror current source, which can mirror the input current in a certain proportion to obtain the output current. For example, the mirroring ratio is 1, which can make the input current equal to the output current; the mirroring ratio is greater than 1, which can make the input current less than the output current; the mirroring ratio is less than 1, which can make the input current greater than the output current. Based on this, the direction of the first target current I3 is the same as that of the first source current I5, but the size of the first target current I3 can be the same as or different from that of the first source current I5. For example, the first source current I5 is equal to the first target current I3. When the first source current I5 increases, the first target current I3 also increases; when the first source current I5 decreases, the first target current I3 also decreases. By determining the first target current I3 according to the first source current I5 through the first mirroring component 202, a stable current is provided to the gate of the first transistor M4, so as to help the circuit reach a stable state and improve the performance of the circuit.

[0089] In an exemplary embodiment, such as Figure 5 As shown, the first mirror assembly 202 includes a third transistor M2 and a fourth transistor M3; the source of the third transistor M2 is grounded, the drain of the third transistor M2 is connected to the drain of the second transistor M1, and the gate of the third transistor M2 is connected to the drain of the second transistor M1 and the gate of the fourth transistor M3, for receiving a first source current I5 and providing a first gate current I to the fourth transistor M3. B1 The source of the fourth transistor M3 is grounded, and the drain of the fourth transistor M3 is connected to the gate of the first transistor M4 to receive the first gate current I. B1 And output the first target current I3 to the gate of the first transistor M4.

[0090] In this example, both the third transistor M2 and the fourth transistor M3 are NMOS transistors. When the actual gate voltage of an NMOS transistor is higher than its threshold voltage, a current path can be formed between the source and drain of the NMOS transistor, and the drain of the NMOS transistor outputs a conduction current to the source through this current path. Furthermore, the lower the actual gate voltage of the NMOS transistor, the smaller the conduction current; the higher the actual gate voltage of the NMOS transistor, the larger the conduction current.

[0091] The source of the third transistor M2 is grounded, making its source voltage zero. Both the drain and gate of the third transistor M2 are connected to the drain of the second transistor M1, causing the drain of the second transistor M1 to supply a first source current I5 to the third transistor M2. This first source current I5 is then shunted into two currents. One of the shunted currents is I0. C0 , is the conduction current between the drain and source of the third transistor M2. The other current obtained by shunting is 2I. B It is used to provide current to the gate of the third transistor M2 and to provide current to the gate of the fourth transistor M3.

[0092] In this configuration, the gate of the third transistor M2 is also connected to the gate of the fourth transistor M3, and the gate of the fourth transistor M3 is also connected to the drain of the second transistor M1. Based on this, the current 2I... B The current is split into two. One of the shunted currents is I. B0 The gate of the third transistor M2 is used for input, with a current I. B0 This corresponds to the gate voltage of the third transistor M2, and the drain-to-source current I of the third transistor M2 can be controlled by this gate voltage. C0 The magnitude of the current. The other current obtained by shunting (i.e., the first gate current) is I. B1 The gate of the fourth transistor M3 is used for input; similarly, the current I... B1The gate voltage of the fourth transistor M3 can correspond to the gate voltage by which the on current of the drain to source of the fourth transistor M3 is controlled, i.e. by which the size of the first target current I3 is controlled. That is, the third transistor M2 receives the first source current I5 and provides the first gate current I B1 , the first gate current I B1 is used to control the size of the first target current I3.

[0093] The source of the fourth transistor M3 is grounded, so that the source voltage is 0. The drain of the fourth transistor M3 is connected to the gate of the first transistor M4, for providing the first target current I3 to the gate of the first transistor M4. Optionally, the first target current I3 is equal to the first source current I5. Alternatively, the first target current I3 is greater than or less than the first source current I5.

[0094] In addition, the first adjusting module 20 further comprises a first current source IREF1. One end of the first current source IREF1 is connected to the gate of the first transistor M4, for providing the first reference current I4 to the gate of the first transistor M4. The first current source IREF1 is a kind of power supply capable of providing constant current in a circuit, and the output current, i.e. the first reference current I4, does not change.

[0095] The gate of the first transistor M4 receives both the first reference current I4 provided by the first current source IREF1 and the first target current I3 provided by the first adjusting unit 201. That is, the current received by the gate of the first transistor M4 is equal to the difference between the first reference current I4 and the first target current I3. The circuit can compare the first reference current I4 with the first target current I3, and determine the second control voltage Vgs2 according to the comparison result, so that the gate of the first transistor M4 receives the second control voltage Vgs2.

[0096] Optionally, the first transistor M4 is a PMOS transistor. When the first target current I3 increases, the first target current I3 is greater than the first reference current I4, so that the second control voltage Vgs2 decreases. Since the first transistor M4 is a PMOS transistor, which has the characteristic of low-level conduction, the decrease of the second control voltage Vgs2 will cause the on current of the first transistor M4 to increase, i.e. the first current I1 to increase. Conversely, when the first target current I3 decreases, the first target current I3 is less than the first reference current I4, so that the second control voltage Vgs2 increases, causing the on current of the first transistor M4 to decrease, i.e. the first current I1 to decrease.

[0097] The first current source IREF1 can be regarded as a current mirror similar to the first mirror component 202, and the first reference current I4 is generated through the current mirror. That is, the current mirror of the first current source IREF1 includes two transistors, which are both NMOS transistors or both PMOS transistors.

[0098] If the first target current I3 decreases and the first reference current I4 is greater than the first target current I3, for example, the first reference current I4 is 2 microamperes and the first target current I3 is less than 2 microamperes. Since the first reference current I4 is greater than the first target current I3, the first current source IREF1 operates based on the first target current I3. At this time, the transistors of the first current source IREF1 are in the linear region (the current is positively correlated with the voltage difference between the source and the drain). Since the first target current I3 decreases, the voltage difference between the source and the drain of the first current source IREF1 decreases, that is, the voltage difference between the two ends of the first current source IREF1 decreases. Since the gate voltage of the first transistor M4 is equal to the supply voltage VIN minus the voltage difference between the two ends of the first current source IREF1, the voltage difference between the two ends of the first current source IREF1 decreases, so that the gate voltage (the second control voltage Vgs2) of the first transistor M4 increases.

[0099] Conversely, if the first target current I3 increases and the first reference current I4 is less than the first target current I3, for example, the first reference current I4 is 2 microamperes and the first target current I3 is greater than 2 microamperes. Since the first reference current I4 is less than the first target current I3, the fourth transistor M3 operates based on the first reference current I4. At this time, the fourth transistor M3 is in the linear region. Since the fourth transistor M3 is in the linear region, the voltage difference between the source and the drain of the fourth transistor M3 decreases. Since the gate voltage of the first transistor M4 is equal to the voltage of the ground end plus the voltage difference between the source and the drain of the fourth transistor M3, the voltage difference between the source and the drain of the fourth transistor M3 decreases, which will decrease the gate voltage (the second control voltage Vgs2) of the first transistor M4.

[0100] From the above, it can be seen that if the first source current I5 increases, the first target current I3 increases, and at this time the gate voltage (the second control voltage Vgs2) of the first transistor M4 decreases. Since the first transistor M4 is a PMOS transistor and has the characteristic of low-level conduction, the conduction current of the first transistor M4 increases, that is, the first current I1 increases. If the first source current I5 decreases, the first target current I3 decreases, and at this time the gate voltage of the first transistor M4 increases, so that the conduction current of the first transistor M4 decreases, that is, the first current I1 decreases.

[0101] The first transistor M4 is adjusted by the first target current and the first reference current, so as to control the size of the conduction current of the first transistor M4, that is, the size of the first current. When the load current increases, the output voltage VOUT decreases, the first control voltage Vgs1 decreases, and the first source current I5 increases. Due to the increase of the first source current I5, the first target current I3 increases, the second control voltage Vgs2 decreases, and the first current I1 increases. By increasing the first current I1, more load current is provided by the first current I1, which hinders the discharge of the capacitor COUT and reduces the decrease of the output voltage VOUT, thereby facilitating the recovery of the output voltage VOUT; when the load current decreases, the output voltage VOUT increases, the first control voltage Vgs1 increases, and the first source current I5 decreases. Due to the decrease of the first source current I5, the first target current I3 decreases, the second control voltage Vgs2 increases, and the first current I1 decreases. By reducing the first current I1, the charging of the capacitor COUT is hindered, and the increase of the output voltage VOUT is reduced, thereby facilitating the recovery of the output voltage VOUT. Therefore, the first current I1 has the function of stabilizing the output voltage VOUT.

[0102] In the implementation manner B, as shown in Figure 6 The first adjusting module 20 includes a second adjusting unit 203, a first comparator CMP1, a fifth transistor M6, and a first resistor R4, one end of the first resistor R4 being connected with the first input end. The second adjusting unit 203 is connected with the voltage detection module 10 and the first comparator CMP1 respectively, and is configured to receive the first control voltage Vgs1 and provide a first target voltage VFB2 to the first comparator CMP1 according to the first control voltage Vgs1; the first comparator CMP1 is connected with the gate of the fifth transistor M6 and the second input end, and is configured to receive the first reference voltage VREF2 and the first target voltage VFB2, and output a third control voltage Vgs3 to the gate of the fifth transistor M6 according to the first reference voltage VREF2 and the first target voltage VFB2, the second input end being configured to provide the first reference voltage VREF2; the source of the fifth transistor M6 is connected with the other end of the first resistor R4, the drain of the fifth transistor M6 is connected with the target output end, and is configured to provide the first current I1 to the target output end according to the third control voltage Vgs3, and the first input end is configured to provide the supply voltage VIN.

[0103] The second adjusting unit 203 is connected with the voltage detection module 10, and is configured to receive the first control voltage Vgs1 provided by the voltage detection module 10. The second adjusting unit 203 is also connected with the first comparator CMP1, and is configured to provide the first target voltage VFB2 to the first comparator CMP1. Optionally, the second adjusting unit 203 is also connected with the first input terminal, and is configured to receive the power supply voltage VIN provided by the first input terminal. The second adjusting unit 203 is also connected with the ground terminal GND, so that the voltage of the ground terminal GND is 0. By connecting the first input terminal and the ground terminal GND, the second adjusting unit 203 can operate normally.

[0104] In actual application, the second adjusting unit 203 can have various structures, and one possible implementation is shown below. As shown in Figure 6 The second adjusting unit 203 includes a sixth transistor M5 and a second resistor R3. The second resistor R3 is connected with the ground terminal GND and the drain of the sixth transistor M5. The source of the sixth transistor M5 is connected with the first input terminal, and the gate of the sixth transistor M5 is connected with the voltage detection module 10, configured to receive the first control voltage Vgs1 and provide the first target voltage VFB2 to the first comparator CMP1 according to the first control voltage Vgs1.

[0105] In this example, the sixth transistor M5 is a PMOS transistor. One end of the second resistor R3 is connected with the ground terminal GND, so that the voltage of the ground terminal GND is 0. The other end of the second resistor R3 is connected with the drain of the sixth transistor M5. The source of the sixth transistor M5 is connected with the first input terminal, configured to receive the power supply voltage VIN provided by the first input terminal. The gate of the sixth transistor M5 is connected with the voltage detection module 10, configured to receive the first control voltage Vgs1 provided by the voltage detection module 10, and the first control voltage Vgs1 is used to control the conduction current of the sixth transistor M5.

[0106] Since the sixth transistor M5 is a PMOS transistor with low-level conduction characteristics, the smaller the first control voltage Vgs1 is, the greater the conduction current of the sixth transistor M5 is, and the greater the first control voltage Vgs1 is, the smaller the conduction current of the sixth transistor M5 is. The voltage difference between the two ends of the second resistor R3 is equal to the conduction current of the sixth transistor M5 multiplied by the resistance value of the second resistor R3, and the first target voltage VFB2 is equal to the voltage of the ground terminal GND plus the voltage difference between the two ends of the second resistor R3. If the first control voltage Vgs1 increases, the conduction current of the sixth transistor M5 decreases, resulting in a decrease in the first target voltage VFB2. If the first control voltage Vgs1 decreases, the conduction current of the sixth transistor M5 increases, resulting in an increase in the first target voltage VFB2.

[0107] The positive terminal of the first comparator CMP1 is connected with the second input terminal, for receiving the first reference voltage VREF2 provided by the second input terminal. The negative terminal of the first comparator CMP1 is connected with the second resistor R3 and the drain of the sixth transistor M5, for receiving the first target voltage VFB2. The first comparator CMP1 is used for comparing the first reference voltage VREF2 and the first target voltage VFB2, and outputting the third control voltage Vgs3 according to the comparison result. When the first reference voltage VREF2 is greater than the first target voltage VFB2, the third control voltage Vgs3 output by the first comparator CMP1 is high, and when the first reference voltage VREF2 is less than the first target voltage VFB2, the third control voltage Vgs3 output by the first comparator CMP1 is low. Based on this, when the first target voltage VFB2 decreases, the third control voltage Vgs3 increases, and when the first target voltage VFB2 increases, the third control voltage Vgs3 decreases.

[0108] The fifth transistor M6 is a PMOS transistor. The gate of the fifth transistor M6 is connected with the output terminal of the first comparator CMP1, for receiving the third control voltage Vgs3 output by the first comparator CMP1. The source of the fifth transistor M6 is connected with one end of the first resistor R4, and the other end of the first resistor R4 is connected with the first input terminal. The supply voltage VIN is divided by the first resistor R4, so that the source voltage of the fifth transistor M6 can be reduced. Since the third control voltage Vgs3 is high or low, by reducing the source voltage of the fifth transistor M6, the voltage difference between the source and the gate of the fifth transistor M6 is reduced, so that the conduction current of the fifth transistor M6, i.e. the first current I1, is in the expected range. The drain of the fifth transistor M6 is connected with the target output terminal of the low-dropout linear regulator, for providing the first current I1 to the target output terminal. Since the fifth transistor M6 is a PMOS transistor and has the characteristic of low-level conduction, the smaller the third control voltage Vgs3 is, the greater the conduction current of the fifth transistor M6 is, i.e. the greater the first current I1 is; the greater the third control voltage Vgs3 is, the smaller the conduction current of the fifth transistor M6 is, i.e. the smaller the first current I1 is.

[0109] The fifth transistor M6 is controlled by the first target voltage and the first reference voltage, so as to control the on current of the fifth transistor M6, i.e. the first current. When the load current increases, the output voltage VOUT decreases, the first control voltage Vgs1 decreases, and the on current of the sixth transistor M5 increases. As the on current of the sixth transistor M5 increases, the first target voltage VFB2 increases, the third control voltage Vgs3 decreases, and the first current I1 increases. By increasing the first current I1, more load current is provided by the first current I1, the capacitor COUT is prevented from discharging, the decrease of the output voltage VOUT is reduced, and the output voltage VOUT is recovered. When the load current decreases, the output voltage VOUT increases, the first control voltage Vgs1 increases, and the on current of the sixth transistor M5 decreases. As the on current of the sixth transistor M5 decreases, the first target voltage VFB2 decreases, the third control voltage Vgs3 increases, and the first current I1 decreases. By decreasing the first current I1, less load current is provided by the first current I1, the capacitor COUT is prevented from charging, the increase of the output voltage VOUT is reduced, and the output voltage VOUT is recovered. Therefore, the first current I1 has the function of stabilizing the output voltage VOUT.

[0110] In the exemplary embodiment, the low-dropout linear voltage regulator further comprises a third regulating module. The third regulating module is connected with the voltage detection module 10, the target output terminal and the ground terminal respectively, and is configured to receive the first control voltage Vgs1 and output a third current according to the first control voltage Vgs1; wherein the third current is a current from the target output terminal to the ground terminal, and the third current is used to stabilize the output voltage.

[0111] The third regulating module is connected with the voltage detection module 10, and is configured to receive the first control voltage Vgs1 output by the voltage detection module 10. The third regulating module is also connected with the target output terminal, and is configured to output the third current. Optionally, the third regulating module is connected with the first input terminal, and is configured to receive the supply voltage VIN provided by the first input terminal, so that the third regulating module can operate normally.

[0112] When the load Rload changes from light load to heavy load, i.e. the load current transiently increases, the output voltage VOUT decreases. Since the third current is used to stabilize the output voltage VOUT, and the third current is the current from the target output terminal to the ground terminal, when the output voltage VOUT decreases, the third current decreases. Conversely, when the load Rload changes from heavy load to light load, i.e. the load current transiently decreases, the output voltage VOUT increases. Since the third current is used to stabilize the output voltage VOUT, and the third current is the current from the target output terminal to the ground terminal, when the output voltage VOUT increases, the third current increases. Based on this, in actual applications, any circuit that meets this function can be used as the third regulating module. The following shows several possible implementation manners, which are shown as implementation manner C and implementation manner D respectively.

[0113] In implementation manner C, as shown in Figure 7 the third regulating module 40 includes a third regulating unit 401, a second current source IREF2 and a seventh transistor M10. The third regulating unit 401 is connected with the voltage detection module 10 and the gate of the seventh transistor M10 respectively, for receiving the first control voltage Vgs1, providing the second target current I6 to the gate of the seventh transistor M10 according to the first control voltage Vgs1; the second current source IREF2 is connected with the gate of the seventh transistor M10, for providing the second reference current I7 to the gate of the seventh transistor M10; the source of the seventh transistor M10 is connected with the target output terminal, and the drain of the seventh transistor M10 is grounded, for outputting the third current I8 according to the fourth control voltage Vgs4, and the fourth control voltage Vgs4 is determined according to the second target current I6 and the second reference current I7.

[0114] One end of the third regulating unit 401 is connected with the voltage detection module 10, for receiving the first control voltage Vgs1 provided by the voltage detection module 10. The other end of the third regulating unit 401 is connected with the gate of the seventh transistor M10, for providing the second target current I6 to the gate of the seventh transistor M10. In addition, the third regulating unit 401 is also connected with the first input terminal, for receiving the supply voltage VIN provided by the first input terminal. The third regulating unit 401 is also connected with the ground terminal GND, so that the voltage of this terminal is 0. By being connected with the first input terminal and the ground terminal GND, the third regulating unit 401 can normally operate.

[0115] The embodiments of the present application do not limit the structure of the third regulating unit 401. Exemplarily, as shown in Figure 7 the third regulating unit 401 includes an eighth transistor M7 and a second mirror component 402.

[0116] The source of the eighth transistor M7 is grounded, the drain of the eighth transistor M7 is connected with the second mirror component 402, the gate of the eighth transistor M7 is connected with the voltage detection module 10, and is used for receiving the first control voltage Vgs1, and providing the second source current I9 to the second mirror component 402 according to the first control voltage Vgs1; the second mirror component 402 is connected with the gate of the seventh transistor M10, is used for receiving the second source current I9, and outputs the second target current I6 to the gate of the seventh transistor M10, and the second target current I6 is the mirror current of the second source current I9.

[0117] In the example, the eighth transistor M7 is an NMOS transistor. The source of the eighth transistor M7 is grounded, so that the source voltage is 0. The drain of the eighth transistor M7 is connected with the second mirror component 402, and is used for providing the second source current I9 to the second mirror component 402, and the second source current I9 is the on current from the drain to the source of the eighth transistor M7. The gate of the eighth transistor M7 is connected with the voltage detection module 10, and is used for receiving the first control voltage Vgs1 provided by the voltage detection module 10, and the first control voltage Vgs1 is used for controlling the size of the second source current I9. Based on the characteristic that the NMOS transistor is turned on at a high level, if the first control voltage Vgs1 decreases, the second source current I9 decreases; if the first control voltage Vgs1 increases, the second source current I9 increases.

[0118] The second mirror component 402 is connected with the source of the eighth transistor M7, and is used for receiving the second source current I9 provided by the source of the eighth transistor M7. The second mirror component 402 is also connected with the gate of the seventh transistor M10, and is used for outputting the second target current I6 to the gate of the seventh transistor M10. The second target current I6 is the mirror current of the second source current I9.

[0119] It should be noted that the second mirror component 402 is a kind of mirror current source, which can mirror the input current according to a certain proportion to obtain the output current. That is, the direction of the second target current I6 is the same as that of the second source current I9, but the second target current I6 and the second source current I9 can be the same size or different size. Exemplarily, the second source current I9 is equal to the second target current I6. When the second source current I9 increases, the second target current I6 also increases; when the second source current I9 decreases, the second target current I6 also decreases. By determining the second target current I6 according to the second source current I9 through the second mirror component 402, a stable current is provided to the gate of the seventh transistor M10, so as to help the circuit to reach a stable state and improve the performance of the circuit.

[0120] In the example embodiment, as shown in FIG. 2, the voltage detection module 10 is connected with the gate of the eighth transistor M7, and is used for providing the first control voltage Vgs1 to the gate of the eighth transistor M7. The first control voltage Vgs1 is used for controlling the size of the second source current I9 provided by the eighth transistor M7. Figure 7As shown, the second mirror component 402 includes a ninth transistor M8 and a tenth transistor M9; a source of the ninth transistor M8 is connected with the first input end, a drain of the ninth transistor M8 is connected with a drain of the eighth transistor M7, a gate of the ninth transistor M8 is connected with the drain of the eighth transistor M7 and a gate of the tenth transistor M9, for receiving the second source current I9 and providing a second gate current to the tenth transistor M9; a drain of the tenth transistor M9 is connected with the gate of the seventh transistor M10, for receiving the second gate current and outputting the second target current I6 to the gate of the seventh transistor M10.

[0121] In the present example, the ninth transistor M8 and the tenth transistor M9 are both PMOS transistors. The source of the ninth transistor M8 is connected with the first input end, for receiving the supply voltage VIN provided by the first input end. The drain and the gate of the ninth transistor M8 are both connected with the drain of the eighth transistor M7, so that the drain of the eighth transistor M7 provides the second source current I9 to the ninth transistor M8, and the second source current I9 is divided into two currents. One of the two currents is the conduction current between the source and the drain of the ninth transistor M8. The other of the two currents is used to provide current to the gate of the ninth transistor M8 and to the gate of the tenth transistor M9.

[0122] The gate of the ninth transistor M8 is also connected with the gate of the tenth transistor M9, and the gate of the tenth transistor M9 is also connected with the drain of the eighth transistor M7. Based on this, the other of the two currents divided from the second source current I9 is further divided into two currents. One of the two currents is used to input the gate of the ninth transistor M8, and this current can correspond to the gate voltage of the ninth transistor M8, and the size of the conduction current between the source and the drain of the ninth transistor M8 is controlled by the gate voltage. The other of the two currents (i.e., the second gate current) is used to input the gate of the tenth transistor M9, and similarly, this current can correspond to the gate voltage of the tenth transistor M9, and the size of the conduction current between the source and the drain of the tenth transistor M9 (i.e., the size of the second target current I6) is controlled by the gate voltage. That is, the ninth transistor M8 receives the second source current I9, provides the second gate current to the tenth transistor M9, and the second gate current is used to control the size of the second target current I6.

[0123] The source of the tenth transistor M9 is connected with the first input end, for receiving the supply voltage VIN provided by the first input end. The drain of the tenth transistor M9 is connected with the gate of the seventh transistor M10, for providing the second target current I6 to the gate of the seventh transistor M10. Optionally, the second target current I6 is equal to the second source current I9. Alternatively, the second target current I6 is greater than or less than the second source current I9.

[0124] In addition, the third adjusting module 40 further comprises a second current source IREF2. One end of the second current source IREF2 is connected with the gate of the seventh transistor M10, for providing a second reference current I7 to the gate of the seventh transistor M10. The second current source IREF2 is a kind of power supply capable of providing constant current in a circuit, and the output current of the second current source IREF2, i.e. the second reference current I7, will not change.

[0125] The gate of the seventh transistor M10 receives both the second reference current I7 provided by the second current source IREF2 and the second target current I6 provided by the third adjusting unit 401. That is, the current received by the gate of the seventh transistor M10 is equal to the difference between the second target current I6 and the second reference current I7. The circuit can compare the second reference current I7 with the second target current I6, and determine the fourth control voltage Vgs4 according to the comparison result, so that the gate of the seventh transistor M10 receives the fourth control voltage Vgs4.

[0126] Optionally, the seventh transistor M10 is an NMOS transistor. When the second target current I6 increases, the second target current I6 is greater than the second reference current I7, so that the fourth control voltage Vgs4 rises. Since the seventh transistor M10 is an NMOS transistor, and the NMOS transistor has the characteristic of high-level conduction, the fourth control voltage Vgs4 rising will increase the conduction current of the seventh transistor M10, i.e. increase the third current I8. Conversely, when the second target current I6 decreases, the second target current I6 is less than the second reference current I7, so that the fourth control voltage Vgs4 decreases, so that the conduction current of the seventh transistor M10 decreases, i.e. the third current I8 decreases.

[0127] The second current source IREF2 can be regarded as a current mirror similar in structure to the second mirror component 402, and the second reference current I7 is generated through the current mirror. That is, the current mirror of the second current source IREF2 comprises two transistors, which are both NMOS transistors or both PMOS transistors, for example.

[0128] If the second target current I6 decreases, the second reference current I7 is greater than the second target current I6, for example, the second reference current I7 is 2 microamperes, and the second target current I6 is less than 2 microamperes. Since the second reference current I7 is greater than the second target current I6, the second current source IREF2 operates based on the second target current I6. At this time, the transistor of the second current source IREF2 is in the linear region (the current is positively correlated with the voltage difference between the source and the drain). Since the second target current I6 decreases, the voltage difference between the source and the drain of the second current source IREF2 decreases, that is, the voltage difference between the two ends of the second current source IREF2 decreases. Since the gate voltage of the seventh transistor M10 is equal to the voltage of the ground terminal GND plus the voltage difference between the two ends of the second current source IREF2, the voltage difference between the two ends of the second current source IREF2 decreases, so that the gate voltage (that is, the fourth control voltage Vgs4) of the seventh transistor M10 decreases.

[0129] Conversely, if the second target current I6 increases, so that the second reference current I7 is less than the second target current I6, for example, the second reference current I7 is 2 microamperes, and the second target current I6 is greater than 2 microamperes. Since the second reference current I7 is less than the second target current I6, the tenth transistor M9 operates based on the second reference current I7. At this time, the tenth transistor M9 is in the linear region. Since the tenth transistor M9 is in the linear region, the voltage difference between the source and the drain of the tenth transistor M9 decreases. Since the gate voltage of the seventh transistor M10 is equal to the supply voltage minus the voltage difference between the source and the drain of the tenth transistor M9, the voltage difference between the source and the drain of the tenth transistor M9 decreases, which causes the gate voltage (that is, the fourth control voltage Vgs4) of the seventh transistor M10 to increase.

[0130] In summary, if the second source current I9 increases, the second target current I6 increases, and at this time, the gate voltage of the seventh transistor M10 increases. Since the seventh transistor M10 is an NMOS transistor and has the characteristic of high-level conduction, the conduction current of the seventh transistor M10 increases, that is, the third current I8 increases. If the second source current I9 decreases, the second target current I6 decreases, and at this time, the gate voltage of the seventh transistor M10 decreases, so that the conduction current of the seventh transistor M10 decreases, that is, the third current I8 decreases.

[0131] The gate voltage of the seventh transistor M10 is adjusted by the second target current and the second reference current, so that the size of the conduction current of the seventh transistor M10, that is, the size of the third current is controlled. When the load current increases, the output voltage VOUT decreases, causing the first control voltage Vgs1 to decrease. As the first control voltage Vgs1 decreases, the second source current I9 decreases, the second target current I6 decreases, and the fourth control voltage Vgs4 decreases. The decrease of the fourth control voltage Vgs4 causes the third current I8 to decrease, so that the current consumption is reduced, and the amount of decrease of the third current I8 can provide the amount of increase of the load current, hinder the discharge of the capacitor COUT, and reduce the amount of decrease of the output voltage VOUT, thereby being more conducive to the recovery of the output voltage VOUT. When the load current decreases, the output voltage VOUT increases, causing the first control voltage Vgs1 to increase. As the first control voltage Vgs1 increases, the second source current I9 increases, the second target current I6 increases, and the fourth control voltage Vgs4 increases. The increase of the fourth control voltage Vgs4 causes the third current I8 to increase, so that the current consumption is increased to extract more load current, hinder the charging of the capacitor COUT, and reduce the amount of increase of the output voltage VOUT, thereby being more conducive to the recovery of the output voltage VOUT. Based on this, the third current I8 has the function of stabilizing the output voltage VOUT.

[0132] It should be noted that Figure 7 the description of other parts in the embodiment A, which will not be repeated here. In actual application, the other parts in the embodiment B can also be implemented based on the embodiment Figure 7 , which will not be repeated here.

[0133] In the embodiment D, as shown in Figure 8 , the third adjusting module 40 includes a fourth adjusting unit 403, a second comparator CMP2, an eleventh transistor M12, and a third resistor R6, one end of the third resistor R6 being grounded. The fourth adjusting unit 403 is connected with the voltage detection module 10 and the second comparator CMP2 respectively, and is configured to receive the first control voltage Vgs1 and provide a second target voltage VFB3 to the second comparator CMP2 according to the first control voltage Vgs1; the second comparator CMP2 is connected with the gate of the eleventh transistor M12 and a fourth input end, and is configured to receive the third reference voltage VREF3 and the second target voltage VFB3, and output a fifth control voltage Vgs5 to the gate of the eleventh transistor M12 according to the third reference voltage VREF3 and the second target voltage VFB3, the fourth input end being configured to provide the third reference voltage VREF3; the source of the eleventh transistor M12 is connected with the other end of the third resistor R6, and the drain of the eleventh transistor M12 is connected with a target output end, and is configured to provide the third current I8 to the target output end according to the fifth control voltage Vgs5.

[0134] The fourth adjusting unit 403 is connected with the voltage detection module 10, and is configured to receive the first control voltage Vgs1 provided by the voltage detection module 10. The fourth adjusting unit 403 is also connected with the second comparator CMP2, and is configured to provide the second target voltage VFB3 to the second comparator CMP2. Optionally, the fourth adjusting unit 403 is also connected with the first input end, and is configured to receive the power supply voltage VIN provided by the first input end. The fourth adjusting unit 403 is also connected with the ground end GND, so that the voltage of the ground end GND is 0. By connecting the first input end and the ground end GND, the fourth adjusting unit 403 can operate normally.

[0135] In actual application, the fourth adjusting unit 403 can have various structures, and one possible implementation is shown below. As shown in FIG. 4, the fourth adjusting unit 403 includes a twelfth transistor M11 and a fourth resistor R5. The fourth resistor R5 is connected with the first input end and the drain of the twelfth transistor M11. The source of the twelfth transistor M11 is grounded, the gate of the twelfth transistor M11 is connected with the voltage detection module 10, and is configured to receive the first control voltage Vgs1 and provide the second target voltage VFB3 to the second comparator CMP2 according to the first control voltage Vgs1. Figure 6 In this example, the twelfth transistor M11 is an NMOS transistor. One end of the fourth resistor R5 is connected with the first input end, and is configured to receive the power supply voltage VIN provided by the first input end. The other end of the fourth resistor R5 is connected with the drain of the twelfth transistor M11. The source of the twelfth transistor M11 is grounded, so that the voltage of the source is 0. The gate of the twelfth transistor M11 is connected with the voltage detection module 10, and is configured to receive the first control voltage Vgs1 provided by the voltage detection module 10, and the first control voltage Vgs1 is used to control the conduction current of the twelfth transistor M11.

[0136] Since the twelfth transistor M11 is an NMOS transistor with the characteristic of high-level conduction, the smaller the first control voltage Vgs1 is, the smaller the conduction current of the twelfth transistor M11 is, and the larger the first control voltage Vgs1 is, the larger the conduction current of the twelfth transistor M11 is. The voltage difference between the two ends of the fourth resistor R5 is equal to the conduction current of the twelfth transistor M11 multiplied by the resistance value of the fourth resistor R5, and the second target voltage VFB3 is equal to the power supply voltage VIN minus the voltage difference between the two ends of the fourth resistor R5. In this case, if the first control voltage Vgs1 increases, the conduction current of the twelfth transistor M11 increases, resulting in a decrease of the second target voltage VFB3. If the first control voltage Vgs1 decreases, the conduction current of the twelfth transistor M11 decreases, resulting in an increase of the second target voltage VFB3.

[0137]

[0138] ​The positive terminal of the second comparator CMP2 is connected with the fourth input terminal, for receiving the third reference voltage VREF3 provided by the fourth input terminal. The negative terminal of the second comparator CMP2 is connected with the fourth resistor R5 and the drain of the twelfth transistor M11, for receiving the second target voltage VFB3. The second comparator CMP2 is used for comparing the third reference voltage VREF3 and the second target voltage VFB3, and determining the fifth control voltage Vgs5 according to the comparison result. When the third reference voltage VREF3 is greater than the second target voltage VFB3, the fifth control voltage Vgs5 is high; when the third reference voltage VREF3 is less than the second target voltage VFB3, the fifth control voltage Vgs5 is low. Based on this, when the second target voltage VFB3 decreases, the fifth control voltage Vgs5 increases; when the second target voltage VFB3 increases, the fifth control voltage Vgs5 decreases.

[0139] The eleventh transistor M12 is an NMOS transistor. The gate of the eleventh transistor M12 is connected with the output terminal of the second comparator CMP2, for receiving the fifth control voltage Vgs5 output by the second comparator CMP2. The source of the eleventh transistor M12 is connected with one end of the third resistor R6, and the other end of the third resistor R6 is grounded. The source voltage of the eleventh transistor M12 can be increased through the third resistor R6. Since the fifth control voltage Vgs5 is high or low, by increasing the source voltage of the eleventh transistor M12, the voltage difference between the source and the gate of the eleventh transistor M12 is reduced, so that the on-current of the eleventh transistor M12, i.e., the third current I8, is in the expected range. The drain of the eleventh transistor M12 is connected with the target output terminal of the low-dropout linear voltage regulator, for outputting the third current I8. Since the eleventh transistor M12 is an NMOS transistor and has the characteristic of high-level conduction, the smaller the fifth control voltage Vgs5 is, the smaller the on-current of the eleventh transistor M12, i.e., the smaller the third current I8 is; the larger the fifth control voltage Vgs5 is, the larger the on-current of the eleventh transistor M12, i.e., the larger the third current I8 is.

[0140] It should be noted that, Figure 8 the description of other parts in the embodiment A can be seen from the description of the embodiment B, and will not be repeated here. In actual application, other parts in the embodiment B can also be realized based on the embodiment A, and will not be repeated here. Figure 8

[0141] ​The gate voltage of the eleventh transistor M12 is adjusted by the second target voltage and the third reference voltage, so as to control the size of the on-current of the eleventh transistor M12, that is, the size of the third current. When the load current increases, the output voltage VOUT decreases, the first control voltage Vgs1 decreases, and the on-current of the twelfth transistor M11 decreases. Due to the decrease of the on-current of the twelfth transistor M11, the second target voltage VFB3 increases, the fifth control voltage Vgs5 decreases, and the third current I8 decreases. By decreasing the third current I8, the current consumption is reduced, and the amount of decrease of the third current I8 can provide the amount of increase of the load current, hinder the discharge of the capacitor COUT, and reduce the amount of decrease of the output voltage VOUT, thereby being more conducive to the recovery of the output voltage VOUT. When the load current decreases, the output voltage VOUT increases, the first control voltage Vgs1 increases, and the on-current of the twelfth transistor M11 increases. Due to the increase of the on-current of the twelfth transistor M11, the second target voltage VFB3 decreases, the fifth control voltage Vgs5 increases, and the third current I8 increases. By increasing the third current I8, more load current is extracted, the charging of the capacitor COUT is hindered, and the amount of increase of the output voltage VOUT is reduced, thereby being more conducive to the recovery of the output voltage VOUT. Based on this, the third current I8 has the function of stabilizing the output voltage VOUT.

[0142] Optionally, as shown in Figure 5 and Figure 6 , the second adjusting module 30 includes a target transistor MP. The source of the target transistor MP is connected with the first input end, the drain of the third transistor MP is connected with the target output end, the gate of the target transistor MP is connected with the voltage detection module 10, for receiving the first control voltage Vgs1, and providing the second current I2 to the target output end according to the first control voltage Vgs1, and the first input end is used for providing the supply voltage VIN.

[0143] The target transistor MP is a PMOS transistor. The source of the target transistor MP is connected with the first input end, for receiving the supply voltage VIN provided by the first input end. The gate of the target transistor MP is connected with the voltage detection module 10, for receiving the first control voltage Vgs1 provided by the voltage detection module 10, and the first control voltage Vgs1 is used for controlling the on-current of the target transistor MP. The drain of the target transistor MP is connected with the target output end, for providing the second current I2 to the target output end.

[0144] Since the target transistor MP is a PMOS transistor, it has the characteristic of low-level conduction. Therefore, when the first control voltage Vgs1 decreases, the second current I2 increases; when the first control voltage Vgs1 increases, the second current I2 decreases.

[0145] When the load current increases, the output voltage VOUT decreases, the first control voltage Vgs1 decreases, and the second current I2 increases. By increasing the second current I2, more load current is provided through the second current I2, which hinders the capacitor COUT from discharging and reduces the decrease of the output voltage VOUT, thereby helping to restore the output voltage VOUT; when the load current decreases, the output voltage VOUT increases, the first control voltage Vgs1 increases, and the second current I2 decreases. By reducing the second current I2, the capacitor COUT is hindered from charging, and the increase of the output voltage VOUT is reduced, thereby helping to restore the output voltage VOUT. Based on this, the second current I2 has the function of stabilizing the output voltage VOUT.

[0146] As can be known from the above, for example, when the low-dropout linear voltage regulator is in a steady state, the load current does not change, at this time, the capacitor COUT no longer charges or discharges, and the output voltage VOUT remains unchanged. The output voltage VOUT is divided by the sampling resistor R1 and the sampling resistor R2 to obtain the feedback voltage VFB1 of the error amplifier EA. The error amplifier EA determines the first control voltage Vgs1 according to the feedback voltage VFB1 and the second reference voltage VREF1, and the first control voltage Vgs1 is used to control the conduction current of the target transistor MP. Since the system is in a steady state, the value of the first control voltage Vgs1 does not change, and the conduction current (i.e., the second current) I2 of the target transistor MP does not change. Figure 5 In addition, the first control voltage Vgs1 is also used to control the conduction current of the second transistor M1. The fourth transistor M3 and the third transistor M2 form a first mirror component, which is used to obtain a mirrored conduction current, i.e., a first target current I3, according to the conduction current of the second transistor M1. The first current source IREF1 is used to provide a first reference current I4, and the first reference current I4 and the first target current I3 are used to determine a second control voltage Vgs2, and the second control voltage Vgs2 is used to control the conduction current of the first transistor M4. Since the system is in a steady state, the value of the second control voltage Vgs2 does not change, so that the conduction current (i.e., the first current) I1 of the first transistor M4 does not change.

[0147] Since the first current I1 and the second current I2 do not change, and the capacitor COUT no longer charges or discharges, the output voltage VOUT is stable, and the load Rload can be stably powered, and the load current of the load Rload remains unchanged.

[0148] If the load Rload jumps from light load to heavy load, i.e., the load current transiently increases, at this time, the capacitor COUT discharges, thereby causing the output voltage VOUT to drop. As shown in FIG. 4, the output voltage VOUT decreases, and the first control voltage Vgs1 decreases, thereby causing the second current I2 to increase. By increasing the second current I2, more load current is provided through the second current I2, which hinders the capacitor COUT from discharging and reduces the decrease of the output voltage VOUT, thereby helping to restore the output voltage VOUT.

[0149] Figure 9 As shown in FIG. 5, when the load current decreases, the output voltage VOUT increases, the first control voltage Vgs1 increases, and the second current I2 decreases. By reducing the second current I2, the capacitor COUT is hindered from charging, and the increase of the output voltage VOUT is reduced, thereby helping to restore the output voltage VOUT. Figure 9 ​(1) in FIG. 1 shows the waveform of the output voltage VOUT, Figure 9 (2) in FIG. 1 shows the waveform of the load current, wherein the negative sign in "-80.0mA" represents the direction of the load current, and the numerical value "80.0mA" represents the magnitude of the load current. It can be known from Figure 9 that when the load current increases from 0 to 80mA, the output voltage VOUT decreases by about 1.77mV. It can be understood that the low-dropout linear regulator has an adjusting capability, and can be re-stabilized after a period of adjustment.

[0150] When the load current transiently increases, the output voltage VOUT decreases, resulting in the decrease of the feedback voltage VFB1, so that the first control voltage Vgs1 decreases, thereby causing the conduction current of the target transistor MP to increase. In addition, the decrease of the first control voltage Vgs1 causes the conduction current of the second transistor M1 to increase, thereby causing the conduction current of the mirror to increase. Since the first reference current provided by the first current source IREF1 is unchanged, but the conduction current of the mirror increases, the second control voltage Vgs2 decreases, so that the conduction current of the first transistor M4 increases. Since the conduction current of the first transistor M4 and the conduction current of the target transistor MP both increase, the decrease amplitude of the output voltage VOUT can be reduced.

[0151] By increasing the conduction current of the first transistor M4 and the conduction current of the target transistor MP, more load current is provided, the discharging speed of the capacitor COUT is slowed down, and thus the decrease amplitude of the output voltage is reduced. Comparing Figure 8 and Figure 2 it can be known that when the load current increases from 0 to 80mA, the decrease amplitude of the output voltage VOUT of the circuit of the embodiment of the present application is about 1.77mV, which is much smaller than the decrease amplitude 6.33mV of the output voltage VOUT in the circuit of the related art. Since the decrease amplitude of the output voltage of the circuit of the embodiment of the present application is low, the transient response of the circuit is high, and the circuit has better performance.

[0152] If the load Rload jumps from heavy load to light load, i.e., the load current decreases, the capacitor COUT is charged, and the output voltage VOUT increases. As Figure 8 shown, when the load current decreases from 80mA to 0, the output voltage VOUT increases by about 1.96mV.

[0153] The output voltage VOUT rises, causing the feedback voltage VFB1 to rise, so that the first control voltage Vgs1 rises, thereby causing the conduction current of the target transistor MP to decrease. In addition, the first control voltage Vgs1 rises, causing the conduction current of the second transistor M1 to decrease, thereby causing the conduction current of the mirror to decrease. Since the first reference current provided by the first current source IREF1 is unchanged, but the conduction current of the mirror decreases, the second control voltage Vgs2 rises, causing the conduction current of the first transistor M4 to decrease. Since the conduction current of the first transistor M4 and the conduction current of the target transistor MP both decrease, the charging speed of the capacitor COUT can be slowed down, thereby reducing the rising amplitude of the output voltage VOUT.

[0154] By reducing the conduction current of the first transistor M4 and the conduction current of the target transistor MP, a smaller load current is provided, the charging speed of the capacitor COUT is slowed down, and the rising amplitude of the output voltage is reduced. Compared with Figure 8 and Figure 2 It can be seen that when the current of the load decreases from 80 mA to 0, the rising amplitude of the output voltage VOUT of the circuit of the embodiment of the present application is about 1.96 mV, which is much smaller than the rising amplitude of the output voltage VOUT of 6.26 mV in the circuit of the related art. Since the rising amplitude of the output voltage of the embodiment of the present application is low, the transient response of the circuit is high, and the performance is better.

[0155] In the system, the voltage detection module can determine the first control voltage according to the output voltage of the target output terminal, the first adjusting module can determine the first current provided to the target output terminal according to the first control voltage, and the second adjusting module can determine the second current provided to the target output terminal according to the first control voltage. Since the first current and the second current are both used to stabilize the output voltage, in the case where the output voltage changes, the output voltage can be restored faster through the first current and the second current, the recovery speed of the output voltage is improved, the transient response of the circuit is improved, and the circuit performance is improved.

[0156] In an example embodiment, a chip is also provided, which includes the low-dropout linear voltage regulator circuit as Figures 4 to 7 described in any of the above.

[0157] In an example embodiment, an electronic device is also provided, which includes the chip as described above, and the chip includes the low-dropout linear voltage regulator circuit as described above. Optionally, the electronic device is a terminal device or a server.

[0158] It should be understood that the "multiple" mentioned herein refers to two or more than two. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after it are in an "or" relationship.

[0159] The above-mentioned sequence numbers of the embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0160] The above-mentioned only for the exemplary embodiments of the present application, and does not limit the present application, any modification, equivalent replacement, improvement, etc. made within the principles of the present application, should be included in the protection scope of the present application.

Claims

1. A low dropout linear voltage regulator circuit, characterized by comprising: The circuit comprises a voltage detection module, a first regulating module and a second regulating module; The voltage detection module is connected with a target output end of the low-dropout linear voltage stabilizing circuit, and is configured to output a first control voltage according to an output voltage of the target output end; The first regulating module is connected with the voltage detection module and the target output end respectively, and is configured to receive the first control voltage and provide a first current to the target output end according to the first control voltage; The second regulating module is connected with the voltage detection module and the target output end respectively, and is configured to receive the first control voltage and provide a second current to the target output end according to the first control voltage; The first control voltage and the output voltage are positively correlated, the first current and the second current are negatively correlated with the first control voltage, the output voltage is used to supply power for a load, an output current formed by the combination of the first current and the second current is used to provide a load current of the load, and the first current and the second current are both used to stabilize the output voltage.

2. The circuit of claim 1, wherein, The first regulating module comprises a first regulating unit, a first current source and a first transistor; The first regulating unit is connected with the voltage detection module and a gate of the first transistor respectively, and is configured to receive the first control voltage and provide a first target current to the gate of the first transistor according to the first control voltage; The first current source is connected with the gate of the first transistor, and is configured to provide a first reference current to the gate of the first transistor; A source of the first transistor is connected with a first input end, and a drain of the first transistor is connected with the target output end, and is configured to provide the first current to the target output end according to a second control voltage, the first input end is configured to provide a supply voltage, and the second control voltage is determined according to the first target current and the first reference current.

3. The circuit of claim 2, wherein, The first regulating unit comprises a second transistor and a first mirror component; A source of the second transistor is connected with the first input end, a drain of the second transistor is connected with the first mirror component, and a gate of the second transistor is connected with the voltage detection module, and is configured to receive the first control voltage and provide a first source current to the first mirror component according to the first control voltage; The first mirror component is connected with the gate of the first transistor, and is configured to receive the first source current and output the first target current to the gate of the first transistor, the first target current being a mirror current of the first source current.

4. The circuit of claim 3, wherein, The first mirror component comprises a third transistor and a fourth transistor; A source of the third transistor is grounded, a drain of the third transistor is connected with the drain of the second transistor, a gate of the third transistor is connected with the drain of the second transistor and a gate of the fourth transistor, and is configured to receive the first source current and provide a first gate current to the fourth transistor; The source of the fourth transistor is grounded, and the drain of the fourth transistor is connected with the gate of the first transistor, for receiving the first gate current and outputting the first target current to the gate of the first transistor.

5. The circuit of claim 1, wherein, The first adjusting module comprises a second adjusting unit, a first comparator, a fifth transistor and a first resistor, one end of the first resistor is connected with a first input terminal; The second adjusting unit is connected with the voltage detecting module and the first comparator respectively, for receiving the first control voltage, and providing a first target voltage to the first comparator according to the first control voltage; The first comparator is connected with the gate of the fifth transistor and a second input terminal, for receiving the first target voltage and a first reference voltage, and outputting a third control voltage to the gate of the fifth transistor according to the first target voltage and the first reference voltage, the second input terminal is used for providing the first reference voltage; The source of the fifth transistor is connected with the other end of the first resistor, and the drain of the fifth transistor is connected with the target output terminal, for providing the first current to the target output terminal according to the third control voltage, and the first input terminal is used for providing a power supply voltage.

6. The circuit of claim 5, wherein, The second adjusting unit comprises a sixth transistor and a second resistor, the second resistor is grounded and connected with the drain of the sixth transistor; The source of the sixth transistor is connected with the first input terminal, and the gate of the sixth transistor is connected with the voltage detecting module, for receiving the first control voltage and providing the first target voltage to the first comparator according to the first control voltage.

7. The circuit of claim 1, wherein, The circuit further comprises a third adjusting module; The third adjusting module is connected with the voltage detecting module, the target output terminal and a ground terminal respectively, for receiving the first control voltage and outputting a third current according to the first control voltage; The third current is the current from the target output terminal to the ground terminal, and the third current is used for stabilizing the output voltage.

8. The circuit of claim 1, wherein, The voltage detecting module comprises a sampling module and an error amplifier; The sampling module is connected with the target output terminal and the error amplifier respectively, for receiving the output voltage and outputting a feedback voltage to the error amplifier according to the output voltage; The error amplifier is connected with a third input terminal, for receiving the feedback voltage and a second reference voltage, and outputting the first control voltage according to the feedback voltage and the second reference voltage, the third input terminal is used for providing the second reference voltage.

9. The circuit of claim 1, wherein, The second adjusting module comprises a target transistor; The source of the target transistor is connected with a first input terminal, the drain of the target transistor is connected with the target output terminal, and the gate of the target transistor is connected with the voltage detecting module, for receiving the first control voltage and providing the second current to the target output terminal according to the first control voltage, and the first input terminal is used for providing a power supply voltage.

10. A chip, characterized by The chip comprises the low-dropout linear voltage stabilizing circuit according to any one of claims 1 to 9.

11. An electronic device, comprising: The electronic device comprises the chip according to claim 10.

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