Memory compression with improved lookup table scheme

Abstract

The invention relates to memory compression with an improved lookup table scheme. A system can include: a memory; and a processing device operably coupled with the memory to perform operations including: segmenting the memory into a plurality of memory partitions, where each of the plurality of memory partitions is associated with a corresponding partition identifier; receiving a host command for accessing data; identifying a compression ratio of the data; identifying a memory partition of the plurality of memory partitions; identifying a location of a plurality of locations on the memory partition by using a segment identifier and a unit offset address, where each of the plurality of locations is associated with a corresponding segment identifier, and where the unit offset address is determined in view of a compression ratio range associated with the memory partition; and performing an operation on the data at the identified location on the memory partition.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to implementing memory compression in a memory subsystem with an improved lookup table scheme. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure relates to a system comprising: a memory; and a processing device operably coupled to the memory to perform operations comprising: dividing the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; receiving a host command to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a range of compression ratios associated with the memory partition; and performing operations on the data at the identified location on the memory partition.

[0004] On the other hand, the present disclosure relates to a method, comprising: dividing a memory into a plurality of memory partitions by a processing device, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; receiving a host command to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a range of compression ratios associated with the memory partition; and performing an operation on the data at the identified location on the memory partition.

[0005] On the other hand, the present disclosure relates to a non-transitory computer-readable storage medium, comprising instructions that, when executed by a processing device, cause the processing device to perform operations including: partitioning a memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; receiving a host command to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a range of compression ratios associated with the memory partition; and performing operations on the data at the identified location on the memory partition. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more completely understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 is a block diagram of an example system implementing memory compression with an improved lookup table scheme according to some embodiments of the present disclosure.

[0009] Figure 3A An example of partitioning a memory to implement memory compression according to some embodiments of the present disclosure is described.

[0010] Figure 3B An example of a memory segment for implementing memory compression according to some embodiments of the present disclosure is described.

[0011] Figure 4 An example of a data structure for implementing memory compression according to some embodiments of the present disclosure is described.

[0012] Figure 5 is a flow chart of an example method for implementing memory compression with an improved lookup table scheme according to some embodiments of the present disclosure.

[0013] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to implementing memory compression using an improved lookup table scheme. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data stored at the memory subsystem and may request data retrieved from the memory subsystem.

[0015] Memory compression can be used to increase the amount of data that can be stored in memory by compressing the contents of the memory. For example, data can be compressed after being stored in memory and decompressed after retrieval. However, compression and decompression operations are computationally intensive and increase access time. Therefore, there is a trade-off between reducing the size of the stored data and increasing overhead, such as increased access time and processing caused by compression. It is desirable to compress data because the benefit of reducing the size of the data outweighs the cost of increased latency over a period of time and the cost of additional access and processing caused by compression and decompression.

[0016] In addition, cache can be used to speed up access to data stored on slower media by temporarily storing portions of the data on faster media that can be accessed faster than slower media. Thus, data in the cache can be read faster than data not in the cache.

[0017] In one example, when the host system sends a request to write data, the memory subsystem controller can compress the data and track the available memory in the memory. The memory subsystem controller can assign a compression address to the compressed data and can write the compressed data at the compression address. The compression address is a memory physical address that references the starting position of the compressed data. Depending on the compression ratio, the compressed data may or may not occupy the entire free space in the memory (e.g., a free cache line, which is the smallest data portion that can be mapped into the cache). The length of the compressed data may depend on the compression ratio of the given data. The request to write data includes a host physical address, and when the compression address is assigned, the compression address is mapped to the host physical address. The memory subsystem controller can maintain a lookup table in the memory to keep a record of the host physical address, the compression address, the length of the compressed data, and the compression ratio. Using the lookup table, the memory subsystem controller can translate between the host physical address and the compression address. In some embodiments, the memory subsystem controller can use a lookup table cache to cache the lookup table. In some embodiments, depending on the cache implementation strategy (i.e., write-through or write-back), the lookup table in the memory can be updated according to the lookup table cache. Because the content stored in the lookup table includes the full address of the host physical address and the full address of the compressed address and the two full addresses occupy a large amount of memory size, the lookup table cache is usually not used to store many contents of the lookup table. When using the lookup table cache to read compressed data, this can cause additional latency penalties.

[0018] Specifically, when the host system sends a request to read data, the memory subsystem controller can use the host memory address specified in the request to search in the lookup table cache and determine whether there is a cache hit or a cache miss in the lookup table cache. If the cache hits, the request content associated with the host memory address is found in the lookup table cache; and if the cache misses, the request content is missing from the lookup table cache. If the search results in a cache miss, the host system accesses the lookup table in the memory and extracts the entry corresponding to the host memory address of the lookup table into the lookup table cache. If the search results in a cache hit, the host system uses the host physical address to obtain the corresponding compressed address, the length of the compressed data, and the compression ratio from the lookup table cache. The compressed data is then read using the compressed address (reference to the starting position of the compressed data) and the length of the compressed data. The host system decompresses the compressed data and sends the decompressed data to the system or device requesting the data. As described above, cache misses that require additional search and extraction steps introduce latency and bandwidth overhead associated with compression. Thus, it is desirable that the size of the memory designated for the lookup table cache is large enough to ensure a high cache hit rate. However, the storage capacity of the cache is typically small compared to the capacity of the memory used for the lookup table. Furthermore, determining whether a particular data item is stored in the cache is difficult because future access requests are typically unpredictable.

[0019] In addition, as memory accesses are performed out of order across the entire memory space, the memory becomes increasingly fragmented, and the size of the compressed data may vary depending on the compression ratio. It is difficult to find contiguous memory space within the fragmented memory to accommodate the compressed data, resulting in suboptimal memory utilization. Suboptimal memory utilization will also require costly tracking of fragmented free space, such as tracking the start address and length of the data.

[0020] Aspects of the present disclosure address the above and other disadvantages by implementing memory compression with an improved lookup table scheme. The improved lookup table scheme uses an improved lookup table to translate host physical addresses into compressed addresses for access operations on data in compressed form. The improved lookup table can be used to store identifiers associated with the memory instead of full addresses. These identifiers can be used to reference locations in the memory that can be used as compressed addresses. The improved lookup table requires a reduced size for storage, and thus, the improved lookup table scheme will provide a higher cache hit rate.

[0021] In order to implement the improved lookup table scheme, the memory compression manager in the subsystem controller may divide the memory into a set of memory partitions. The memory is designated for storing data, at least some of which is in compressed form. Each memory partition may be referenced by a corresponding partition identifier. The size of each memory partition is configurable. The memory compression manager may associate a compression ratio range with the memory partition so that the data stored in the memory partition is compressed with a compression ratio that falls within the range. The compression ratio (CR) refers to the ratio between the size of the data in uncompressed form and in compressed form (e.g., 2:1, 4:1, 8:1). Each memory partition corresponds to a compression ratio range (e.g., 2:1≤CR<4:1, 4:1≤CR<8:1, CR≥8:1). In some implementations, the subsystem controller may associate a compression ratio range with a memory partition when the memory partition is allocated for storing data.

[0022] The memory compression manager receives a request to write data in the memory, and the request may specify a host physical address. The memory compression manager may compress the data (e.g., by a compression component) and obtain a compression ratio for compressing the data. The memory compression manager identifies a memory partition in the memory partition group based on the compression ratio. In some embodiments, the memory compression manager may determine that the compression ratio falls within a compression ratio range and identify a memory partition associated with this range. The memory compression manager may obtain a partition identifier that identifies the memory partition.

[0023] The memory compression manager then determines the location for storing compressed data in the identified memory partition. For example, the memory compression manager can determine the location based on the available space in the identified memory partition. The location can be identified using a unit offset address and a segment identifier. Specifically, the memory compression manager can determine the unit offset address in view of the compression ratio range associated with the memory partition, and determine the segment identifier that specifies how many unit offset addresses will be shifted from the starting address of the memory partition. The unit offset address refers to the unit address shifted from the starting address of the memory partition to the location for storing compressed data. That is, the unit offset address is equal to the offset between the starting addresses of adjacent segment identifiers. By using the partition identifier, the segment identifier and the unit offset address, the location for storing compressed data in the identified memory partition of the host memory can be identified. In some implementations, the location refers to the starting location for storing compressed data and is selected from a group of locations, and the location group is determined according to the compression ratio range associated with the memory partition. For example, a compression ratio range associated with a memory partition may indicate a minimum value within the compression ratio range, the number of locations in the memory partition is determined based on the minimum value within the compression ratio range, and the offset between adjacent locations in a location group is equal to a unit offset address, so that the location group divides the memory partition into segments of equal size.

[0024] As described above, the memory compression manager may obtain a partition identifier that identifies a memory partition and a segment identifier associated with the identified memory partition. The identifier, when used with a single-bit offset address, may reference a location (also referred to as a compressed address) where compressed data is stored. That is, the partition identifier may be used to reference a memory partition for storing compressed data, and the segment identifier used with the single-bit offset address may reference a location within the memory partition where compressed data is stored. The memory compression manager may store the identifier in a lookup table. Because the size of the identifier is small, the size of the lookup table will also be small. Thus, when the memory compression manager uses a lookup table cache, the lookup table cache may contain most (if not all) of the contents of the lookup table without much concern for size limitations.

[0025] In some embodiments, the memory compression manager may further index the host physical address specified in the request and use the host physical address (HPA) index to sort in the lookup table. For each write request, the HPA index points to an entry in the lookup table, where the entry includes a partition identifier that identifies the memory partition and a segment identifier associated with the identified memory partition. In some embodiments, the memory compression manager may store a compression ratio value (e.g., a compression ratio for compressed data that can be used to derive a minimum value within a range of compression ratios associated with the identified memory partition) that can be used to obtain a unit offset address for the identified memory partition in the lookup table.

[0026] When the memory compression manager receives a request to read data stored in compressed form, the request may specify a host physical address. The memory compression manager may determine an HPA index based on the host physical address. The host system controller may use the HPA index to locate an entry in the lookup table cache. In response to locating the entry in the lookup table cache, the host system controller may obtain a compression ratio value for a partition identifier, a segment identifier, and a unit offset address. The compression ratio value is used to obtain the unit offset address. The partition identifier is used to reference a memory partition for reading compressed data, and the segment identifier with the unit offset address is used to reference a location within the memory partition for reading compressed data. Thus, the memory compression manager may obtain a compression address that references a location for reading compressed data.

[0027] Advantages of the present disclosure include: reducing the amount of data stored in the lookup table cache so that a higher cache hit rate can be achieved with a small cache size; and reducing operation complexity and latency through address shifting for translation between host physical addresses and compressed addresses. Aspects of the present disclosure also improve system performance through higher cache hit rates and simple address translation. Compared to existing memory compression schemes with longer latency and high bandwidth overhead, aspects of the present disclosure minimize latency and bandwidth overhead to increase memory compression value at a lower cost.

[0028] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (such as memory device 140), one or more non-volatile memory devices (such as memory device 130), or a combination thereof.

[0029] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0030] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0031] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0032] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0033] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] The NVMe interface is a communication interface / protocol developed to enable SSDs to operate on a host and memory device linked by a PCIe interface. The NVMe protocol provides a command queue and completion path for accessing data stored in the memory device by the host system 120. In some embodiments, the interface between the host system and the memory device may implement one or more alternative protocols supported by another interface standard. For example, the interface may implement one or more alternative protocols supported by PCIe (e.g., non-PCIe protocols). In some embodiments, the interface may be represented by a Compute Express Link (CXL) interface or any communication link that allows cache line granularity updates and shared coherency control with a processing device.

[0035] The CXL system is a cache-coherent interconnect for processors, memory extensions, and accelerators. The CXL system maintains memory coherence between the CPU memory space and the memory on the attached device, which allows resource sharing to achieve higher performance, reduce software stack complexity, and reduce total system cost. In general, CXL is an interface standard that can support several protocols that can run on top of PCIe, including the CXL.io protocol, the CXL.mem protocol, and the CXL.cache protocol. The CXL.io protocol is a PCIe-like protocol that can be considered an "enhanced" PCIe protocol that can partition managed memory. CXL.io can be used for initialization, linking, device discovery and enumeration, register access, and can provide an interface for I / O devices. The CXL.mem protocol enables the host to access the memory of the attached device using memory semantics (e.g., load and store commands). This method can support both volatile and persistent memory architectures. The CXL.cache protocol can define host-device interactions to achieve efficient caching of host memory with low latency using a request and response method. Traffic (such as NVMe traffic) can run over the CXL.io protocol, and the CXL.mem and CXL.cache protocols can share a common link layer and transaction layer. Therefore, the CXL protocol can be multiplexed and transmitted over the PCIe physical layer.

[0036] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0037] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can perform bit storage based on body resistance changes in combination with a stackable cross-gate data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0038] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks. Some types of memory, such as 3D crosspoints, may group pages across dies and channels to form management units (Mu).

[0039] Although non-volatile memory components such as a 3D cross-point array of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory or electrically erasable programmable read-only memory (EEPROM).

[0040] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0041] The memory subsystem controller 115 may include a processing device, including one or more processors, such as the processor 117, configured to execute instructions stored in the local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0042] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0043] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system that communicates with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0044] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0045] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., the local media controller 135) located on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0046] In some embodiments, the memory device 140 includes a lookup table 116 for storing mapping information for compressed data, such as Figures 2 to 6 Detailed description. In some embodiments, the driver of the storage subsystem controller 115 may allocate one or more portions of the local memory 119 that can be accessed more quickly (referred to herein as cache). In some implementations, the cache may include a lookup table cache 118 for caching the contents of the lookup table 116.

[0047] In some embodiments, the memory subsystem controller 115 includes a memory compression manager 113. In some embodiments, the memory compression manager 113 is part of an application or operating system. More details on the operation of the memory compression manager 113 are provided below. Figures 2 to 6 describe.

[0048] It will be appreciated by those skilled in the art that additional circuitry and signals may be provided and simplified. Figure 1 It should be recognized that the reference Figure 1 The functionality of the various block components described is not necessarily separated into distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1 Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1 The functionality of a single block component.

[0049] Figure 22 is a schematic block diagram of a system 200 for implementing memory compression using an improved lookup table scheme. In various embodiments, the system 200 may be a memory subsystem (e.g., the memory subsystem 110). In various embodiments, the system 200 may include a memory compression manager 113, a compression / decompression component 211, a memory 205, a lookup table 206, and a lookup table cache 207. In some embodiments, aspects of the memory compression manager 113 (including hardware and / or firmware functionality) are included in the compression / decompression component 211.

[0050] The compression / decompression component 211 can compress data into a compressed form and / or decompress the compressed data. For example, the compressed form can be generated by a computer program instruction executed on a server computing device or by a memory subsystem. Compression and decompression can be performed using a Lempel-Zip compressor or other suitable compression algorithm. The compression algorithm can be implemented using computer program instructions, hardware devices, or a combination thereof. Data compression can be performed before storing the data in the memory 205. Similarly, data decompression can be performed after retrieving the compressed form of the data from the memory 205. The compression and decompression operations can be performed in response to requests to store and retrieve data in the memory 205, respectively. Because the compressed form is stored in the memory 205, the same data item actually uses less memory space in the memory 205 compared to the uncompressed form. Due to the compression and decompression operations, data write and data read operations performed on the memory 205 generally have greater delays than data write and data read operations performed on the uncompressed form. The present disclosure illustrated with the system 200 can reduce delays and reduce processor usage introduced by the compression and decompression operations.

[0051] The memory 205 is designated for storing data, at least some of which is compressed. The memory 205 may be a volatile memory device, such as a RAM. The memory compression manager 113 may partition the memory 205 into a set of memory partitions, and each memory partition may be referenced by a corresponding partition identifier. The size of each memory partition is configurable. In some embodiments, the size of each memory partition is the same. For example, the memory 205 has a size of 512GB, and the memory compression manager 113 partitions the memory 205 into 512 1GB memory partitions. The memory compression manager 113 may associate a compression ratio range with the memory partition so that the data stored in the memory partition will have a compression ratio that falls within a range. Thus, each memory partition corresponds to a compression ratio range. In some embodiments, the memory compression manager 113 may associate a compression ratio range with the memory partition when the memory partition is allocated for storing data.

[0052] As Figure 3A, the memory compression manager 113 may partition the memory 205 into a plurality of memory partitions, where each memory partition may be identified by a corresponding partition identifier (Partition 1, Partition 2, Partition 3, or Partition X). At time start, within partition 310A, Partition 1, Partition 2, Partition 3, and Partition X are not yet allocated for use. At time t1, within partition 320A, for example, when the memory compression manager 113 receives a request to access data, Partition 1 is allocated for use, where the data has been compressed according to a compression ratio within a first range (e.g., 2:1≤CR<4:1). The memory compression manager 113 thus associates the first range of compression ratios with Partition 1. Partition 1 will be used to store compressed data in response to the request. At time t1, within partition 320A, Partition 2, Partition 3, and Partition X are not yet allocated for use. When the memory compression manager 113 receives another request to access data, where the data has also been compressed according to a compression ratio within the first range, if Partition 1 has not yet reached its maximum storage capacity, then Partition 1 will be used to store compressed data in response to this request.

[0053] At time t2, within partition 330A, for example, when the memory compression manager 113 receives a request to access data, partition 2 is allocated for use, where the data has been compressed according to a compression ratio within a second range (e.g., 4:1≤CR<8:1). The memory compression manager 113 thus associates the second range of compression ratios with partition 2. Partition 2 will be used to store compressed data in response to the request. At time t2, within partition 330A, partition 3 and partition X have not been allocated for use. When the memory compression manager 113 receives another request to access data, where the data has also been compressed according to a compression ratio within the second range, if partition 2 has not yet reached its maximum storage capacity, then partition 2 will be used to store compressed data in response to this request.

[0054] At time t3, within partition 340A, for example, when the memory compression manager 113 receives a request to access data, partition 3 is allocated for use, where the data has been compressed according to a compression ratio within a first range (e.g., 2:1≤CR<4:1), but partition 1 has reached its maximum storage capacity. The memory compression manager 113 therefore associates the first range of compression ratios with partition 3. Partition 3 will be used to store compressed data in response to the request. At time t3, within partition 340A, partition X has not been allocated for use. When the memory compression manager 113 receives another request to access data, where the data has also been compressed according to a compression ratio within the first range, if partition 3 has not reached its maximum storage capacity, then partition 3 will be used to store compressed data in response to this request.

[0055] Return to reference Figure 2, a request 251 to write data is received by the compression / decompression component 211. The write request 251 may include the data to be compressed. The write request 251 may specify a host physical address. In some embodiments, the compression / decompression component 211 may compress the data and obtain a compression ratio for the compressed data. In some embodiments, the compression / decompression component 211 may determine the compression ratio and compress the data accordingly. The compression / decompression component 211 may send a request 253 to store the compressed data to the memory compression manager 113. The request 253 may specify a compression ratio associated with the compressed data.

[0056] The memory compression manager 113 may identify a memory partition in the memory partition group based on the compression ratio. The memory compression manager 113 may determine that the compression ratio specified in the request 253 falls within a compression ratio range and identify a memory partition associated with the range. For example, Figure 3B 350B. The memory compression manager 113 may determine that the compression ratio specified in the request 253 falls within the first range, and identify the memory partition associated with the first range, as shown in FIG. 360B. The memory compression manager 113 may determine that the compression ratio specified in the request 253 falls within the second range, and identify the memory partition associated with the second range, as shown in FIG. 370B. The memory compression manager 113 may determine that the compression ratio specified in the request 253 falls within the third range, and identify the memory partition associated with the third range, as shown in FIG. 370B. The memory compression manager 113 may obtain a partition identifier that identifies the memory partition.

[0057] The memory compression manager 113 then determines a location in the identified memory partition for storing compressed data. For example, the memory compression manager 113 may determine the location based on the available space in the identified memory partition. The location may be identified using a unit offset address and a segment identifier. Specifically, the memory compression manager 113 may determine the unit offset address in view of the compression ratio range associated with the memory partition, and determine the segment identifier that specifies how many unit offset addresses will be shifted. By using the partition identifier, the segment identifier, and the unit offset address, a location in the identified memory partition of the memory 205 for storing compressed data may be identified. In some implementations, the location refers to a starting location for storing compressed data and is selected from a group of locations, and the group of locations is determined based on the compression ratio range associated with the memory partition. In some implementations, the number of locations in the memory partition is determined based on the minimum value within the compression ratio range, and the offset between the locations is equal to the unit offset address so that the location divides the memory partition into segments of equal size.

[0058] For example, as Figure 3B 350B shown in FIG. 350B , when the memory partition is associated with a first range of compression ratios (i.e., 2:1≤CR<4:1), the number of locations, and therefore the number of segments of the memory partition, is equal to the minimum value of the first range (i.e., 2). In the example, the two locations include address [0X4000_0000] and address [0X2000_0000], where address [0X4000_0000] is a modified physical address corresponding to the starting position of the second segment (e.g., Seg1) of the memory partition, and address [0X2000_0000] is a modified physical address corresponding to the starting position of the first segment (e.g., Seg0) of the identified memory partition. In the example, the two-segment configuration is determined based on a 2:1 compression ratio scheme. Address [0X2000_0000] is a 1-bit shift from address [0X4000_0000], and the shift corresponds to a single-bit offset address of [0X2000_0000].

[0059] When the memory compression manager 113 receives the request 253, if the memory partition is not yet in use or the first segment of the memory partition has the capacity to store the compressed data in the request 253, the memory compression manager 113 may identify the location for storing the compressed data as the starting location of the first segment of the memory partition. Therefore, the memory compression manager 113 may obtain a segment identifier that references the second segment (e.g., Seg1). The memory compression manager 113 may then calculate the location by, for example, multiplying the value of the segment identifier by a unit offset address (e.g., multiplying 2 by [0X2000_0000]) and determine the calculated location as the location in the memory partition of the memory 205 for storing the compressed data.

[0060] When the memory compression manager 113 receives the request 253, if the memory partition is already in use or the first segment of the memory partition has reached its maximum capacity, the memory compression manager 113 may identify the location for storing the compressed data as the starting location of the second segment of the memory partition. Therefore, the memory compression manager 113 may obtain a segment identifier that references the first segment (e.g., Seg0). The memory compression manager 113 may then calculate the location by, for example, multiplying the value of the segment identifier by a unit offset address (e.g., multiplying 1 by [0X2000_0000]) and determine the calculated location as the location in the memory partition of the memory 205 for storing the compressed data.

[0061] For the second range, the location includes address [0X4000_0000], address [0X3000_0000], address [0X2000_0000], and address [0X1000_0000], wherein address [0X4000_0000] is a modified physical address corresponding to a start address of a fourth segment (e.g., Seg3) of the identified memory partition, address [0X3000_0000] is a modified physical address corresponding to a start address of a third segment (e.g., Seg2) of the identified memory partition, address [0X2000_0000] is a modified physical address corresponding to a start address of a second segment (e.g., Seg1) of the identified memory partition, and address [0X1000_0000] is a modified physical address corresponding to a start address of a first segment (e.g., Seg0) of the identified memory partition. The 4-segment configuration is determined based on a 4:1 compression ratio scheme, which corresponds to a minimum compression scheme in the range. Address [0X1000_0000] is a 2-bit shift from address [0X4000_0000]. For the third range, the location includes 8 addresses, each of which corresponds to the start address of a segment, and the memory partition includes 8 segments. The 8-segment configuration is determined based on an 8:1 compression ratio scheme, which corresponds to the minimum compression scheme in the range. Address [0X0800_0000] is a 4-bit shift from address [0X4000_0000].

[0062] As Figure 3BAs shown in Figure 360B, when the memory partition is associated with a second range of compression ratios (i.e., 4:1≤CR<8:1), the number of locations, and therefore the number of segments of the memory partition, is equal to the minimum value of the second range (i.e., 4). In the example, the 4 locations include address [0X4000_0000], address [0X3000_0000], address [0X2000_0000], and address [0X1000_0000], wherein address [0X4000_0000] is a modified physical address corresponding to the start position of the fourth segment (e.g., Seg3) of the memory partition, address [0X3000_0000] is a modified physical address corresponding to the start position of the third segment (e.g., Seg2) of the memory partition, address [0X2000_0000] is a modified physical address corresponding to the start position of the second segment (e.g., Seg1) of the memory partition, and address [0X1000_0000] is a modified physical address corresponding to the start position of the first segment (e.g., Seg0) of the identified memory partition. In the example, the 4-segment configuration is determined based on a 4:1 compression ratio scheme. The address [0X1000_0000] is a 2-bit shift from the address [0X4000_0000], and the shift corresponds to a unit offset address of [0X1000_0000].

[0063] When the memory compression manager 113 receives the request 253, if the memory partition is not yet in use or the first segment of the memory partition has capacity to store the compressed data in the request 253, the memory compression manager 113 may identify the location for storing the compressed data as the starting location of the first segment of the memory partition. Therefore, the memory compression manager 113 may obtain a segment identifier that references the fourth segment (e.g., Seg3). The memory compression manager 113 may then calculate the location by, for example, multiplying the value of the segment identifier by a unit offset address (e.g., multiplying 4 by [0X1000_0000]) and determine the calculated location as the location in the memory partition of the memory 205 for storing the compressed data.

[0064] When the memory compression manager 113 receives the request 253, if the memory partition is already in use or the first segment of the memory partition has reached its maximum capacity, the memory compression manager 113 may identify the location for storing the compressed data as the starting location of the second segment of the memory partition. Therefore, the memory compression manager 113 may obtain a segment identifier that references the third segment (e.g., Seg2). The memory compression manager 113 may then calculate the location by, for example, multiplying the value of the segment identifier by a unit offset address (e.g., multiplying 3 by [0X1000_0000]) and determine the calculated location as the location in the memory partition of the memory 205 for storing the compressed data.

[0065] When the memory compression manager 113 receives the request 253, if the first and second segments of the memory partition have reached their maximum capacities, the memory compression manager 113 may identify the location for storing the compressed data as the starting location of the third segment of the memory partition. Therefore, the memory compression manager 113 may obtain a segment identifier that references the second segment (e.g., Seg1). The memory compression manager 113 may then calculate the location by, for example, multiplying the value of the segment identifier by a unit offset address (e.g., multiplying 2 by [0X1000_0000]) and determine the calculated location as the location in the memory partition of the memory 205 for storing the compressed data.

[0066] When the memory compression manager 113 receives the request 253, if the first, second, and third segments of the memory partition have reached their maximum capacity, the memory compression manager 113 may identify the location for storing compressed data as the starting location of the fourth segment of the memory partition. Therefore, the memory compression manager 113 may obtain a segment identifier that references the first segment (e.g., Seg0). The memory compression manager 113 may then calculate a location by, for example, multiplying the value of the segment identifier by a unit offset address (e.g., multiplying 1 by [0X1000_0000]) and determine the calculated location as the location in the memory partition of the memory 205 for storing compressed data.

[0067] As Figure 3BAs shown in Figure 370B, when the memory partition is associated with the third range of compression ratios (i.e., CR≥8:1), the number of locations, and therefore the number of segments of the memory partition, is equal to the minimum value of the third range (i.e., 8). In the example, the eight locations include address [0X4000_0000], address [0X3800_0000], address [0X3000_0000], address [0X2800_0000], address [0X2000_0000], address [0X1800_0000], address [0X1000_0000], and address [0X0800_0000], wherein address [0X4000_0000] is a modified physical address corresponding to the starting position of the eighth segment (e.g., Seg7) of the memory partition, address [0X3800_0000] is a modified physical address corresponding to the starting position of the seventh segment (e.g., Seg6) of the memory partition, and address [0X3000_0000] is a modified physical address corresponding to the starting position of the sixth segment (e.g., Seg7) of the memory partition. The modified physical address of the starting position of the memory partition (e.g., Seg5), the modified physical address of the starting position of the fifth segment (e.g., Seg4) of the memory partition, the modified physical address of the starting position of the fourth segment (e.g., Seg3) of the memory partition, the modified physical address of the starting position of the third segment (e.g., Seg2) of the memory partition, the modified physical address of the starting position of the second segment (e.g., Seg1) of the identified memory partition, and the modified physical address of the starting position of the first segment (e.g., Seg0) of the identified memory partition. In the example, the 8-segment configuration is determined based on an 8:1 compression ratio scheme. The address [0X0800_0000] is a 4-bit shift from the address [0X4000_0000], and the shift corresponds to a single-bit offset address of [0X0800_0000].

[0068] When the memory compression manager 113 receives the request 253, if the memory partition is not yet in use or the first segment of the memory partition has the capacity to store the compressed data in the request 253, the memory compression manager 113 may identify the location for storing the compressed data as the starting location of the first segment of the memory partition. Therefore, the memory compression manager 113 may obtain a segment identifier that references the eighth segment (e.g., Seg7). The memory compression manager 113 may then calculate the location by, for example, multiplying the value of the segment identifier by a unit offset address (e.g., multiplying 8 by [0X0800_0000]) and determine the calculated location as the location in the memory partition of the memory 205 for storing the compressed data.

[0069] When the memory compression manager 113 receives the request 253, if the memory partition is already in use or the first segment of the memory partition has reached its maximum capacity, the memory compression manager 113 may identify the location for storing the compressed data as the starting location of the second segment of the memory partition. Therefore, the memory compression manager 113 may obtain a segment identifier that references the seventh segment (e.g., Seg6). The memory compression manager 113 may then calculate the location by, for example, multiplying the value of the segment identifier by a unit offset address (e.g., multiplying 7 by [0X0800_0000]) and determine the calculated location as the location in the memory partition of the memory 205 for storing the compressed data.

[0070] The process for determining the sixth segment (e.g., Seg5) and the corresponding position (e.g., multiplying 6 by [0X0800_0000]), the fifth segment (e.g., Seg4) and the corresponding position (e.g., multiplying 5 by [0X0800_0000]), the fourth segment (e.g., Seg3) and the corresponding position (e.g., multiplying 4 by [0X0800_0000]), the third segment (e.g., Seg2) and the corresponding position (e.g., multiplying 3 by [0X0800_0000]), the second segment (e.g., Seg1) and the corresponding position (e.g., multiplying 2 by [0X0800_0000]), and the first segment (e.g., Seg0) and the corresponding position (e.g., multiplying 1 by [0X0800_0000]) is similar to the description above.

[0071] Return to reference Figure 2 For request 253, the memory compression manager 113 may obtain a partition identifier that identifies a memory partition and a segment identifier associated with the identified memory partition. The identifier, when used with a single-bit offset address, may reference an address storing compressed data (also referred to as a compressed address). That is, the partition identifier may be used to reference a memory partition for storing compressed data, and the segment identifier used with a single-bit offset address may reference a location within the memory partition storing compressed data. The memory compression manager 113 may store the identifier in the lookup table 206. Because the size of the identifier is small, the size of the lookup table 206 will also be small. For example, assume that a memory device of size 512 GB is divided into 512 memory partitions, each of which is 1 GB in size. The partition identifier requires only 9 bits of space. For an 8-segment configuration, the segment identifier requires only 3 bits of space. Thus, when the memory compression manager 113 uses a cache (e.g., the lookup table cache 207), the lookup table cache 207 may contain most (if not all) of the contents of the lookup table 206 without much concern for size limitations. In some implementations, the lookup table 206 may be stored in DRAM and the lookup table cache 207 may be stored in SRAM. In some implementations, the lookup table 206 may be stored in the same device as the memory 205.

[0072] The memory compression manager 113 may further index the host physical address specified in the request 253 and use the host physical address (HPA) index to sort in the lookup table 260. For the request 253, the HPA index points to an entry in the lookup table 260, where the entry includes a partition identifier identifying the memory partition and a segment identifier associated with the identified memory partition. In some implementations, the memory compression manager 113 may store a compression ratio value (e.g., 2:1 in FIG. 350B, 4:1 in FIG. 360B, 8:1 in FIG. 370B) associated with the unit offset address identifying the memory partition in the lookup table 206. In some implementations, the compression ratio value stored in the lookup table 206 is the same as the compression ratio used to compress the data in the request 253. Figure 4 An example lookup table 400 is illustrated. The lookup table 400 includes a plurality of records. Each record may correspond to a request to store compressed data. Each record includes a partition identifier 420, a segment identifier 430, and a compression ratio value (for a unit offset address) 440.

[0073] Return to reference Figure 2 , a request 252 to read data is received by the memory compression manager 113. The read request 252 may specify a host physical address indicating a location where the data to be read is located. The memory compression manager 113 may determine an HPA index based on the host physical address. The memory compression manager 113 may use the HPA index to locate an entry in the lookup table cache 207. In response to locating the entry in the lookup table cache 207, the memory compression manager 113 may obtain a compression ratio value for the partition identifier, the segment identifier, and the unit offset address in the entry. The compression ratio value is used to obtain the unit offset address, such as the compression ratio value for the partition identifier, the segment identifier, and the unit offset address. Figure 3B Description. The partition identifier is used to reference the memory partition for reading compressed data, and the segment identifier with a single-bit offset address is used to reference the location within the memory partition where the compressed data is read. Thus, the memory compression manager 113 can obtain a compression address that references the location where the compressed data is read.

[0074] exist Figure 3B In the example of FIG. 350B in FIG. 350B , a compression ratio of 2:1 is used to obtain a single-bit offset address [0X2000_0000]; assuming the partition number is Partition 1 and the segment identifier is Seg0, the compressed address can be represented as "Partition 1 && Seg0 && [0X2000_0000]", which references the 50% line position of the block in FIG. 350B . Figure 3BIn the example of FIG. 360B in FIG. 360B , a compression ratio of 4:1 is used to obtain a single-bit offset address [0X1000_0000]; assuming the partition number is Partition 1 and the segment identifier is Seg0, the compressed address can be represented as "Partition 1 && Seg0 && [0X1000_0000]", which references the 25% line position of the block in FIG. 360B . Figure 3B In the example of Figure 370B, a compression ratio of 8:1 is used to obtain the unit offset address [0X0800_0000]; assuming the partition number is Partition 1 and the segment identifier is Seg0, the compressed address can be expressed as "Partition 1&&Seg0&&[0X0800_0000]", which references the 12.5% ​​line position of the block in Figure 370B.

[0075] Return to reference Figure 2 , the memory compression manager 113 may access the memory 205 at the location referenced by the compression address and read the compressed data, and send the compressed data 254 to the compression / decompression component 211 to decompress the compressed data.

[0076] In some implementations, certain ranges of compression ratios may be used more frequently than other ranges. Figure 3A and 3B In the example, the first range (e.g., 2:1≤CR<4:1) may be used more frequently than the second range (e.g., 4:1≤CR<8:1) and the third range (e.g., CR≥8:1). Thus, more memory partitions will be associated with a particular range than other ranges of compression ratios, and this may help limit the number of different compression ratio ranges used in memory compression, thereby reducing the complexity of configuring the lookup table.

[0077] Figure 5 5 is a flow chart of an example method 500 for implementing memory compression using an improved lookup table scheme according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 and Figure 2 The memory compression manager 113 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, unless otherwise specified, the order of the processes may be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not every embodiment requires all processes. Other process flows are possible.

[0078] At operation 510, processing logic may partition the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier. In some implementations, the memory may be Figure 1 The host memory 105 or Figure 2 205 of the memory. In some embodiments, the processing logic may associate the compression ratio range with the memory partition. In some embodiments, the processing logic may associate the compression ratio range with the memory partition in response to receiving a first data access request for the memory partition. In some embodiments, the memory is a volatile memory device.

[0079] At operation 520, processing logic may receive a host command to access (e.g., write or read) data. In some embodiments, the host command specifies a host physical address. At operation 530, processing logic may identify a compression ratio for the data. In some embodiments, processing logic identifies the compression ratio by calculating the compression ratio for the compressed data after the data is compressed. In some embodiments, processing logic identifies the compression ratio by searching in a lookup table or a lookup table cache, for example, when the host command is a read command and specifies a host physical address that can be used to index in the lookup table or the lookup table cache.

[0080] At operation 540, processing logic may identify a memory partition in a plurality of memory partitions. In some embodiments, processing logic determines whether a compression ratio of the data falls within a compression ratio range. In some embodiments, in response to determining that the compression ratio of the data falls within a compression ratio range, processing logic identifies a memory partition in a plurality of memory partitions. In some embodiments, processing logic obtains a partition identifier that identifies the memory partition. In some embodiments, processing logic may identify a partition identifier by searching in a lookup table or a lookup table cache, for example, when a host command is a read command and specifies a host physical address that can be used to index in a lookup table or a lookup table cache, and identify the memory partition by using the partition identifier.

[0081] At operation 550, processing logic can identify the position in a plurality of positions on the memory partition by using segment identifier and unit offset address, wherein each of the plurality of positions is associated with the corresponding segment identifier, and wherein the unit offset address is determined in view of the compression ratio range associated with the memory partition. In some embodiments, a plurality of positions on the memory partition are determined based on the compression ratio range associated with the memory partition. In some embodiments, a plurality of positions on the memory partition are determined based on the minimum value of the compression ratio range associated with the memory partition. In some embodiments, the distance between adjacent positions in a plurality of positions on the memory partition is the same. In some embodiments, the number of positions on the memory partition is equal to the minimum value of the compression ratio range associated with the memory partition.

[0082] In some embodiments, processing logic may store a record indexable by a physical address specified in a host command in a data structure, wherein the record includes a partition identifier and a segment identifier for a memory partition. In some embodiments, the record includes a value within a compression ratio range associated with the memory partition. In some embodiments, processing logic may cache the data structure.

[0083] At operation 560, processing logic may perform an operation with respect to the data at the identified location on the memory partition. The operation may write the data at the identified location on the memory partition, wherein the data is in compressed form. The operation may read the data at the identified location on the memory partition, wherein the data is in compressed form; and the read data may then be decompressed.

[0084] Figure 6 An example machine illustrating a computer system 600 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110) or can be used to perform operations of the controller (for example, to execute an operating system to execute a corresponding Figure 1 and Figure 2 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0085] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0086] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630. In some embodiments, the main memory 604 may be a Figure 1 The host memory 105 or Figure 2 Memory 205.

[0087] The processing device 602 represents one or more general purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. The processing device 602 may also be one or more special purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 608 to communicate over a network 620.

[0088] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside completely or at least partially within the main memory 604 and / or the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0089] In one embodiment, instructions 626 include instructions for implementing a method corresponding to a memory management component (e.g., Figure 1 and Figure 2The term "machine-readable storage medium" should be taken to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. Thus, the term "machine-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0090] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is generally conceived here to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0091] It should be remembered, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0092] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0093] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will appear as set forth in the appended claims. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that various programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0094] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0095] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It should be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory; and A processing device operatively coupled to the memory to perform operations comprising: partitioning the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; Receive host commands to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location of a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a range of compression ratios associated with the memory partition; and An operation is performed with respect to the data at the identified location on the memory partition.

2. The system of claim 1, wherein the processing device is configured to perform operations further comprising: A record indexable by a physical address specified in the host command is stored in a data structure, wherein the record includes a partition identifier of the memory partition and the segment identifier.

3. The system of claim 2, wherein the record contains a value within the compression ratio range associated with the memory partition.

4. The system of claim 2, wherein the processing device is configured to perform operations further comprising: The data structure is cached.

5. The system of claim 1, wherein the processing device is configured to perform operations further comprising: The compression ratio range is associated with the memory partition.

6. The system of claim 5, wherein identifying the memory partition among the plurality of memory partitions further comprises: It is determined that the compression ratio of the data falls within the compression ratio range.

7. The system of claim 1, wherein the plurality of locations on the memory partition are determined based on the compression ratio range associated with the memory partition.

8. The system of claim 1, wherein the memory comprises at least one of: a volatile memory device or a non-volatile memory device.

9. A method comprising: partitioning, by a processing device, a memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; Receive host commands to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location of a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a range of compression ratios associated with the memory partition; and An operation is performed with respect to the data at the identified location on the memory partition.

10. The method according to claim 9, further comprising: A record indexable by a physical address specified in the host command is stored in a data structure, wherein the record includes a partition identifier of the memory partition and the segment identifier.

11. The method of claim 10, wherein the record contains a value within the compression ratio range associated with the memory partition.

12. The method according to claim 10, further comprising: The data structure is cached.

13. The method according to claim 9, further comprising: The compression ratio range is associated with the memory partition.

14. The method of claim 13, wherein identifying the memory partition among the plurality of memory partitions further comprises: It is determined that the compression ratio of the data falls within the compression ratio range.

15. The method of claim 9, wherein the plurality of locations on the memory partition are determined based on the compression ratio range associated with the memory partition.

16. The method of claim 9, wherein the memory comprises at least one of: a volatile memory device or a non-volatile memory device.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: partitioning a memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; Receive host commands to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location of a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a range of compression ratios associated with the memory partition; and An operation is performed with respect to the data at the identified location on the memory partition.

18. The non-transitory computer-readable storage medium of claim 17, wherein the processing device is configured to perform operations further comprising: A record indexable by a physical address specified in the host command is stored in a data structure, wherein the record includes a partition identifier of the memory partition and the segment identifier.

19. The non-transitory computer-readable storage medium of claim 18, wherein the record includes a value within the compression ratio range associated with the memory partition.

20. The non-transitory computer-readable storage medium of claim 18, wherein the processing device is configured to perform operations further comprising: The data structure is cached.

Images