A signal processing method for a photoelectric implementation matrix multiplication system based on ZYNQ

Abstract

The application relates to the technical field of photoelectric signals and discloses a signal processing method of a photoelectric implementation matrix multiplication system based on ZYNQ, wherein the output of an analog level and the measurement of an optical power signal are carried out through the PL end of the ZYNQ, the calculation of a proportional coefficient, the confirmation of a delay time and the synchronous calibration are completed by using the PS end, and the conversion and accumulation of the optical power signal into a standard result are completed. The flexibility of the PS end is combined with the parallel processing capability and real-time capability of the PL end, so that the signal processing efficiency can be effectively improved. The multiplication operation of data is converted into the optical domain, and the acceleration of large-scale matrix multiplication is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photoelectric signal, in particular to a signal processing method for implementing matrix multiplication system based on ZYNQ. BACKGROUND

[0002] There are a large number of problems in the field of scientific computing that need to be solved by matrix multiplication. For example, machine learning, software simulation, digital signal processing, etc. In the existing technology, such as GPU and FPGA, the parallel operation units are usually used to accelerate matrix operation. However, low-cost devices have limited parallelism, which is not conducive to large-scale matrix operation; while devices that can support large-scale parallelism for large-scale matrix operation are expensive.

[0003] The prior art discloses a sparse matrix multiplication acceleration method, FPGA, computing system and storage medium. The method is used for calculating the product of sparse matrix A and matrix B. The sparse matrix A is stored in the off-chip memory in the form of sparse blocks. The method comprises the following steps: configuring the parallel degree parameter of the computing unit according to the available computing resources on the FPGA chip and the sparse block size of the sparse matrix A; determining the storage structure of the off-chip memory and the storage form of the data in the on-chip buffer according to the parallel degree parameter and the data bit width of the off-chip memory; transmitting the data in the on-chip memory to the on-chip buffer, and the sparse core computing unit on the FPGA chip calculates the data stored in the on-chip buffer to obtain the product of the sparse matrix A and the matrix B. The patent uses the parallel operation unit to accelerate matrix operation. However, low-cost devices have limited parallelism, which is not conducive to large-scale matrix operation; while devices that can support large-scale parallelism for large-scale matrix operation are expensive. SUMMARY

[0004] The purpose of the present application is to provide a signal processing method for implementing matrix multiplication system based on ZYNQ, which can effectively improve the signal processing efficiency and realize the acceleration of large-scale matrix multiplication.

[0005] In order to achieve the above purpose, the present application provides a signal processing method for implementing matrix multiplication system based on ZYNQ, which comprises ZYNQ and MZM intensity modulator, ZYNQ comprises PS end and PL end, comprising the following steps:

[0006] S1, the PS end configures the analog level signal of the preset waveform, and sends multiple data packets to the PL end in units of single maximum transmission length;

[0007] S2, the PL end receives the data sent by the PS end, and outputs the data to the MZM intensity modulator in the form of analog level, and receives the optical power signal modulated by the MZM intensity modulator.

[0008] S3, the PS end reads the optical power signal received by the PL end, performs synchronization and scale factor confirmation;

[0009] S4, the PS end configures an analog level signal for matrix multiplication operation, and sends single-row vector multiplication data to the PL end;

[0010] S5, the PL end receives the data sent by the PS end and outputs the data to the MZM intensity modulator in the form of an analog level, and the MZM intensity modulator performs vector multiplication operation to obtain the multiplication result, and the MZM intensity modulator outputs the multiplication result to the PL end in the form of an optical power signal;

[0011] S6, the PS end reads the multiplication result from the PL end, performs scale conversion and accumulation operation, and calculates the matrix multiplication result;

[0012] S7, the steps of S4-S6 are repeatedly executed until each element in the matrix multiplication is calculated, and the result is sent to the host computer.

[0013] As a preferred solution, it further includes a DDR, an ADC chip and a DAC chip, the PS end is connected to the DDR, the PL end includes an AXI DMA module, an ADC control module and a DAC control module, the PL end communicates with the PS end through the AXI DMA module, the ADC control module is connected to the ADC chip, and the DAC control module is connected to the DAC chip, and step S1 includes:

[0014] S101, the PS end initializes the AXI DMA module, opens the MM2S and S2MM channels, and opens the receiving interrupt and the sending interrupt;

[0015] S102, the PS end sets the value of the parameter register;

[0016] S103, the PS end reads 16-bit level data of single maximum transmission length from the DDR, and sets the head address and transmission length of the transmission data;

[0017] S104, the PS end executes the transmission command and waits for the transmission completion interrupt;

[0018] S105, after receiving the transmission completion interrupt command, the next packet data in units of single maximum transmission length is read, and the cycle is repeated.

[0019] As a preferred solution, in step S102, the value of the parameter register includes: ADC zero level parameter and the maximum length of single transmission .

[0020] As a preferred solution, step S2 includes:

[0021] S201 and PL receive data from PS in packets and store it in FIFO_0;

[0022] After receiving all the data, S202 and PL send enable signals to the DAC control module and the ADC control module.

[0023] After receiving the enable signal, the S203 and DAC control modules extract the data from FIFO_0 and output it as 14-bit data through their IO ports to the MZM intensity modulator, which then modulates the MZM intensity modulator to generate an optical power signal.

[0024] After receiving the enable signal, the ADC control module at the S204 and PL terminals enables the data valid signal of the ADC control module, reads 12-bit digital level data from the IO port of the ADC control module, and inputs it into FIFO_2 in the form of a data stream.

[0025] S205. After receiving data of length LEN, enable the S2MM data transmission channel, read FIFO_2 data in units of maximum single transmission length, and transmit the data to the AXIDMA module.

[0026] As a preferred embodiment, in step S203, the optical power signal generated by the MZM intensity modulator is: the MZM intensity modulator is set to operate at the bias point. When the MZM intensity modulator operates at the bias point Its optical power is When a level is applied At that time, its optical power was ,in This is the proportionality coefficient obtained in step S3.

[0027] As a preferred embodiment, step S3 includes:

[0028] The PS end compares the received data with the transmitted data and calculates the number of clock cycles between transmission and reception; the calculation is based on... The voltage level at the bias point is converted to a voltage level. Standard values ​​between; calculate the proportional coefficient for the conversion of signal level to optical power;

[0029] The The standard values ​​between are: The ratio of modulated optical power to bias point optical power, for an MZM intensity modulator, the maximum optical power is... Twice the bias point power, It is a positive real value not greater than 2.

[0030] As a preferred embodiment, step S4 includes:

[0031] S401, the PS end reads the vectors A and B stored in the DDR in the form of 16-bit elements, and performs and encoding on the same symbol, and the low 16 bits of the 32-bit array to be transmitted store the vector A data, and the high 16 bits store the vector B data;

[0032] S402, the host computer sets the head address and the transmission length of the transmission data, and the PS end executes the transmission command and waits for the transmission completion interrupt;

[0033] S403, after receiving the transmission completion interrupt command, the next packet of data in the unit of the maximum single transmission length is read, and the cycle is repeated until the two-column vectors are transmitted.

[0034] As a preferred solution, step S5 comprises:

[0035] S501, the PL end receives the data from the PS end in the unit of packet, and stores the data in FIFO_0 and FIFO_1 according to the high 16 bits as the vector A and the low 16 bits as the vector B;

[0036] S502, after receiving all the data, the PL end sends an enable signal to the DAC control module and the ADC control module;

[0037] S503, after receiving the enable signal, the DAC control module takes out the data in FIFO_0 and FIFO_1, and outputs the 14-bit data from the double-channel ch1 and ch2 to the IO port of the MZM intensity modulator; the vector multiplication operation is completed by the cascaded MZM intensity modulator; after receiving the enable signal, the ADC control module of the PL end enables the data valid signal of the ADC control module, reads the 12-bit digital level data from the IO port of the ADC control module, and inputs the data stream into FIFO_2;

[0038] S504, after receiving the data with the length of LEN, the S2MM data transmission channel is enabled, the FIFO_2 data is read in the unit of the maximum single transmission length, and the multiplication result data in the form of optical power signals is transmitted to the DMA direct memory reading module.

[0039] As a preferred solution, in step 503, the vector multiplication operation completed by the cascaded MZM intensity modulator is: when the analog levels of and are applied to the cascaded MZM intensity modulator respectively, the optical power is .

[0040] As a preferred solution, step S6 comprises:

[0041] S601. Based on the delay time period and proportional coefficient calculated in step S2, determine the range of valid data in the received data;

[0042] S602. Based on the size of the matrix, divide and concatenate the received data, organizing it into corresponding rows and columns; calculate... The voltage level at the bias point is determined, and the data is converted into a standard value between 0 and 2. Based on the scaling factor calculated in step S2, the standard value is converted into the result of the dot product of vector A and vector B. The method for converting the standard value into the result of the dot product of vector A and vector B is as follows: based on the method mentioned in step S4 for the same symbol... and The method of performing two encodings is for and The result of multiplying the optical power will be: and ,have And there are ,in The proportionality coefficient obtained in step S3, and These are the standard values ​​obtained respectively;

[0043] S603. Accumulate the results of the dot product of vector A and vector B to obtain the values ​​of the corresponding rows and columns in the result matrix.

[0044] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0045] This invention uses the PL terminal of the ZYNQ sensor for analog level output and optical power signal measurement, and the PS terminal for calculating the scaling factor, confirming the delay time, and performing synchronization calibration, as well as converting and accumulating the optical power signal to a standard result. Combining the flexibility of the PS terminal with the parallel processing and real-time capabilities of the PL terminal effectively improves signal processing efficiency. This invention converts data multiplication operations to be performed in the optical domain, accelerating large-scale matrix multiplication. Attached Figure Description

[0046] Fig. 1 This is a flowchart of a signal processing method for a ZYNQ-based optoelectronic matrix multiplication system according to an embodiment of the present invention.

[0047] Fig. 2 This is a schematic diagram of the control flow at the PS end in an embodiment of the present invention.

[0048] Fig. 3 This is a schematic diagram of the system structure according to an embodiment of the present invention.

[0049] Fig. 4This is a schematic diagram of the functional modules of an embodiment of the present invention. Detailed Implementation

[0050] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0051] ZYNQ consists of two parts: the PS (Processing System) and the PL (Programmable Logic, i.e., FPGA). The PS is the ARM (Advanced RISC Machine) processor, and the PL is the FPGA (Field Programmable Gate Array). When using ZYNQ, communication between the PS and PL is inevitable. In most cases, the PS acts as the master and the PL as the slave, with communication between the PS and PL achieved through the AXI bus.

[0052] The MZI intensity modulator is called the "MZM Mach-Zehnder Modulator".

[0053] Example 1

[0054] like Figs. 1 to 4 As shown in the preferred embodiment of the present invention, a signal processing method for a photoelectric matrix multiplication system based on ZYNQ includes a ZYNQ and an MZM intensity modulator. The ZYNQ includes a PS terminal and a PL terminal, and includes the following steps:

[0055] The S1 and PS terminals are configured with preset waveform analog level signals to send multiple data packets to the PL terminal in units of the maximum single transmission length.

[0056] S2 and PL terminals receive data sent by PS terminal and output the data to MZM intensity modulator in analog level form. At the same time, they receive the optical power signal modulated by MZM intensity modulator.

[0057] S3 and PS terminals read the optical power signal received by PL terminal to perform synchronization and proportional coefficient confirmation.

[0058] The S4 and PS terminals are configured with analog level signals for matrix multiplication operations, and send single-row vector multiplication data to the PL terminal.

[0059] S5 and PL terminals receive data sent by PS terminals and output the data to the MZM intensity modulator in analog level form. The MZM intensity modulator performs vector multiplication to obtain the multiplication result, and outputs the multiplication result to the PL terminal in the form of an optical power signal.

[0060] S6 and PS terminals read the multiplication results from PL terminals, perform proportional conversion and accumulation operations, and calculate the matrix multiplication results.

[0061] S7. Repeat steps S4 to S6 until every element in the matrix multiplication has been calculated, and send the result to the host computer.

[0062] This embodiment uses the PL terminal of the ZYNQ for analog level output and optical power signal measurement, and the PS terminal for calculating the scaling factor, confirming the delay time, and performing synchronization calibration, as well as converting the optical power signal to a standard result and accumulating it. Combining the flexibility of the PS terminal with the parallel processing and real-time capabilities of the PL terminal effectively improves signal processing efficiency. Furthermore, converting data multiplication operations to be performed in the optical domain accelerates large-scale matrix multiplication.

[0063] In this embodiment, the MZM intensity modulator includes multiple MZM structures, which are cascaded together. The cascading of MZM structures can improve the sensitivity and accuracy of the sensing.

[0064] Furthermore, in this embodiment, the ZYNQ selected is XC7Z020CLG400-2. The starting addresses of the transmit data and receive data areas are 0x01200000 and 0x01400000, respectively.

[0065] Example 2

[0066] The difference between this embodiment and Embodiment 1 is that, based on Embodiment 1, this embodiment provides a detailed explanation of steps S1 to S3.

[0067] This embodiment of a signal processing method for a photoelectric matrix multiplication system based on ZYNQ includes a ZYNQ, an MZM intensity modulator, a DDR, an ADC chip, and a DAC chip. The ZYNQ includes a PS terminal and a PL terminal. The PS terminal is connected to the DDR. The PL terminal includes an AXIDMA module, an ADC control module, and a DAC control module. The PL terminal communicates with the PS terminal through the AXIDMA module. The ADC control module is connected to the ADC chip, and the DAC control module is connected to the DAC chip. In this embodiment, the PS terminal is connected to a host computer through a USB-to-serial port chip.

[0068] Specifically:

[0069] ADC chip: Outputs the preset waveform or vector to be multiplied to the IO port in the form of analog level, and modulates the MZM intensity modulator for proportional calibration or vector multiplication;

[0070] DAC chip: receive modulated optical power signal or vector multiplied optical power signal, transmit data to AXI DMA waiting PS end to initiate reception;

[0071] PL AXI DMA module: initiate data read command to PL end, or store data from PS end to PL end storage unit;

[0072] PL ADC control module: respond to data read command initiated by PS end, output analog level from IO port;

[0073] PL DAC control module: respond to data reception command initiated by PS end, receive analog level from external IO port;

[0074] PS end: initialize AXI control module and interrupt control module; initialize parameter register; initiate sending and receiving commands to PL end; respond to AXI reception interrupt and sending interrupt; and transmit matrix result to host computer through USB-to-serial chip;

[0075] DDR memory: store preset waveform and matrix data.

[0076] The method comprises the following steps:

[0077] S1, the PS end configures the analog level signal of the preset waveform, and transmits multiple data packets to the PL end in units of single maximum transmission length; specifically, step S1 comprises:

[0078] S101, the PS end initializes the AXI DMA module, opens the MM2S and S2MM channels, and opens the reception interrupt and sending interrupt;

[0079] S102, the PS end sets the value of the parameter register; wherein in step S102, the set value of the parameter register includes: ADC zero level parameter and the maximum length of single transmission ; the ZYNQ further comprises a parameter register for storing and transmitting data, so that the PS end and the PL end can exchange data and communicate with each other, and realize cooperative work.

[0080] S103, the PS end reads 16-bit level data of single maximum transmission length from the DDR, sets the head address and transmission length of the transmission data;

[0081] S104, the PS end executes the transmission command and waits for the transmission completion interrupt;

[0082] S105, after receiving the transmission completion interrupt command, read the next packet data in units of single maximum transmission length, and repeat the cycle.

[0083] S2, the PL terminal receives data sent by the PS terminal and outputs the data to the MZM intensity modulator in analog level form, while simultaneously receiving the optical power signal modulated by the MZM intensity modulator; in this embodiment, data is received through the DMA direct memory access module and outputted in analog level form through the DAC. Specifically, step S2 includes:

[0084] S201 and PL receive data from PS in packets and store it in FIFO_0;

[0085] After receiving all the data, S202 and PL send enable signals to the DAC control module and the ADC control module.

[0086] After receiving the enable signal, the S203 and DAC control modules extract the data from FIFO_0 and output it as 14-bit data through their IO ports to the MZM intensity modulator, which then modulates the MZM intensity modulator to generate an optical power signal.

[0087] In step S203, the optical power signal generated by the MZM intensity modulator is generated by modulating the level signal: the MZM intensity modulator is set to operate at the bias point. When the MZM intensity modulator operates at the bias point Its optical power is When a level is applied At that time, its optical power was ,in The proportionality coefficient obtained in step S3;

[0088] After receiving the enable signal, the ADC control module at the S204 and PL terminals enables the data valid signal of the ADC control module, reads 12-bit digital level data from the IO port of the ADC control module, and inputs it into FIFO_2 in the form of a data stream.

[0089] S205. After receiving data of length LEN, enable the S2MM data transmission channel, read FIFO_2 data in units of maximum single transmission length, and transmit the data to the AXIDMA module.

[0090] S3. The PS terminal reads the optical power signal received by the PL terminal to perform synchronization and proportional coefficient confirmation; specifically, step S3 includes:

[0091] The PS end compares the received data with the transmitted data and calculates the number of clock cycles between transmission and reception; the calculation is based on... The voltage level at the bias point is converted to a voltage level. Standard values ​​between; calculate the proportional coefficient for the conversion of signal level to optical power;

[0092] The The standard value between them is: The ratio of the modulated optical power to the bias point optical power is not greater than 2. The maximum optical power of the MZM intensity modulator is The bias point power is not greater than 2.

[0093] S4, the PS end configures the analog level signal of matrix multiplication operation, and sends single row vector multiplication data to the PL end.

[0094] S5, the PL end receives the data sent by the PS end and outputs the data in the form of analog level to the MZM intensity modulator, and the MZM intensity modulator performs vector multiplication operation to obtain the multiplication result. The MZM intensity modulator outputs the multiplication result in the form of optical power signal to the PL end.

[0095] S6, the PS end reads the multiplication result from the PL end, performs proportional conversion and accumulation operation, and calculates to obtain the matrix multiplication result.

[0096] S7, the steps of S4-S6 are repeatedly executed until each element in the matrix multiplication is calculated, and the result is sent to the host computer.

[0097] Embodiment three

[0098] The difference between this embodiment and embodiment two is that on the basis of embodiment two, steps S4-S6 are further described in this embodiment.

[0099] The signal processing method of the ZYNQ-based photoelectric implementation matrix multiplication system of the embodiment, which comprises ZYNQ, MZM intensity modulator, DDR, ADC chip and DAC chip, ZYNQ comprises PS end and PL end, PS end is connected with DDR, PL end comprises AXIDMA module, ADC control module and DAC control module, PL end communicates with PS end through AXIDMA module, ADC control module is connected with ADC chip, and DAC control module is connected with DAC chip, and comprises the following steps:

[0100] S1, the PS end configures the analog level signal of the preset waveform, and sends multiple data to the PL end in units of single maximum transmission length.

[0101] S2, the PL end receives the data sent by the PS end, and outputs the data in the form of analog level to the MZM intensity modulator, and receives the optical power signal modulated by the MZM intensity modulator.

[0102] S3, the PS end reads the optical power signal received by the PL end, and performs synchronization and proportional coefficient confirmation.

[0103] S4, the PS end configures an analog level signal for matrix multiplication operation, and sends single-row vector multiplication data to the PL end; specifically, step S4 includes:

[0104] S401, the PS end reads vectors A and B stored in the form of 16 bits from the DDR, and performs and encoding on the same code element twice, so that for an array of a single element to be transmitted, the lower 16 bits store vector A data, and the upper 16 bits store vector B data;

[0105] S402, the head address and transmission length of the transmitted data are set by the upper computer, the PS end executes the transmission command, and waits for the transmission completion interrupt;

[0106] S403, after receiving the transmission completion interrupt command, the next packet data in the unit of single maximum transmission length is read, and the cycle is repeated until the two-column vectors are transmitted.

[0107] S5, the PL end receives the data sent by the PS end and outputs the data to the MZM intensity modulator in the form of an analog level, the MZM intensity modulator performs vector multiplication operation to obtain the operation multiplication result, and the MZM intensity modulator outputs the operation multiplication result to the PL end in the form of an optical power signal; specifically, step S5 includes:

[0108] S501, the PL end receives the data from the PS end in the unit of packet, and according to the upper 16 bits as vector A and the lower 16 bits as vector B, stores them in FIFO_0 and FIFO_1 respectively;

[0109] S502, after receiving all the data, the PL end sends an enable signal to the DAC control module and the ADC control module;

[0110] S503, after receiving the enable signal, the DAC control module takes out the data in FIFO_0 and FIFO_1, and outputs 14-bit data from the double channels ch1 and ch2 to the IO port of the MZM intensity modulator; the vector multiplication operation is completed by the cascaded MZM intensity modulator; after receiving the enable signal, the ADC control module of the PL end enables the data valid signal of the ADC control module, reads 12-bit digital level data from the IO port of the ADC control module, and inputs the data into FIFO_2 in the form of a data stream;

[0111] In step 503, the vector multiplication operation completed by the cascaded MZM intensity modulator is: when the analog levels of and are applied to the cascaded MZM intensity modulator respectively, the optical power is ;

[0112] S504, after receiving the data with the length of LEN, enabling the S2MM data transmission channel to read the FIFO_2 data in the unit of single maximum transmission length, and transmitting the multiplication result data in the form of optical power signal to the DMA direct memory reading module.

[0113] S6, the PS end reads the operation multiplication result from the PL end, performs proportional conversion and accumulation operation, and calculates the matrix multiplication result; specifically, step S6 includes:

[0114] S601, determining the interval of the valid data in the received data according to the delay time period calculated in step S2 and the proportional coefficient;

[0115] S602, segmenting and splicing the received data according to the size of the matrix, arranging in the unit of corresponding rows and columns; calculating the level size when the offset point is , and converting the data into the standard value between 0 and 2, converting the standard value into the result after the dot multiplication of the vector A and the vector B according to the proportional coefficient calculated in step S2; wherein the method of converting the standard value into the result after the dot multiplication of the vector A and the vector B is: according to the method of encoding the same symbol twice mentioned in step S4, for the optical power multiplication result of and , there will be and , there will be and , there will be , and there will be , wherein is the proportional coefficient obtained in step S3, and are the standard values obtained respectively;

[0116] S603, accumulating the result after the dot multiplication of the vector A and the vector B to obtain the value of the corresponding row and column in the result matrix.

[0117] S7, cyclically performing the steps of S4-S6 until each element in the matrix multiplication is calculated, and transmitting the result to the upper computer. In this embodiment, the method of transmitting to the upper computer in step S7 is serial communication, and the matrix data is transmitted by using the UART (universal asynchronous receiver transmitter) interface protocol.

[0118] In summary, the embodiment of the present application provides a signal processing method for a photoelectric implementation matrix multiplication system based on ZYNQ, which outputs analog level and measures optical power signal through the PL end of ZYNQ, uses the PS end to complete the calculation of proportional coefficient, the confirmation of delay time and the synchronization calibration, and completes the conversion and accumulation of the optical power signal to the standard result. The flexibility of the PS end is combined with the parallel processing capability and real-time capability of the PL end, which can effectively improve the signal processing efficiency. And the multiplication operation of data is converted to the optical domain, which realizes the acceleration of large-scale matrix multiplication.

[0119] The above merely describes the preferred embodiments of the present application, and it should be noted that those skilled in the art can make several improvements and replacements without departing from the technical principles of the present application, and these improvements and replacements should also be considered as the protection scope of the present application.

Claims

1. A signal processing method for implementing a matrix multiplication system optoelectronically based on ZYNQ, characterized in that, The application relates to a matrix multiplication method and device, which comprises a ZYNQ and an MZM intensity modulator, the ZYNQ comprises a PS end and a PL end, and comprises the following steps: S1, the PS end configures an analog level signal of a preset waveform, and transmits multiple data packets to the PL end in units of single maximum transmission length; S2, the PL end receives the data transmitted by the PS end, and outputs the data to the MZM intensity modulator in the form of an analog level signal, and receives an optical power signal modulated by the MZM intensity modulator; S3, the PS end reads the optical power signal received by the PL end, and performs synchronization and proportional coefficient confirmation; S4, the PS end configures an analog level signal for matrix multiplication operation, and transmits single-row vector multiplication data to the PL end; S5, the PL end receives the data transmitted by the PS end and outputs the data to the MZM intensity modulator in the form of an analog level signal, the MZM intensity modulator performs vector multiplication operation to obtain multiplication results, and the MZM intensity modulator outputs the multiplication results to the PL end in the form of an optical power signal; S6, the PS end reads the multiplication results from the PL end, performs proportional conversion and accumulation operation, and calculates matrix multiplication results; S7, the steps of S4-S6 are circularly executed until each element in the matrix multiplication is calculated, and the results are transmitted to an upper computer.

2. The signal processing method for ZYNQ-based optoelectronic implementation of matrix multiplication system according to claim 1, characterized in that, The application further comprises a DDR, an ADC chip and a DAC chip, the PS end is connected with the DDR, the PL end comprises an AXI DMA module, an ADC control module and a DAC control module, the PL end communicates with the PS end through the AXI DMA module, the ADC control module is connected with the ADC chip, the DAC control module is connected with the DAC chip, and the step S1 comprises the following steps: S101, the PS end initializes the AXI DMA module, opens the MM2S and S2MM channels, and opens the receiving interrupt and the sending interrupt; S102, the PS end sets the value of a parameter register; S103, the PS end reads 16-bit level data of single maximum transmission length from the DDR, sets the head address and transmission length of the transmission data; S104, the PS end executes a transmission command and waits for a transmission completion interrupt; S105, after receiving the transmission completion interrupt command, the next packet data in units of single maximum transmission length is read, and the cycle is repeated.

3. The signal processing method for ZYNQ-based optoelectronic implementation of matrix multiplication system according to claim 2, characterized in that, In step S102, the value of the set parameter register includes: the ADC zero level parameter and the maximum length of a single transmission .

4. The signal processing method for ZYNQ-based optoelectronic implementation of matrix multiplication system according to claim 3, characterized in that, The step S2 comprises the following steps: S201, the PL end receives the data from the PS end in units of packets, and stores the data into a FIFO_0; S202, after receiving all the data, the PL end sends an enable signal to the DAC control module and the ADC control module; S203, after receiving the enable signal, the DAC control module takes out the data in the FIFO_0, and outputs 14-bit data to the MZM intensity modulator through an IO port, so that the MZM intensity modulator generates an optical power signal; S204, after receiving the enable signal, the ADC control module of the PL end enables the data valid signal of the ADC control module, reads 12-bit digital level data from the IO port of the ADC control module, and inputs the data into a FIFO_2 in the form of a data stream; S205, after receiving data with length LEN, enable S2MM data transmission channel, read FIFO_2 data in single maximum transmission length unit, and transmit data to AXI DMA module.

5. The signal processing method for ZYNQ-based optoelectronic implementation of matrix multiplication system according to claim 4, characterized in that, In step S203, the level signal modulates the MZM intensity modulator to produce an optical power signal: Set the MZM intensity modulator to operate at a bias point When the MZM intensity modulator operates at a bias point , its optical power is , when a level is applied, its optical power is , where is the proportional coefficient obtained in step S3.

6. The signal processing method for ZYNQ-based optoelectronic implementation of matrix multiplication system according to claim 5, wherein, Step S3 includes: The PS end compares the received data with the transmitted data, calculates the number of clock cycles between the transmission and the reception, and calculates the level size at the offset point and converts the level into a standard value between and calculates the proportional coefficient of the level signal and the optical power conversion; The The standard value between them is: The ratio of the modulated optical power to the bias point optical power, for an MZM intensity modulator, is maximum optical power Bias point power is twice, Is a positive real value not greater than 2.

7. The signal processing method for ZYNQ-based optoelectronic implementation of matrix multiplication system according to claim 6, wherein, Step S4 includes: S401, the PS end reads the vector A and the vector B stored in the DDR in the form of 16-bit elements, and encodes the same symbol twice and After the encoding mode of twice encoding, for an array of 32-bit elements to be transmitted, the lower 16 bits store the vector A data, and the upper 16 bits store the vector B data. S402, set the head address and transmission length of the transmission data by the upper computer, execute the transmission command by the PS end, and wait for the transmission completion interrupt; S403, after receiving the transmission completion interrupt command, read the next packet data in single maximum transmission length unit, and cycle until two column vectors are transmitted.

8. The signal processing method for ZYNQ-based optoelectronic implementation of matrix multiplication system according to claim 7, characterized in that, Step S5 includes: S501, the PL end receives data from the PS end in packet unit, stores vector A in high 16 bits and vector B in low 16 bits into FIFO_0 and FIFO_1 respectively; S502, after receiving all data, the PL end sends an enable signal to the DAC control module and the ADC control module; S503, after receiving the enable signal, the DAC control module takes out the data in FIFO_0 and FIFO_1, and outputs 14-bit data from double channels ch1 and ch2 to the IO port to the MZM intensity modulator; the vector multiplication operation is completed by the cascaded MZM intensity modulator; after receiving the enable signal, the ADC control module of the PL end enables the data valid signal of the ADC control module, reads 12-bit digital level data from the IO port of the ADC control module, and inputs the data into FIFO_2 in data stream form; S504, after receiving data with length LEN, enable S2MM data transmission channel, read FIFO_2 data in single maximum transmission length unit, and transmit the multiplication result data in the form of optical power signal to the DMA direct memory read module.

9. The signal processing method for ZYNQ-based optoelectronic implementation of matrix multiplication system according to claim 8, wherein, In step 503, the operation of vector multiplication is accomplished by the cascaded MZM intensity modulators as follows: when the analog levels of and are applied to the cascaded MZM intensity modulators respectively, the optical power of the output light is .

10. The signal processing method of the ZYNQ-based optoelectronic implementation matrix multiplication system according to claim 9, wherein, Step S6 includes: S601, according to the delay time period and the proportional coefficient calculated in step S2, determine the interval of valid data in the received data; S602, according to the size of the matrix, the received data is segmented and spliced, to correspond to each other in the unit of rows and columns to arrange; to calculate the level size when the offset point, and the data into the standard value between 0~2, according to the proportion coefficient calculated in step S2, the standard value is converted into the result of the dot product of vector A and vector B; wherein, the method for the standard value is converted into the result of the dot product of vector A and vector B is: according to the step S4 mentioned for the same symbol is And And The method of twice encoding, for And The optical power multiplication result will have And , there are , and , wherein The proportion coefficient obtained in step S3, And The standard value obtained respectively; S603, accumulate the result after the dot product of vector A and vector B, and get the corresponding row and column values in the result matrix.

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