Method for tracing and querying interconnected network in three-dimensional integrated circuit layout
By acquiring and converting interconnection rules in the 3D integrated circuit layout and automatically performing traceability queries using EDA tools, the problem of inaccurate traceability of interconnection networks between 3D chips in existing technologies is solved, thereby improving design efficiency and accuracy.
Patent Information
- Application Number
- CN202411669943.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-03-11
AI Technical Summary
Existing EDA tools cannot accurately trace the interconnect network between three-dimensional stacked chips, resulting in low efficiency and unreliability of manual tracing.
A method for tracing and querying interconnects in a 3D integrated circuit layout is provided. The interconnect rules of each silicon wafer layer are obtained from the 3D stacked layout and converted into 3D interconnect rules. The interconnect rules are classified and summarized by combining metal vias, direct metal or via connections, blocking and marking layers. The method uses EDA tools to perform the traceability operation, replacing manual traceability query.
It improves the design efficiency of layout engineers, avoids design errors, and enables accurate traceability and automated processing of 3D interconnect networks.
Smart Images
Figure CN119598947A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic design automation (EDA), and in particular to a method for tracing and querying interconnection network in a three-dimensional integrated circuit layout. Background Art
[0002] As chip manufacturing processes continue to shrink, the growth rate of transistor (MOS) density has gradually slowed down, and traditional two-dimensional planar integrated circuits have encountered many problems in manufacturing and performance, such as increased process difficulty, increased power consumption, and heat generation. These problems make it increasingly difficult to continue to follow Moore's Law, prompting researchers to explore new technologies and methods to improve the performance and density of integrated circuits.
[0003] Three-dimensional integrated circuits (3D-ICs) achieve higher packaging density and faster data transmission speed by stacking multiple layers of silicon wafers (dies) in the vertical direction, thus meeting the needs of high-performance computing, communication, storage and other fields. Three-dimensional integrated circuits (3D-ICs) can not only solve the challenges of heat dissipation and power consumption control faced by two-dimensional integrated circuits, but also effectively utilize limited chip area to improve the performance and efficiency of the overall system.
[0004] At present, in EDA tools, the trace net query (Trace Net) of interconnection lines in the layout of planar processes (2D) cannot accurately trace the interconnection lines between three-dimensional stacked chips (die). Layout engineers can only manually trace the interconnection lines, which takes a lot of time and cannot guarantee accuracy, greatly affecting the design efficiency of integrated circuit layout engineers. Summary of the invention
[0005] In order to solve the defects of the prior art, the purpose of the present invention is to provide a method for tracing and querying interconnection networks in a three-dimensional integrated circuit layout, which is used in EDA tools and overcomes the problem that existing EDA tools cannot accurately trace and query interconnection networks between three-dimensional stacked chips.
[0006] In order to achieve the above object, the present invention provides a method for tracing and querying interconnection network in a three-dimensional integrated circuit layout, comprising:
[0007] Obtaining interconnection rules of each layer of silicon wafers from a three-dimensional stacking layout; each layer of silicon wafers includes a top silicon wafer, a middle silicon wafer, and a bottom silicon wafer;
[0008] Based on the principle of layer-by-layer information of silicon wafers, the interconnection rules of the silicon wafers of the layers are converted into three-dimensional interconnection rules;
[0009] Classifying and summarizing the three-dimensional interconnection rules according to metal through-hole interconnection, metal or through-hole direct connection, blocking and marking levels;
[0010] The three-dimensional interconnection rule is combined with the interconnection rule of the top silicon wafer to perform a traceback network operation.
[0011] Furthermore, the interconnection rules of each layer of silicon wafer include: minimum width rule, minimum spacing rule, minimum enclosing rule, minimum extension rule, contact hole and lead hole rule, substrate connection rule, parallel and series connection rule.
[0012] Furthermore, the method further includes: increasing or decreasing the three-dimensional interconnection rules to meet different interconnection inspection requirements.
[0013] Furthermore, the interconnection rules of the top silicon wafer include: vertical stacking structure, insulation layer isolation, through-hole interconnection, unidirectional and bidirectional electrical connection.
[0014] Furthermore, it also includes:
[0015] Use existing EDA tools to create layout data for each layer of silicon wafer;
[0016] Using the layout data of the silicon wafer, creating a three-dimensional chip layout in a multi-process form; opening the advanced interconnection network command, selecting the three-dimensional mode, and performing a trace network operation;
[0017] Complete the wire net tracing according to the current 3D interconnection rules, and highlight the traced wire net in 3D mode.
[0018] Furthermore, it supports importing a file storing the interconnection rules and saving the file again after modification.
[0019] To achieve the above-mentioned purpose, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is used to execute the computer program stored in the memory to implement the method for tracing and querying an interconnect network in a three-dimensional integrated circuit layout as described above.
[0020] To achieve the above objectives, the present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the method of tracing and querying an interconnect network in a three-dimensional integrated circuit layout as described above.
[0021] The method for tracing and querying interconnection network in a three-dimensional integrated circuit layout provided by the present invention has the following beneficial effects compared with the prior art:
[0022] Based on the three-dimensional stacked layout identified by EDA tools, the interconnection rules of the planar process of each layer of silicon wafer are converted into three-dimensional interconnection rules, and the three-dimensional wire network tracing operation is performed according to the three-dimensional interconnection rules, replacing the manual tracing query of the interconnection wire network, avoiding design errors, and greatly improving the design efficiency of layout engineers.
[0023] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:
[0025] Figure 1 A flow chart of a method for tracing and querying interconnection networks in a three-dimensional integrated circuit layout according to an embodiment of the present invention;
[0026] Figure 2 A schematic diagram of reading interconnection rules of each layer of silicon wafer according to an embodiment of the present invention;
[0027] Figure 3 A schematic diagram of the classification and summary of three-dimensional interconnection rules according to an embodiment of the present invention;
[0028] Figure 4 A schematic diagram of an interconnection network highlighted in accordance with an embodiment of the present invention;
[0029] Figure 5 A schematic diagram of deselecting and selecting a three-dimensional interconnection rule according to an embodiment of the present invention;
[0030] Figure 6 A schematic diagram of a file for storing three-dimensional interconnection rules according to an embodiment of the present invention;
[0031] Figure 7 A schematic diagram of reading a three-dimensional interconnection rule file according to an embodiment of the present invention;
[0032] Figure 8 The figure is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0033] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.
[0034] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.
[0035] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.
[0036] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.
[0037] In an embodiment of the present invention, a method for tracing and querying interconnection network in a three-dimensional integrated circuit layout is provided, comprising the following steps: obtaining the interconnection rules of each layer of silicon wafers from a three-dimensional stacked layout; converting the interconnection rules of the silicon wafers in each layer into three-dimensional interconnection rules based on the principle of layer-by-layer information of the silicon wafers; classifying and summarizing the three-dimensional interconnection rules according to metal through-hole interconnection, metal or through-hole direct connection, blocking and marking layers; and performing tracing network operations in combination with the three-dimensional interconnection rules of the silicon wafers in each layer and the top-level interconnection rules.
[0038] Figure 1 The flowchart of the method for tracing back and querying interconnection network in the three-dimensional integrated circuit layout according to the embodiment of the present invention is shown below. In order to make the purpose, technical scheme and advantages of the present invention clearer, Figure 1 The embodiments of the present invention are described in further detail.
[0039] In step 101, the interconnection rules of each layer of silicon chips (die) are obtained from a three-dimensional stacking layout.
[0040] In some exemplary embodiments, an existing EDA tool is used to identify a 3D (three-dimensional) stacking layout, and the interconnection rules of each layer of die (such as a top silicon wafer, a middle silicon wafer, and a bottom silicon wafer) are obtained in the layout.
[0041] In integrated circuit layout design, the interconnection rules of each layer of die mainly include the following aspects:
[0042] Minimum width rule: Each layer (such as metal layer, polysilicon layer, active area, etc.) must maintain a minimum width. This is to ensure that the pattern can be accurately transferred and etched during the manufacturing process.
[0043] Minimum spacing rule: The distance between different layers needs to meet the minimum spacing requirements. For example, the spacing between metal lines, the spacing between polysilicon and active areas, etc. This helps prevent short circuits and parasitic capacitance effects.
[0044] Minimum surrounding rule: Some areas need to be surrounded by other layers, and the surrounding range needs to meet the minimum surrounding requirements. For example, the N-well, N+ ion implantation and P+ ion implantation should have enough margins to surround the active area; polysilicon, active area and metal should maintain a certain coverage around the contact hole.
[0045] Minimum extension rule: Some layers need to extend a certain distance beyond a specific area. For example, the polysilicon gate must extend a certain distance beyond the active area. This helps ensure the performance and reliability of the device.
[0046] Contact hole and lead hole rules: When establishing electrical connections between different layers, it is necessary to use contact holes (such as source and drain contact holes) and lead holes (such as through holes between metals). The size, shape and spacing of these holes also need to meet specific design rules.
[0047] Substrate connection rules: For PMOS and NMOS tubes, their substrates need to be connected to the corresponding potential (the substrate of the PMOS tube is connected to a high potential, and the substrate of the NMOS tube is connected to a low potential). This needs to be clearly marked and implemented in the layout.
[0048] Parallel and series rules: When designing a large-size device, you may need to connect multiple small-size devices in parallel or in series. At this time, you need to pay attention to maintaining the consistency of the aspect ratio and arrange the connections of the gate, source, and drain properly.
[0049] By following these rules, the correctness and reliability of integrated circuit layout design can be ensured, thereby improving chip performance and manufacturing success rate.
[0050] In step 102, the interconnection rules of each layer of dies are converted into three-dimensional interconnection rules (3D Trace Rule) based on the principle that the layer is accompanied by the die information of each layer. The die information attached to the layer is mainly the instance name of each layer of die. Only by attaching these instance names can the three-dimensional interconnection rules and the established three-dimensional structure Trace net be distinguished.
[0051] In step 103, 3D TraceRules are classified and summarized according to four categories: metal through hole interconnection (Via Layers), metal or through hole direct connection (ConnectedLayers), blocking (Stop Layer) and marking layer (Exclude Purposes). Figure 2 and Figure 3 , exemplarily showing the interconnection rules for reading each layer of die and classifying and summarizing the 3D Trace Rule.
[0052] Metal or through-hole direct connection (Connected Layers) and metal through-hole interconnection (Via Layers) both refer to metal wires used to connect transistors, capacitors, resistors and other components inside the chip, but the two play different roles in chip manufacturing, although they are both for achieving chip electrical connection. Specifically, metal or through-hole direct connection is mainly used for the connection between the silicon substrate and the first metal interconnection layer. Its main purpose is to establish an electrical connection between the source, drain or gate of the transistor in the silicon and the metal interconnection wire. Metal or through-hole direct connection acts as a bridge between silicon and metal to ensure that electrical signals can be transferred from the semiconductor to the metal interconnection layer, or from the metal interconnection layer to the semiconductor. Metal through-hole interconnection is used to connect electrical connections between different metal interconnection layers. With the increasing complexity of integrated circuits, integrated circuits now have up to 10 or more metal interconnection layers. These metal interconnection layers are separated by dielectric layers, and then holes are punched in the dielectric layer, namely vias. Via itself is a vertical channel, which is insulated and empty. In order to conduct the circuit, metal needs to be filled in the via to form an electrical path.
[0053] Stop Layer refers to the material or structure used to prevent a specific process in an integrated circuit, such as an etch stop layer, a diffusion barrier layer, a passivation layer, a solder mask, etc.
[0054] Marking hierarchy (Exclude Purposes) refers to the marks used to identify and define different functional areas and structures. These marks are usually made on the chip through a graphic transfer process to help realize the complex functions on the chip. The setting of the marking hierarchy is crucial to the design and manufacture of the chip. It ensures that the various functional units (such as transistors) can be correctly integrated together and achieve the expected electrical performance.
[0055] In some exemplary embodiments, 3D Trace Rules may be added or reduced according to actual needs to meet different interconnection inspection requirements. Trace Rule import may also be supported and saved again after modification.
[0056] In step 104, the 3D Trace Rule of each layer of die is combined with the top Trace Rule to perform Tracenet operation. Figure 4 , indicating that after executing the Trace Net operation, the interconnection network is highlighted. In an embodiment of the present invention, a new Top Tracer (top-level tracer) assembler is created for data allocation and process scheduling. Multiple die tracers (silicon wafer tracers) are constructed in the Top Tracer for Trace net in the die. This step is consistent with 2D network tracing. The Top tracer is responsible for rule verification and scheduling, and then merges the data for external input. If the Top contains the Top die (top silicon wafer), middledie (middle silicon wafer), and bottom die (bottom silicon wafer), the corresponding die tracer will be constructed first to query (extract) the data in each die, and the Top tracer will query the trace (trace information) between the dies in the top layer, and then merge the four trace results and output them.
[0057] In some exemplary embodiments, the top trace rule refers to the interconnection rule of the top silicon wafer, which mainly includes the following aspects:
[0058] Vertical stacking structure: 3D integrated circuits form a 3D structure by stacking multiple chips in the vertical direction. This structure allows chips with different functions to be stacked closely together, thereby improving integration density and system performance.
[0059] Insulation layer isolation: Insulation layers are used to isolate the layers of the circuit to ensure electrical isolation between the layers and prevent signal interference. This isolation measure helps improve the stability and reliability of the circuit.
[0060] Perforated interconnection: The interconnection between layers is achieved through perforation technology. In a three-dimensional integrated circuit, signals need to be transmitted between layers through perforations, so the location and size of the perforations have an important impact on the interconnection performance.
[0061] Unidirectional and bidirectional electrical connections: In some cases, top-level interconnects may need to be unidirectional in some layers and bidirectional in other layers. This design can optimize signal transmission paths and reduce signal interference.
[0062] Packaging: 3D integrated circuits are essentially still traditional semiconductor integrated circuits based on silicon materials, but their packaging is different from that of traditional 2D integrated circuits. Traditional integrated circuit packaging distributes the wafers (bare chips) in the XY two-dimensional plane, while 3D integrated circuits stack multiple wafers to increase packaging density.
[0063] The above rules and design methods together constitute the top-level interconnect rules of three-dimensional integrated circuits, which aim to optimize circuit performance, increase integration density and reduce signal interference.
[0064] In some exemplary embodiments, the corresponding Trace rule can be checked or unchecked as needed to meet different interconnection inspection requirements, and the corresponding interconnection network can be highlighted. Figure 5 , exemplarily indicating the selection and checking of 3D TraceRule.
[0065] In some exemplary embodiments, the currently highlighted interconnection net can be saved as needed, or the existing interconnection net result can be read. Figure 6 and Figure 7 , which exemplarily shows saving and reading a 3D Trace Rule file.
[0066] The method for tracing and querying interconnection wire nets in a three-dimensional integrated circuit layout provided by the present invention is based on a three-dimensional stacked layout identified by an EDA tool, and traces and queries interconnection wire nets according to corresponding interconnection rules, replacing manual traceback and query of interconnection wire nets, avoiding design errors, and greatly improving the design efficiency of layout engineers. The present invention is applied to EDA tools, and can automatically convert the original interconnection rules of each layer of silicon wafer plane process into three-dimensional interconnection rules, and perform three-dimensional wire net tracing operations according to the three-dimensional interconnection rules, and the wire net tracing results support storage and reloading.
[0067] For example: Use existing EDA technology to create layout data for each layer of die; and use the above die layout data to create a 3D Chip layout in Multi-Tech form; open the Advanced Trace Net command, select 3D mode, and perform Trace Net operations; complete the net trace according to the current 3D Trace Rule, and highlight the traced net in 3D mode. Among them, create or open the Top layout with the Multi-Tech engine, and then bring in the die Instance. Each die is treated as a whole, and the EDA tool believes that each die is in a different dimension and needs to be connected in series through Top interconnection. Edit in place or descend into the instance die, and it will switch to the plane (2D) engine.
[0068] In an embodiment of the present invention, an electronic device is also provided. Figure 8 Schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Figure 8 As shown, the electronic device of the present invention includes a processor 201 and a memory 202, wherein:
[0069] The memory 202 stores a computer program. When the computer program is read and executed by the processor 201, the computer program executes the steps of the method embodiment for tracing back and querying an interconnection network in a three-dimensional integrated circuit layout as described above.
[0070] In an embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps in the method embodiment of tracing back and querying an interconnection network in a three-dimensional integrated circuit layout as described above when running.
[0071] In this embodiment, the above-mentioned computer-readable storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.
[0072] Those skilled in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A method for tracing back and querying interconnection networks in a three-dimensional integrated circuit layout, characterized in that: The following steps are involved: Obtain the interconnection rules of each layer of silicon wafer from the three-dimensional stacking layout; The silicon wafers of each layer include: a top silicon wafer, a middle silicon wafer and a bottom silicon wafer; Based on the principle of layer-by-layer information of silicon wafers, the interconnection rules of the silicon wafers of the layers are converted into three-dimensional interconnection rules; Classifying and summarizing the three-dimensional interconnection rules according to metal through-hole interconnection, metal or through-hole direct connection, blocking and marking levels; The three-dimensional interconnection rule is combined with the interconnection rule of the top silicon wafer to perform a traceback network operation.
2. The method for tracing back and querying interconnection network in a three-dimensional integrated circuit layout according to claim 1, characterized in that: The interconnection rules of each layer of silicon wafer include: minimum width rule, minimum spacing rule, minimum enclosing rule, minimum extension rule, contact hole and lead hole rule, substrate connection rule, parallel and series connection rule.
3. The method for tracing back and querying interconnection network in a three-dimensional integrated circuit layout according to claim 1, characterized in that: Also includes: The three-dimensional interconnection rules are increased or decreased to meet different interconnection inspection requirements.
4. The method for tracing back and querying interconnection network in a three-dimensional integrated circuit layout according to claim 1, characterized in that: The interconnection rules of the top silicon wafer include: vertical stacking structure, insulation layer isolation, through-hole interconnection, and unidirectional and bidirectional electrical connection.
5. The method for tracing back and querying interconnection network in a three-dimensional integrated circuit layout according to claim 1, characterized in that: Also includes: Use existing EDA tools to create layout data for each layer of silicon wafer; Using the layout data of the silicon wafer, creating a three-dimensional chip layout in a multi-process form; Open the Advanced Interconnection Net command, select the 3D mode, and perform the trace net operation; Complete the wire net tracing according to the current 3D interconnection rules, and highlight the traced wire net in 3D mode.
6. The method for tracing back and querying interconnection network in a three-dimensional integrated circuit layout according to claim 5, characterized in that: Supports importing a file containing the three-dimensional interconnection rules and saving it again after modification.
7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: The processor is used to execute the computer program stored in the memory to implement the method for tracing and querying an interconnection network in a three-dimensional integrated circuit layout as described in any one of claims 1-6.
8. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, which is loaded and executed by a processor to implement the method for tracing and querying an interconnection network in a three-dimensional integrated circuit layout as described in any one of claims 1 to 6.