Chip design rule violation prediction method based on deep learning

Abstract

The invention belongs to the field of semiconductor chip design, and discloses a chip design rule violation prediction method based on deep learning, and the method comprises the steps: 1, data preparation: constructing a feature map and a target map, and enabling the feature map and the target map to jointly form data needed by a CNN linear regression training model; and 2, model training: carrying out linear regression by using a convolutional neural network (CNN) to train and evaluate a DRV prediction model. According to the method, the CNN linear regression model is adopted, factors such as multi-scale feature fusion and boundary effect are considered, the feature map is supplemented, and design rule violation can be predicted more quickly and accurately after the global wiring stage. By analyzing Gcell information and device placement data, the potential DRV number of each Gcell in the chip is predicted. According to the method, a prediction mechanism is introduced in the early stage of the design process, the design efficiency is remarkably improved, and the requirement for later modification is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor chip design, and in particular relates to a chip design rule violation prediction method based on deep learning. Background Art

[0002] In modern electronic system design, as the scale and complexity of integrated circuits (ICs) continue to increase, the prediction and management of design rule checking (DRC) violations have become particularly important. DRV violations may lead to defects in the chip manufacturing process, thereby affecting product yield, increasing the rate of rework, and may even cause the failure of the entire chip design. Therefore, technologies and methods that can accurately predict DRV violations are crucial to improving chip design efficiency and reducing costs.

[0003] Currently, detection of DRV violations is usually performed in the later stages of chip design, relying on computationally intensive simulation and verification processes. These methods often require a lot of computing resources, and the accuracy of predictions is limited by the algorithms and techniques used. Traditional DRV violation detection methods are mainly based on rule matching and geometric analysis, but these methods are relatively inefficient when dealing with large-scale and complex integrated circuit designs, and are difficult to adapt to changing design rules.

[0004] As process nodes continue to shrink, the patterns and types of DRV violations are also evolving, requiring DRV violation detection technology to be able to meet new challenges. Current technology often ignores the dynamic changes in the design process and the mutual influence between different design stages when predicting DRV violations.

[0005] The existing DRV violation detection methods have the following major problems: 1. High computational cost: The existing DRV detection process usually requires a lot of computing resources and time, which is particularly prominent in large-scale designs; 2. Lack of real-time performance: Due to the high computational cost, existing methods find it difficult to achieve real-time or near real-time DRV violation prediction, which limits their application in rapid design iterations; 3. Difficult to adapt to new processes: With the continuous advancement of integrated circuit processes, new types and patterns of DRV violations continue to emerge, and existing technologies find it difficult to quickly adapt to these changes.

[0006] In recent research, Hung et al. proposed a DRV violation prediction method based on global routing information and using convolutional neural networks. This method can predict DRV in the early stages of the design process, thereby accelerating the design convergence. However, since the cross entropy loss function is used when training the model, and factors such as multi-scale feature fusion and boundary effects are not taken into account, the prediction accuracy of the model is low. Summary of the invention

[0007] The purpose of the present invention is to provide a chip design rule violation prediction method based on deep learning, so as to solve the problem that in the general chip design process, DRV inspection is usually carried out in the later stage. Once a large number of devices are moved at this stage, the chip timing convergence will be seriously affected; in the chip design process driven by deep learning, the existing DRV prediction model is often not comprehensive and fails to effectively consider factors such as multi-scale feature fusion and boundary effects, resulting in the technical problem of low prediction accuracy of the model.

[0008] In order to solve the above technical problems, the specific technical solution of a chip design rule violation prediction method based on deep learning of the present invention is as follows: A chip design rule violation prediction method based on deep learning includes the following steps: Step 1: Data preparation: construct feature maps and target maps, which together constitute the data required for the convolutional neural network CNN linear regression training model; Step 2: Model training: Convolutional neural network (CNN) is used to perform linear regression to train and evaluate the DRV prediction model.

[0009] Furthermore, the feature map in step 1 is composed of layout features and global routing features. The layout features are various parameters used to describe the placement of devices on the chip in the back-end design of digital ICs, and they provide important information about the routable area on the chip; the global routing features are used to describe various parameters related to Gcell generated in the global routing stage in digital IC design, and are used to predict problems that may occur in the detailed routing stage.

[0010] Furthermore, the layout features include the following: Design Boundary Feature, Grid Attribute, Row Attribute, Track Attribute, Net Attribute, and Instance Attribute; the local wiring features include: Total Track in vertical and horizontal directions, Remaining Track, and Overflow Track.

[0011] Furthermore, the step 1 includes the following specific steps: Step 1.1: Based on the layout feature and global routing feature, multi-scale feature fusion factors are considered. For each Gcell, the feature values ​​of other Gcells nearby are considered, including design boundary attributes, grid attributes, and row attributes, and the average values ​​are taken respectively. The average values ​​calculated by the neighbor Gcells reflect the routing difficulty of the target Gcell. When training the model, the neighbor attribute is defined; Step 1.2: Define the boundary attribute Boundary Attribute. If the Gcell is at the boundary, the boundary attribute is 1, otherwise it is 0; Step 1.3: Define the Gcell Size Attribute and the standard cell Track Attribute respectively; Step 1.4: The present invention adopts undersampling technology to improve the generalization ability of the model.

[0012] Furthermore, the step 1.4 includes the following specific steps: Step 1.4.1: Classify all Gcells into three categories: Gcells with DRV, Gcells close to the first category of Gcells but without DRV, and Gcells without DRV and Gcells nearby that do not have DRV; Step 1.4.2: The first type of Gcells and the second type of Gcells participate in model training normally; Step 1.4.3: Randomly select 20% or even less of the third category Gcells as training samples, and the remaining third category Gcells do not participate in model training.

[0013] Furthermore, the target map Target Maps in step 1 is composed of the number of DRVs contained in each Gcell. The target map is used to indicate whether there is a violation in each Gcell of the chip layout. The target map is regarded as the "correct answer" that the model attempts to learn and predict.

[0014] Furthermore, the step 2 includes the following specific steps: Step 2.1: In the model training phase, first you need to obtain data from the process in step 1. This data includes the Gcell information and placement information extracted from the global routing phase, as well as the corresponding DRV information. Step 2.2: The acquired data will be randomly divided into two groups: training data set and validation data set. The training data set is used for the initial training of the model. The model learns the relationship between the features and labels in these data to master the ability to predict DRV. The validation data set is used to evaluate the performance of the model after the initial training is completed to determine whether the model has learned enough information and can make accurate predictions on unseen data. Step 2.3: During the training process, the performance of the model is monitored by prediction speed and prediction accuracy. If the model does not meet the predetermined performance standards on the validation dataset, the model parameters need to be adjusted and optimized, and then the model is retrained using all the data - the combined training and validation datasets. Step 2.4: Once the model reaches a satisfactory performance standard on the validation dataset, it is considered as the optimal DRV prediction model and used for subsequent prediction tasks; Step 2.5: Testing phase: In this phase, the optimal model will be finally evaluated on a set of independent test datasets to verify the generalization ability and practical application effect of the model.

[0015] The chip design rule violation prediction method based on deep learning of the present invention has the following advantages: 1. The CNN linear regression model is used, and the loss function uses the mean square error to evaluate the performance of the regression task.

[0016] 2. Considering multi-scale feature fusion, while analyzing a single Gcell, consider the possible impact of its neighboring Gcells on the Gcell and use it as input features for model training. By combining design information at different levels, the model's ability to identify violations of complex design rules is enhanced.

[0017] 3. Consider the boundary effect. When analyzing a single Gcell, consider whether the coordinate position of the Gcell is at the boundary of the standard cell area and use it as an input feature for model training. Separately processing the Gcells at the boundary can enhance the generalization ability of the model and improve the robustness of the model.

[0018] 4. Considering that different designs may use Gcells of different sizes, the model trained by the present invention can effectively analyze Gcells of different sizes.

[0019] 5. Considering that different designs may use standard cells with different Track heights, the model trained by the present invention can effectively analyze designs with standard cells with different Track heights.

[0020] 6. The use of undersampling technology can not only improve training efficiency and accelerate model convergence, but also alleviate the problem of imbalance between positive and negative samples in the data set and reduce the impact of misclassification.

[0021] 7. Write a script to model and draw pictures of all Gcells, highlighting the Gcells that may be predicted to be true by DRV, so as to facilitate intuitive feedback.

[0022] The chip design rule violation prediction method proposed in the present invention can predict possible DRV violation areas immediately after the global routing stage is completed, thereby avoiding large-scale modifications in the later stage of design and improving design efficiency. In addition, the prediction results of the present invention can provide intuitive feedback to designers to guide them to optimize and improve the device layout and power ground network in the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the data preparation stage in the chip design rule violation prediction method proposed by the present invention.

[0024] Figure 2 It is a schematic diagram of the model training phase in the chip design rule violation prediction method proposed in the present invention. DETAILED DESCRIPTION

[0025] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a chip design rule violation prediction method based on deep learning of the present invention in conjunction with the accompanying drawings.

[0026] The present invention adopts a CNN linear regression model, considers factors such as multi-scale feature fusion and boundary effects, and supplements the feature map, which can predict design rule violations (DRVs) more quickly and accurately after the global routing stage. By analyzing Gcell information and device placement data, the present invention constructs a CNN linear regression model to predict the potential number of DRVs for each Gcell in the chip. This method significantly improves design efficiency and reduces the need for later modifications by introducing a prediction mechanism in the early stages of the design process. The core of the method of the present invention is that by utilizing a deep learning algorithm, the model can learn from historical design data and predict violations, thereby guiding designers to make more informed decisions during the design process.

[0027] Specifically, a chip design rule violation prediction method based on deep learning of the present invention includes the following steps: Step 1: Data preparation: Construct feature maps and target maps. The feature maps and target maps together constitute the data required for the convolutional neural network (CNN) linear regression training model.

[0028] Attached Figure 1It is a schematic diagram of the data preparation stage in the chip design rule violation prediction method proposed in the present invention. Feature Maps are composed of placement features and global routing features. Among them, placement features are various parameters used to describe the placement of devices on the chip in the back-end design of digital ICs, and they provide important information about the routable area on the chip. When constructing feature maps, layout features usually include the following: design boundary feature, grid attribute, row attribute, track attribute, line attribute, device attribute, etc. In addition, global routing features are used to describe various parameters related to Gcell generated in the global routing stage in digital IC design, which can be used to predict problems that may occur in the detailed routing stage. Global routing features mainly include: total track number in vertical and horizontal directions, remaining track number, overflow track number, etc.

[0029] Step 1.1: Based on the above features, the present invention considers multi-scale feature fusion factors. For each Gcell, the feature values ​​of other Gcells nearby are considered, including design boundary attributes, grid attributes, row attributes, etc., and the average values ​​are taken. The average values ​​calculated by the neighbor Gcells can reflect the difficulty of the target Gcell to a certain extent. Therefore, when training the model, the present invention defines the above neighbor attributes (Neighbor Attribute), which can promote the accuracy of the training model; Step 1.2: The present invention considers the boundary effect and defines a boundary attribute. If the Gcell is at the boundary, the boundary attribute is 1, otherwise it is 0. In the above case, the model can more accurately predict the DRV probability of boundary Gcells and non-boundary Gcells.

[0030] Step 1.3: The present invention considers the size of the Gcell and the Track height of the standard cell in the Gcell, and defines the Gcell size attribute (Gcell Size Attribute) and the standard cell Track attribute (Std Track Attribute) respectively, which effectively enhances the generalization ability of the model.

[0031] Step 1.4: The present invention adopts undersampling technology to improve the generalization ability of the model. The steps are as follows: Step 1.4.1: All Gcells are divided into three categories: Gcells with DRV, Gcells close to the first category of Gcells but without DRV, and Gcells without DRV and whose neighboring Gcells also have no DRV.

[0032] Step 1.4.2: The first type of Gcells and the second type of Gcells participate in model training normally.

[0033] Step 1.4.3: Randomly select 20% or even less of the third type of Gcells as training samples, and the remaining third type of Gcells do not participate in model training to avoid affecting model convergence.

[0034] Since most Gcells are of the third type, if the data is not processed before the model is trained, the trained model will not converge easily and will have low accuracy. Undersampling technology can not only improve the generalization ability of the model, but also help the model learn a more balanced feature representation, avoid the model from being biased towards a certain category when predicting, and improve the recognition rate of minority classes. By retaining positive samples and reducing negative samples, the model's recognition rate for minority classes (i.e., Gcells containing DRV) can be improved. In addition, undersampling technology can effectively improve model performance indicators, such as precision, recall, and F1 score, especially when the number of positive samples is small.

[0035] Target Maps consist of the number of DRVs contained in each Gcell (from 0 to 100, with values ​​greater than 100 counted as 100). Target maps are used to indicate whether there are violations in each Gcell of the chip layout. These target maps can be considered the "correct answers" that the model is trying to learn and predict.

[0036] Feature maps and target maps together constitute the data required for the CNN linear regression training model.

[0037] Step 2: Model training: A convolutional neural network (CNN) was used for linear regression to train and evaluate the DRV prediction model.

[0038] Attached Figure 2 It is a schematic diagram of the model training phase in the chip design rule violation prediction method proposed in the present invention.

[0039] This workflow describes in detail how to use a convolutional neural network (CNN) for linear regression to train and evaluate a DRV prediction model. The steps are as follows: Step 2.1: In the model training phase, you first need to obtain data from the process in step 1. This data includes the Gcell information and Placement information extracted from the global routing phase, as well as the corresponding DRV information.

[0040] Step 2.2: The acquired data will be randomly divided into two groups: training data set and validation data set. The training data set is used for the initial training of the model. The model learns the relationship between the features and labels in these data to master the ability to predict DRV. The validation data set is used to evaluate the performance of the model after the initial training is completed to determine whether the model has learned enough information and can make accurate predictions on unseen data.

[0041] Step 2.3: During the training process, the performance of the model is monitored by prediction speed and prediction accuracy. If the model does not meet the predetermined performance standards on the validation dataset, the model parameters need to be adjusted and optimized, and then the model is retrained using all the data (the combined training and validation datasets).

[0042] Step 2.4: Once the model achieves a satisfactory performance criterion on the validation dataset, we regard it as the optimal DRV prediction model and use it for subsequent prediction tasks.

[0043] Step 2.5: The present invention includes a testing phase, during which the optimal model will be finally evaluated on a set of independent test data sets to verify the generalization ability and practical application effect of the model.

[0044] The training and evaluation process proposed in the present invention ensures that the proposed DRV prediction model is both accurate and reliable and can meet the actual needs of digital IC design.

[0045] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A chip design rule violation prediction method based on deep learning, characterized in that: Including steps such as: Step 1: Data preparation: construct feature maps and target maps, which together constitute the data required for the convolutional neural network CNN linear regression training model; Step 2: Model training: A convolutional neural network (CNN) is used to perform linear regression to train and evaluate the DRV prediction model.

2. The chip design rule violation prediction method based on deep learning according to claim 1, characterized in that: The feature map in step 1 is composed of layout features and global routing features. The layout features are various parameters used to describe the placement of devices on the chip in the back-end design of digital ICs. They provide important information about the routable area on the chip. The global routing features are used to describe various parameters related to Gcell generated in the global routing stage in digital IC design, and are used to predict problems that may occur in the detailed routing stage.

3. The chip design rule violation prediction method based on deep learning according to claim 2 is characterized in that: The layout features include the following: Design boundary feature Design Boundary Feature, grid attribute Grid Attribute, row attribute Row Attribute, track attribute Track Attribute, line attribute NetAttribute, device attribute Instance Attribute; the local wiring features include: the total number of tracks Total Track in the vertical and horizontal directions, the number of remaining tracks Remaining Track, and the number of overflow tracks Overflow Track.

4. The chip design rule violation prediction method based on deep learning according to claim 3 is characterized in that: The step 1 comprises the following specific steps: Step 1.1: Based on the layout feature and global routing feature, multi-scale feature fusion factors are considered. For each Gcell, the feature values ​​of other Gcells nearby are considered, including design boundary attributes, grid attributes, and row attributes, and the average values ​​are taken respectively. The average values ​​calculated by the neighbor Gcells reflect the routing difficulty of the target Gcell. When training the model, the neighbor attribute is defined; Step 1.2: Define the boundary attribute Boundary Attribute. If the Gcell is at the boundary, the boundary attribute is 1, otherwise it is 0; Step 1.3: Define the Gcell Size Attribute and the standard cell Track Attribute respectively; Step 1.4: The present invention adopts undersampling technology to improve the generalization ability of the model.

5. The chip design rule violation prediction method based on deep learning according to claim 4 is characterized in that: The step 1.4 includes the following specific steps: Step 1.4.1: Classify all Gcells into three categories: Gcells with DRV, Gcells close to the first category of Gcells but without DRV, and Gcells without DRV and Gcells nearby that do not have DRV; Step 1.4.2: The first type of Gcells and the second type of Gcells participate in model training normally; Step 1.4.3: Randomly select 20% or even less of the third category Gcells as training samples, and the remaining third category Gcells do not participate in model training.

6. The chip design rule violation prediction method based on deep learning according to claim 1 is characterized in that: Step 1: The target map Target Maps is composed of the number of DRVs contained in each Gcell. The target map is used to indicate whether there is a violation in each Gcell of the chip layout. The target map is regarded as the "correct answer" that the model attempts to learn and predict.

7. The chip design rule violation prediction method based on deep learning according to claim 1 is characterized in that: The step 2 comprises the following specific steps: Step 2.1: In the model training phase, first you need to obtain data from the process in step 1. This data includes the Gcell information and placement information extracted from the global routing phase, as well as the corresponding DRV information. Step 2.2: The acquired data will be randomly divided into two groups: training data set and validation data set. The training data set is used for the initial training of the model. The model learns the relationship between the features and labels in these data to master the ability to predict DRV. The validation data set is used to evaluate the performance of the model after the initial training is completed to determine whether the model has learned enough information and can make accurate predictions on unseen data. Step 2.3: During the training process, the performance of the model is monitored by prediction speed and prediction accuracy. If the model does not meet the predetermined performance standards on the validation dataset, the model parameters need to be adjusted and optimized, and then the model is retrained using all the data - the combined training and validation datasets. Step 2.4: Once the model reaches a satisfactory performance standard on the validation dataset, it is considered as the optimal DRV prediction model and used for subsequent prediction tasks; Step 2.5: Testing phase: In this phase, the optimal model will be finally evaluated on a set of independent test datasets to verify the generalization ability and practical application effect of the model.

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