Data processing method, processing circuit, circuit control method and processing system

Abstract

The invention discloses a data processing method, a processing circuit, a circuit control method and a processing system, and the method comprises the steps: copying a value of each pixel point on a focal plane into a plurality of processing units, and carrying out different convolution calculation operations at the same time through employing a plurality of same input values and different weight values, thereby obtaining a plurality of convolution results. According to the data processing method provided by the invention, a plurality of convolution operations on the focal plane can be simultaneously carried out, the calculation efficiency is improved, and the degree of parallelism and the running speed are improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a data processing method, a processing circuit, a circuit control method and a processing system. Background Art

[0002] In the data processing method in the prior art, when performing a convolution operation on data, the image sensor reads the image data row by row, reading a row of pixel values ​​each time. The read row data is then stored in a memory unit in preparation for the convolution calculation. Alternatively, each element of the convolution kernel is mapped to the corresponding pixel position of the image sensor array, and a convolution multiplication is performed. Move one step to the right after each convolution operation. When all convolution kernels return to the initial position of the same row, move one step downward. Repeat the above steps until all convolution kernels traverse the entire image, summarize all convolution results, and obtain a complete convolution image. Finally, return to the initial state by moving rightward and downward several times.

[0003] However, the convolution operation in the existing data processing methods is not efficient. When a row of pixel values ​​is read each time and stored in the memory unit for convolution calculation, the calculation speed is impaired due to the performance limitations of bus bandwidth, data transmission or local memory. Alternatively, when the convolution kernel is mapped to the corresponding pixel position of the image sensor array and moves right and downward by the corresponding step size to traverse the entire image for convolution operation, a large number of invalid convolution operations will be performed, wasting power and time. Summary of the invention

[0004] The present invention provides a data processing method, a processing circuit, a circuit control method and a processing system to realize different convolution calculation operations using multiple processing units with the same value and different weight values, so that multiple convolution operations on the focal plane can be performed simultaneously, thereby improving calculation efficiency.

[0005] According to a first aspect of the present invention, there is provided a data processing method, the method comprising:

[0006] For each pixel on the focal plane, copy processing units; wherein the width and height of the convolution kernel are both n, and n≥1; the convolution step length is s; wherein s≥1;

[0007] In one convolution operation, each of the processing units in the pixel point is multiplied by the weight of the corresponding convolution kernel to obtain a first convolution result; the first convolution results of the processing units corresponding to the same convolution kernel are accumulated on the same row to obtain a second convolution result;

[0008] The second convolution results between rows are accumulated and the final convolution result is output.

[0009] According to a second aspect of the present invention, there is provided a data processing circuit, the data processing circuit comprising: a focal plane module and a pulse width generator module;

[0010] The focal plane module and the pulse width generator module are connected;

[0011] The pulse width generator module is used to output a pulse width modulation signal representing the weights of different convolution kernels to the focal plane;

[0012] The focal plane module includes a plurality of pixel point circuits;

[0013] The plurality of pixel point circuits of the focal plane module are used to multiply n identical input values ​​with corresponding pulse width modulation signals to obtain a first convolution result;

[0014] Accumulating the first convolution results in the pixel point circuits corresponding to the same convolution kernel on the same row to obtain a second convolution result;

[0015] The second convolution results between rows are accumulated and the final convolution result is output.

[0016] According to a third aspect of the present invention, a data processing circuit control method is provided, wherein the data processing circuit comprises a controller module; the pulse width generator module comprises a weighted register unit and a pulse generating unit;

[0017] The data processing circuit control method comprises:

[0018] The controller module controls the adjacent The pixel point circuits obtain the value of the same pixel point; wherein n is the size of the convolution kernel, and s is the step size of the convolution;

[0019] In a convolution operation, the controller module controls the weight register unit to generate a weight value according to the convolution kernel and sends it to the pulse generation unit; the controller module controls the pulse generation unit to generate a pulse width modulation signal according to the received weight value and simultaneously sends it to each pixel point circuit of the focal plane;

[0020] The controller module controls the accumulation of output results of the pixel point circuits in the focal plane according to the moment when each pixel point circuit in the focal plane receives the pulse width modulation signal;

[0021] After the output results of the pixel point circuit are accumulated, the controller module controls the output of the accumulated results.

[0022] According to a fourth aspect of the present invention, there is provided a data processing system, the data processing system comprising:

[0023] The data processing circuit and analog-to-digital conversion module provided by any embodiment of the present invention;

[0024] The analog-to-digital conversion module is connected to the data processing circuit, and is used to perform analog-to-digital conversion on the signal output by the data processing circuit.

[0025] The present invention provides a data processing method, a processing circuit, a circuit control method and a processing system. In the technical solution provided by the embodiment of the present invention, the pixel points in the focal plane are copied, and for each processing unit, the weight values ​​in the corresponding convolution kernels are multiplied according to their different positions to obtain the final convolution result. The product of the processing units in the same row of each convolution kernel and the weight value is the first convolution result, the first convolution results between the same row of the same convolution kernel are added to obtain the second convolution result, and the second convolution results between different rows are added to obtain the final convolution result. In this way, different convolution calculation operations are performed using multiple identical input values ​​and different weight values ​​to obtain multiple convolution results, thereby improving the degree of parallelism and running speed.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic diagram of a data processing method provided in the related art;

[0029] Figure 2 A schematic diagram of another data processing method provided in the related art;

[0030] Figure 3 A flow chart of a data processing method provided by an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of a data processing method provided by an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of another data processing method provided by an embodiment of the present invention;

[0033] Figure 6A schematic diagram of a data processing circuit structure provided by an embodiment of the present invention;

[0034] Figure 7 A focal plane module pixel circuit diagram provided by an embodiment of the present invention;

[0035] Figure 8 A schematic diagram of another data processing circuit structure provided by an embodiment of the present invention;

[0036] Fig. 9 A flow chart of a data processing circuit control method provided by an embodiment of the present invention;

[0037] Fig.10 A structural schematic diagram of a data processing system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0040] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0041] Figure 1 A schematic diagram of a data processing method provided in the related art is shown in FIG. Figure 1As shown, the control module 010 controls the row control module 020 to read the data in the image sensor, and sends the data of each row to the data storage module 030 for storage, and then performs a convolution calculation operation. When the convolution kernel is 3×3, the control module 010 first controls the row control module 020 to read the first row of data in the focal plane and send it to the data storage module 030 for storage, and then the control module 010 sequentially controls the row control module 020 to read the second and third rows of data in the focal plane and send them to the data storage module for storage. After reading and storing the data of the first, second and third rows, a convolution operation is performed on the data stored in the data storage module 030. After the convolution is completed, the next convolution is performed, that is, the data of the second, third and fourth rows are read, stored and convolved in this way. Until the data read by all image sensors in the entire focal plane is processed.

[0042] Figure 1 In the data processing method shown in , on the one hand, the control module and the row control module need to read and store data row by row, and then perform the corresponding convolution after the storage is completed. Because only one row of data can be read at a time, the parallelism is small, which limits the calculation speed and cannot achieve the required performance level in applications that require high throughput. On the other hand, when reading and storing data row by row, frequent data transmission is required, which will lead to bus bandwidth and data transmission delays, and increase the system's demand for local memory, especially when processing high-resolution images, the capacity demand for the row buffer is large.

[0043] Figure 2 A schematic diagram of another data processing method provided in the related art, such as Figure 2As shown, the 3×3 convolution kernel is flattened on the focal plane to obtain 9 regions, among which the 3×3 region includes the first region W1, the second region W2, the fourth region W4 and the fifth region W5, the 3×1 region includes the third region W3 and the sixth region W6, the 1×3 region includes the seventh region W7 and the eighth region W8, and the 1×1 region includes the ninth region W9. Among them, the third region W3, the sixth region W6, the seventh region W7, the eighth region W8 and the ninth region W9 cannot be completely placed because the size does not match the convolution kernel, making the calculation of these positions invalid. And only the first region W1, the second region W2, the fourth region W4 and the fifth region W5 can actually perform convolution operations. When performing convolution operations, the corresponding regions of the first region W1, the second region W2, the fourth region W4 and the fifth region W5 perform convolution operations, and then move one step to the right after each convolution operation. When all convolution kernels return to the initial position of the same row, move down one step. Repeat the above steps until all convolution kernels traverse the entire image, and then summarize all convolution results to get a complete convolution image. Finally, return to the initial state by moving rightward and downward several times.

[0044] Figure 2 In the data processing method shown in , although this technology can ensure a large degree of computational parallelism in convolution calculation, it can also be intuitively seen that due to the mismatch between the convolution kernel and the image size, the distribution of the convolution kernel on the focal plane will be irregular. This irregular distribution will make it impossible to place a convolution kernel completely in the edge area of ​​the image, making the calculation of these positions invalid. Therefore, some redundant convolution operations will be introduced, wasting energy and time.

[0045] Figure 3 A flow chart of a data processing method provided by an embodiment of the present invention is as follows: Figure 3 As shown, the method includes:

[0046] S101, for each pixel on the focal plane, copy processing units; wherein the width and height of the convolution kernel are both n, and n≥1; the convolution step length is s; wherein s≥1;

[0047] Specifically, n is the width and height of the convolution kernel. When performing convolution on the focal plane, a multi-channel convolution operation is performed to perform different convolution calculation operations using multiple identical input values ​​(i.e., the values ​​of the pixels on the focal plane) and different weight values ​​(i.e., the corresponding weight values ​​in the convolution kernel) to obtain multiple convolution results. When the width and height of the convolution kernel are 3 and the convolution step size is 1, the pixels on the focal plane are multiplied with up to 3 different weight values ​​in one convolution operation. Therefore, in step S101, 1 is copied for each pixel on the focal plane. processing units to assign different weight values ​​to each processing unit.

[0048] Figure 4 A schematic diagram of a data processing method provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, data processing is performed on a focal plane 201 with 7 pixel columns, wherein the size of the convolution kernel 202 is 3×3 and the convolution step is 1. Three processing units 203 are replicated for the pixel.

[0049] Exemplarily, three processing units are copied for the pixel 02 in the 1st row and the 3rd column, including: the 1st processing unit PE02-1 of the pixel 02 in the 1st row and the 3rd column, the 2nd processing unit PE02-2 of the pixel 02 in the 1st row and the 3rd column, and the 3rd processing unit PE02-3 of the pixel 02 in the 1st row and the 3rd column.

[0050] S102, in a convolution operation, multiplying each processing unit in the pixel point by the weight of the corresponding convolution kernel to obtain a first convolution result;

[0051] Specifically, the pixel is copied After processing units are generated, each processing unit is multiplied by the weight of the corresponding convolution kernel to obtain the first convolution result.

[0052] For example, Figure 4 As described above, for the pixels in the first two columns and the last two columns of the focal plane 201, since they are not multiplied with all the weight values ​​of the convolution kernel during the convolution operation, these pixels are not multiplied with all the weight values ​​of the corresponding rows of the convolution kernel.

[0053] For the pixel point 00 in the 1st row and 1st column of the focal plane 201, it is only multiplied by the weight value w00 in the 1st row and 1st column of the convolution kernel 202. Therefore, the 1st processing unit PE00-1 in the 1st row and 1st column of the pixel point 00 only needs to be multiplied by the weight value w00 in the 1st row and 1st column of the convolution kernel 202. For the pixel point 05 in the 1st row and 6th column of the focal plane 201, it is only multiplied by the weight value w01 in the 1st row and 2nd column and the weight value w02 in the 1st row and 3rd column of the convolution kernel 202. Therefore, the 2nd processing unit PE05-2 in the 1st row and 6th column of the pixel point 05 is multiplied by the weight value w01 in the 1st row and 2nd column; the 3rd processing unit PE05-3 in the 1st row and 6th column of the pixel point 05 is multiplied by the weight value w02 in the 1st row and 3rd column.

[0054] When the value of the number of columns j3 of the pixel point on the focal plane is: n≤j3≤j-n+1, ​​the pixel point is located between the first n columns and the last n columns of the focal plane. Then the pixel point is multiplied by the three weight values ​​of the corresponding row of the convolution kernel. For example, Figure 4Pixel 12 in the second row and third column on the focal plane 201 in the image: Pixel 12 in the second row and third column is multiplied by weight value w10 in the second row and first column, weight value w11 in the second row and second column, and weight value w12 in the second row and third column on the corresponding row of the convolution kernel. Therefore, the first bit processing unit PE12-1 of pixel 12 in the second row and third column is multiplied by weight value w10 in the second row and first column, the second bit processing unit PE12-2 of pixel 12 in the second row and third column is multiplied by weight value w11 in the second row and second column, and the third bit processing unit PE12-3 of pixel 12 in the second row and third column is multiplied by weight value w12 in the second row and third column. The corresponding products are the first convolution results.

[0055] S103, accumulating the first convolution results of the processing units corresponding to the same convolution kernel on the same row to obtain a second convolution result;

[0056] like Figure 4 As shown, for the 1st row, 1st column, 1st bit processing unit PE00-1 in the processing unit group 204, it is multiplied by the 1st row, 1st column weight value w00, the 1st row, 2nd column, 2nd bit processing unit PE01-2 is multiplied by the 1st row, 2nd column weight value w01, and the 1st row, 3rd column, 3rd bit processing unit PE02-3 is multiplied by the 1st row, 3rd column weight value w02. Therefore, the three first convolution results are obtained by performing convolution operations on the processing units corresponding to the same convolution kernel on the same row, and the three first convolution results are accumulated to obtain the second convolution result. Similarly, the 1st processing unit PE10-1 of the pixel in the 2nd row and 1st column is multiplied by the weight value w10 in the 2nd row and 1st column, the 2nd processing unit PE11-2 of the 2nd row and 2nd column is multiplied by the weight value w11 in the 2nd row and 2nd column, and the 3rd processing unit PE12-3 of the 2nd row and 3rd column is multiplied by the weight value w12 in the 2nd row and 3rd column. These three first convolution results are obtained by performing convolution operations on the processing units corresponding to the same convolution kernel on the same row. The three first convolution results are accumulated to obtain the second convolution result.

[0057] S104, accumulating the second convolution results between rows and outputting a final convolution result;

[0058] Continue to refer Figure 4, the first bit processing unit PE00-1 of the first row and first column pixel point, the first row and second column and the second bit processing unit PE01-2 and the first row and third column and the third bit processing unit PE02-3 in the same processing unit group 204 perform convolution operation to obtain a second convolution result; the first bit processing unit PE10-1 of the second row and first column pixel point, the second bit processing unit PE11-2 and the second row and third column and the third bit processing unit PE12-3 perform convolution operation to obtain another second convolution result; the first bit processing unit PE20-1 of the third row and first column, the second bit processing unit PE21-2 and the third row and third column and the third bit processing unit PE22-3 perform convolution operation to obtain another second convolution result. The pixel point column number composition corresponding to these three second convolution results is all the first column, the second column and the third column, and these three second convolution results are accumulated to finally output the final convolution result.

[0059] Figure 5 A schematic diagram of another data processing method provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, in combination with the above embodiment, when the number of columns of the focal plane 201 is 7, the convolution kernel 202 is 3×3, and the convolution step length is 1, in the first convolution operation, the 1st to 3rd rows are the first convolution area 211, and the 4th to 6th rows are the second convolution area 212. Corresponding convolution operations are performed on the first convolution area 211 and the second convolution area 212. When the convolution kernel size is 3×3 and the convolution step length is 1, the first convolution area 211 has 5 pixel point groups for convolution calculation during convolution; and 5 pixel point groups are also obtained in the second convolution area 212 for convolution calculation.

[0060] After the first convolution operation is completed, the convolution kernel moves downward by one step, and the second convolution operation begins. In the second convolution operation, the focal plane 201 can be divided into two convolution regions: the second to fourth rows are the third convolution region 213, and the fifth to seventh rows are the fourth convolution region 214. Convolution operations are performed in the third convolution region and the fourth convolution region 214.

[0061] After the second convolution operation is completed, the convolution kernel moves down one step, and the third convolution operation begins. In the third convolution operation, the focal plane can be divided into three parts, where the first and second rows are the first part, the third and fifth rows are the second part, and the sixth and seventh rows are the third part. The convolution operation is performed in the second part.

[0062] After the three convolution operations are completed, all the convolution results on the focal plane can be obtained.

[0063] Specifically, taking the first convolution operation as an example, in a data processing method provided by an embodiment of the present invention, when performing a convolution operation, a convolution operation can be performed simultaneously for each part that needs to be convolutionally operated. In this convolution operation, a value is assigned between the pixels in the first column and the last column and the convolution kernel, that is, the pixels in the first column and the weight value in the first column of the convolution kernel are multiplied correspondingly, and the pixels in the last column and the weight value in the third column of the convolution kernel are multiplied correspondingly. For example, the pixel point 00 in the first row and the first column is multiplied with the weight value w00 in the first row and the first column of the convolution kernel only in the first pixel point group 221.

[0064] Two values ​​are assigned between the pixels in the second column and the second-to-last column and the convolution kernel, that is, two corresponding multiplication operations are performed between the pixels in the second column and the weight values ​​in the first column and the second column of the convolution kernel, and two corresponding multiplication operations are performed between the pixels in the second-to-last column and the weight values ​​in the second column and the third column of the convolution kernel. For example, the pixel 01 in the first row and the second column is multiplied with the weight value in the first row and the second column of the convolution kernel w01 in the first pixel group 221, and is multiplied with the weight value in the first row and the first column of the convolution kernel w00 in the second pixel group 222.

[0065] The pixel points of the remaining columns of the focal plane are multiplied with the weight values ​​of all columns of the convolution kernel, that is, three multiplication operations are performed. For example, the pixel point 02 in the first row and third column is multiplied with the weight value w02 in the first row and third column of the convolution kernel in the first pixel point group 221, multiplied with the weight value w01 in the first row and second column of the convolution kernel in the second pixel point group 222, and multiplied with the weight value w00 in the first row and first column of the convolution kernel in the third pixel point group 223.

[0066] In summary, if Figure 5As shown, when a convolution operation with a step size of 1 and a convolution kernel size of 3×3 is performed on the focal plane 201, three processing units are copied for each pixel point on the focal plane 201. In one convolution operation, each of the processing units in the pixel point is multiplied by the weight of the corresponding convolution kernel to obtain a first convolution result. The pixels in the first column and the last column are multiplied by one weight value of the convolution kernel; the pixels in the second column and the second to last column are multiplied by two weight values ​​of the convolution kernel; and the pixels in the remaining columns are multiplied by three weight values ​​of the convolution kernel. The first convolution results of the processing units corresponding to the same convolution kernel are accumulated on the same row to obtain a second convolution result. When the three first convolution results are obtained by performing a convolution operation on the processing units corresponding to the same convolution kernel on the same row, the three first convolution results are accumulated to obtain a second convolution result. The second convolution results between rows are accumulated to output the final convolution result. In the second convolution results between different rows, if the three second convolution results of the pixels correspond to the same number of three pixel columns, the three second convolution results are accumulated to obtain the final convolution result. Finally, the data processing of the focus plane 201 is realized.

[0067] In the data processing method provided in the embodiment of the present invention, the pixel points in the focal plane are copied. For each processing unit, the weight values ​​in the corresponding different convolution kernels are multiplied according to their different positions to obtain the final convolution result. The product of the processing units in the same row of each convolution kernel and the weight value is the first convolution result, the first convolution results between the same row of the same convolution kernel are added to obtain the second convolution result, and the second convolution results between different rows are added to obtain the final convolution result. In this way, different convolution calculation operations are performed using multiple identical input values ​​and different weight values ​​to obtain multiple convolution results, thereby improving parallelism and running speed.

[0068] In combination with the above embodiment, after one convolution calculation, the convolution kernel area is moved down by one step to perform the next convolution operation until the final convolution result on the entire focal plane is obtained; wherein, the height of the convolution area is equal to the height of the convolution kernel, the width of the convolution area is equal to the width of the focal plane, and along the height direction of the focal plane, the boundaries of adjacent convolution areas are adjacent.

[0069] Specifically, Figure 5 As shown, when performing the first convolution operation, the focal plane has two convolution areas: the 1st to 3rd rows of the focal plane are the first convolution area 211, and the 4th to 6th rows of the focal plane are the second convolution area 212.

[0070] After the convolution operation is completed in the two convolution areas, the convolution kernel moves down by one step, and the second convolution operation is performed. The second to fourth rows of the focal plane are the third convolution area 213, and the fifth to seventh rows of the focal plane are the fourth convolution area 214.

[0071] In combination with the above embodiments, Figure 3 The step S102 shown includes: when the focal plane is the jth column and s=1, in each convolution area, for the pixel in the j1th column and the n1th row, multiply the h1th bit processing unit of the pixel by the weight of the n1th row and the h1th column in the convolution kernel, where j1<n, h1≤j1; where n1 is the number of rows where the pixel is located in the convolution area, n1≤n.

[0072] For details, please refer to Figure 4 , taking the convolution kernel size of 3×3, the convolution step size of 1 and the number of focal plane columns of 7 as an example, that is, n=3, j=7, at this time j1<3, h1≤j1. At this time, j1=1 or 2; when j1=1, h1=1, when j1=2, h1=1 or 2.

[0073] When j1=1, n1=1, h1=1. Multiply the first bit processing unit of the pixel point 00 in the first row and first column by the weight value w00 in the first row and first column of the convolution kernel, that is, multiply the first bit processing unit of the pixel point by the weight value w00 in the first row and first column of the convolution kernel to obtain the first convolution result.

[0074] When j1=2, n1=2, h1=1 or 2. Then the second processing unit of the pixel 11 is multiplied by the weight of the first row and second column in the convolution kernel, that is, the first processing unit of the pixel is multiplied by the weight value w01 of the first row and second column in the convolution kernel to obtain the first convolution result. Alternatively, the first processing unit of the pixel is multiplied by the weight of the first row and first column in the convolution kernel, that is, the first processing unit of the pixel is multiplied by the weight value w00 of the first row and first column in the convolution kernel to obtain the first convolution result.

[0075] The method for obtaining the first convolution result for the remaining pixel points in the j1th column and the n1th row is the same as that in the above embodiment, which will not be described herein again.

[0076] In each convolution area, for the pixel in the j2th column and the n1th row, multiply the weights in the convolution kernel of the h2th processing unit of the pixel in the n1th row and the h2th column, where j-n+1<j2≤j, nj-j2≤h2≤n;

[0077] For details, please refer to Figure 4 , that is, n = 3, j = 7. At this time, 5 < j2 ≤ 7, when j2 = 6, h2 = 2 or 3; when j2 = 7, h2 = 3.

[0078] When j2=6, n1=2, h2=2 or 3. When h2=2, the second bit processing unit of the pixel point 15 in the second row and the sixth column is multiplied by the weight of the second row and the second column in the convolution kernel, that is, the second bit processing unit of the pixel point 15 in the second row and the sixth column is multiplied by the weight value w11 in the second row and the second column in the convolution kernel to obtain the first convolution result. When h2=3, the third bit processing unit of the pixel point 15 in the second row and the sixth column is multiplied by the weight of the second row and the third column in the convolution kernel, that is, the third bit processing unit of the pixel point 15 in the second row and the sixth column is multiplied by the weight value w12 in the second row and the third column in the convolution kernel to obtain the first convolution result.

[0079] When j2 = 7, n1 = 1, h2 = 3. Multiply the 3rd processing unit of the pixel 06 in the 1st row and 7th column by the weight in the 1st row and 3rd column of the convolution kernel, that is, multiply the 3rd processing unit of the pixel by the weight value w02 in the 1st row and 3rd column of the convolution kernel to obtain the first convolution result.

[0080] The method for obtaining the first convolution result for the remaining pixel points in the j2th column and the n1th row is the same as that in the above embodiment, which will not be described herein again.

[0081] In each convolution area, for the pixel in the j3th column and the n1th row, multiply the h3th bit processing unit of the pixel by the n1th row and the h3th column weight in the convolution kernel to obtain the first convolution result; where n≤j3≤j-n+1, ​​h3≤n;

[0082] For details, please refer to Figure 4 , that is, n = 3, j = 7. At this time, 3≤j3≤5, h3≤3.

[0083] When j3=3, n1=2, h2=1 or 2 or 3.

[0084] When h2=1, the first processing unit of the pixel point 12 in the second row and third column is multiplied by the weight of the second row and first column in the convolution kernel, that is, the first processing unit of the pixel point 12 in the second row and third column is multiplied by the weight value w10 of the second row and first column in the convolution kernel to obtain the first convolution result.

[0085] When h2=2, the 2nd processing unit of the pixel point 12 in the 2nd row and 3rd column is multiplied by the weight of the 2nd row and 2nd column in the convolution kernel, that is, the 2nd processing unit of the pixel point 12 in the 2nd row and 3rd column is multiplied by the weight value w11 of the 2nd row and 2nd column in the convolution kernel to obtain the first convolution result.

[0086] When h2=3, the 3rd processing unit of the pixel point 12 in the 2nd row and 3rd column is multiplied by the weight in the 2nd row and 3rd column in the convolution kernel, that is, the 3rd processing unit of the pixel point 12 in the 2nd row and 3rd column is multiplied by the weight value w12 in the 2nd row and 3rd column in the convolution kernel to obtain the first convolution result.

[0087] The method for obtaining the first convolution result for the remaining pixel points in the j3th column and the n1th row is the same as that in the above embodiment, which will not be repeated here.

[0088] In combination with the above embodiments, Figure 3 Step S103 shown includes: adding the first convolution result corresponding to the 1st processing unit of the j4th column pixel point in each row of the focal plane to the first convolution result corresponding to the n2th processing unit of the n-1 j5th column pixel points adjacent to the right, to obtain a second convolution result, where j4<j5≤n+j4-1; n2=j5-j4+1.

[0089] Exemplary, combined Figure 4 , 5 As in the above embodiment, the convolution kernel size is 3×3 and the number of focal plane columns is 7, that is, n=3 and j=7.

[0090] Among all the pixels in the first row of the focal plane, the first row and first column pixel 00 processing unit PE00-1 is its first bit processing unit. The n-1 j5th column pixels adjacent to the right of the first row and first column pixel 00 are pixel 01 in the first row and second column and pixel 02 in the first row and third column, that is, 1<j5≤3. The first convolution result corresponding to the first bit processing unit PE00-1 of the first row and first column pixel 00 is added to the second bit processing unit PE01-2 of the first row and second column pixel 01 and the third bit processing unit PE01-3 of the first row and third column pixel 02 to obtain the second convolution result.

[0091] In combination with the above embodiments, Figure 3 Step S104 shown includes: in the column direction of each convolution area, when the number of columns of n pixels corresponding to each first convolution result in the n second convolution results are the same, adding the n second convolution results to output the final convolution result.

[0092] Specific, combined Figure 4As with the above embodiment, there are the following three second convolution results: the second convolution result obtained by the first processing unit PE00-1 of the 1st row and 1st column pixel 00, the second processing unit PE01-2 of the 1st row and 2nd column pixel 01 and the third processing unit PE02-3 of the 1st row and 3rd column pixel 02; the second convolution result obtained by the first processing unit PE10-1 of the 2nd row and 1st column pixel 00, the second processing unit PE11-2 of the 2nd row and 2nd column pixel 11 and the third processing unit PE12-3 of the 2nd row and 3rd column pixel 12; the second convolution result obtained by the first processing unit PE20-1 of the 3rd row and 1st column pixel 20, the second processing unit PE21-2 of the 3rd row and 2nd column pixel 21 and the third processing unit PE22-3 of the 3rd row and 3rd column pixel 22. It can be seen from the three second convolution results of the above embodiment that they are respectively the second convolution results obtained by the pixel point 00 in the first row and the first column, the pixel point 01 in the first row and the second column, and the second convolution results obtained by the pixel point 10 in the second row and the first column, the pixel point 11 in the second row and the second column, and the second convolution results obtained by the pixel point 20 in the third row and the first column, the pixel point 21 in the third row and the second column, and the second convolution results obtained by the pixel point 22 in the third row and the third column. The three pixel point column numbers corresponding to these three second convolution results are all 1, 2, and 3, so these three second convolution results are added together to output the final convolution result.

[0093] Figure 6 A schematic diagram of a data processing circuit structure provided by an embodiment of the present invention is shown in FIG. Figure 6 As shown, the focal plane module 301 and the pulse width generator module 302 are connected; the pulse width generator module 302 is used to output a pulse width modulation signal representing the weights of different convolution kernels to the focal plane; the focal plane module 301 includes a plurality of pixel point circuits 303; the plurality of pixel point circuits 303 of the focal plane module 301 are used to multiply n identical input values ​​with the corresponding pulse width modulation signal to obtain a first convolution result; the first convolution results in the pixel point circuits 303 corresponding to the same convolution kernel are accumulated on the same row to obtain a second convolution result; the second convolution results between rows are accumulated to output a final convolution result.

[0094] Specifically, the pulse width generator module 302 generates a series of pulse width modulation (PWM) signals according to the preset convolution kernel weight values. Optionally, the pulse width of the pulse width modulation signal is set according to the value of each weight in the corresponding convolution kernel. The larger the weight, the wider the pulse width; the smaller the weight, the narrower the pulse width.

[0095] After the focal plane module 301 receives the PWM signal from the pulse width generator module 302, it multiplies these signals with n identical input values. Specifically, the input value is the value of the photocurrent collected by the focal plane module 301. In the multiple pixel point circuits 303 of the focal plane module 301, each pixel point circuit 303 includes a photoelectric conversion element, and the input value is the light intensity value of the pixel point to be convolved. The light intensity of the pixel point to be convolved is collected by the photoelectric conversion element, and different photocurrent sizes are obtained according to different light intensities. In the pixel point circuit, according to the different photocurrent sizes, the energy storage element of the pixel point circuit has different discharge currents when discharging. Optionally, the photoelectric conversion element is a photodiode, and the energy storage element is a capacitor.

[0096] Among them, "multiplication" is to control the switch circuit through the PWM signal, so that the input value is passed (or accumulated in some way) when the PWM signal is at a high level, and is ignored or attenuated when it is at a low level. Therefore, each processing unit generates a "weighted" value proportional to the weight according to the corresponding PWM signal, that is, the first convolution result.

[0097] Optionally, the pixel circuit 303 in the focal plane module 301 can be controlled by a PWM signal. The pixel circuit 303 converts the input value into a discharge of the pixel circuit 303, and the PWM signal controls the discharge time of the pixel circuit 303. The longer the pulse width of the PWM signal, the longer the discharge time of the controlled pixel circuit 303; otherwise, the shorter it is. Then the weighted calculation of the input value and the convolution kernel is converted into the control of the discharge time of the pixel circuit 303.

[0098] The convolution operation on the input value in the focal plane module 301 is converted into the conduction time of the pixel point circuit 303 controlled by the input value and the pulse width of the pulse width modulation signal.

[0099] On the same row, the first convolution results generated by all processing units are accumulated according to the convolution kernels to which they belong, and the second convolution result corresponding to the row is obtained. This implements the weighted sum calculation within the horizontal sliding window of the convolution kernel in the convolution operation.

[0100] In different rows, the second convolution results between rows are accumulated again to finally obtain the output result of the entire convolution operation. Specifically, according to the positions of the pixel points corresponding to the second convolution results between rows, the corresponding second convolution kernels are added to obtain the final convolution result.

[0101] Optionally, the accumulation of the first convolution result and the second convolution result may be a series connection of output signals of the pixel point circuit 303 in the corresponding focal plane module 301 .

[0102] An embodiment of the present invention provides a data processing circuit, wherein a pulse width generator module outputs a pulse width modulation signal representing different convolution kernel weight values ​​to a focal plane, and performs weighted calculation of the focal plane input value to obtain a first convolution result. The corresponding convolution results between the same row and different rows are then accumulated to obtain the final convolution result. In this way, fine control of the PWM signal is achieved, and a high-precision weight representation can be achieved, thereby maintaining the accuracy of the convolution operation. Moreover, the PWM signal can also be controlled for multiple pixel point circuits on the focal plane at the same time to achieve global parallelism and multi-bit convolution calculation functions for data processing, thereby improving parallelism and operating speed. Complex analog signal processing is avoided, the response speed is improved, and the delay is reduced. Using the PWM signal to control the switch discharge time to achieve the multiplication operation helps to reduce the quantization error and improve the accuracy of the convolution calculation.

[0103] Figure 7 A focal plane module pixel circuit diagram provided by an embodiment of the present invention, such as Figure 7 As shown, the focal plane module 301 includes multiple pixel circuits 303, each pixel circuit 303 includes a control terminal PWM_IN, and the output end of the pulse width generator module 302 includes multiple sub-output terminals, which are connected one-to-one with the control terminal PWM_IN of the pixel circuit 303 of the focal plane.

[0104] The pulse width generator module 302 generates a pulse width modulation signal about the convolution kernel weight value, and the generated pulse width modulation signal is output through the sub-output terminal of the pulse width generator module 302 and sent to the control terminal PWM_IN of the pixel circuit 303. The pixel circuit 303 performs corresponding data processing according to the received pulse width modulation signal.

[0105] Continue to refer Figure 7 The focal plane module pixel circuit also includes: a P-type field effect transistor PMOS1, an N-type field effect transistor NMOS1, a photodiode PD1 and a first capacitor C1; wherein the first end of the P-type field effect transistor PMOS1, the first end of the N-type field effect transistor NMOS1 and the negative end of the photodiode PD1 are connected; the second end of the N-type field effect transistor NMOS1 is connected to the first power supply, the second end of the P-type field effect transistor PMOS1 is connected to the first end of the first capacitor C1 and the pixel output end, the positive end of the photodiode PD1 is grounded; the second end of the first capacitor C1 is grounded.

[0106] Specifically, the photodiode PD1 is used to capture the optical signal and convert it into an electrical signal as an input value for subsequent convolution calculation. The control end of the N-type field effect transistor NMOS1 can be used as a reset end REST to receive a reset signal sent by the control module.

[0107] In the initialization state, the pulse width generator module 302 sends a low level signal, and the P-type field effect transistor PMOS1 is in the on state. When the reset terminal REST receives a high level signal, the N-type field effect transistor NMOS1 is turned on. At this time, the photodiode PD1 and the power supply terminal VDD charge the first capacitor C1, and the photodiode PD1 is reverse biased.

[0108] After a certain period of time, the first capacitor C1 is fully charged. A low-level signal is sent to the reset terminal REST, and the N-type field effect transistor NMOS1 is turned off. The convolution operation begins, and the control terminal PWM_IN receives the PWM signal sent by the pulse width generator module 302. Each pixel point circuit 303 is turned on for a corresponding time according to the pulse width of the corresponding PWM signal, and the capacitor is discharged to realize the multiplication operation through the photocurrent and the discharge time of the P-type field effect transistor PMOS1. The multiplication amount is the photocurrent size and the P-type field effect transistor PMOS1 conduction time. The photocurrent obtains different discharge values ​​through the combined effect of the discharge time, and finally leaves different amounts of charge on the capacitor. Finally, the input value in each pixel point circuit 303 is multiplied by the corresponding pulse width modulation signal to obtain the first convolution result.

[0109] Continue to refer Figure 7 In the focal plane module 301, a first switch is connected in series between the output terminals OUT of two adjacent pixel point circuits 303 in the same row.

[0110] The output terminals OUT of the pixel point circuits 303 in each column are connected, and a second switch is connected in series between the output terminals OUT of two adjacent pixel point circuits 303 in the same column.

[0111] When performing the initialization operation, all the first switches and the second switches are controlled to be disconnected to charge the first capacitor C1. After the convolution operation is completed, that is, after the first convolution result is obtained in all pixel point circuits 303, the first convolution results of the pixel point circuits 303 corresponding to the same convolution kernel on the same row are accumulated by controlling the conduction and disconnection of the first switches to obtain the second convolution result;

[0112] By controlling the on and off of the second switch, the second convolution results between rows are accumulated and the final convolution result is output.

[0113] Figure 8 This is another schematic diagram of the structure of a data processing circuit provided by an embodiment of the present invention, wherein the data processing circuit further includes a controller module 304 ; the pulse width generator module 302 includes a weighted register unit 3021 and a pulse generating unit 3022 .

[0114] The controller module 304 is connected to the weighted register unit 3021 , the pulse generating unit and the focal plane module 301 , the weighted register unit 3021 is connected to the pulse generating unit 3022 , and the pulse generating unit is connected to the focal plane module 301 .

[0115] Specifically, the controller controls the weight register unit 3021 to generate different multi-bit weights according to the weight value of the convolution kernel and sends them to the pulse generating unit 3022; the pulse generating unit 3022 generates a corresponding pulse width modulation signal according to the received multi-bit weight value. The corresponding pulse width modulation signal is sent to the pixel point circuit 303 of the focal plane module 301 to perform corresponding data processing operations.

[0116] Optionally, the pulse generating unit 3022 receives a plurality of weight values ​​of bits, each weight value representing one bit. The pulse width generator module 302 also includes a clock signal generating unit for synchronizing the generation of the pulse width modulation signal.

[0117] Fig. 9 A flow chart of a data processing circuit control method provided by an embodiment of the present invention is shown in FIG. Fig. 9 As shown, the data processing circuit further includes a controller module; the pulse width generator module includes a weighted register unit and a pulse generating unit, and the method includes:

[0118] S201, the controller module controls the adjacent The pixel circuits obtain the value of the same pixel.

[0119] Where n is the size of the convolution kernel, and s is the step size of the convolution. When performing convolution on the focal plane, a multi-channel convolution operation is performed to use multiple identical input values ​​(i.e., the values ​​of the pixels on the focal plane) and different weight values ​​(i.e., the corresponding weight values ​​in the convolution kernel) to perform different convolution calculation operations to obtain multiple convolution results. The pixel point circuits obtain the value of the same pixel point to achieve the simultaneous execution of multiple convolution calculations on the same pixel point.

[0120] S202, in a convolution operation, the controller module controls the weight register unit to generate a weight value according to the convolution kernel and sends it to the pulse width generator module;

[0121] Specifically, in combination with the above embodiment, in the weight register unit, a corresponding multi-bit weight value is generated according to the convolution kernel, and the weight value is sent to the pulse generation unit. The number of bits of the multi-bit weight value is selected according to the actual situation and is not limited here.

[0122] S203, the controller module controls the pulse generating unit to generate a pulse width modulation signal according to the received weight value and simultaneously sends the pulse width modulation signal to each pixel point circuit of the focal plane;

[0123] The pulse generating unit generates a pulse width modulation signal corresponding to the pulse width according to the received multi-bit weight value. Optionally, the larger the weight value, the larger the pulse width of the generated pulse width modulation signal.

[0124] The generated pulse width modulation signal is sent to each pixel circuit in the focal plane at the same time.

[0125] Specifically, as in the above-mentioned embodiment, in a data processing method provided by the present invention, the value of a pixel point is copied to multiple processing units, and multiple processing units with the same value are multiplied by the weight values ​​of different convolution kernels. Similarly, in a control method for a data processing circuit provided by an embodiment of the present invention, after generating pulse width modulation signals corresponding to different weight values ​​in different convolution kernels, the corresponding pulse width modulation signals are sent to each pixel point circuit of the focal plane at the same time.

[0126] For example, Figure 4 As shown in the data processing method, for the pixel point 03 in the 1st row and the 4th column, three processing units are copied for the pixel point 03 in the 1st row and the 4th column: the 1st processing unit PE03-1 in the 1st row and the 4th column, the 2nd processing unit PE03-2 in the 1st row and the 4th column, and the 3rd processing unit PE03-3 in the 1st row and the 4th column. Then, the 1st processing unit PE03-1 in the 1st row and the 4th column is multiplied by the weight value w00 in the 1st row and the 1st column in the convolution kernel, the 2nd processing unit PE03-2 in the 1st row and the 4th column is multiplied by the weight value w01 in the 1st row and the 2nd column in the convolution kernel, and the 3rd processing unit PE03-3 in the 1st row and the 4th column is multiplied by the weight value w02 in the 1st row and the 3rd column in the convolution kernel. Then in the control method of the data processing circuit provided by the embodiment of the present invention, for the pixel point 03 in the 1st row and the 4th column, the pulse generating unit can send the PWM signal corresponding to the weight value w00 in the 1st row and the 1st column of the convolution kernel to the first pixel point circuit that has obtained the value of the pixel point 03 in the 1st row and the 4th column; the pulse generating unit can send the PWM signal corresponding to the weight value w01 in the 1st row and the 2nd column of the convolution kernel to the second pixel point circuit that has obtained the value of the pixel point 03; the pulse generating unit can send the PWM signal corresponding to the weight value w02 in the 1st row and the 3rd column of the convolution kernel to the third pixel point circuit that has obtained the value of the pixel point 03 in the 1st row and the 4th column. Among them, these three times of sending the PWM signal are carried out simultaneously, and the first pixel point circuit, the second pixel point circuit and the third pixel point circuit are adjacent.

[0127] Optional, combined Figure 4 As shown, in each convolution region, adjacent pixel circuits that replicate the same pixel value are a pixel circuit unit;

[0128] When data processing is performed on the convolution area of ​​the first to third rows of pixels on the focal plane to be convolved, for the pixel circuit unit that obtains the pixel value 00 in the first row and the first column and the pixel value 03 in the first row and the fourth column, the pulse width modulation signal received by the first pixel circuit of each pixel circuit unit is generated according to the weight value w00 of the first row and the first column of the convolution kernel. The remaining pixels receive the pulse width modulation signal sent by the pulse generating unit. Among them, the pixel circuit unit that obtains the pixel value 01 in the first row and the second column and the pixel value 04 in the first row and the fifth column, the pulse width modulation signal received by the second pixel circuit of each pixel circuit unit is generated according to the weight value w01 of the first row and the second column of the convolution kernel; the pixel circuit unit that obtains the pixel value 02 in the first row and the third column and the pixel value 05 in the first row and the sixth column, the pulse width modulation signal received by the third pixel circuit of each pixel circuit unit is generated according to the weight value w02 of the first row and the third column of the convolution kernel.

[0129] When the convolution area of ​​the first to third rows of pixels in the focal plane is processed, for the pixel circuit units that obtain the pixel value 01 in the first row and second column and the pixel value 04 in the first row and fifth column, the first pixel circuit of each pixel circuit unit receives the pulse width modulation signal sent by the pulse generation unit. The pulse width modulation signal is generated according to the weight value w00 in the first row and first column of the convolution kernel. The remaining pixels receive the pulse width modulation signal sent by the pulse generation unit. Among them, the pixel circuit unit that obtains the pixel point 02 value in the 1st row and 3rd column and the pixel point 05 value in the 1st row and 6th column, wherein the pulse width modulation signal received by the second pixel circuit of each pixel circuit unit is generated according to the weight value w01 of the 1st row and 2nd column of the convolution kernel; the pixel circuit unit that obtains the pixel point 03 value in the 1st row and 4th column and the pixel point 06 value in the 1st row and 7th column, wherein the pulse width modulation signal received by the third pixel circuit of each pixel circuit unit is generated according to the weight value w02 of the 1st row and 3rd column of the convolution kernel.

[0130] When data processing is performed on the convolution area of ​​the first to third rows of pixels on the focal plane, for the pixel circuit unit that obtains the value of pixel 02 in the first row and third column, the first pixel circuit of each pixel circuit unit receives the pulse width modulation signal sent by the pulse generation unit. The pulse width modulation signal is generated according to the weight value w00 of the first row and first column of the convolution kernel. The remaining pixels receive the pulse width modulation signal sent by the pulse generation unit. Among them, the pixel circuit unit that obtains the value of pixel 03 in the first row and fourth column, the pulse width modulation signal received by the second pixel circuit of each pixel circuit unit is generated according to the weight value w01 of the first row and second column of the convolution kernel; among them, the pixel circuit unit that obtains the value of pixel 04 in the first row and fifth column, the pulse width modulation signal received by the third pixel circuit of each pixel circuit unit is generated according to the weight value w02 of the first row and third column of the convolution kernel.

[0131] S204, the controller module controls the accumulation of output results of the pixel point circuits in the focal plane according to the moment when each pixel point circuit in the focal plane receives the pulse width modulation signal;

[0132] Specifically, Figure 4 As described in the above embodiment, in a data processing method provided by the present invention, the first convolution results corresponding to the processing units of the corresponding bits in the same row are added, and the corresponding second convolution results of the adjacent columns of the same convolution area are added. Correspondingly, in the control method of the data processing circuit provided by the embodiment of the present invention, the controller module controls the output results of the pixel point circuit in the focal plane to be accumulated according to the moment when each pixel point in the focal plane receives the pulse width modulation signal.

[0133] Exemplarily, in combination with the above embodiments and Figure 4As shown, when the convolution area of ​​the first row to the third row of the pixel points of the focal plane to be convolved is processed, for the pixel point circuit unit that obtains the pixel point 00 value of the first row and the first column and the pixel point 03 value of the first row and the fourth column, the pulse width modulation signal received by the first pixel point circuit of each pixel point circuit unit is generated according to the weight value w00 of the first row and the first column of the convolution kernel. The remaining pixels receive the pulse width modulation signal sent by the pulse generating unit. Among them, the pixel point circuit unit that obtains the pixel point 01 value of the first row and the second column and the pixel point 04 value of the first row and the fifth column, the second pixel point circuit of each pixel point circuit unit, the pulse width modulation signal received is generated according to the weight value w01 of the first row and the second column of the convolution kernel; among them, the pixel point circuit unit that obtains the pixel point 02 value of the first row and the third column and the pixel point 05 value of the first row and the sixth column, the pulse width modulation signal received by the third pixel point circuit of each pixel point circuit unit is generated according to the weight value w02 of the first row and the third column of the convolution kernel.

[0134] Then, in the row direction, the output results of the first pixel point circuit in the pixel point circuit unit corresponding to the pixel point value 00 in the first row and the first column, the second pixel point circuit in the pixel point circuit unit corresponding to the pixel point value 01 in the first row and the second column, and the third pixel point circuit in the pixel point circuit unit corresponding to the pixel point value 02 in the first row and the third column are added;

[0135] The output results of the pixel point circuit corresponding to the first pixel point circuit in the pixel point circuit unit corresponding to the pixel point 03 value in the 1st row and 4th column, the second pixel point circuit in the pixel point circuit unit corresponding to the pixel point 04 value in the 1st row and 5th column, and the pixel point circuit corresponding to the third pixel point circuit in the pixel point circuit unit corresponding to the pixel point 05 value in the 1st row and 6th column are added.

[0136] In the row direction, for the pixel point circuit unit that obtains the value of pixel point 10 in the second row and the first column and the value of pixel point 13 in the second row and the fourth column, the first pixel point circuit of each pixel point circuit unit receives the pulse width modulation signal sent by the pulse generation unit. The pulse width modulation signal is generated according to the weight value w10 of the second row and the first column of the convolution kernel. The pixel point circuit unit that obtains the value of pixel point 11 in the second row and the second column and the value of pixel point 14 in the second row and the fifth column, the pulse width modulation signal received by the second pixel point circuit of each pixel point circuit unit is generated according to the weight value w11 of the second row and the second column of the convolution kernel; the pixel point circuit unit that obtains the value of pixel point 12 in the second row and the third column and the value of pixel point 15 in the second row and the sixth column, the pulse width modulation signal received by the third pixel point circuit of each pixel point circuit unit is generated according to the weight value w12 of the second row and the third column of the convolution kernel. Then in the row direction, the output results of the pixel circuits corresponding to the first pixel circuit of the pixel circuit unit that obtains the value of pixel 10 in the second row and the first column, the second pixel circuit of the pixel circuit unit that obtains the value of pixel 11 in the second row and the second column, and the third pixel circuit of the pixel circuit unit that obtains the value of pixel 12 in the second row and the third column are added; the output results of the pixel circuits corresponding to the first pixel circuit of the pixel circuit unit that obtains the value of pixel 13 in the second row and the fourth column, the second pixel circuit of the pixel circuit unit that obtains the value of pixel 14 in the second row and the fifth column, and the third pixel circuit of the pixel circuit unit that obtains the value of pixel 15 in the second row and the sixth column are added.

[0137] Similarly, for the pixel point circuit unit that obtains the value of the pixel point 20 in the 3rd row and the 1st column and the value of the pixel point 23 in the 3rd row and the 4th column, the first pixel point circuit of each pixel point circuit unit receives the pulse width modulation signal sent by the pulse generation unit. The pulse width modulation signal is generated according to the weight value w20 of the 3rd row and the 1st column of the convolution kernel. The pixel point circuit unit that obtains the value of the pixel point 21 in the 3rd row and the 2nd column and the value of the pixel point 24 in the 3rd row and the 5th column, the pulse width modulation signal received by the second pixel point circuit of each pixel point circuit unit is generated according to the weight value w21 of the 3rd row and the 2nd column of the convolution kernel; the pixel point circuit unit that obtains the value of the pixel point 22 in the 3rd row and the 3rd column and the value of the pixel point 25 in the 3rd row and the 6th column, the pulse width modulation signal received by the third pixel point circuit of each pixel point circuit unit is generated according to the weight value w22 of the 3rd row and the 3rd column of the convolution kernel. Then in the row direction, the output results of the pixel circuits corresponding to the first pixel circuit of the pixel circuit unit that obtains the value of pixel 20 in the 3rd row and 1st column, the second pixel circuit of the pixel circuit unit that obtains the value of pixel 21 in the 3rd row and 2nd column, and the third pixel circuit of the pixel circuit unit that obtains the value of pixel 22 in the 3rd row and 3rd column are added; the output results of the pixel circuits corresponding to the first pixel circuit of the pixel circuit unit that obtains the value of pixel 23 in the 3rd row and 4th column, the second pixel circuit of the pixel circuit unit that obtains the value of pixel 24 in the 3rd row and 5th column, and the third pixel circuit of the pixel circuit unit that obtains the value of pixel 25 in the 3rd row and 6th column are added.

[0138] Then in the column direction, the result of adding the output results of the first pixel circuit of the pixel circuit unit that obtains the value of pixel point 00 in the 1st row and 1st column, the second pixel circuit of the pixel circuit unit that obtains the value of pixel point 01 in the 1st row and 2nd column, and the third pixel circuit of the pixel circuit unit that obtains the value of pixel point 02 in the 1st row and 3rd column is added to the result of adding the output results of the first pixel circuit of the pixel circuit unit that obtains the value of pixel point 10 in the 2nd row and 1st column, the second pixel circuit of the pixel circuit unit that obtains the value of pixel point 11 in the 2nd row and 2nd column, and the third pixel circuit of the pixel circuit unit that obtains the value of pixel point 12 in the 2nd row and 3rd column, as well as the output results of the first pixel circuit of the pixel circuit unit that obtains the value of pixel point 20 in the 3rd row and 1st column, the second pixel circuit of the pixel circuit unit that obtains the value of pixel point 21 in the 3rd row and 2nd column, and the third pixel circuit of the pixel circuit unit that obtains the value of pixel point 22 in the 3rd row and 3rd column is added. The output results of the circuits corresponding to the other pixels in the convolution area are similar and will not be elaborated here.

[0139] The same applies when data processing is performed on the fourth to sixth rows of pixels in the focal plane or other pixel circuit convolution areas at a certain moment, which will not be elaborated here.

[0140] S205, after the output results of the pixel point circuit are accumulated, the controller module controls the output of the accumulated results.

[0141] After the value output by the corresponding pixel point circuit is obtained through the steps of the above embodiment, the controller module controls the output of the accumulated result.

[0142] In the data processing circuit control method provided by the embodiment of the present invention, according to the weight value of the convolution kernel, the weight register unit generates a corresponding weight signal. These weight signals represent the value of each element in the convolution kernel. The pulse generation unit receives the weight signal from the weight register unit and converts these weight values ​​into a pulse width modulation signal. Each weight value corresponds to a pulse of a specific width, and the width of the pulse directly reflects the size of the weight. These PWM signals are then sent to each pixel point circuit on the focal plane. The controller module is responsible for monitoring the moment when each pixel point circuit receives the PWM signal, and controls the output results of the pixel point circuit to accumulate according to these moments. This process simulates the product and accumulation steps in the convolution operation, but replaces the traditional numerical multiplication by using PWM signals. Finally, the controller module collects and processes the output results from all pixel point circuits to complete the entire data processing circuit control. In this way, by converting the weight value into a PWM signal, the data processing circuit control method can improve the parallel processing capability of the data processing circuit and accelerate the convolution operation process. The calculation speed is improved, the convolution efficiency is greatly improved, and global parallel operation is achieved.

[0143] In combination with the above embodiment, the data processing circuit control method further includes: before the pulse generating unit generates a pulse width modulation signal according to the received weight value and simultaneously sends it to each pixel point circuit of the focal plane, the controller module controls the pixel point circuit to initialize;

[0144] Combination Figure 7 As shown, before the pulse generating unit sends the pulse width modulation signal to each pixel circuit of the focal plane, the pixel circuit needs to be initialized. Specifically, the control end of the N-type field effect transistor NMOS1 of the pixel circuit can be used as the reset end REST to receive the reset signal sent by the control module. When the reset end REST receives a high-level signal, the N-type field effect transistor NMOS1 is turned on, and at this time, the photodiode PD1 and the power supply end VDD charge the first capacitor C1, and the photodiode PD1 is reverse biased.

[0145] After each convolution operation, the weight register unit generates weight values ​​according to the next row of weights of the convolution kernel and sends them to the pulse width generator module.

[0146] Combining the above embodiments and Figure 4 As shown, in a convolution operation, the pixel point circuits in the pixel point circuit units corresponding to the pixel points in rows 1 to 3 are controlled; at the same time, the pixel point circuits in the pixel point circuit units corresponding to the pixel points in rows 4 to 6 are controlled. After this convolution operation is completed, the weight register unit generates a weight value according to the next row weight of the convolution kernel and sends it to the pulse width generator module. That is, another convolution operation is started at this time. At this time, the pixel point circuits corresponding to the pixel point circuits in the pixel point units in rows 2 to 4 are controlled; the pixel point circuits in the pixel point circuit units corresponding to the pixel points in rows 5 to 7 are controlled.

[0147] In combination with the above embodiment, step S202 and step S203 of the data processing circuit control method further include:

[0148] When the convolution step is 1, the focal plane is j columns, the width and height of the convolution kernel are both n, and n ≥ 3;

[0149] In each convolution region, adjacent pixel point circuits with the same pixel point value are copied into a pixel point circuit unit;

[0150] For the pixel point circuit unit in the j1th column and the n1th row, the weight register module generates an input weight value according to the weight of the n1th row and the h1th column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the pixel point circuit unit in the j1th column and the n1th row, wherein j1<n, h1≤j1, n1 is the number of rows where the pixel point circuit unit is located in the convolution area, and n1≤n;

[0151] In each convolution area, for the pixel point circuit unit in the j2th column and the n1th row, the weight register module generates an input weight value according to the weight in the n1th row and the h2th column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the pixel point circuit unit in the j2th column and the n1th row, wherein j-n+1<j2≤j, nj-j2≤h2≤n;

[0152] In each convolution area, for the pixel point in the j3th column and the n1th row, the weighted register module generates an input weight value according to the weight of the n1th row and the h3th column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the pixel point circuit unit in the j3th column and the n1th row, wherein n≤j3≤j-n+1, ​​h3≤n.

[0153] Specifically, Figure 5 Taking the first convolution region 211 from the 1st row to the 3rd row in as an example,

[0154] Weight multiplication is performed on the first pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 1st and 4th columns, the weighted register module generates an input weight value according to the weight of the 1st row, the 2nd row and the 3rd row and the 1st column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the first pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 1st and 4th columns.

[0155] At the same time, weight multiplication is performed on the second pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 2nd and 5th columns, the weighted register module generates an input weight value according to the weights of the 1st row, the 2nd row and the 3rd row and the 2nd column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the second pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 2nd and 5th columns.

[0156] At the same time, weight multiplication is performed on the third pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd and 6th columns of the 3rd row, the weighted register module generates an input weight value according to the weights of the 1st row, the 2nd row and the 3rd column of the 3rd row in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the third pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd and 6th columns of the 3rd row.

[0157] At the same time, weight multiplication is performed on the first pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 2nd and 5th columns, the weighted register module generates an input weight value according to the weight of the 1st row, the 2nd row and the 3rd row and the 1st column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the first pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 2nd and 5th columns.

[0158] At the same time, weight multiplication is performed on the second pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd and 6th columns of the 3rd row, the weighted register module generates an input weight value according to the weight of the 1st row, the 2nd row and the 3rd column of the 3rd row in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the second pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd and 6th columns of the 3rd row.

[0159] At the same time, weight multiplication is performed on the third pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row, and the 3rd row and the 4th and 7th columns, the weighted register module generates an input weight value according to the weights of the 1st row, the 2nd row, and the 3rd row and the 3rd column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the third pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row, and the 3rd row and the 4th and 7th columns.

[0160] At the same time, weight multiplication is performed on the first pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 3rd column, the weighted register module generates an input weight value according to the weights of the 1st row, the 2nd row and the 3rd row and the 1st column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the first pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 3rd column.

[0161] At the same time, weight multiplication is performed on the second pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 4th column, the weighted register module generates an input weight value according to the weights of the 1st row, the 2nd row and the 3rd row and the 2nd column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the second pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 4th column.

[0162] At the same time, weight multiplication is performed on the third pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 5th column, the weighted register module generates an input weight value according to the weights of the 1st row, the 2nd row and the 3rd row and the 3rd column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the third pixel point circuit in the circuit unit that obtains the pixel point values ​​of the 1st row, the 2nd row and the 3rd row and the 5th column.

[0163] The weight value assignment operation of the pixel point circuits in the pixel circuit units for obtaining the pixel point values ​​to be convolved in the remaining rows is similar to the above.

[0164] In summary, for each convolution area, when the convolution kernel size is n and the convolution step is 1, the weight value assignment operation can be performed on the entire convolution area at one moment.

[0165] In combination with the above embodiment, the output ends of the pixel point circuits in each row are connected, and a first switch is connected in series between two pixel point circuits. Step S204 of the data processing circuit control method further includes:

[0166] Close the first switch between the first pixel circuit of the pixel circuit unit of the j4th column in each row of the focal plane and the n2th pixel circuit of the pixel circuit unit of the n-1th column adjacent to the right.

[0167] Specifically, in combination with the above embodiments and Figure 4 , 5 As shown. Figure 5 Take the first convolution area 211 of the 1st to 3rd rows in as an example. Among all the pixels in the 1st row of the focal plane to be convolved, the first switch between the first pixel point circuit in the pixel point circuit unit that obtains the pixel point 00 value in the 1st row and the 1st column and the n2th pixel point circuit in the pixel point circuit unit in the n-1th j5th column on the right is closed, that is, the first switch between the second pixel point circuit in the pixel point circuit unit that obtains the pixel point 01 value in the 1st row and the 2nd column and the third pixel point circuit in the pixel point circuit unit in the 1st row and the 3rd column is closed to obtain the second convolution result. The first switch closure of the pixel point circuits in the remaining rows and columns or the remaining convolution areas is the same as in the above embodiment and will not be repeated here.

[0168] In combination with the above embodiment, the output ends of the pixel point circuits in each column are connected, and a second switch is connected in series between two pixel points. Step S204 of the data processing circuit control method further includes:

[0169] In the column direction of each convolution region, in the first pixel point circuit group composed of n adjacent pixel point circuits with the first switch turned on, when the number of columns of the pixel point circuit units included in each adjacent first pixel point circuit group is the same, the second switches between the adjacent first pixel point circuit groups are controlled to be turned on. Specifically, in combination with the above embodiment, still with Figure 5Taking the first convolution area 211 as an example, the above discusses the closing status of the first switch. In the column direction of each convolution area, the first pixel circuit group includes: the first pixel circuit in the pixel circuit unit that obtains the value of pixel 00 in the 1st row and 1st column, the second pixel circuit in the pixel circuit unit that obtains the value of pixel 01 in the 1st row and 2nd column, and the third pixel circuit in the pixel circuit unit that obtains the value of pixel 02 in the 1st row and 3rd column; the first pixel circuit in the pixel circuit unit that obtains the value of pixel 10 in the 2nd row and 1st column, the second pixel circuit in the pixel circuit unit that obtains the value of pixel 11 in the 2nd row and 2nd column, and the third pixel circuit in the pixel circuit unit that obtains the value of pixel 12 in the 2nd row and 3rd column; the first pixel circuit in the pixel circuit unit that obtains the value of pixel 20 in the 3rd row and 1st column, the second pixel circuit in the pixel circuit unit that obtains the value of pixel 21 in the 3rd row and 2nd column, and the third pixel circuit in the pixel circuit unit that obtains the value of pixel 22 in the 3rd row and 3rd column. It can be known that the number of bits of the pixel circuits in the pixel circuit units in the pixel circuit group are all bit 1, bit 2 and bit 3. Therefore, the second switches between the three first pixel circuit groups are turned on.

[0170] The closing conditions of the second switches at other times, in other convolution areas or in other first pixel circuit groups are the same as those in the above embodiment and will not be elaborated here.

[0171] Fig.10 A schematic diagram of the structure of a data processing system provided by an embodiment of the present invention is shown in FIG. Fig.10 As shown, the data processing system includes: a data processing circuit 301 and an analog-to-digital conversion module 302 provided by any embodiment of the present invention;

[0172] The analog-to-digital conversion module 301 is connected to the data processing circuit 302 , and the analog-to-digital conversion module 302 is used to perform analog-to-digital conversion on the signal output by the data processing circuit 301 .

[0173] A data processing system provided in an embodiment of the present invention can achieve the same technical effect as the data processing circuit provided in the above-mentioned embodiment of the invention, and will not be described in detail here.

[0174] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data processing method, characterized in that: The method comprises: For each pixel on the focal plane, copy processing units; wherein the width and height of the convolution kernel are both n, and n≥1; the convolution step length is s; wherein s≥1; In one convolution operation, each of the processing units in the pixel point is multiplied by the weight of the corresponding convolution kernel to obtain a first convolution result; the first convolution results of the processing units corresponding to the same convolution kernel are accumulated on the same row to obtain a second convolution result; The second convolution results between rows are accumulated and the final convolution result is output.

2. The data processing method according to claim 1, characterized in that: Also includes: After one convolution calculation, the convolution area is moved down by one step to perform the next convolution operation until the final convolution result on the entire focal plane is obtained; wherein, the height of the convolution area is equal to the height of the convolution kernel, the width of the convolution area is equal to the width of the focal plane, and along the height direction of the focal plane, the boundaries of adjacent convolution areas are adjacent.

3. The data processing method according to claim 2, characterized in that: The focal plane is j columns, and when s=1, in one convolution operation, each processing unit in the pixel point is multiplied by the weight of the corresponding convolution kernel to obtain a first convolution result, including: In each convolution region, for the pixel in the j1th column and the n1th row, multiply the h1th bit processing unit of the pixel by the weight of the n1th row and the h1th column in the convolution kernel, where j1<n, h1≤j1, n1 is the number of rows where the pixel is located in the convolution region, and n1≤n; In each convolution area, for the pixel in the j2th column and the n1th row, multiply the weights in the n1th row and the h2th column of the convolution kernel in the h2th bit processing unit of the pixel, where j-n+1<j2≤j, nj-j2≤h2≤n; In each convolution area, for a pixel in the j3th column and the n1th row, multiply the h3th bit processing unit of the pixel by the n1th row and the h3th column weight in the convolution kernel to obtain the first convolution result; wherein n≤j3≤j-n+1, ​​h3≤n; Accumulating the first convolution results of the processing units corresponding to the same convolution kernel on the same row to obtain a second convolution result includes: The first convolution result corresponding to the first bit processing unit of the j4th column pixel point in each row of the focal plane is added to the first convolution result corresponding to the n2th bit processing unit of the n-1th j5th column pixel points adjacent to the right, to obtain the second convolution result, where j4<j5≤n+j4-1; n2=j5-j4+1; The step of accumulating the second convolution results between rows and outputting the final convolution result includes: In the column direction of each convolution area, when the number of columns of n pixels corresponding to each first convolution result in the n second convolution results is the same, the n second convolution results are added together to output the final convolution result.

4. A data processing circuit, characterized in that: The data processing circuit comprises: a focal plane module and a pulse width generator module; The focal plane module and the pulse width generator module are connected; The pulse width generator module is used to output a pulse width modulation signal representing the weights of different convolution kernels to the focal plane; The focal plane module includes a plurality of pixel point circuits; The plurality of pixel point circuits of the focal plane module are used to multiply n identical input values ​​with corresponding pulse width modulation signals to obtain a first convolution result; Accumulating the first convolution results in the pixel point circuits corresponding to the same convolution kernel on the same row to obtain a second convolution result; The second convolution results between rows are accumulated and the final convolution result is output.

5. The data processing circuit according to claim 4, characterized in that: Each pixel point circuit includes a control terminal, and the output terminal of the pulse width generator module includes a plurality of sub-output terminals, and the sub-output terminals are connected to the control terminals of the pixel point circuits of the focal plane in a one-to-one correspondence.

6. The data processing circuit according to claim 5, characterized in that: The pixel point circuit includes: a P-type field effect transistor, an N-type field effect transistor, a photodiode and a first capacitor; wherein the first end of the P-type field effect transistor, the first end of the N-type field effect transistor and the negative terminal of the photodiode are connected; The second end of the N-type field effect transistor is connected to the first power supply, the second end of the P-type field effect transistor is connected to the first end of the first capacitor and the pixel output end, and the positive end of the photodiode is grounded; The second terminal of the first capacitor is grounded; The focal plane module also includes: The output ends of the pixel point circuits in each row are connected, and a first switch is connected in series between the output ends of two pixel point circuits in the same row; The output ends of the pixel point circuits in each column are connected, and a second switch is connected in series between the output ends of two pixel point circuits in the same column.

7. A data processing circuit control method, applied to the data processing circuit of any one of claims 4 to 6, characterized in that: include: The data processing circuit includes a controller module; the pulse width generator module includes a weighted register unit and a pulse generating unit; The controller module controls the adjacent The pixel point circuits obtain the value of the same pixel point; wherein n is the size of the convolution kernel, and s is the step size of the convolution; In a convolution operation, the controller module controls the weight register unit to generate a weight value according to the convolution kernel and sends it to the pulse generation unit; the controller module controls the pulse generation unit to generate a pulse width modulation signal according to the received weight value and simultaneously sends it to each pixel point circuit of the focal plane; The controller module controls the accumulation of output results of the pixel point circuits in the focal plane according to the moment when each pixel point circuit in the focal plane receives the pulse width modulation signal; After the output results of the pixel point circuit are accumulated, the controller module controls the output of the accumulated results.

8. The data processing circuit control method according to claim 7, characterized in that: The method further comprises: Before the pulse generating unit generates a pulse width modulation signal according to the received weight value and sends it to each pixel point circuit of the focal plane at the same time, the controller module controls the pixel point circuit unit to initialize; After each convolution operation, the control module controls the weight register unit to generate a weight value according to the previous row of weights of the convolution kernel and sends it to the pulse width generator module.

9. The data processing circuit control method according to claim 7, characterized in that: The controller module controls the weight register unit to generate a weight value according to the convolution kernel and sends it to the pulse generation unit; The controller module controls the pulse generating unit to generate a pulse width modulation signal according to the received weight value and simultaneously sends the pulse width modulation signal to each pixel point circuit of the focal plane, including: When the convolution step length s=1, the focal plane is j columns, the width and height of the convolution kernel are both n, and n≥1; In each convolution region, adjacent pixel point circuits with the same pixel point value are copied into a pixel point circuit unit; For the pixel point circuit unit in the j1th column and the n1th row, the weight register module generates an input weight value according to the weight of the n1th row and the h1th column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the pixel point circuit unit in the j1th column and the n1th row, wherein j1<n, h1≤j1, n1 is the number of rows where the pixel point circuit unit is located in the convolution area, and n1≤n; In each convolution area, for the pixel point circuit unit in the j2th column and the n1th row, the weight register module generates an input weight value according to the weight in the n1th row and the h2th column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the pixel point circuit unit in the j2th column and the n1th row, wherein j-n+1<j2≤j, nj-j2≤h2≤n; In each convolution area, for the pixel point in the j3th column and the n1th row, the weight register module generates an input weight value according to the weight in the n1th row and the h3th column in the convolution kernel, and the pulse width generation module generates a pulse width modulation signal according to the received input weight value and sends it to the pixel point circuit unit in the j3th column and the n1th row, wherein n≤j3≤j-n+1, ​​h3≤n; The output ends of the pixel point circuits of each row are connected, and a first switch is connected in series between two pixel point circuits. The controller module controls the accumulation of the output results of the pixel point circuits in the focal plane according to the moment when each pixel point circuit in the focal plane receives a pulse width modulation signal, including: Close the first switch between the first pixel point circuit of the pixel point circuit unit of the j4th column in each row of the focal plane and the n2th pixel point circuit of the pixel point circuit unit of the n-1th column of the j5th column adjacent to the right, where j4<j5≤n+j4-1; n2=j5-j4+1; The output ends of the pixel point circuits in each column are connected, and a second switch is connected in series between two pixel points. The controller module controls the accumulation of the output results of the pixel point circuits in the focal plane according to the moment when each pixel point circuit in the focal plane receives the pulse width modulation signal, and also includes: In the column direction of each convolution area, in the first pixel point circuit group composed of n adjacent pixel point circuits that have turned on the first switch, when the number of columns of the pixel point circuit units included in each adjacent first pixel point circuit group is the same, the second switch between the adjacent first pixel point circuit groups is controlled to be turned on.

10. A data processing system, characterized in that: include: The data processing circuit and analog-to-digital conversion module according to any one of claims 4 to 6; The analog-to-digital conversion module is connected to the data processing circuit, and is used to perform analog-to-digital conversion on the signal output by the data processing circuit.

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