Display device

Abstract

Provided is a display device in which operating characteristics of internal compensation pixels are applied to degradation compensation modeling to achieve accurate degradation compensation. The display device may include: a display panel including internal compensation pixels; a data driver configured to apply a data voltage to the display panel; and a controller configured to compensate the image data based on the degradation compensation modeling. The deterioration compensation modeling includes deterioration compensation modeling representing an operating characteristic of the internal compensation pixel during the light emission period, and deterioration compensation modeling representing an operating characteristic of the internal compensation pixel during the sensing period. The compensated image data is provided to a data driver.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device in which operation characteristics of internal compensation pixels are applied to degradation compensation modeling to achieve accurate degradation compensation. Background Art

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting display devices (OLEDs) that emit light by themselves and liquid crystal display devices (LCDs) that require a separate light source.

[0003] The application range of display devices is becoming more and more diverse, ranging from computer monitors and TVs to personal portable devices. Research is being conducted on display devices having a large display area but reduced in size and weight.

[0004] The display device may include a data driving circuit that provides data signals to data lines of the display panel and a gate driving circuit that provides gate signals to gate lines of the display panel. Summary of the invention

[0005] An object of the present disclosure is to provide a display device in which the operating characteristics of an internal compensation pixel are applied to degradation compensation modeling to achieve accurate degradation compensation.

[0006] In addition, an object of the present disclosure is to provide a display device, wherein the operating characteristics of an internally compensated pixel include a first operating characteristic corresponding to a light emitting period for emission of a light emitting element and a second operating characteristic corresponding to a sensing period for sensing a threshold voltage of a driving transistor, and the first operating characteristic and the second operating characteristic are respectively applied to degradation compensation modeling, thereby achieving accurate degradation compensation.

[0007] The purpose according to the present disclosure is not limited to the above-mentioned purpose. Other purposes and advantages according to the present disclosure that are not mentioned can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the purpose and advantages according to the present disclosure can be achieved using the devices shown in the claims or their combinations.

[0008] In order to achieve the above-mentioned purpose, a display device according to one aspect of the present disclosure includes: a display panel, the display panel including a plurality of internal compensation pixels; and a data driver, the data driver being configured to apply a data voltage to the display panel; and a controller, the controller being configured to compensate image data based on degradation compensation modeling, wherein the degradation compensation modeling includes degradation compensation modeling representing operating characteristics of the internal compensation pixels during a light emitting period, and degradation compensation modeling representing operating characteristics of the internal compensation pixels during a sensing period; and providing the compensated image data to the data driver.

[0009] In order to achieve the above-mentioned purpose, a display device according to another aspect of the present disclosure includes a display panel, wherein the display panel includes a plurality of internal compensation pixels, wherein each of the internal compensation pixels is configured to sense a threshold voltage of a driving transistor during a sensing period and to emit light at a data voltage during a light emitting period, wherein the display device is configured to: apply operating characteristics of the internal compensation pixels during the light emitting period to a first compensation modeling; apply operating characteristics of the internal compensation pixels during the sensing period to a second compensation modeling; and compensate image data based on the first compensation modeling and the second compensation modeling.

[0010] According to an embodiment of the present disclosure, the operating characteristics of the internal compensation pixel may be applied to degradation compensation modeling to achieve accurate degradation compensation.

[0011] In addition, according to an embodiment of the present disclosure, the operating characteristics of the internal compensation pixel include a first operating characteristic corresponding to a light emitting period for emission of the light emitting element and a second operating characteristic corresponding to a sensing period for sensing the threshold voltage of the driving transistor, and the first operating characteristic and the second operating characteristic can be respectively applied to degradation compensation modeling, thereby achieving accurate degradation compensation.

[0012] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

[0013] In addition to the above-described effects, specific effects of the present disclosure are described while describing specific details for implementing the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings, which are given by way of illustration only and thus do not limit the present disclosure.

[0015] Figure 1 is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0016] Figure 2 is a cross-sectional view illustrating a stacked structure of a display device according to an embodiment of the present disclosure.

[0017] Figure 3 is a view of a configuration of a gate driver in a display device according to an embodiment of the present disclosure.

[0018] Figure 4 is a view showing a pixel circuit of a display device according to an embodiment of the present disclosure.

[0019] Figure 5 is a timing chart showing the operation of the pixel circuit of the display device according to the embodiment of the present disclosure.

[0020] Figure 6 It is shown as Figure 4 A view of the operating characteristics of an internal compensation pixel of a pixel circuit during a light emission period is shown.

[0021] Figure 7 It is shown as Figure 4 A view of the operating characteristics of an internally compensated pixel of a pixel circuit during a sensing period is shown. DETAILED DESCRIPTION

[0022] The advantages and features of the present disclosure and the methods for achieving these advantages and features will become apparent with reference to the embodiments described in detail later in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. Therefore, these embodiments are set forth only to complete the present disclosure and fully inform the ordinary technicians of the technical field to which the present disclosure belongs, and the present disclosure is limited only by the scope of the claims.

[0023] For simplicity and clarity of explanation, the elements in the drawings are not necessarily drawn to scale. The same reference numerals in different drawings represent the same or similar elements, and therefore perform similar functions. In addition, in order to simplify the description, the description and details of well-known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, processes, components and circuits are not described in detail, so as not to make the various aspects of the present disclosure unnecessarily difficult to understand. Examples of various embodiments are further shown and described below. It should be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover substitutions, modifications and equivalent transformations that may be included in the spirit and scope of the present disclosure defined by the appended claims.

[0024] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of the present disclosure are illustrative, and the embodiments of the present disclosure are not limited thereto.

[0025] The terms used herein are intended only to describe the purpose of a particular embodiment and are not intended to limit the present disclosure. As used herein, the singular formations "a" and "an" are intended to also include plural formations, unless the context clearly states otherwise. It will be further understood that when used in this specification, the terms "comprise", "comprising", "include" and "including" specify the presence of the features, integers, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, operations, elements, parts and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of ... " can modify the entire element list when after the element list, and may not modify the individual elements of the list. In the interpretation of numerical values, even without its explicit description, errors or tolerances therein may also occur.

[0026] In addition, it should be understood that when a first element or layer is referred to as being present "on," "above," "over," etc., a second element or layer, the first element may be directly disposed on the second element, or may be indirectly disposed on the second element, wherein a third element or layer is disposed between the first element or layer and the second element or layer. It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly on, connected to, or coupled to another element or layer, or one or more intermediate elements or layers may be present. In addition, it should be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0027] In addition, as used herein, when a layer, film, region, plate, etc. is disposed "on" or "on top" of another layer, film, region, plate, etc., the former may directly contact the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed "on" or "on top" of another layer, film, region, plate, etc., the former may directly contact the latter, and another layer, film, region, plate, etc. may not be disposed between the former and the latter. In addition, as used herein, when a layer, film, region, plate, etc. is disposed "below" or "below" of another layer, film, region, plate, etc., the former may directly contact the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed "below" or "below" of another layer, film, region, plate, etc., the former may directly contact the latter, and another layer, film, region, plate, etc. may not be disposed between the former and the latter.

[0028] In the description of a temporal relationship, for example, a temporal precedent relationship between two events, such as “after,” “after,” “before,” etc., unless it indicates “immediately after,” “immediately after,” or “immediately before,” another event may occur between them.

[0029] When specific embodiments can be implemented differently, the functions or operations specified in a specific block may occur in an order different from the order specified in the flow chart. For example, two consecutive blocks may actually be executed substantially simultaneously, or the two blocks may be executed in reverse order according to the functions or operations involved.

[0030] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or time periods, these elements, components, regions, layers and / or time periods should not be limited by these terms and cannot define an order or sequence. These terms are used to distinguish one element, component, region, layer or time period from another element, component, region, layer or time period. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or time period described below may be referred to as a second element, component, region, layer or time period.

[0031] The features of various embodiments of the present disclosure may be partially or completely combined with each other, and may be technically associated with each other or operate with each other. The embodiments may be implemented independently of each other, and may be implemented together in an associated relationship.

[0032] When interpreting numerical values, the values ​​are interpreted as including the error range unless explicitly stated otherwise.

[0033] It should be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly on, connected to or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it should be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0034] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as those commonly understood by those skilled in the art to which the present disclosure is conceived. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such in this article.

[0035] As used herein, "embodiment," "example," "aspect," etc. should not be construed as making any aspect or design described better or advantageous over other aspects or designs.

[0036] Additionally, the term "or" is intended to mean an inclusive or rather than an exclusive or. That is, unless specified otherwise or clear from the context, the expression "x employs a or b" means any of the natural inclusive permutations.

[0037] The terms used in the following description have been selected to be common in the relevant technical field. However, other terms besides these terms may exist according to the development and / or change of technology, convention, preference of technicians, etc. Therefore, the terms used in the following description should not be understood as limiting the technical concept, but should be understood as examples of terms used to illustrate the embodiments.

[0038] In addition, in certain cases, the terms may be arbitrarily selected by the applicant, and in this case, their detailed meanings will be described in the corresponding description period. Therefore, the terms used in the following description should be understood not only based on the names of the terms, but also based on the meanings of the terms and the contents in the entire detailed description section.

[0039] In the description of a signal flow, for example, when a signal is transmitted from node A to node B, this may include a case where the signal is transmitted from node A to node B via another node unless the phrase “immediately transmitted” or “directly transmitted” is used.

[0040] Furthermore, the term “may” includes all meanings and coverages of the term “can.” The term “disclosure” may be used interchangeably with the term “invention” or include all meanings and coverages of the term “invention.”

[0041] All components of each display device or apparatus according to all embodiments of the present disclosure are operably coupled and configured.

[0042] Hereinafter, a display device according to some embodiments will be described in which operation characteristics of an internal compensation pixel are applied to degradation compensation modeling to achieve accurate degradation compensation.

[0043] Figure 1 is a block diagram schematically illustrating a display device according to an embodiment of the present disclosure.

[0044] refer to Figure 1 The display device 10 includes a display panel 100 including a plurality of pixels P, a controller 200 and a gate driver 300, a data driver 400, and a power supply 500, wherein the gate driver 300 provides a gate signal to each of the plurality of pixels P, the data driver 400 provides a data signal to each of the plurality of pixels P, and the power supply 500 provides each of the plurality of pixels P with power required for operation.

[0045] In the display panel 100, a plurality of gate lines GL and a plurality of data lines DL intersect each other, and each of a plurality of pixels P is connected to the gate line GL and the data line DL. Specifically, one pixel P receives a gate signal from a gate driver 300 via the gate line GL, receives a data signal from a data driver 400 via the data line DL, and receives a high potential driving voltage EVDD and a low potential driving voltage EVSS from a power source 500 via a power line.

[0046] The gate line GL provides a scan signal SC and a light emission control signal EM to the pixel, and the data line DL provides a data voltage Vdata to the pixel. In addition, according to various embodiments, the gate line GL may include a plurality of scan lines SCL providing the scan signal SC and a light emission control signal line EML providing the light emission control signal EM. In addition, the plurality of pixels P may further include at least one power line VL, and may receive an initialization voltage Vini, an anode reset voltage Var, and a reference voltage Vref via the at least one power line VL.

[0047] In addition, each pixel P includes a light-emitting element and a pixel circuit for controlling the operation of the light-emitting element. The pixel circuit includes a plurality of switching elements, a driving element and a capacitor. In this regard, each of the switching element and the driving element can be implemented as a thin film transistor. In the pixel circuit, the driving element controls the amount of current supplied to the light-emitting element based on the data voltage to adjust the amount of light emitted from the light-emitting element. In addition, the plurality of switching elements receive a scanning signal SC provided via a plurality of scanning lines SCL and a light-emitting control signal EM provided via a light-emitting control signal line EML, and operate the pixel circuit based on the scanning signal SC and the light-emitting control signal EM.

[0048] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device, where an image is displayed on a screen and a real object in the background is visible to a viewer in front of the display device. The display panel 100 may be manufactured as a flexible display panel. The flexible display panel may be implemented as an OLED panel using a plastic substrate.

[0049] The pixels P may include red pixels, green pixels, and blue pixels to emit light of corresponding colors. The pixels P may also include white pixels. Each pixel P includes a pixel circuit.

[0050] The touch sensor may be provided on the display panel 100. The touch input may be sensed using a separate touch sensor, or may be sensed by the pixel P. The touch sensor may be provided on the screen of the display panel in an on-cell type or an add-on type, or may be implemented as an in-cell type touch sensor built into the display panel 100.

[0051] The controller 200 processes the image data RGB input from an external source such as a host system so as to be adapted to the size and resolution of the display panel 100, and provides the processed image data to the data driver 400. The controller 200 generates a gate control signal GCS and a data control signal DCS based on synchronization signals (e.g., a clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync) input from an external source, and provides the generated gate control signal GCS and data control signal DCS to the gate driver 300 and the data driver 400, respectively, thereby controlling the gate driver 300 and the data driver 400.

[0052] The controller 200 may include a degradation compensation model to compensate for degradation of the display panel. The degradation compensation model may be stored in an internal memory or an external memory of the controller 200.

[0053] The controller 200 may compensate the image data RGB based on the degradation compensation modeling and may provide the compensated image data to the data driver 400. The data voltage applied to the pixel during light emission, the temperature, and the initial threshold voltage distribution of the driving transistor may be applied to the degradation compensation modeling.

[0054] Specifically, the controller 200 may calculate compensation data for degradation compensation of pixels based on the following Equation 1 of degradation compensation modeling.

[0055] Equation 1

[0056] ΔV th=(t / τ) β

[0057] Where t represents the operating time of the display panel, τ represents the characteristic time scale of degradation, β represents the stretch index, A represents the process and component distribution coefficient, V gs represents the gate-source voltage of the driving transistor based on the data voltage, n represents the acceleration factor, E a denotes activation energy, R denotes the ideal gas constant, and T denotes the absolute temperature.

[0058] The controller 200 can compensate for the V gs The degradation of the driving transistor occurs due to the size of (eg, the data voltage applied to the pixel to emit light). The above equation 1 can be applied to the degradation compensation modeling of the external compensation display device, where the degradation occurs in the light emission period.

[0059] In addition, in an embodiment of the present disclosure, in order to compensate for the degradation of the internal compensation display device, the operating characteristics of the internal compensation pixel may include a first operating characteristic corresponding to the light emitting period and a second operating characteristic corresponding to the sensing period. In other words, the operating characteristics of the internal compensation pixel may include a first operating characteristic during the light emitting period for the light emitting element to emit light and a second operating characteristic during the sensing period for sensing the threshold voltage of the driving transistor of the pixel in the pixel.

[0060] In an internal compensation pixel, a high level of peak current is applied to its driving transistor during a sensing period according to operating characteristics. Therefore, the driving transistor may degrade during the sensing period.

[0061] According to an embodiment of the present disclosure, a first operating characteristic during a light emitting period for light emitting elements and a second operating characteristic during a sensing period for sensing a threshold voltage of a driving transistor may be applied to degradation compensation modeling to achieve accurate degradation compensation of an internal compensation display panel.

[0062] The degradation compensation modeling may include first compensation modeling representing degradation characteristics of a driving transistor of the internal compensation pixel during a light emitting period, and second compensation modeling representing degradation characteristics of the driving transistor of the internal compensation pixel during a sensing period.

[0063] The first compensation modeling may be used to calculate compensation data based on the following Equation 2 to compensate for degradation characteristics during the light emission period.

[0064] Equation 2

[0065] ΔV th_d =(t / τ_d) β_d ,

[0066]

[0067] Where t represents the operation time of the display panel, τ_d represents the characteristic time scale of degradation during the light-emitting period, β_d represents the stretching index during the light-emitting period, A_d represents the process and component distribution coefficient during the light-emitting period, V gs denotes a gate-source voltage of the driving transistor based on the data voltage, n denotes an acceleration coefficient, Ea_d denotes activation energy during a light emitting period, R denotes an ideal gas constant, and T denotes an absolute temperature.

[0068] The second compensation modeling may be used to calculate compensation data based on the following Equation 3 to compensate for degradation characteristics during the sensing period.

[0069] Equation 3

[0070] ΔV th_s =(t / τ_s) β_s ,

[0071]

[0072] Wherein t represents the operating time of the display panel, τ_s represents the characteristic time scale of degradation during the sensing period, β_s represents the stretching index during the sensing period, A_s represents the process and component distribution coefficient during the sensing period, Ea_s represents the activation energy during the sensing period, R represents the ideal gas constant, and T represents the absolute temperature.

[0073] Since the sensing operation of the internal compensation circuit is performed under global conditions, it can be based only on the temperature and initial threshold voltage of the drive transistor without V gs The acceleration factor is used to create a second compensation modeling that is different from the first compensation modeling during the light emitting period.

[0074] Different β, A and Ea factors can be based on different degradation characteristics of the light emitting period and the sensing period, and thus can be applied to the first compensation modeling and the second compensation modeling, respectively. That is, the β, A and Ea factors during the light emitting period can be set to have different values ​​from the β, A and Ea factors during the sensing period.

[0075] As described above, the controller 200 may generate compensation data based on a first compensation modeling representing operating characteristics of an internal compensation pixel during a light emission period and a second compensation modeling representing operating characteristics during a sensing period thereof, and may use the generated compensation data to compensate image data.

[0076] The controller 200 may be configured to be coupled to various processors, such as a microprocessor, a mobile processor, an application processor, etc., depending on the type of device in which the controller is installed.

[0077] The host system may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system.

[0078] The controller 200 generates a gate control signal GCS for controlling the operation timing of the gate driver 300 and a data control signal DCS for controlling the operation timing of the data driver 400 based on the timing signals Vsync, Hsync, and DE received from the host system. The controller 200 controls the operation timings of the gate driver 300 and the data driver 400 so that the gate driver 300 and the data driver 400 are synchronized with each other.

[0079] The level shifter converts the voltage level of the gate control signal GCS output from the controller 200 into gate-on voltages VGL and VEL and gate-off voltages VGH and VEH, and then provides the gate-on voltages VGL and VEL and gate-off voltages VGH and VEH to the gate driver 300. The level shifter converts the low-level voltage of the gate control signal GCS into the gate low voltage VGL, and converts the high-level voltage of the gate control signal GCS into the gate high voltage VGH. The gate control signal GCS includes a start pulse and a shift clock.

[0080] The gate driver 300 supplies the scan signal SC to the gate line GL according to the gate control signal GCS supplied from the controller 200. The gate driver 300 may be disposed on one side or each of two opposite sides of the display panel 100 in a GIP (gate in panel) manner.

[0081] The gate driver 300 sequentially outputs gate signals to the plurality of gate lines GL under the control of the controller 200. The gate driver 300 may shift the gate signals using a shift register and sequentially provide the shifted gate signals to the gate lines GL.

[0082] In an organic light-emitting display device, a gate signal may include a scan signal SC and a light-emitting control signal EM. The scan signal SC includes a scan pulse swinging between a gate-on voltage VGL and a gate-off voltage VGH. The light-emitting control signal may include a light-emitting control signal pulse swinging between a gate-on voltage VEL and a gate-off voltage VEH.

[0083] The scan pulse is synchronized with the data voltage Vdata to select a row of pixels to which data is to be written. The light emission control signal EM selects a row of pixels from which a driving current is to be sensed.

[0084] The gate driver 300 may include a light emitting control signal driver 310 and at least one scan driver 320. The light emitting control signal driver 310 outputs a light emitting control signal pulse in response to a start pulse and a shift clock received from the controller 200, and sequentially shifts the light emitting control signal pulse according to the shift clock. Each of the at least one scan driver 320 outputs a scan pulse in response to a start pulse and a shift clock received from the controller 200, and shifts the scan pulse according to the shift clock timing.

[0085] The data driver 400 converts the image data RGB into the data voltage Vdata according to the data control signal DCS provided from the controller 200 and provides the converted data voltage Vdata to the pixel P through the data line DL.

[0086] exist Figure 1 In the embodiment, one data driver 400 is disposed on one side of the display panel 100. However, the number and position of the data driver 200 are not limited thereto. That is, the data driver 400 may be implemented as a plurality of integrated circuits (ICs), which may be disposed on one side of the display panel 100 and may be arranged separately along one side.

[0087] The power supply 500 uses a DC-DC converter to generate direct current (DC) power required for operating the pixel array and the display panel driver of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 500 receives a DC input voltage applied from a host system and generates DC voltages such as gate-on voltages VGL and VEL, gate-off voltages VGH and VEH, a high potential drive voltage EVDD, a low potential drive voltage EVSS, etc. The gate-on voltages VGL and VEL and the gate-off voltages VGH and VEH are provided to the level shifter and the gate driver 300. Each of the high potential drive voltage EVDD and the low potential drive voltage EVSS is commonly provided to the pixel.

[0088] In addition, the power supply 500 may generate a DC voltage such as an initialization voltage Vini, an anode reset voltage Var, and a reference voltage Vref. The initialization voltage Vini, the reference voltage Vref, and the anode reset voltage Var are provided to the pixel P via at least one power line VL. In this regard, at least one power line VL may include a reference voltage bus VrefL, an anode reset voltage bus VarL, and an initialization voltage bus ViniL. In one example, the reference voltage bus VrefL, the anode reset voltage bus VarL, and the initialization voltage bus ViniL may be provided between the gate driver 300 and the display area AA. However, embodiments of the present disclosure are not limited thereto.

[0089] Figure 2is a cross-sectional view illustrating a stacked structure of a display device according to an embodiment of the present disclosure.

[0090] refer to Figure 2 , the display panel 100 includes a display area AA (or active area) where the pixels P are located and a non-display area NA (or non-active area) surrounding the display area AA. The gate driver 300 and the data driver 400 are disposed in the non-display area NA. The non-display area NA may completely or partially surround the display area AA.

[0091] The display panel 100 according to the embodiment of the present disclosure includes a substrate 101 , thin film transistors TFT1 and TFT2 , a bank layer 165 , a light emitting element EL, an encapsulation layer 180 , a touch layer 190 , a touch protection film 197 , a dam DAM, and a pad 198 .

[0092] The thin film transistor TFT1 may be disposed on the substrate 101. The thin film transistor TFT1 drives the light emitting element EL of the display area AA.

[0093] The substrate 101 supports various components of the display panel 100. The substrate 101 may be made of a transparent insulating material, such as glass or plastic. When the substrate 101 is made of plastic, the substrate may be referred to as a plastic film or a plastic substrate. For example, the substrate 101 may be in the form of a film including one of a polyimide-based polymer, a polyester-based polymer, a silicone-based polymer, an propylene-based polymer, a polyolefin-based polymer, and a copolymer thereof. However, the embodiments of the present disclosure are not limited thereto.

[0094] The thin film transistor TFT1 may include a semiconductor layer 115, a gate electrode 125, and source and drain electrodes 140. The thin film transistor TFT1 is a driving transistor (eg, Figure 4 DT in). The semiconductor layer 115 may be made of polycrystalline silicon (p-Si). In this case, a predetermined region thereof may be doped with impurities. In addition, the semiconductor layer 115 may be made of amorphous silicon a-Si or various organic semiconductor materials such as pentacene. The semiconductor layer 115 may be made of an oxide. The embodiments of the present disclosure are not limited to the materials constituting the semiconductor layer 115. The semiconductor layer 115 may be an active layer. However, the embodiments of the present disclosure are not limited thereto.

[0095] The gate electrode 125 may be disposed on the top of the semiconductor layer 115. The gate electrode 125 may be made of various conductive materials, such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, etc. However, the embodiments of the present disclosure are not limited thereto.

[0096] The gate insulating layer may be disposed between the semiconductor layer 115 and the gate electrode 125. The gate insulating layer may be a layer that insulates the semiconductor layer 115 and the gate electrode 125 from each other, and may be made of an insulating material. For example, the gate insulating layer may be composed of a single layer or a double layer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the embodiments of the present disclosure are not limited thereto.

[0097] The source electrode and the drain electrode 140 may be electrically connected to the semiconductor layer 115 and spaced apart from each other. The source electrode and the drain electrode 140 may be disposed on the insulating layer. Each of the source electrode and the drain electrode 140 may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof. However, the embodiments of the present disclosure are not limited thereto.

[0098] The capacitor Cst may be disposed on the substrate 101. The capacitor Cst may include a first gate electrode 142 and a second gate electrode 144. The gate insulating layer 124 may be disposed between the first gate electrode 142 and the second gate electrode 144. At least one of the first gate electrode 142 and the second gate electrode 144 may be connected to an electrode of the thin film transistor TFT1. The capacitor Cst may be connected to the thin film transistor TFT1 via a connection electrode 157.

[0099] Another thin film transistor TFT2 may be disposed on the substrate 101. The thin film transistor TFT2 may include a semiconductor layer 116, a gate electrode 126, and source and drain electrodes 112. The thin film transistor TFT2 may be one of the first to third transistors T1 to T3 (eg, see Figure 4 ). The gate insulating layer 122 may be disposed between the semiconductor layer 116 and the gate electrode 126 .

[0100] The interlayer insulating layer 128 may be disposed between the thin film transistor TFT2 and the capacitor Cst, or between the thin film transistor TFT1 and another thin film transistor TFT2.

[0101] For the convenience of explanation, among various thin film transistors that may be included in the display device 10, only two thin film transistors are shown, namely, corresponding to the driving transistor ( Figure 4 The thin film transistor TFT1 and the thin film transistors TFT1 and TFT1 corresponding to the first transistor T1 to the sixth transistor T6 ( Figure 4 However, the display panel 100 may include a thin film transistor TFT2 which is one of the first to sixth transistors T1 to T6 ( Figure 4 Other thin film transistors corresponding to the remaining transistors in (in). In addition, an example in which the thin film transistor has a coplanar structure is described. However, the thin film transistor can be implemented to have other structures, such as a staggered structure. The present disclosure is not limited thereto.

[0102] The thin film transistor TFT1 may receive a high potential driving voltage EVDD in response to a data voltage Vdata supplied to the gate electrode 125 of the thin film transistor TFT1 to control the amount of current supplied to the light emitting element EL, thereby adjusting the amount of light emitted from the light emitting element EL. The thin film transistor TFT1 may provide a constant current based on the voltage charged in the capacitor Cst to maintain the light emission of the light emitting element EL until the data voltage Vdata of the next frame is supplied thereto. The high potential power line may extend in parallel with the data line.

[0103] The thin film transistor TFT includes a semiconductor layer 115 disposed on an interlayer insulating layer 128, a gate electrode 125 overlapping the semiconductor layer 115 (while a second insulating layer 120 is interposed between the semiconductor layer 115 and the gate electrode 125), and a source electrode and a drain electrode 140 formed on a third insulating layer 135 and contacting the semiconductor layer 115.

[0104] The semiconductor layer 115 can be used as a region for forming a channel during the operation of the thin film transistor TFT1. The semiconductor layer 115 can be made of an oxide semiconductor, or can be made of various organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or pentacene. The present disclosure is not limited to this. The semiconductor layer 115 can be formed on the interlayer insulating layer 128. The semiconductor layer 115 may include a channel region, a source region, and a drain region. The channel region may overlap with the gate electrode 125, with the second insulating layer 120 inserted therebetween. A channel region may be generated between the source electrode and the drain electrode 140. The source region may be electrically connected to the source electrode 140 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain region may be electrically connected to the drain electrode 140 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135.

[0105] The buffer layer 105 and the first insulating layer 110 may be disposed between the semiconductor layer 116 and the substrate 101. The buffer layer 105 may delay diffusion of moisture and / or oxygen intruding into the substrate 101. The first insulating layer 110 may protect the semiconductor layer 115 and may block various types of defects introduced from the substrate 101.

[0106] The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of a material having an etching characteristic different from that of each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of silicon nitride (SiN x ) and silicon oxide (SiO x). Each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of silicon nitride (SiN x ) and silicon oxide (SiO x ). For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of silicon nitride (SiN x ), and each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of silicon oxide (SiO x ) is made. The present disclosure is not limited thereto.

[0107] The gate electrode 125 may be formed on the second insulating layer 120 and may overlap the channel region of the semiconductor layer 115 with the second insulating layer 120 interposed therebetween. The gate electrode 125 may be made of a first conductive material and may be implemented as a single layer or multiple layers made of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. The present disclosure is not limited thereto.

[0108] The source electrode 140 may be connected to the exposed source region of the semiconductor layer 115 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain electrode 140 may be opposite to the source electrode 140 and may be connected to the drain region of the semiconductor layer 115 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. Each of the source electrode and the drain electrode 140 may be made of a second conductive material and may be implemented as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. The present disclosure is not limited thereto.

[0109] The connection electrode 155 may be disposed between the first intermediate layer 150 and the second intermediate layer 160. The connection electrode 155 may be connected to the drain electrode 140 via a connection electrode contact hole 156 extending through the protective film 145 and the first intermediate layer 150. The connection electrode 155 may be made of a material having a low resistivity and being the same as or similar to the drain electrode 140. The present disclosure is not limited thereto.

[0110] The reference voltage line VrefL may be a sub power line branched from the reference voltage bus of the power line VL, and may be provided in the same layer as the source and drain electrodes 140 of the thin film transistor TFT1. The embodiments of the present disclosure are not limited thereto, and the reference voltage line VrefL may be provided on the interlayer insulating layer 128 or the second insulating layer 120.

[0111] The light emitting element EL including the light emitting layer 172 may be disposed on the second intermediate layer 160 and the bank layer 165. The light emitting element 170 may include an anode electrode 171, at least one light emitting layer 172 formed on the anode electrode 171, and a cathode electrode 173 formed on the light emitting layer 172.

[0112] The anode electrode 171 may be electrically connected to an exposed portion of the connection electrode 155 disposed on the first intermediate layer 150 and facing the second intermediate layer 160 via a contact hole extending through the second intermediate layer 160 .

[0113] The anode electrode 171 of each pixel is not covered by the bank layer 165. The bank layer 165 can be made of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer 165 may include a light shielding material including at least one of a color pigment, organic black, and carbon black. The present disclosure is not limited thereto.

[0114] At least one light-emitting layer 172 may be formed on a portion of the anode electrode 171 corresponding to the light-emitting region defined by the bank layer 165. At least one light-emitting layer 172 may include a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer 172, an electron injection layer, an electron blocking layer, and an electron transport layer on the anode electrode 171. The stacking order of the hole transport layer, the hole injection layer, the hole blocking layer, the light-emitting layer 172, the electron injection layer, the electron blocking layer, and the electron transport layer may be based on the light-emitting direction. In addition, the light-emitting layer 172 may include a first light-emitting stack and a second light-emitting stack facing each other, with a charge generation layer inserted therebetween. In this case, the light-emitting layer 172 of one of the first and second light-emitting stacks may generate blue light, while the light-emitting layer 172 of the other of the first and second light-emitting stacks may generate yellow-green light, so that white light may be generated from a combination of the first and second light-emitting stacks. The white light generated by the combination of the first light-emitting stack and the second light-emitting stack may be incident on a color filter located above or below the light-emitting layer 172, so that a color image may be realized. In another example, each light emitting layer 172 can generate each color light corresponding to each pixel without a separate color filter, so that a color image can be rendered. For example, the light emitting layer 172 of a red (R) pixel emits red light, the light emitting layer 172 of a green (G) pixel emits green light, and the light emitting layer 172 of a blue (B) pixel emits blue light.

[0115] The cathode electrode 173 may be formed to face the anode electrode 171 with the light emitting layer 172 disposed therebetween, and the cathode electrode 173 may receive a high potential driving voltage EVDD.

[0116] The encapsulation layer 180 can block external moisture or oxygen from penetrating into the light emitting element EL that is susceptible to external moisture or oxygen. To this end, the encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The present disclosure is not limited thereto. In the present disclosure, the structure of the encapsulation layer 180 in which the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 are sequentially stacked is described by way of example.

[0117] The first encapsulation layer 181 is formed on the substrate 101 on which the cathode electrode 173 has been formed. The third encapsulation layer 183 is formed on the substrate 101 on which the second encapsulation layer 182 has been formed. The third encapsulation layer 183 and the first encapsulation layer 181 may surround the top surface, the bottom surface, and the side surfaces of the second encapsulation layer 182. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent external moisture or oxygen from penetrating into the light emitting element EL. Each of the first encapsulation layer 181 and the third encapsulation layer 183 may be made of an inorganic insulating material that can be deposited at a low temperature, such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON) or aluminum oxide (Al2O3). Each of the first encapsulation layer 181 and the third encapsulation layer 183 is deposited in a low temperature atmosphere. Therefore, during the deposition process of the first encapsulation layer 181 and the third encapsulation layer 183, the light emitting element EL that is susceptible to the high temperature atmosphere can be prevented from being damaged.

[0118] The second encapsulation layer 182 is used as a shock absorbing layer to relieve the stress between the layers caused by the bending of the display device 10, and can flatten the steps between the layers. The second encapsulation layer 182 can be made of a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene or silicon oxycarbide (SiOC), or a photosensitive organic insulating material such as a photo acrylic resin. The present disclosure is not limited to this. When the second encapsulation layer 182 is formed using an inkjet method, a dam DAM can be provided to prevent the liquid second encapsulation layer 182 from diffusing to the edge of the substrate 101. The dam DAM can be closer to the edge of the substrate 101 than the second encapsulation layer 182. The dam DAM can prevent the liquid second encapsulation layer 182 from diffusing to the pad area where the conductive pad provided at the outermost side of the substrate 101 is provided.

[0119] The dam DAM is designed to prevent diffusion of the second encapsulation layer 182. However, when the second encapsulation layer 182 overflows the dam DAM during the process, the second encapsulation layer 182 as an organic layer may be exposed to the outside, so that moisture, etc. may invade the light emitting element. Therefore, in order to prevent the invasion, at least ten dam DAMs may be stacked.

[0120] The dam DAM may be disposed on an interlayer insulating layer disposed on the third insulating layer 135 and in the non-display area NA. However, embodiments of the present disclosure are not limited thereto, and the interlayer insulating layer may be the third insulating layer 135 .

[0121] In addition, the dam DAM, the first intermediate layer 150, and the second intermediate layer 160 may be formed simultaneously. The first intermediate layer 150 and the lower layer of the dam may be formed simultaneously. The second intermediate layer 160 and the upper layer of the dam DAM may be formed simultaneously. Therefore, the dam DAM may have a double-layer structure.

[0122] Therefore, the dam DAM may be made of the same material as each of the first intermediate layer 150 and the second intermediate layer 160. However, embodiments of the present disclosure are not limited thereto.

[0123] The dam DAM may overlap the low potential driving power line VSS. For example, the low potential driving power line VSS may be formed in a layer below the dam DAM and in the non-display area NA.

[0124] The low potential driving power line VSS and the gate driver 300 in the form of a gate in panel (GIP) may surround the periphery of the display panel. The low potential driving power line VSS may be located outside the gate driver 300. In addition, the low potential driving power line VSS may be connected to the anode electrode 171 to apply a common voltage thereto. The gate driver 300 is simply shown in the plan view and the cross-sectional view. However, the gate driver 300 may be constructed using a thin film transistor TFT having the same structure as that of the thin film transistor TFT of the display area AA.

[0125] The low potential driving power line VSS is disposed outside the gate driver 300. The low potential driving power line VSS is disposed outside the gate driver 300 and surrounds the display area AA. The low potential driving power line VSS may be made of the same material as each of the source electrode and the drain electrode 140 of the thin film transistor TFT. The present disclosure is not limited thereto. For example, the low potential driving power line VSS may be made of the same material as the gate electrode 125.

[0126] In addition, a low potential driving power line VSS may be electrically connected to the anode electrode 171. The low potential driving power line VSS may provide a low potential driving voltage EVSS to a plurality of pixels in the display area AA.

[0127] The low potential driving power line VSS may be disposed on the third insulating layer 135. Alternatively, the low potential driving power line VSS may be disposed on a layer of the source and drain electrodes 140 or the gate electrode 125 of the thin film transistor TFT1. However, embodiments of the present disclosure are not limited thereto.

[0128] At least one power line VL may be disposed between the gate driver 300 and the display area AA. At least one power line VL may be disposed in the same layer as the layer of the source electrode and the drain electrode 140 of the thin film transistor TFT. However, the embodiments of the present disclosure are not limited thereto. At least one power line VL is shown in a simple manner in the cross-sectional view. However, the reference voltage bus VrefL, the anode reset voltage bus VarL, and the initialization voltage bus ViniL constituting the at least one power line VL may be arranged side by side and may be disposed in the same layer. Alternatively, the reference voltage bus VrefL, the anode reset voltage bus VarL, and the initialization voltage bus ViniL may be disposed in different layers in an overlapping or non-overlapping manner. The initialization voltage bus may provide the initialization voltage Vini to a plurality of pixels in the display area AA. The anode reset voltage bus VarL may provide the anode reset voltage Var to a plurality of pixels in the display area AA. The reference voltage bus VrefL may provide the reference voltage Vref to a plurality of pixels in the display area AA. At least one power line VL is shown as being located between the gate driver 300 and the display area AA. However, the embodiments of the present disclosure are not limited thereto.

[0129] The touch layer 190 may be disposed on the encapsulation layer 180. In the touch layer 190, a touch buffer film 191 may be located between a touch sensor metal including touch electrode connection lines 192 and 194 and touch electrodes 195 and 196 and a cathode electrode 173 of the light emitting element EL.

[0130] The touch buffer film 191 can prevent chemicals (developer, etchant, etc.) used in the manufacturing process of the touch sensor metal provided on the touch buffer film 191 or moisture from the outside from intruding into the light emitting layer 172 including organic materials. Therefore, the touch buffer layer 191 can prevent damage to the light emitting layer 172 that is susceptible to chemicals or moisture.

[0131] The touch buffer film 191 may be made of an organic insulating material that may be formed at a low temperature lower than or equal to a specific temperature (100 degrees Celsius) to prevent damage to the light emitting layer 172 including an organic material susceptible to high temperature, and has a low dielectric constant of 1 to 3. For example, the touch buffer layer 191 may be made of an propylene-based, epoxy-based, or siloxane-based material. The touch buffer film 191 made of an organic insulating material and having a planarization property may prevent damage to the encapsulation layer 180 and fracture of a touch sensor metal formed on the touch buffer film 191 due to bending of the organic light emitting display device.

[0132] According to a mutual capacitance-based touch sensor structure, the touch electrodes 195 and 196 may be disposed on the touch buffer layer 191 , and the touch electrodes 195 and 196 may be disposed to intersect each other.

[0133] The touch electrode connection lines 192 and 194 may electrically connect the touch electrodes 195 and 196 to each other. The touch electrode connection lines 192 and 194 and the touch electrodes 195 and 196 may be located on different layers with the touch insulating film 193 interposed therebetween.

[0134] The touch electrode connection lines 192 and 194 may overlap the bank layer 165 , thereby preventing the aperture ratio from being reduced.

[0135] In one example, a portion of the touch electrode connection line 192 may extend along the upper and side surfaces of the encapsulation layer 180 and the upper and side surfaces of the dam DAM, and then may be electrically connected to the touch driver circuit via the pad 198. Thus, the touch electrodes 195 and 196 may be electrically connected to the touch driver circuit.

[0136] A portion of the touch electrode connection line 192 may receive a touch driving signal from a touch driver circuit and transmit it to the touch electrodes 195 and 196 , and may receive a touch sensing signal from the touch electrodes 195 and 196 and transmit it to the touch driver circuit.

[0137] The touch protection film 197 may be disposed on the touch electrodes 195 and 196. In the figure, it is shown that the touch protection film 197 is disposed only on the touch electrodes 195 and 196. However, the embodiments of the present disclosure are not limited thereto. The touch protection film 197 may extend to the inner end or the outer end of the dam DAM, and thus may also be disposed on the touch electrode connection line 192.

[0138] In addition, a color filter may be further disposed on the encapsulation layer 180 , and the color filter may be located on the touch layer 190 or between the encapsulation layer 180 and the touch layer 190 .

[0139] Figure 3 is a view of a configuration of a gate driver in a display device according to an embodiment of the present disclosure.

[0140] refer to Figure 3 , the gate driver 300 includes a first light emission control signal driver 312 and a second light emission control signal driver 314. In addition, the gate driver 300 also includes first scan drivers 322_O and 322_E, a second scan driver 324, and a third scan driver 326. The first scan drivers 322_O and 322_E may be composed of an odd-numbered scan driver 322_O and an even-numbered scan driver 322_E.

[0141] The gate driver 300 may include a shift register, which may be symmetrically arranged on two opposite sides of the display area AA, respectively. In addition, in the gate driver 300, the shift register on one side of the display area AA may be configured to include first scan drivers 322_O and 322_E, a first light emission control signal driver 312, and a second scan driver 324. The shift register on the other side of the display area AA may be configured to include first scan drivers 322_O and 322_E, a second light emission control signal driver 314, and a third scan driver 326. However, the embodiments of the present disclosure are not limited thereto, and the first light emission control signal driver 312, the second light emission control signal driver 314, the first scan drivers 322_O, 322_E, the second scan driver 324, and the third scan driver 326 may be arranged in a manner that varies according to the embodiments of the present disclosure.

[0142] Each of the stages STG(1) to STG(n) of the shift register may include each of the first scan signal generators SC1_O(1) to SC1_O(n) and SC1_E(1) to SC1_E(n), each of the first light emission control signal generators EM1(1) to EM1(n), each of the second light emission control signal generators (EM2(1) to EM2(n)), each of the second scan signal generators SC2(1) to SC2(n), and each of the third scan signal generators SC3(1) to SC3(n). Here, n is a real number such as a positive integer.

[0143] The first scan signal SC1(n) may be used to drive the first transistor T1 (see Figure 4 The second scanning signal SC2(n) may be used to drive the second transistor T2 (see Figure 4 The third scan signal SC3(n) may be used to drive the fifth transistor T5 (see Figure 4 ) and the sixth transistor T6 (see Figure 4 The first light emitting control signal EM1(n) may be used to drive the third transistor T3 (see Figure 4 The second light emitting control signal EM2(n) may be used to drive the fourth transistor T4 (see Figure 4 ) signal.

[0144] refer to Figure 3 , a reference voltage bus VrefL, an anode reset voltage bus VarL, and an initialization voltage bus ViniL may be disposed between and connected to the gate driver 300 and the display area AA.

[0145] The reference voltage bus VrefL, the anode reset voltage bus VarL, and the initialization voltage bus ViniL may respectively provide the reference voltage Vref, the anode reset voltage VarL, and the initialization voltage Vini from the power supply 500 to the pixel circuit.

[0146] As an example, it is shown that each of the reference voltage bus VrefL, the anode reset voltage bus VarL, and the initialization voltage bus ViniL is only set on one of the left side or the right side of the display area AA. However, the embodiments of the present disclosure are not limited to this. The reference voltage bus VrefL may be respectively set on two opposite sides of the display area AA. The anode reset voltage bus VarL may be respectively set on two opposite sides of the display area AA. The initialization voltage bus ViniL may be respectively set on two opposite sides of the display area AA. When each of the reference voltage bus VrefL, the anode reset voltage bus VarL, and the initialization voltage bus ViniL is only set on one of the two opposite sides of the display area AA, one side is not limited to the left side or the right side.

[0147] Alternatively, each of the reference voltage bus VrefL, the anode reset voltage bus VarL, and the initialization voltage bus ViniL is only set on one of the upper side or the lower side of the display area AA. However, the embodiments of the present disclosure are not limited to this. The reference voltage bus VrefL can be set on the upper side and the lower side of the display area AA, respectively. The anode reset voltage bus VarL can be set on the upper side and the lower side of the display area AA, respectively. The initialization voltage bus ViniL can be set on the upper side and the lower side of the display area AA, respectively. However, the embodiments of the present disclosure are not limited to this.

[0148] The first scan drivers 322_O and 322_E, the second scan driver 324, and the first light emission control signal driver 312 may be disposed in one side region around the display area AA. The third scan driver 326, the first scan drivers 322_O and 322_E, and the second light emission control signal driver 314 may be disposed in the other side region around the display area AA. However, the embodiments of the present disclosure are not limited thereto, and according to an embodiment, at least one of the first scan drivers 322_O and 322_E, the second scan driver 324, and the first light emission control signal driver 312 may be disposed in the other side region around the display area AA, and at least one of the third scan driver 326, the first scan drivers 322_O and 322_E, and the second light emission control signal driver 314 may be disposed in the one side region around the display area AA.

[0149] In a side area around the display area AA, the first scan drivers 322_O and 322_E may be disposed adjacent to the display area AA, and the second scan driver 324 may be disposed in an outermost area, and the first light emitting control signal driver 312 may be disposed between the first scan drivers 322_O and 322_E and the second scan driver 324.

[0150] Alternatively, according to an embodiment of the present disclosure, the first light emitting control signal driver 312 may be disposed in the outermost area.

[0151] In addition, in the other side area around the display area AA, the first scan drivers 322_O and 322_E can be set adjacent to the display area AA, and the third scan driver 326 can be set in the outermost area, and the second light emitting control signal driver 314 can be set between the first scan drivers 322_O and 322_E and the third scan driver 326.

[0152] Alternatively, according to an embodiment of the present disclosure, the second light emitting control signal driver 314 may be disposed in the outermost region.

[0153] In addition, the first scan driver 322_O and 322_E can be divided into an odd-numbered scan driver 322_O and an even-numbered scan driver 322_E. The odd-numbered scan driver 322_O can be respectively arranged on two opposite sides of the display area AA. The even-numbered scan driver 322_E can be respectively arranged on two opposite sides of the display area AA. When the first scan driver is configured so that the odd-numbered scan driver 322_O and the even-numbered scan driver 322_E operate separately, sufficient time required for sampling the data voltage Vdata can be ensured. In addition, the odd-numbered scan driver 322_O is respectively arranged on two opposite sides of the display area AA, and the even-numbered scan driver 322_E is respectively arranged on two opposite sides of the display area AA, thereby reducing the difference between the sampling times of the data voltage Vdata in the pixel. Therefore, when the first scan drivers 322_O and 322_E operate, sufficient time for sampling the data voltage Vdata can be ensured, and the difference between its sampling times in the pixel can be reduced, thereby improving the image quality of the display panel.

[0154] Figure 4 is a view showing a pixel circuit in a display device according to an embodiment of the present disclosure. Specifically, Figure 4 An example of an internal compensation pixel circuit is shown for explanation. The display device according to an embodiment of the present disclosure may also be applied to other internal compensation circuits having 4T1C, 7T1C, and 8T1C structures.

[0155] refer to Figure 4 , each of the plurality of internal compensation pixels P may include a pixel circuit including a driving transistor DT and a light emitting element EL connected to the pixel circuit.

[0156] The pixel circuit may control the driving current flowing through the light emitting element EL to drive the light emitting element EL. The pixel circuit may include a driving transistor DT, a first transistor T1 to a sixth transistor T6, and a capacitor Cst. Each of the transistors DT, T1 to T6 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0157] Each of the transistors DT and T1 to T6 may be a P-type thin film transistor or an N-type thin film transistor. Figure 4 In the embodiment of the present disclosure, each of the transistors DT and T1 to T6 is implemented as an N-type thin film transistor. However, the embodiments of the present disclosure are not limited thereto. According to the embodiment, each of all or some of the transistors DT and T1 to T6 may be a P-type thin film transistor or an N-type thin film transistor. In addition, the N-type thin film transistor may be implemented as an oxide thin film transistor. The P-type thin film transistor may be implemented as a polysilicon thin film transistor.

[0158] Hereinafter, an example is described in which each of the transistors DT and T1 to T6 is implemented as an N-type thin film transistor. Therefore, when a high voltage is applied to each of the transistors DT and T1 to T6, each of the transistors DT and T1 to T6 may be turned on.

[0159] According to one example, the first transistor T1 constituting the pixel circuit can be used as a data supply transistor, the second transistor T2 constituting the pixel circuit can be used as an initialization transistor, and each of the third transistor T3 and the fourth transistor T4 constituting the pixel circuit can be used as a light emission control transistor. In addition, each of the fifth transistor T5 and the sixth transistor T6 constituting the pixel circuit can be used as an initialization transistor.

[0160] The light emitting element EL may include an anode electrode and a cathode electrode. The anode electrode of the light emitting element EL may be connected to a fourth node N4, and the cathode electrode may be connected to a low potential driving voltage EVSS. The fourth node N4 may be connected to a source electrode of a fourth transistor T4. The light emitting element EL may include a capacitor Cel generated between the anode electrode and the cathode electrode. The capacitor Cel may be a parasitic capacitor generated between the anode electrode and the cathode electrode of the light emitting element EL. The capacitor Cel may have a capacitance value of the light emitting element EL.

[0161] The driving transistor DT may include a drain electrode connected to the source electrode of the third transistor T3, a gate electrode connected to the first node N1, and a source electrode connected to the third node N3. The driving transistor DT may provide a driving current to the light emitting element EL based on the voltage of the first node N1 (or the data voltage Vdata stored in the capacitor Cst, which will be described later).

[0162] The first transistor T1 may include a first electrode connected to the data line DL or receiving a data voltage Vdata, a second electrode connected to the first node N1, and a gate electrode receiving a first scan signal SC1(n). The first transistor T1 may be turned on in response to the first scan signal SC1(n) and thus may transmit the data voltage Vdata to the first node N1. The first transistor T1 may be a data voltage supply transistor.

[0163] The capacitor Cst may be connected to the first node N1 and the third node N3 and disposed between the first node N1 and the third node N3. The capacitor Cst may sample and store or maintain therein the data voltage Vdata supplied thereto.

[0164] The second transistor T2 may include a first electrode connected to a reference voltage Vref, a second electrode connected to the first node N1, and a gate electrode receiving a second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n), and thus may provide the reference voltage Vref to the node N1. The second transistor T2 may be an initialization transistor.

[0165] The third transistor T3 may be connected to the high potential driving voltage EVDD and the driving transistor DT and disposed between the high potential driving voltage EVDD and the driving transistor DT. The third transistor T3 may include a first electrode receiving the high potential driving voltage EVDD, a second electrode connected to the driving transistor DT, and a gate electrode receiving the first light emission control signal EM1(n). The third transistor T3 may be turned on in response to the first light emission control signal EM1(n), and thus may provide the high potential driving voltage EVDD to the driving transistor DT. The third transistor T3 may be a light emission control transistor.

[0166] The fourth transistor T4 may be connected to the light emitting element EL and the driving transistor DT and disposed between the light emitting element EL and the driving transistor DT. The fourth transistor T4 may include a first electrode connected to the light emitting element EL, a second electrode connected to the driving transistor DT, and a gate electrode receiving the second light emitting control signal EM2(n). The fourth transistor T4 may be turned on in response to the second light emitting control signal EM2(n), and thus may provide a driving current controlled by the driving transistor DT to the light emitting element EL. The fourth transistor T4 may be a light emitting control transistor.

[0167] The fifth transistor T5 may be connected to the initialization voltage Vini and the third node N3 and disposed between the initialization voltage Vini and the third node N3. The fifth transistor T5 may include a first electrode connected to the initialization voltage Vini, a second electrode connected to the third node N3, and a gate electrode receiving the third scan signal SC3(n). The fifth transistor T5 may be turned on in response to the third scan signal SC3(n), and thus may provide the initialization voltage Vini to the third node N3. The fifth transistor T5 may be an initialization transistor.

[0168] The pixel circuit may have a capacitor Ca generated between the high potential driving voltage EVDD and the third node N3. The capacitor Ca may be a parasitic capacitor generated by the third transistor T3 and the driving transistor DT. The fifth transistor T5 may initialize the third node N3 and the capacitor Ca in response to the third scan signal SC3(n).

[0169] The sixth transistor T6 may be connected to the anode reset voltage Var and the fourth node N4 and disposed between the anode reset voltage Var and the fourth node N4. The sixth transistor T6 may include a first electrode connected to the anode reset voltage Var, a second electrode connected to the fourth node N4, and a gate electrode receiving the third scan signal SC3 (n). The sixth transistor T6 may be turned on in response to the third scan signal SC3 (n), and thus may provide the anode reset voltage Var to the fourth node N4. The sixth transistor T6 may be an initialization transistor. The sixth transistor T6 may initialize the fourth node N4 and the capacitor Ce1 in response to the third scan signal SC3 (n).

[0170] In this way, the internal compensation pixel P may include a light emitting element EL that emits light in response to a driving current, a driving transistor DT that controls the driving current, a capacitor Cst connected to a gate electrode and a source electrode of the driving transistor DT and disposed between the gate electrode and the source electrode of the driving transistor DT, a first transistor T1 for applying a data voltage Vdata to the gate electrode of the driving transistor DT based on a first scan signal SC1(n), a second transistor T2 for applying a reference voltage Vref to the gate electrode of the driving transistor DT based on a second scan signal SC2(n), a third transistor T3 for applying a high potential driving voltage EVDD to the drain electrode of the driving transistor DT based on a first light emitting control signal EM1(n), a fourth transistor T4 for applying a driving current from the driving transistor DT to the light emitting element based on a second light emitting control signal EM2(n), a fifth transistor T5 for applying an initialization voltage Vini to the source electrode of the driving transistor DT based on a third scan signal SC3(n), and a sixth transistor T6 for applying an anode reset voltage Var to the anode electrode of the light emitting element EL based on the third scan signal SC3(n).

[0171] Figure 5 is a timing chart showing the operation of the pixel circuit of the display device according to the embodiment of the present disclosure.

[0172] refer to Figure 5 , the operation period of the pixel circuit of the display device may include an initialization period Ti, a sensing period Ts, a writing period Tw, an anode reset period Tar, and a light emitting period Tb. However, this is only an example, and the pixel circuit of the display device may not be limited to this order.

[0173] In the initialization period Ti, each of the first light emission control signal EM1(n), the second light emission control signal EM2(n), the third scan signal SC3(n), and the first scan signal SC1(n) is in a low state, and the second scan signal SC2(n) is in a high state. Therefore, the first transistor T1 and the third to sixth transistors T3, T4, T5, and T6 of the pixel circuit are in a cut-off state, and the second transistor T2 enters a turn-on state.

[0174] In the initialization period Ti, the second transistor T2 supplies the reference voltage Vref to the first node N1 in response to the second scan signal SC2 (n).

[0175] In the initialization period Ti, the second transistor T2 initializes the gate electrode of the driving transistor DT, the first node N1, and the capacitor Cst by supplying the reference voltage Vref to the first node N1.

[0176] In the sensing period Ts, each of the second light emitting control signal EM2(n), the third scan signal SC3(n), and the first scan signal SC1(n) is in a low state, and each of the second scan signal SC2(n) and the first light emitting control signal EM1(n) is in a high state.

[0177] Therefore, the first transistor T1 and the fourth to sixth transistors T4 , T5 , and T6 of the pixel circuit enter a cut-off state, and the second transistor T2 , the third transistor T3 , and the driving transistor DT enter a turn-on state.

[0178] In the sensing period Ts, the third transistor T3 provides the high potential driving voltage EVDD to the drain electrode of the driving transistor DT in response to the first light emitting control signal EM1(n), so that the driving transistor DT is turned on, and the voltage of the third node N3 increases the threshold voltage of the driving transistor DT, and the capacitor Cst samples the threshold voltage of the driving transistor DT.

[0179] In the writing period Tw, each of the second light emission control signal EM2(n), the second scan signal SC2(n) and the third scan signal SC3(n) is in a low state, and each of the first scan signal SC1(n) and the first light emission control signal EM1(n) is in a high state. Therefore, the second transistor T2 and the fourth to sixth transistors T4, T5 and T6 of the pixel circuit enter the off state, and the first transistor T1 and the third transistor T3 enter the on state.

[0180] In the writing period Tw, the first transistor T1 provides the data voltage Vdata to the gate electrode of the driving transistor DT in response to the first scanning signal SC1 (n), so that the voltage level of the first node N1 rises by the data voltage Vdata, and the capacitor Cst samples the data voltage Vdata. At this time, the threshold voltage Vth of the driving transistor DT is offset by the previously sampled threshold voltage Vth, so that only the data voltage Vdata can be sampled to the capacitor Cst. In addition, in the writing period Tw, the gate-source voltage V between the gate electrode and the source electrode of the driving transistor can be used. gs To sense the mobility Mob of the driving transistor.

[0181] In the anode reset period Tar, the first light emission control signal EM1(n), the second light emission control signal EM2(n), the first scan signal SC1(n), and the second scan signal SC2(n) are in a low state, and the third scan signal SC3(n) is in a high state. Therefore, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 of the pixel circuit enter a cut-off state, and the fifth transistor T5 and the sixth transistor T6 enter a turn-on state.

[0182] In the anode reset period Tar, the fifth transistor T5 supplies the initialization voltage Vini to the third node N3 in response to the third scan signal SC3(n). The fifth transistor T5 initializes the source electrode of the driving transistor DT, the third node N3 and the capacitor Ca by supplying the initialization voltage Vini to the third node N3.

[0183] In the anode reset period Tar, the sixth transistor T6 supplies the anode reset voltage Var to the fourth node N4 in response to the third scan signal SC3(n). The sixth transistor T6 initializes the anode electrode of the light emitting element, the fourth node N4 and the capacitor Cel by supplying the anode reset voltage Var to the fourth node N4.

[0184] In the light emitting period Tb, each of the first light emitting control signal EM1(n) and the second light emitting control signal EM2(n) is in a high state, and each of the first scanning signal SC1(n), the second scanning signal SC2(n) and the third scanning signal SC3(n) is in a low state. Therefore, the third transistor T3, the driving transistor DT and the fourth transistor T4 of the pixel circuit enter the on state, and the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 enter the off state.

[0185] In the light emitting period Tb, the third transistor T3, the driving transistor DT and the fourth transistor T4 enter the on state, thereby establishing a current path between the high potential driving voltage EVDD and the low potential driving voltage EVSS, thereby providing the driving current to the light emitting element EL. The intensity of the driving current is determined based on the value of the data voltage Vdata sampled to the capacitor Cst. Since the light emitting element EL operates based on the value of the data voltage Vdata regardless of the value of the threshold voltage Vth of the driving transistor DT, the threshold voltage Vth of the driving transistor DT can be compensated.

[0186] The internal compensation pixel is configured so that the driving transistor DT operates during the light emission period Tb in which the light emitting element emits light, and the driving transistor DT also operates during the sensing period Ts in which the threshold voltage of the driving transistor is sensed. Therefore, the degradation compensation modeling for compensating for the degradation of the internal compensation pixel may include a first degradation compensation modeling regarding the operating characteristics of the internal compensation pixel in the light emission period in which light from the light emitting element is emitted, and a second degradation compensation modeling regarding the operating characteristics of the internal compensation pixel in the sensing period Ts in which the threshold voltage of the driving transistor of the sensing pixel is sensed.

[0187] According to an embodiment of the present disclosure, in order to compensate for degradation of an internal compensation display device, operating characteristics in a period for light emitting elements to emit and operating characteristics in a period for sensing a threshold voltage of a driving transistor of a pixel inside the pixel may be applied to degradation compensation modeling.

[0188] According to the operating characteristics of the internal compensation pixel, a high-level peak current may be applied to the driving transistor DT during the sensing period Ts of sensing the threshold voltage of the driving transistor DT, which may cause degradation of the driving transistor DT.

[0189] According to the present disclosure, in order to achieve accurate degradation compensation of the internal compensation display panel, the operating characteristics during the light-emitting period of the light-emitting element can be applied to the first compensation modeling, and the operating characteristics during the sensing period of the threshold voltage of the sensing driving transistor can be applied to the second compensation modeling.

[0190] The first compensation modeling may be used to calculate compensation data to compensate for degradation characteristics during the light emitting period. The first compensation data corresponding to the degradation characteristics of the light emitting period Tb may be calculated based on Equation 2 as follows.

[0191] Equation 2

[0192] ΔV th_d =(t / τ_d) β_d ,

[0193]

[0194] Where t represents the operation time of the display panel, τ_d represents the characteristic time scale of degradation during the light-emitting period, β_d represents the stretching index during the light-emitting period, A_d represents the process and component distribution coefficient during the light-emitting period, V gs denotes a gate-source voltage of the driving transistor based on the data voltage, n denotes an acceleration coefficient, Ea_d denotes activation energy during a light emitting period, R denotes an ideal gas constant, and T denotes an absolute temperature.

[0195] The second compensation modeling may be used to calculate compensation data to compensate for the degradation characteristics during the sensing period Ts. The second compensation data corresponding to the degradation characteristics of the sensing period Ts may be calculated based on the following equation 3:

[0196] Equation 3

[0197] ΔV th_s =(t / τ_s) β_s ,

[0198]

[0199] Wherein t represents the operating time of the display panel, τ_s represents the characteristic time scale of degradation during the sensing period, β_s represents the stretching index during the sensing period, A_s represents the process and component distribution coefficient during the sensing period, Ea_s represents the activation energy during the sensing period, R represents the ideal gas constant, and T represents the absolute temperature.

[0200] In this regard, since the sensing operation of the internal compensation circuit during the sensing period is performed under global conditions, it is possible to determine the value of the sensing operation based only on the temperature T and the factor A_s related to the initial threshold voltage of the driving transistor without V gs The acceleration factor is used to create a second compensation modeling that is different from the first compensation modeling during the light emitting period.

[0201] In addition, different β, A and Ea factors can be based on different degradation characteristics of the light emitting period and the sensing period, and thus can be applied to the first compensation modeling and the second compensation modeling, respectively. That is, the β, A and Ea factors during the light emitting period can be set to have different values ​​from the β, A and Ea factors during the sensing period.

[0202] According to an embodiment of the present disclosure, the display device may generate compensation data based on equation 2 of the first compensation modeling representing the operating characteristics during the light emitting period Tb of the internal compensation pixel and equation 3 of the second compensation modeling representing the operating characteristics during the sensing period Ts, and then the compensation data may be used to compensate the image data. The present disclosure shows an example in which the controller 200 performs compensation. However, the embodiments of the present disclosure are not limited thereto. According to another embodiment, the data driver 200 or a separate degradation compensation device may calculate compensation data based on the first compensation modeling and the second compensation modeling, and apply the compensation data to the image data.

[0203] Figure 6 It is shown Figure 4 A view of the operating characteristics of an internally compensated pixel of a pixel circuit during a light emission period is shown.

[0204] refer to Figure 6 , the operation characteristics of the internal compensation pixel during the light emission period Tb indicate that the threshold voltage of the driving transistor in each of the R, G, and B pixels changes with the lapse of operation time (or degradation time).

[0205] In the embodiment of the present disclosure, during the light emission period, the changes in the threshold voltages of the driving transistors in the R, G, and B pixels are different from each other. Therefore, different degradation characteristics can be applied to the degradation compensation modeling in the R, G, and B pixels, respectively.

[0206] In one example, in order to apply different degradation characteristics during the light emission period to the degradation compensation modeling in the R, G, and B pixels, respectively, at least one of the β_d, A_d, and Ea_d factors of the first compensation modeling may be set (or calculated) to have different values ​​in the R, G, and B pixels. That is, at least one of the β_d, A_d, and Ea_d factors in the above equation 2 of the first compensation modeling may be set (or calculated) to have different values ​​in the R, G, and B pixels.

[0207] Figure 7 It is shown Figure 4 A view of the operating characteristics of an internally compensated pixel of a pixel circuit during a sensing period is shown.

[0208] refer to Figure 7 , the operation characteristics of the internal compensation pixel during the sensing period Ts indicate that the threshold voltage of the driving transistor in each of the R, G, and B pixels changes with the lapse of operation time (or degradation time).

[0209] In an embodiment of the present disclosure, during the sensing period Ts, changes in the threshold voltages of the driving transistors in the R, G, and B pixels are different from each other. Therefore, different degradation characteristics can be applied to degradation compensation modeling in the R, G, and B pixels, respectively.

[0210] In one example, in order to apply different degradation characteristics during the sensing period Ts to the degradation compensation modeling in the R, G, and B pixels, respectively, at least one of the β_s, A_s, and Ea_s factors of the second compensation modeling may be set (or calculated) to have different values ​​in the R, G, and B pixels. That is, at least one of the β_s, A_s, and Ea_s factors in the above equation 3 of the second compensation modeling may be set (or calculated) to have different values ​​in the R, G, and B pixels.

[0211] A display device according to various aspects and features of the present disclosure may be described as follows.

[0212] A first aspect of the present disclosure provides a display device, comprising: a display panel, the display panel comprising a plurality of internal compensation pixels; and a data driver, the data driver being configured to apply a data voltage to the display panel; and a controller, the controller being configured to: compensate image data based on degradation compensation modeling, wherein the degradation compensation modeling comprises degradation compensation modeling representing operating characteristics of the internal compensation pixels during a light emitting period, and degradation compensation modeling representing operating characteristics of the internal compensation pixels during a sensing period; and provide the compensated image data to the data driver.

[0213] According to some features of the display device of the first aspect, the degradation compensation modeling includes: a first compensation modeling, which represents the degradation characteristics of the driving transistor of the internal compensation pixel during the light-emitting period; and a second compensation modeling, which indicates the degradation characteristics of the driving transistor of the internal compensation pixel during the sensing period.

[0214] According to some features of the display device of the first aspect, the sensing period is set to a period in which the internal compensation pixel senses the threshold voltage of the driving transistor, wherein the light emitting period is set to a period in which the light emitting element of the internal compensation pixel emits light under the data voltage.

[0215] According to some features of the display device of the first aspect, the first compensation modeling is defined based on the following equation 1:

[0216] Equation 1

[0217] ΔV th_d =(t / τ_d) β_d ,

[0218]

[0219] Where t represents the operation time of the display panel, τ_d represents the characteristic time scale of degradation during the light-emitting period, β_d represents the stretching index during the light-emitting period, A_d represents the process and component distribution coefficient during the light-emitting period, V gs denotes a gate-source voltage of the driving transistor based on the data voltage, n denotes an acceleration coefficient, Ea_d denotes activation energy during a light emitting period, R denotes an ideal gas constant, and T denotes an absolute temperature.

[0220] According to some features of the display device of the first aspect, at least one of the β_d, A_d and Ea_d factors of the first compensation modeling is set to have different values ​​in the R, G and B pixels, so that the different degradation characteristics during the light-emitting period are respectively applied to the first degradation compensation modeling in the R, G and B pixels.

[0221] According to some features of the display device of the first aspect, the second compensation modeling is defined based on the following equation 2:

[0222] Equation 2

[0223] ΔV th_s =(t / τ_s) β_s ,

[0224]

[0225] Wherein t represents the operating time of the display panel, τ_s represents the characteristic time scale of degradation during the sensing period, β_s represents the stretching index during the sensing period, A_s represents the process and component distribution coefficient during the sensing period, Ea_s represents the activation energy during the sensing period, R represents the ideal gas constant, and T represents the absolute temperature.

[0226] According to some features of the display device of the first aspect, at least one of the β_s, A_s and Ea_s factors of the second compensation modeling is set to have different values ​​in the R, G and B pixels, so that the different degradation characteristics during the sensing period are applied to the second degradation compensation modeling in the R, G and B pixels, respectively.

[0227] According to some features of the display device of the first aspect, the controller is configured to compensate the image data based on a sum of a value calculated by the first compensation modeling and a value calculated by the second compensation modeling.

[0228] According to some features of the display device of the first aspect, the internal compensation pixel includes: a light-emitting element, the light-emitting element is used to emit light under a driving current; a driving transistor, the driving transistor is configured to control the driving current; a capacitor, the capacitor is connected to the gate electrode and the source electrode of the driving transistor and is arranged between the gate electrode and the source electrode of the driving transistor; a first transistor, the first transistor is configured to apply the data voltage to the gate electrode of the driving transistor in response to receiving a first scanning signal; a second transistor, the second transistor is configured to apply a reference voltage to the gate electrode of the driving transistor in response to receiving a second scanning signal a gate electrode; a third transistor, the third transistor being configured to apply a high potential driving voltage to the drain electrode of the driving transistor in response to receiving a first light emitting control signal; a fourth transistor, the fourth transistor being configured to apply the driving current from the driving transistor to the light emitting element in response to receiving a second light emitting control signal; a fifth transistor, the fifth transistor being configured to apply an initialization voltage to the source electrode of the driving transistor in response to receiving a third scan signal; and a sixth transistor, the sixth transistor being configured to apply an anode reset voltage to the anode electrode of the light emitting element in response to receiving the third scan signal.

[0229] According to some features of the display device of the first aspect, the internal compensation pixel is configured to control the light-emitting element to emit light at the data voltage during the light-emitting period, wherein the degradation characteristics of the driving transistor during the light-emitting period are applied to the first compensation modeling of the degradation compensation modeling.

[0230] According to some features of the display device of the first aspect, the internal compensation pixel is configured to sense the threshold voltage of the driving transistor during the sensing period, wherein the degradation characteristics of the driving transistor during the sensing period are applied to the second compensation modeling of the degradation compensation modeling.

[0231] A second aspect of the present disclosure provides a display device, comprising: a display panel, the display panel comprising a plurality of internal compensation pixels, wherein each of the internal compensation pixels is configured to sense a threshold voltage of a driving transistor during a sensing period and to emit light at a data voltage during a light emitting period, wherein the display device is configured to: apply operating characteristics of the internal compensation pixels during the light emitting period to a first compensation modeling; apply operating characteristics of the internal compensation pixels during the sensing period to a second compensation modeling; and compensate image data based on the first compensation modeling and the second compensation modeling.

[0232] According to some features of the display device of the second aspect, the first compensation modeling is defined based on the following equation 1:

[0233] Equation 1

[0234] ΔV th_d =(t / τ_d) β_d ,

[0235]

[0236] Where t represents the operation time of the display panel, τ_d represents the characteristic time scale of degradation during the light-emitting period, β_d represents the stretching index during the light-emitting period, A_d represents the process and component distribution coefficient during the light-emitting period, V gs denotes a gate-source voltage of the driving transistor based on the data voltage, n denotes an acceleration coefficient, Ea_d denotes activation energy during a light emitting period, R denotes an ideal gas constant, and T denotes an absolute temperature.

[0237] According to some features of the display device of the second aspect, at least one of the β_d, A_d and Ea_d factors of the first compensation modeling is set to have different values ​​in the R, G and B pixels, so that the different degradation characteristics during the light-emitting period are respectively applied to the first degradation compensation modeling in the R, G and B pixels.

[0238] According to some features of the display device of the second aspect, the second compensation modeling is defined based on the following equation 2:

[0239] Equation 2

[0240] ΔV th_s=(t / τ_s) β_s ,

[0241]

[0242] Wherein t represents the operating time of the display panel, τ_s represents the characteristic time scale of degradation during the sensing period, β_s represents the stretching index during the sensing period, A_s represents the process and component distribution coefficient during the sensing period, Ea_s represents the activation energy during the sensing period, R represents the ideal gas constant, and T represents the absolute temperature.

[0243] According to some features of the display device of the second aspect, at least one of the β_s, A_s and Ea_s factors of the second compensation modeling is set to have different values ​​in the R, G and B pixels, so that the different degradation characteristics during the sensing period are applied to the second degradation compensation modeling in the R, G and B pixels, respectively.

[0244] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments, but can be implemented in various different forms. It will be appreciated by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive but illustrative in all aspects.

Claims

1. A display device, comprising: a display panel, the display panel comprising internal compensation pixels; a data driver configured to apply a data voltage to the display panel; as well as A controller, the controller being configured to: compensating the image data based on degradation compensation modeling, wherein operating characteristics of the internal compensation pixels during a light emission period and operating characteristics of the internal compensation pixels during a sensing period are applied to the degradation compensation modeling; as well as The compensated image data is provided to the data driver.

2. The display device according to claim 1, wherein: The degradation compensation modeling includes: first compensation modeling representing degradation characteristics of a drive transistor of the internal compensation pixel during the light emission period; and Second compensation modeling representing degradation characteristics of the drive transistor of the internal compensation pixel during the sensing period.

3. The display device according to claim 2, wherein: The sensing period is set to be a period during which the internal compensation pixel senses a threshold voltage of the driving transistor, and The light emitting period is set as a period during which the light emitting element of the internal compensation pixel emits light under the data voltage.

4. The display device according to claim 3, wherein: The first compensation modeling is defined based on the following equation 1: Equation 1 ΔV th_d =(t / τ_d) β_d , Wherein, t represents the operation time of the display panel, τ_d represents the characteristic time scale of degradation during the light-emitting period, β_d represents the stretching index during the light-emitting period, A_d represents the process and component distribution coefficient during the light-emitting period, V gs denotes a gate-source voltage of the driving transistor based on the data voltage, n denotes an acceleration coefficient, Ea_d denotes activation energy during the light emitting period, R denotes an ideal gas constant, and T denotes an absolute temperature.

5. The display device according to claim 4, wherein: At least one of the β_d, A_d and Ea_d factors of the first compensation modeling is set to have different values ​​in red (R) pixels, green (G) pixels and blue (B) pixels, so that different degradation characteristics during the light-emitting period are applied to the first compensation modeling in the R pixels, the G pixels and the B pixels, respectively.

6. The display device according to claim 4, wherein: The second compensation modeling is defined based on the following equation 2: Equation 2 ΔV th_s =(t / τ_s) β_s , Wherein, t represents the operating time of the display panel, τ_s represents the characteristic time scale of degradation during the sensing period, β_s represents the stretching index during the sensing period, A_s represents the process and component distribution coefficient during the sensing period, Ea_s represents the activation energy during the sensing period, R represents the ideal gas constant, and T represents the absolute temperature.

7. The display device according to claim 6, wherein: At least one of the β_s, A_s and Ea_s factors of the second compensation modeling is set to have different values ​​in red (R) pixels, green (G) pixels and blue (B) pixels, so that different degradation characteristics during the sensing period are applied to the second compensation modeling in the R pixels, the G pixels and the B pixels, respectively.

8. The display device according to claim 6, wherein: The first compensation modeling is configured to calculate compensation data to compensate for degradation characteristics of the driving transistor during the light emission period, and The second compensation modeling is configured to calculate compensation data to compensate for degradation characteristics of the driving transistor during the sensing period.

9. The display device according to claim 8, wherein: The controller is configured to compensate the image data based on a sum of a value calculated by the first compensation modeling and a value calculated by the second compensation modeling.

10. The display device according to claim 2, wherein: The internal compensation pixel comprises: a light emitting element configured to emit light under a driving current; a driving transistor configured to control the driving current; a capacitor disposed between a gate electrode and a source electrode of the driving transistor; a first transistor configured to apply the data voltage to the gate electrode of the driving transistor in response to receiving a first scan signal; a second transistor configured to apply a reference voltage to the gate electrode of the driving transistor in response to receiving a second scan signal; a third transistor configured to apply a high potential driving voltage to a drain electrode of the driving transistor in response to receiving a first light emission control signal; a fourth transistor configured to apply the drive current from the drive transistor to the light emitting element in response to receiving a second light emitting control signal; a fifth transistor configured to apply an initialization voltage to the source electrode of the driving transistor in response to receiving a third scan signal; and A sixth transistor is configured to apply an anode reset voltage to an anode electrode of the light emitting element in response to receiving the third scan signal.

11. The display device according to claim 10, wherein: The internal compensation pixel is configured to control the light emitting element to emit light at the data voltage during the light emitting period, and Wherein, the degradation characteristic of the driving transistor during the light emission period is applied to the first compensation modeling of the degradation compensation modeling.

12. The display device according to claim 11, wherein: The internal compensation pixel is configured to sense the threshold voltage of the driving transistor during the sensing period, and The degradation characteristic of the driving transistor during the sensing period is applied to the second compensation modeling of the degradation compensation modeling.

13. A display device, comprising: a display panel comprising a plurality of internal compensation pixels, wherein one of the plurality of internal compensation pixels is configured to sense a threshold voltage of a driving transistor during a sensing period and emit light at a data voltage during a light emitting period, Wherein, the display device is configured as: applying operating characteristics of the one internal compensation pixel during the light emission period to a first compensation model; applying operating characteristics of the one internal compensation pixel during the sensing period to a second compensation model; and Image data is compensated based on the first compensation modeling and the second compensation modeling.

14. The display device according to claim 13, wherein: The first compensation modeling is defined based on the following equation 1: Equation 1 ΔV th_d =(t / τ_d) β_d , Wherein t represents the operation time of the display panel, τ_d represents the characteristic time scale of degradation during the light-emitting period, β_d represents the stretching index during the light-emitting period, A d represents the process and component distribution coefficient during the light-emitting period, Vgs represents the gate-source voltage of the driving transistor based on the data voltage, n represents the acceleration coefficient, Ea_d represents the activation energy during the light-emitting period, R represents the ideal gas constant, and T represents the absolute temperature.

15. The display device according to claim 14, wherein: At least one of the β_d, A_d and Ea_d factors of the first compensation modeling is set to have different values ​​in red (R) pixels, green (G) pixels and blue (B) pixels, so that different degradation characteristics during the light-emitting period are applied to the first compensation modeling in the R pixels, the G pixels and the B pixels, respectively.

16. The display device according to claim 14, wherein: The second compensation modeling is defined based on the following equation 2: Equation 2 ΔV th_s =(t / τ_s) β_s , Wherein t represents the operating time of the display panel, τ_s represents the characteristic time scale of degradation during the sensing period, β_s represents the stretching index during the sensing period, A_s represents the process and component distribution coefficient during the sensing period, Ea_s represents the activation energy during the sensing period, R represents the ideal gas constant, and T represents the absolute temperature.

17. The display device according to claim 16, wherein: At least one of the β_s, A_s and Ea_s factors of the second compensation modeling is set to have different values ​​in red (R) pixels, green (G) pixels and blue (B) pixels, so that different degradation characteristics during the sensing period are applied to the second compensation modeling in the R pixels, the G pixels and the B pixels, respectively.

Images