Implementation method of self-alignment dual imaging technology, controller and chip production system

Abstract

The invention discloses an implementation method of a self-alignment dual-imaging technology, a controller and a chip production system. The method comprises the following steps: performing metal hard mask deposition operation on a target area of a chip; carrying out OX and APF deposition operation on the chip; performing etching stop layer deposition operation on the chip; carrying out photoresist coating and developing operation on the chip; performing CDI and ESL trimming dry etching operation on the chip based on the chip parameters after the etching stop layer deposition operation; performing metal hard mask dry etching and APF removal operation on the chip based on the chip parameters after the metal hard mask deposition operation; and sequentially carrying out ALD spacer cyclic deposition operation, ALD spacer dry etching operation and metal hard mask core belt wet etching operation on the chip to obtain a target chip. Therefore, according to the method, the chip parameters output after corresponding operation are predicted in real time based on the virtual measurement system, and data feedback in the production process and accurate regulation and control of the production parameters can be achieved.

Description

Technical Field

[0001] The present application relates to the field of chip production technology, and in particular to a method for implementing a self-aligned dual imaging technology, a computer-readable storage medium, a controller, and a chip production system. Background Art

[0002] Self-aligned Double Patterning (SADP) is a technology used in semiconductor manufacturing, mainly used to achieve high-precision pattern replication. After completing a photolithography, this technology uses non-photolithography process steps (such as thin film deposition, etching, etc.) to achieve spatial frequency doubling of the photolithography pattern, and finally removes the redundant pattern through another photolithography and etching to obtain the desired pattern.

[0003] In the related technology, the corresponding machine is controlled by preset control parameters to realize the self-aligned dual imaging technology and complete chip production. To ensure the quality of the chip, the machine is tested for chip control before the chip is officially produced, and the chip production is carried out using a machine that meets the standards. However, this technical solution only controls the chip process based on the chip control detection results of the offline test, which is prone to data deviation and causes inaccurate automatic process control. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present application is to propose a method for implementing a self-aligned dual imaging technology, which can realize data feedback during the implementation process based on a virtual measurement system to predict chip parameters output after corresponding operations in real time, and send chip parameters to corresponding production processes to achieve precise control.

[0005] A second object of the present application is to provide a computer-readable storage medium.

[0006] The third objective of the present application is to provide a controller.

[0007] The fourth objective of this application is to provide a chip production system.

[0008] To achieve the above-mentioned purpose, the first embodiment of the present application proposes a method for realizing self-aligned dual imaging technology, which includes: performing a metal hard mask deposition operation on a target area of ​​a chip, and determining chip parameters after the metal hard mask deposition operation based on a corresponding virtual measurement system; performing OX (oxidation) and APF (Advanced Patterning Film) deposition operations on the chip after the metal hard mask deposition operation; performing an etch stop layer deposition operation on the chip after the OX and APF deposition operations, and determining chip parameters after the etch stop layer deposition operation based on a corresponding virtual measurement system; performing photoresist coating and development operations on the chip after the etch stop layer deposition operation; performing CDI (Critical Dimension Inspection) and ESL (Etch Stop) on the chip after the photoresist coating and development operations based on the chip parameters after the etch stop layer deposition operation. The invention discloses a method for performing a metal hard mask dry etching operation on a chip after the CDI and ESL trimming dry etching operations; performing a metal hard mask dry etching and APF removal operation on the chip after the metal hard mask dry etching and APF removal operations based on the chip parameters after the metal hard mask deposition operation; performing an ALD (Atomic Layer Deposition) spacer cyclic deposition operation, an ALD spacer dry etching operation and a metal hard mask core tape wet etching operation in sequence on the chip after the metal hard mask dry etching and APF removal operations to obtain a target chip.

[0009] According to the implementation method of the self-aligned dual imaging technology of the embodiment of the present application, a metal hard mask deposition operation is performed on the target area of ​​the chip, and the chip parameters after the metal hard mask deposition operation are determined based on the corresponding virtual measurement system, OX and APF deposition operations are performed on the chip after the metal hard mask deposition operation, an etch stop layer deposition operation is performed on the chip after the OX and APF deposition operations, and the chip parameters after the etch stop layer deposition operation are determined based on the corresponding virtual measurement system, and photoresist coating and development operations are performed on the chip after the etch stop layer deposition operation; CDI and ESL trimming dry etching operations are performed on the chip after the photoresist coating and development operations based on the chip parameters after the etch stop layer deposition operation, metal hard mask dry etching and APF removal operations are performed on the chip after the CDI and ESL trimming dry etching operations based on the chip parameters after the metal hard mask deposition operation, and ALD spacer cyclic deposition operation, ALD spacer dry etching operation and metal hard mask core strip wet etching operation are sequentially performed on the chip after the metal hard mask dry etching and APF removal operations to obtain the target chip. Therefore, the method can predict the chip parameters output after the corresponding operation in real time based on the virtual measurement system, realize data feedback during the implementation process, and send the chip parameters to the corresponding production process to achieve precise control.

[0010] In addition, the method for implementing the self-aligned dual imaging technology according to the above embodiment of the present application may also have the following additional technical features:

[0011] According to one embodiment of the present application, before performing a metal hard mask deposition operation on a chip, the method for implementing the self-aligned double imaging technology also includes: performing a transfer ARC (Anti-Reflection Coating) deposition operation on the chip, and determining chip parameters after the transfer ARC deposition operation based on a corresponding virtual measurement system; the method for implementing the self-aligned double imaging technology also includes: performing a transfer ARC dry etching operation on the chip after the metal hard mask core strip wet etching operation based on the chip parameters after the transfer ARC deposition operation.

[0012] According to one embodiment of the present application, the implementation method of the self-aligned dual imaging technology also includes: performing a metal hard mask post-core dry etching CDI operation on the chip after the metal hard mask dry etching and APF removal operations, and determining the chip parameters after the metal hard mask post-core dry etching CDI operation based on the corresponding virtual measurement system; performing CDI and ESL trimming dry etching operations on the chip after the photoresist coating and development operations based on the chip parameters after the metal hard mask deposition operation, and also includes: performing CDI and ESL trimming dry etching operations on the chip after the photoresist coating and development operations based on the chip parameters after the etching stop layer deposition operation and the chip parameters after the metal hard mask post-core dry etching CDI operation.

[0013] According to one embodiment of the present application, the method for implementing the self-aligned dual imaging technology also includes: performing an ALD spacer cyclic deposition operation on the chip after the metal hard mask post-core dry etching CDI operation based on chip parameters after the metal hard mask post-core dry etching CDI operation.

[0014] According to one embodiment of the present application, the implementation method of the self-aligned dual imaging technology also includes: performing a post-ALD spacer dry etching CDI operation on the chip after the ALD spacer dry etching operation, and determining the chip parameters after the post-ALD spacer dry etching CDI operation based on the corresponding virtual measurement system; performing an ALD spacer cyclic deposition operation on the chip after the metal hard mask post-core dry etching CDI operation based on the chip parameters after the metal hard mask post-core dry etching CDI operation, and also includes: performing an ALD spacer cyclic deposition operation on the chip after the metal hard mask post-core dry etching CDI operation based on the chip parameters after the metal hard mask post-core dry etching CDI operation and the chip parameters after the post-ALD spacer dry etching CDI operation.

[0015] According to an embodiment of the present application, the method for implementing the self-aligned dual imaging technology further includes: performing an ALD spacing removal operation on the chip after the transfer ARC dry etching operation.

[0016] According to an embodiment of the present application, the method for implementing the self-aligned dual imaging technology further includes: performing a substrate dry etching operation on the chip after the ALD spacing removal operation.

[0017] To achieve the above-mentioned objectives, the second aspect of the present application proposes a computer-readable storage medium on which an implementation program of the self-aligned dual imaging technology is stored. When the implementation program of the self-aligned dual imaging technology is executed by a processor, the implementation method of the self-aligned dual imaging technology is implemented.

[0018] According to the computer-readable storage medium of the embodiment of the present application, the implementation method of the self-aligned dual imaging technology is implemented when the implementation program of the self-aligned dual imaging technology is executed by the processor. Based on the implementation method of the self-aligned dual imaging technology, data feedback and precise control can be realized in the implementation process of the self-aligned dual imaging technology.

[0019] To achieve the above-mentioned objectives, the third aspect embodiment of the present application proposes a controller, including a memory, a processor, and an implementation program of the self-aligned dual imaging technology stored in the memory and executable on the processor. When the processor executes the implementation program of the self-aligned dual imaging technology, the implementation method of the above-mentioned self-aligned dual imaging technology is implemented.

[0020] According to the controller of the embodiment of the present application, when the processor executes the implementation program of the self-aligned dual imaging technology, the implementation method of the above-mentioned self-aligned dual imaging technology is implemented. Based on the implementation method of the above-mentioned self-aligned dual imaging technology, data feedback and precise control can be realized in the implementation process of the self-aligned dual imaging technology.

[0021] To achieve the above objectives, the fourth aspect of the present application proposes a chip production system, including the above controller.

[0022] According to the chip production system of the embodiment of the present application, based on the above-mentioned controller, data feedback and precise regulation in the chip production process can be achieved.

[0023] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A flowchart of a method for implementing the self-aligned dual imaging technology according to an embodiment of the present application;

[0025] Figure 2 It is a flow chart of a method for implementing the self-aligned dual imaging technology according to a specific embodiment of the present application;

[0026] Figure 3 is a block diagram of a controller according to an embodiment of the present application;

[0027] Figure 4 Schematic diagram of a chip production system according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0029] The following describes the implementation method of the self-aligned dual imaging technology proposed in the embodiments of the present application, the computer-readable storage medium, the controller and the chip production system with reference to the accompanying drawings.

[0030] Figure 1 The figure is a flow chart of a method for implementing the self-aligned dual imaging technology according to an embodiment of the present application.

[0031] like Figure 1 As shown, the implementation method of the self-aligned dual imaging technology of the embodiment of the present application may include:

[0032] S1, performing a metal hard mask deposition operation on a target area of ​​a chip, and determining chip parameters after the metal hard mask deposition operation based on a corresponding virtual measurement system;

[0033] S2, performing OX and APF deposition operations on the chip after metal hard mask deposition;

[0034] S3, performing an etch stop layer deposition operation on the chip after the OX and APF deposition operations, and determining chip parameters after the etch stop layer deposition operation based on a corresponding virtual measurement system;

[0035] S4, performing photoresist coating and development operations on the chip after the etching stop layer deposition operation;

[0036] S5, performing CDI and ESL trimming dry etching operations on the chip after the photoresist coating and development operations based on the chip parameters after the etching stop layer deposition operation;

[0037] S6, performing metal hard mask dry etching and APF removal operations on the chip after the CDI and ESL trimming dry etching operations based on chip parameters after the metal hard mask deposition operation;

[0038] S7, sequentially performing an ALD spacer cyclic deposition operation, an ALD spacer dry etching operation, and a metal hard mask core strip wet etching operation on the chip after the metal hard mask dry etching and APF removal operations to obtain a target chip.

[0039] Specifically, in the chip production process, the main function of metal hard mask deposition is to protect sensitive areas and ensure the smooth progress of subsequent processes. Specifically, by depositing a layer of metal mask on the sensitive area (target area), the target area is protected from the influence of subsequent processes, so as to achieve the effects of protecting sensitive areas, improving etching accuracy, enhancing window durability, and promoting dual functions, so as to ensure the high quality and reliability of the chip. At the same time, a virtual measurement system is provided for the production process of performing metal hard mask deposition operation on the target area of ​​the chip, and the chip parameters after the metal hard mask deposition operation are determined based on the virtual measurement system of the production process, such as chip thickness, metal mask size formed by the metal hard mask deposition operation, etc.

[0040] The chip after metal hard mask deposition is then subjected to OX and APF deposition operations, where the main function of oxidation is to form a thin layer of silicon dioxide (SiO2) film on the surface of the wafer. This oxide film acts as an insulator to protect the silicon underneath and serves as a template in subsequent steps. The oxidation process can prevent the wafer from being affected by chemical impurities, prevent leakage current from entering the circuit, prevent diffusion during ion implantation, and prevent the wafer from slipping during etching. The main function of the APF deposition operation is to deposit very thin films on the wafer surface of the chip. These films may be conductive or insulating and are used to build different parts of the circuit.

[0041] Then, the chip after the OX and APF deposition operations is subjected to an etch stop layer deposition operation. The main function of the etch stop layer deposition is to serve as an end point mark for etching, ensuring that etching stops after the etching depth reaches a predetermined depth, thereby protecting the underlying structure from further etching. The etch stop layer is usually made of a material with a higher resistivity, such as silicon nitride (SiN), to prevent copper atoms from diffusing into the underlying layer. At the same time, a virtual measurement system is provided for the process of performing the etch stop layer deposition operation, and the chip parameters after the etch stop layer deposition operation, such as the total thickness of the chip, the deposition thickness of the etch stop layer, etc., are determined based on the virtual measurement system of the process.

[0042] After the etching stop layer deposition operation, the chip is subjected to photoresist coating and development operation to precisely control the structure of the chip surface. The photoresist coating is sprayed on the chip surface, and the required area is exposed by ultraviolet exposure equipment, while the developer dissolves the part not exposed to light, leaving the required graphic structure. Its main functions include protecting the chip surface and precisely controlling the structure. The development operation is to remove the part not exposed to light, specifically, the developer dissolves the photoresist coating not exposed to ultraviolet light, leaving the part exposed to light, and forming the required graphic structure.

[0043] CDI and ESL correction dry etching are performed on the chips after photoresist coating and development operations. CDI is used to measure and detect the minimum feature size on the silicon wafer to ensure that the processing parameters of the chips after photoresist coating and development operations meet the design requirements, and to detect whether there are defects on the wafer surface that affect the yield. ESL trimming dry etching is a trimming technology based on plasma etching. It is mainly used to remove the sidewall damage caused by the etching process and improve the etching accuracy and surface quality. This technology introduces specific chemical or physical conditions during the etching process to selectively treat the sidewalls, thereby reducing sidewall damage and improving device performance and reliability. At the same time, the process can determine the control parameters based on the chip parameters after the etching stop layer deposition operation to improve the operation accuracy. It should be noted that CDI and ESL correction dry etching adjust the production parameters based on the chip parameters after the etching stop layer deposition operation, such as target parameters, control parameters of process tools, etc., to achieve precise control.

[0044] Based on the chip parameters after the metal hard mask deposition operation, the chip after the CDI and ESL correction dry etching operation is subjected to metal hard mask dry etching and APF removal operations. Among them, metal hard mask dry etching is mainly used to remove unnecessary materials to form the required circuit structure. Specifically, dry etching removes materials through plasma or other gas chemical reactions, has high selectivity and precision, and can reduce particle damage while ensuring the etching rate. The APF removal operation is mainly used to remove the protective film on the surface of the chip for subsequent processing steps, so as to carry out the next etching or deposition operation. At the same time, it is achieved through the APF removal technology, which can ensure the complete removal of the protective film, thereby ensuring the quality and accuracy of the subsequent process. It should be noted that the metal hard mask dry etching and APF removal operations adjust the production parameters based on the chip parameters after the metal hard mask deposition operation, such as target parameters, control parameters of process tools, etc., to achieve precise control.

[0045] The chip after the metal hard mask dry etching and APF removal operation is sequentially subjected to ALD spacer cyclic deposition operation, ALD spacer dry etching operation and metal hard mask core strip wet etching operation to obtain the target chip. In addition, the chip after the metal hard mask dry etching and APF removal operation can also be sequentially subjected to metal hard mask back core dry etching CDI operation, ALD spacer cyclic deposition operation, ALD spacer dry etching operation, metal hard mask core strip wet etching operation, transfer ARC dry etching, ALD spacer removal operation and substrate dry etching operation to obtain the target chip that meets the production requirements. Among them, the main function of the ALD spacer cyclic deposition operation is to form a 3D structure with a high aspect ratio and ensure uniform film thickness on complex shapes. The ALD spacer dry etching operation is mainly used to remove unnecessary materials on the surface of the silicon wafer to form precise patterns and structures. In the chip production process, the main function of the metal hard mask in wet etching is to protect the circuit pattern and ensure the accuracy and controllability of the etching process. The metal hard mask core strip wet etching operation is an inorganic thin film material generated by chemical vapor deposition (CVD), which is mainly used to protect the circuit pattern from being damaged during the wet etching process. At the same time, by using a hard mask, the etching depth and width can be more accurately controlled to ensure the size of the circuit pattern.

[0046] It should be noted that the chip parameters output by the corresponding production process determined by the preset virtual measurement system are used for feedback production control. In addition to the above implementation method, they can also be used for feedforward, such as forward feedback to the previous operation, and can also be used to adjust the control parameters of the operation itself, so that the chip parameters output by the current operation reach the target parameter data. Therefore, this embodiment realizes real-time feedback of production data based on the preset virtual measurement system, improves production accuracy, and meets the requirements of precise control. In addition, a corresponding preset measurement system can be set for each operation, which is not limited here.

[0047] In one embodiment of the present application, before performing a metal hard mask deposition operation on a chip, the method for implementing the self-aligned double imaging technology also includes: performing a transfer ARC deposition operation on the chip, and determining chip parameters after the transfer ARC deposition operation based on a corresponding virtual measurement system; the method for implementing the self-aligned double imaging technology also includes: performing a transfer ARC dry etching operation on the chip after a metal hard mask core strip wet etching operation based on the chip parameters after the transfer ARC deposition operation.

[0048] Specifically, the anti-reflection layer formed by the transfer ARC deposition operation absorbs or interferes with the reflected light to reduce the impact of reflection, thereby avoiding problems such as overexposure of the photoresist layer and image distortion, so as to reduce the light reflection effect during the photolithography process, thereby improving the accuracy and resolution of the photolithography. At the same time, in the production process of performing the transfer ARC deposition operation, the chip parameters after the transfer ARC operation, such as the thickness of the anti-reflection layer, are obtained based on its own virtual measurement system, and the product parameters are fed back to the transfer ARC dry etching operation to adjust the production parameters of the transfer ARC dry etching operation. Among them, the transfer ARC dry etching is mainly used to remove materials on the surface of the silicon wafer to form the required circuit pattern.

[0049] In one embodiment of the present application, the implementation method of the self-aligned dual imaging technology also includes: performing a metal hard mask post-core dry etching CDI operation on the chip after the metal hard mask dry etching and APF removal operations, and determining the chip parameters after the metal hard mask post-core dry etching CDI operation based on the corresponding virtual measurement system; performing CDI and ESL trimming dry etching operations on the chip after the photoresist coating and development operations based on the chip parameters after the metal hard mask deposition operation, and also includes: performing CDI and ESL trimming dry etching operations on the chip after the photoresist coating and development operations based on the chip parameters after the etching stop layer deposition operation and the chip parameters after the metal hard mask post-core dry etching CDI operation.

[0050] Specifically, the main purpose of dry etching after the metal hard mask is to define the critical dimension (CD) in the vertical direction to ensure the accuracy and consistency of the circuit pattern. Among them, the main function of the metal hard mask is to provide a hard mask layer in the vertical direction to protect sensitive areas in subsequent process steps. The hard mask has high hardness, high chemical inertness, high melting point and high etching selectivity, which can achieve deep target depth etching at a thin thickness. Dry etching uses plasma or other gas chemical reactions to remove materials with high selectivity and accuracy. Dry etching after the metal hard mask can remove the parts not protected by photolithography to form a circuit pattern. At the same time, in the production process of performing CDI and ESL trimming dry etching operations, the chip parameters after the CDI and ESL trimming dry etching operations, such as etching thickness, total chip thickness, etc., are acquired based on its own virtual measurement system, and the product parameters are fed back to the CDI and ESL trimming dry etching operations. The CDI and ESL trimming dry etching operations adjust the production parameters based on the chip parameters after the etch stop layer deposition operation and the chip parameters after the metal hard mask post-core dry etching CDI operation.

[0051] In one embodiment of the present application, the method for implementing the self-aligned dual imaging technology also includes: performing an ALD spacer cyclic deposition operation on the chip after the metal hard mask post-core dry etching CDI operation based on chip parameters after the metal hard mask post-core dry etching CDI operation.

[0052] That is, the control parameters of the process tool performing the ALD spacer cyclic deposition operation are determined according to the chip parameters output after the metal hard mask post-core dry etching CDI operation, so as to achieve precise control and improve the chip process operation effect.

[0053] In one embodiment of the present application, the implementation method of the self-aligned dual imaging technology also includes: performing a post-ALD spacer dry etching CDI operation on the chip after the ALD spacer dry etching operation, and determining the chip parameters after the post-ALD spacer dry etching CDI operation based on the corresponding virtual measurement system; performing an ALD spacer cyclic deposition operation on the chip after the metal hard mask post-core dry etching CDI operation based on the chip parameters after the metal hard mask post-core dry etching CDI operation, and also includes: performing an ALD spacer cyclic deposition operation on the chip after the metal hard mask post-core dry etching CDI operation based on the chip parameters after the metal hard mask post-core dry etching CDI operation and the chip parameters after the post-ALD spacer dry etching CDI operation.

[0054] Specifically, the main role of post-ALD spacer dry etching CDI operation is to remove unwanted materials and form circuit structures. Among them, dry etching is a key material removal technology that uses the effectiveness of plasma (a highly reactive and energetic gas) to selectively remove materials from the substrate. Plasma generation is induced by applying an electric field to a low-pressure gas, causing the gas molecules to ionize and produce a mixture of ions, electrons, and neutral species. These reactive entities come into contact with the substrate surface and coordinate material removal through the synergistic effect of chemical reactions and physical sputtering.

[0055] The production process performing the ALD spacer cyclic deposition operation receives the chip operation fed forward by the metal hard mask post-core dry etching CDI operation and the product parameters fed back by the metal hard mask post-core dry etching CDI operation to control the process tool performing the ALD spacer cyclic deposition operation to meet the target production requirements.

[0056] In one embodiment of the present application, the method for implementing the self-aligned dual imaging technology further includes: performing an ALD spacing removal operation on the chip after the transfer ARC dry etching operation.

[0057] Specifically, the ALD interval removal operation is mainly to remove unreacted precursor molecules and by-products to ensure the uniformity and quality of the film. The following steps can be taken: Cleaning and pretreatment: Place the substrate to be deposited into the reaction chamber, first perform surface cleaning and pretreatment to ensure that the surface is clean and provide active sites; Gas-phase precursor feeding: Introduce two or more gas-phase precursor molecules into the reaction chamber in sequence. After each feeding, the precursor molecules will be adsorbed on the surface; Cleaning step: After each precursor feeding, purge with an inert gas (such as nitrogen or argon) to remove unreacted precursor molecules and by-products; Reaction step: Introduce a reducing agent or a chemical reaction activation source to promote the chemical reaction of the precursor molecules with the surface to form a thin film. After the reaction is completed, the remaining precursors and by-products are pumped away; Repeating step: Repeat the above steps until the desired film thickness is reached.

[0058] In one embodiment of the present application, the method for implementing the self-aligned dual imaging technology further includes: performing a substrate dry etching operation on the chip after the ALD spacing removal operation.

[0059] Specifically, substrate dry etching operations are used to remove residues left over from the mechanical thinning process to obtain chips with good surface flatness.

[0060] As a specific embodiment of the present application, Figure 2 As shown, the method for implementing the self-aligned dual imaging technology includes the following 15 steps performed in sequence: transfer ARC deposition operation, metal hard mask deposition operation, OX and APF deposition operation, etch stop layer (ESL) deposition operation, photo-coating and development operation, CDI and ESL correction dry etching operation, metal hard mask dry etching and APF removal operation, metal hard mask post-core dry etching CDI operation, ALD spacer cycle deposition operation, ALD spacer dry etching operation, post-ALD spacer dry etching CDI operation, metal hard mask core strip wet etching operation, transfer ARC dry etching operation, ALD spacer removal operation and substrate dry etching operation.

[0061] In addition, the implementation method of the self-aligned dual imaging technology can set up a virtual measurement system in the corresponding operation to obtain data on the chip products produced and output by the corresponding process, so as to provide real-time prediction data for precise adjustment of the automatic process control system. At the same time, according to the process integration requirements, it can provide fast and effective data to supply related upstream and downstream process sites for precise adjustment of the automatic process control system, and timely correct the process parameters for the next chip.

[0062] In summary, according to the implementation method of the self-aligned dual imaging technology of the embodiment of the present application, a metal hard mask deposition operation is performed on the target area of ​​the chip, and the chip parameters after the metal hard mask deposition operation are determined based on the corresponding virtual measurement system, OX and APF deposition operations are performed on the chip after the metal hard mask deposition operation, an etch stop layer deposition operation is performed on the chip after the OX and APF deposition operations, and the chip parameters after the etch stop layer deposition operation are determined based on the corresponding virtual measurement system, and photoresist coating and development operations are performed on the chip after the etch stop layer deposition operation; CDI and ESL trimming dry etching operations are performed on the chip after the photoresist coating and development operations based on the chip parameters after the etch stop layer deposition operation, metal hard mask dry etching and APF removal operations are performed on the chip after the CDI and ESL trimming dry etching operations based on the chip parameters after the metal hard mask deposition operation, and ALD spacer cyclic deposition operation, ALD spacer dry etching operation and metal hard mask core strip wet etching operation are sequentially performed on the chip after the metal hard mask dry etching and APF removal operations to obtain the target chip. Therefore, the method can predict the chip parameters output after the corresponding operation in real time based on the virtual measurement system, realize data feedback during the implementation process, and send the chip parameters to the corresponding production process to achieve precise control.

[0063] Corresponding to the above embodiments, the present application also proposes a computer-readable storage medium.

[0064] The computer-readable storage medium of the embodiment of the present application stores a program for implementing the self-aligned dual imaging technology, and when the program for implementing the self-aligned dual imaging technology is executed by a processor, the method for implementing the self-aligned dual imaging technology is implemented.

[0065] According to the computer-readable storage medium of the embodiment of the present application, the implementation method of the self-aligned dual imaging technology is implemented when the implementation program of the self-aligned dual imaging technology is executed by the processor. Based on the implementation method of the self-aligned dual imaging technology, data feedback and precise control can be realized in the implementation process of the self-aligned dual imaging technology.

[0066] Corresponding to the above embodiments, the present application also proposes a controller.

[0067] like Figure 3 As shown, the controller 100 of the embodiment of the present application includes a memory 110, a processor 120, and an implementation program of the self-aligned dual imaging technology stored in the memory 110 and executable on the processor 120. When the processor 120 executes the implementation program of the self-aligned dual imaging technology, the implementation method of the above-mentioned self-aligned dual imaging technology is implemented.

[0068] According to the controller of the embodiment of the present application, when the processor executes the implementation program of the self-aligned dual imaging technology, the implementation method of the above-mentioned self-aligned dual imaging technology is implemented. Based on the implementation method of the above-mentioned self-aligned dual imaging technology, data feedback and precise control can be realized in the implementation process of the self-aligned dual imaging technology.

[0069] Corresponding to the above embodiments, the present application also proposes a chip production system.

[0070] like Figure 4 As shown, the chip production system 1000 of the embodiment of the present application includes the above-mentioned controller 100.

[0071] According to the chip production system of the embodiment of the present application, based on the above-mentioned controller, data feedback and precise regulation in the chip production process can be achieved.

[0072] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0073] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0074] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0075] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0076] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0077] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for implementing a self-aligned dual imaging technique, characterized in that: The method comprises: Performing a metal hard mask deposition operation on a target area of ​​the chip, and determining chip parameters after the metal hard mask deposition operation based on a corresponding virtual measurement system; Performing OX and APF deposition operations on the chip after metal hard mask deposition; Performing an etch stop layer deposition operation on the chip after the OX and APF deposition operations, and determining chip parameters after the etch stop layer deposition operation based on a corresponding virtual measurement system; Performing photoresist coating and developing operations on the chip after the etch stop layer deposition operation; Based on the chip parameters after the etching stop layer deposition operation, the chip after the photoresist coating and the development operation is subjected to CDI and ESL trimming dry etching operation; Based on the chip parameters after the metal hard mask deposition operation, performing metal hard mask dry etching and APF removal operations on the chip after the CDI and ESL trimming dry etching operations; The chip after the metal hard mask dry etching and APF removal operations is sequentially subjected to ALD spacer cyclic deposition operation, ALD spacer dry etching operation and metal hard mask core strip wet etching operation to obtain a target chip.

2. The method for implementing the self-aligned dual imaging technology according to claim 1, characterized in that: Before performing a metal hard mask deposition operation on the chip, the method further includes: Performing a transfer ARC deposition operation on the chip, and determining chip parameters after the transfer ARC deposition operation based on a corresponding virtual measurement system; The method further comprises: A transfer ARC dry etching operation is performed on the chip after the metal hard mask core strip wet etching operation based on the chip parameters after the transfer ARC deposition operation.

3. The method for implementing the self-aligned dual imaging technology according to claim 1, characterized in that: The method further comprises: Performing a metal hard mask post-core dry etching CDI operation on the chip after the metal hard mask dry etching and APF removal operations, and determining chip parameters after the metal hard mask post-core dry etching CDI operation based on a corresponding virtual measurement system; The chip parameters after the metal hard mask deposition operation are used to perform CDI and ESL trimming dry etching operations on the chip after the photoresist coating and development operations, and further includes: Based on the chip parameters after the etching stop layer deposition operation and the chip parameters after the metal hard mask back core dry etching CDI operation, CDI and ESL trimming dry etching operations are performed on the chip after the photoresist coating and development operations.

4. The method for implementing the self-aligned dual imaging technology according to claim 3, characterized in that: The method further comprises: An ALD spacer cyclic deposition operation is performed on the chip after the metal hard mask post-core dry etching CDI operation based on the chip parameters after the metal hard mask post-core dry etching CDI operation.

5. The method for implementing the self-aligned dual imaging technology according to claim 4, characterized in that: The method further comprises: performing a post ALD spacer dry etch CDI operation on the chip after the ALD spacer dry etch operation, and determining chip parameters after the post ALD spacer dry etch CDI operation based on a corresponding virtual measurement system; The method of performing an ALD spacer cyclic deposition operation on the chip after the metal hard mask back core dry etching CDI operation based on the chip parameters after the metal hard mask back core dry etching CDI operation also includes: Based on the chip parameters after the metal hard mask post core dry etch CDI operation and the chip parameters after the ALD spacer post dry etch CDI operation, an ALD spacer cyclic deposition operation is performed on the chip after the metal hard mask post core dry etch CDI operation.

6. The method for implementing the self-aligned dual imaging technology according to claim 2, characterized in that: The method further comprises: An ALD spacer removal operation is performed on the chip after the transfer ARC dry etching operation.

7. The method for implementing the self-aligned dual imaging technology according to claim 6, characterized in that: The method further comprises: The chip after the ALD spacer removal operation is subjected to substrate dry etching operation.

8. A computer-readable storage medium, characterized in that: An implementation program of the self-aligned dual imaging technology is stored thereon, and when the implementation program of the self-aligned dual imaging technology is executed by a processor, an implementation method of the self-aligned dual imaging technology according to any one of claims 1-7 is implemented.

9. A controller, characterized in that: The invention comprises a memory, a processor and an implementation program of the self-aligned dual imaging technology which is stored in the memory and can be run on the processor. When the processor executes the implementation program of the self-aligned dual imaging technology, the implementation method of the self-aligned dual imaging technology according to any one of claims 1 to 7 is implemented.

10. A chip production system, characterized in that: Comprising a controller according to claim 9.

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