Method for ion beam sputter deposition of metal layers for interconnects in integrated circuits

Abstract

The application discloses an ion beam sputtering deposition method for an integrated circuit interconnection metal layer, and belongs to the technical field of micro-nano manufacturing. In the deposition process of the metal layer, a glancing angle ion beam sputtering (IBS) physical vapor deposition (PVD) mode is adopted, so that high-quality conformal filling of metal films such as molybdenum (Mo) and ruthenium (Ru) in a tens-of-nanometer feature size (CD) and a large aspect ratio (AR) trench structure can be realized, that is, the metal films have excellent hole-filling capacity, can realize 100% sidewall coverage, and can avoid the emergence of adverse modes such as overhang and void. The application introduces the ion beam sputtering technology into the integrated circuit manufacturing process, and provides a new process solution for the deposition and filling of integrated circuit gate metal materials, middle and later interconnection pad liner / barrier / seed layer / conductive metal materials and 3D-DRAM capacitor electrode materials.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of micro-nano manufacturing technology, and particularly relates to a method for ion beam sputtering deposition of an interconnection metal layer of an integrated circuit. BACKGROUND

[0002] Ion beam sputtering (IBS), also known as ion beam deposition (IBD), is a process of depositing a film on a substrate by bombarding a target with a high-energy ion beam so that atoms are sputtered out of the target and deposited on the substrate. IBS can accurately control the film thickness and deposit a very dense high-quality thin film because the ions in the ion beam have the same energy and high collimation.

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. The work of the presently named inventors, to the extent the work is described in this background section as well as in other portions of this disclosure, was not envisioned to provide an enabling or constructive presentation of the prior art ab initio nor to render it obvious to those skilled in the art. SUMMARY

[0004] The technical purpose of the present application is to provide a method for ion beam sputtering deposition of an interconnection metal layer of an integrated circuit. The method comprises: etching a multi-layer structure deposited on a substrate to form a patterned via or trench. The multi-layer structure comprises an anti-reflection layer, a hard mask layer, a dielectric layer, and an etching stop layer in the lithography process. The method further comprises: conformally coating or filling the sidewall of the patterned via or trench with a conductive material; filling the conductive material into the via or trench using the material as a seed layer; and planarizing the material after filling. The specific steps are as follows:

[0005] S1: preparing an etching stop layer in the etching of a dielectric material: based on a single-throw substrate, a certain thickness of SiCN thin film is deposited on the front surface (polished surface) by chemical vapor deposition (CVD) method;

[0006] S2: preparing a dielectric material: a certain thickness of SiCOH dielectric material is deposited on the above-mentioned SiCN thin film by chemical vapor deposition (CVD) method;

[0007] S3: preparing a hard mask layer: a certain thickness of tetraethyl orthosilicate (TEOS) is deposited as a hard mask layer on the above-mentioned SiCOH material by chemical vapor deposition (CVD) method.

[0008] S4: preparing an anti-reflection layer and planarizing the surface: a certain thickness of carbon coating (SOC) is spin-coated on the substrate with the above-mentioned film layer structure; and then a certain thickness of silicon-based anti-reflection layer is spin-coated.

[0009] S5 patterning substrate: spin coating photoresist on the substrate with multi-layer structure as described above; then perform exposure process, after development, get patterned photoresist; then use photoresist as mask, down etching anti-reflective layer by inductively coupled plasma (ICP) etching method; then etch hard mask layer by inductively coupled plasma (ICP) etching method; then in situ ashing and peeling off the remaining photoresist and bottom anti-reflective layer; then etching dielectric material by plasma etching equipment until etching to stop layer; finally, etching stop layer by plasma etching equipment, completing the etching of via / trench.

[0010] S6 ion beam sputtering deposition material; using glancing angle ion beam sputtering (IBS) physical vapor deposition (PVD) method to deposit conductive material into the via / trench obtained in the previous step, wherein the conductive material includes but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), nickel (Ni), iron (Fe), platinum (Pt), ruthenium (Ru) or a combination thereof.

[0011] S7 planarization of metal filled substrate; using chemical mechanical polishing equipment (CMP), polishing and grinding the uneven surface of the filled substrate, planarizing the surface and removing excess material to meet the subsequent process flow.

[0012] As described above, as an integrated circuit interconnection metal layer ion beam sputtering deposition method of the present application, has the following beneficial effects:

[0013] 1. The obtained filling structure has the characteristics of compactness, smooth surface and tight bonding with the substrate;

[0014] 2. No need to worry about product changes caused by stress;

[0015] 3. Can further expand the application scenarios of ion beam sputtering, such as integrated circuit interconnection metal layer deposition. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 The figure shows the step flow diagram of an integrated circuit interconnection metal layer ion beam sputtering deposition method of the present application.

[0017] Figure 2 The cross-sectional view after etching stop layer in the process of etching dielectric material corresponding to step 1.

[0018] Figure 3 The cross-sectional view after preparing dielectric material in step 2.

[0019] Figure 4 The cross-sectional view after preparing hard mask layer in step 3.

[0020] Figure 5 Cross-sectional view of the first anti-reflective layer after step 4.

[0021] Figure 6 Cross-sectional view of the second silicon-based anti-reflective layer after step 4.

[0022] Figure 7 Cross-sectional view of the photoresist after step 5.

[0023] Figure 8 Cross-sectional view of the patterned photoresist after step 5.

[0024] Figure 9 Cross-sectional view of the ion beam sputtering after step 6.

[0025] Figure 10 Cross-sectional view of the ion beam sputtering (IBS) deposition of conductive material or other methods such as electroplating (EP) after step 6.

[0026] Figure 11 Cross-sectional view of the chemical mechanical polishing (CMP) method after step 7.

[0027] Figure 12 SEM cross-sectional view after using ion beam sputtering for trench filling. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail with specific reference felt to the drawings. The skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in the specification. The present application can also be implemented or applied in other different embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the drawings provided in the present embodiment only illustrate the basic concept of the present application in a schematic manner, and only show the relevant part of the process flow in the present application, not all the detailed process steps when the actual process flow is implemented. The actual process flow and related experimental parameters can be changed according to actual needs.

[0029] The technical solution adopted by the present application is an ion beam sputtering deposition method for integrated circuit interconnection metal layer, and the specific steps are as follows:

[0030] Step 1: Prepare a thin film on the substrate as an etching stop layer.

[0031] Step 2, Low-K material is prepared on the thin film as the intermetal dielectric;

[0032] Step 3, the dielectric is deposited on the thin film as a hard mask for covering the dielectric material and transferring the exposure pattern;

[0033] Step 4, SoC is used to planarize the surface;

[0034] Step 5, ARC is used to absorb the lithography reflection light at the interface;

[0035] Step 6, photoresist is used to spin on the sample surface, and the photoresist pattern is prepared by exposure and development. Then, the photoresist pattern is used as a mask to perform multi-step etching of different materials in subsequent processes;

[0036] Step 7, the sidewall insulation layer is deposited;

[0037] Step 8, the barrier layer / adhesion layer / seed layer is deposited, and the specific control parameters are as follows: the substrate temperature is 20°C, the sputtering gas pressure is 0.02 ~1Pa, the Ar gas flow is 20~40sccm, the substrate rotation speed is 10~20r / min, and the film layer is not more than 10nm thick;

[0038] Step 9, the trench and via are filled with metal;

[0039] Step 10, CMP is used to remove excess material and polish the surface.

[0040] Further, in step 1, the substrate is a single-side polished silicon substrate, and the doping type is not limited.

[0041] Further, in step 1, the thin film is a SiCN thin film, which is deposited on the front side (polished surface) of the substrate using a CVD device.

[0042] Further, in step 2, the low dielectric constant material is SiCOH, and the deposition method is CVD.

[0043] Further, in step 3, the hard mask material for covering the dielectric material and transferring the exposure pattern is Tetraethyl Orthosilicate (TEOS), and the deposition method is CVD.

[0044] Further, the anti-reflection coating in step 5 is Si-ARC, SoC, and Developable Bottom Anti-Reflection Coating (DBARC).

[0045] Further, the photoresist in step 6 can be PMMA, SU8, HSQ, ZEP, ARP, UV5, etc.

[0046] Further, the method of depositing the barrier / adhesion / seed layer in step 8 is glancing angle ion beam sputtering physical vapor deposition, ion beam energy is 500-700eV, beam current is 5-10mA, and acceleration voltage is 200-500V ion beam.

[0047] Further, the barrier / adhesion / seed layer material can be molybdenum (Mo), ruthenium (Ru), cobalt (Co), copper (Cu), tungsten (W), tantalum (Ta), titanium (Ti), etc.

[0048] Further, the barrier / adhesion / seed layer has the ability to fill with high quality after deposition, can achieve 100% sidewall coverage after filling in nanometer feature size (CD) and large aspect ratio (AR) trench, good thickness uniformity, and can avoid the problems of overhang and void which will cause failure.

[0049] Further, the nanometer feature size is between about 50nm and about 200nm.

[0050] Further, the large aspect ratio is between about 3 and 10.

[0051] Further, the thickness uniformity is the uniformity of the filled metal thickness of the sidewall and bottom, and the uniformity is ≥0.5%.

[0052] Further, the metal material filling method in step 9 includes physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating (Electroplating), atomic layer deposition (ALD).

[0053] Further, the metal material filling in step 9 has the characteristics of no void, low stress, and low resistivity.

[0054] Further, the polishing liquid in step 10 contains deionized water, oxidizing agent, silicon oxide, cerium oxide, aluminum oxide, PH adjuster, composite abrasive, dispersant.

[0055] Further, the preparation method includes but is not limited to using the process flow mentioned in the above specific steps, and the emphasis is on the technical solutions of "glancing angle ion beam sputtering deposition" and "small CD and large AR trench conformal filling".

[0056] An ion beam sputtering deposition device, the device comprises:

[0057] Ion beam source chamber;

[0058] Vacuum system;

[0059] A control system configured to provide instructions to perform the following operations:

[0060] The control system directs the target material in the ion beam source chamber in the vacuum system to be bombarded by a high-energy ion beam, so that the surface atoms of the target material are detached from the target material and fall on the substrate to form a film.

[0061] The ion beam source has a higher deposition energy, so that the deposited thin film has the characteristics of greater density and fewer defects. The working pressure of the vacuum system can be lower than 1e-2 Pa, and the limit pressure is ≤7.0e-5 Pa.

[0062] The target material and the substrate in the ion beam source chamber have the characteristics of completely neutral surface, and the ion beam can be completely neutralized.

[0063] The ion beam source chamber has the characteristics of being able to independently control the ion energy and the beam current of the ion beam.

[0064] The ion beam source chamber has the characteristics of being able to pre-clean the substrate to improve the adhesion effect of the base material and the thin film material.

[0065] The control system has the characteristics of being able to accurately control each parameter in the ion beam sputtering process.

[0066] Embodiment 1: A method for ion beam sputtering deposition of an integrated circuit interconnection metal layer:

[0067] Step 1, preparing a hard mask layer: on a silicon substrate material, a 200nm thick silicon oxide is deposited as a hard mask layer by chemical vapor deposition (CVD) method.

[0068] Step 2, patterning the substrate: spin coating photoresist on the obtained substrate; then performing exposure process, and after developing, obtaining patterned photoresist; then using the photoresist as a mask, etching the hard mask layer downward by inductively coupled plasma (ICP) etching method; then etching the substrate material by inductively coupled plasma (ICP) etching method to form a trench;

[0069] Step 3, ion beam sputtering deposition of material: after the vacuum is pumped to 1e-4 Pa, the through hole / trench obtained in the previous step is deposited with conductive material by glancing angle ion beam sputtering (IBS) physical vapor deposition (PVD) method, wherein the ion beam energy is 500eV, the argon gas flow is 10sccm, the beam current is 7mA, the substrate rotation speed is 10r / min, the substrate temperature is 15℃, the deposition time is 150s, and the Mo film thickness is 90nm. Figure 12A metal cross-section SEM picture was prepared for Example 1. It can be seen that the sidewall coverage is 100%, the post-filling sidewall is steep, the cross-section is dense, flat, and tightly combined with the substrate without voids and cracks.

[0070] The above-described specific examples, working principles and preparation methods further explain the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is not intended to limit the present application, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An ion beam sputter deposition method for integrated circuit interconnect metal layer separation, characterized by, The specific steps of the method are as follows: Step 1, preparing a thin film on the substrate as an etching stop layer; Step 2, preparing a low dielectric constant material on the thin film as an intermetallic dielectric; Step 3, depositing a thin film on the dielectric as a hard mask for transferring the exposure pattern and covering the dielectric material; Step 4, spin-coating a carbon coating layer to planarize the surface; Step 5, spin-coating an anti-reflection layer to absorb the lithography reflected light at the interface; Step 6, spin-coating a photoresist on the surface of the sample and performing exposure and development to prepare a photoresist pattern; then using the photoresist pattern as a mask to perform a multi-step etching process for different materials; Step 7, depositing a sidewall insulating layer; Step 8, depositing a barrier layer / adhesion layer / seed layer, with specific control parameters: substrate temperature 20℃, sputtering gas pressure 0.02~1Pa, Ar gas flow rate 20~40sccm, substrate rotation speed 10~20r / min, and depositing a film layer with a thickness not exceeding 10nm; Step 9, filling the trench and via with metal; Step 10, removing excess material and polishing the surface using chemical mechanical planarization (CMP).

2. The method of claim 1 wherein the method is used for ion beam sputter deposition of metal layers for interconnects in integrated circuits. In step 1, the substrate is a single-side polished silicon substrate; the thin film is a SiCN thin film, which is deposited on the front side of the substrate, i.e. the polished surface, using a chemical vapor deposition (CVD) device.

3. The method of claim 1 wherein the metal layer is an interconnect metal layer of an integrated circuit. In step 2, the low dielectric constant material is SiCOH, and the deposition method is CVD.

4. The method of claim 1 wherein the metal layer is an interconnect metal layer of an integrated circuit. In step 3, the hard mask material for transferring the exposure pattern and covering the dielectric material is tetraethyl orthosilicate (TEOS), and the deposition method is CVD.

5. The method of claim 1 wherein the metal layer is an interconnect metal layer of an integrated circuit. In step 5, the anti-reflection coating is Si-ARC, SoC, or a developable bottom anti-reflection coating (DBARC).

6. The method of claim 1 wherein the metal layer is an interconnect metal layer of an integrated circuit. In step 6, the photoresist is PMMA, SU8, HSQ, ZEP, ARP, or UV5 photoresist material.

7. The method of claim 1 wherein the metal layer is an interconnect metal layer of an integrated circuit. In step 8, the method for depositing the barrier layer / adhesion layer / seed layer is glancing angle ion beam sputtering physical vapor deposition (PVD), with an ion beam energy of 500~700eV, a beam current of 5~10mA, and an acceleration voltage of 200~500V ion beam; The barrier layer / adhesion layer / seed layer material is molybdenum, ruthenium, cobalt, copper, tungsten, tantalum, titanium metal, or a compound thereof; The deposited barrier layer / adhesion layer / seed layer has high-quality filling capability, enabling 100% sidewall coverage after filling in a nanometer feature size CD and a large aspect ratio AR trench; the nanometer feature size is between 50nm and 200nm; the large aspect ratio is between 3 and 10; the thickness uniformity is the uniformity of the filled metal thickness on the sidewall and the bottom, and the uniformity is ≥0.5%.

8. The method of claim 1 wherein the metal layer is an interconnect metal layer of an integrated circuit. The metal material filling method in step 9 includes physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, and atomic layer deposition.

9. The method of claim 1 wherein the metal layer is an interconnect metal layer of an integrated circuit. The polishing liquid in step 10 includes deionized water, an oxidizing agent, silicon oxide, cerium oxide, aluminum oxide, a PH adjuster, a composite abrasive, and a dispersant.

10. An ion beam sputter deposition apparatus for carrying out the ion beam sputter deposition method of an integrated circuit interconnect metal layer according to any one of claims 1 to 9, characterized in that The device includes: an ion beam source chamber; a vacuum system; a control system configured to provide instructions to perform the following operations; The control system performs high-energy ion beam bombardment on the target material in the ion beam source chamber of the vacuum system, so that the atoms on the surface of the target material are detached from the target material and fall on the substrate to form a film; The working pressure of the vacuum system is less than 1e-2 Pa, and the limit pressure is ≤7.0e-5 Pa; The target material and the substrate in the ion beam source chamber have the characteristics of completely neutral surface, and the ion beam can be completely neutralized; The ion beam source chamber independently controls the ion energy and the ion beam current; The ion beam source chamber can pre-clean the substrate to improve the adhesion between the substrate material and the thin film material; The control system can accurately control each parameter in the ion beam sputtering process.

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