Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors, the semiconductor device comprises a substrate, a semiconductor epitaxial layer, an electrode layer, a source field plate and a conductive block, the semiconductor epitaxial layer comprises a first channel layer, a first barrier layer, a second channel layer and a second barrier layer; the electrode layer comprises a source electrode, a gate electrode and a drain electrode, and the source field plate is arranged on the side, away from the substrate, of the second barrier layer; the conductive block is arranged between the first channel layer and the first barrier layer; first two-dimensional electron gas insulated from the drain electrode is formed between the first channel layer and the first barrier layer, and the conductive block is electrically connected to the source electrode through the first two-dimensional electron gas. Compared with the prior art, the embodiment of the invention can shield electric field lines from epitaxy and a substrate by additionally designing the conductive block, reduce the electric field intensity at the gate pin of the gate electrode, avoid the phenomenon of unstable threshold voltage, improve the stability of the device and reduce the phenomenon of self-oscillation.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] The development direction of GaN-based RF power devices is higher operating frequency and higher power gain, which brings about the problem of insufficient device stability and easy self-excitation, which leads to failure. Specifically, when the RF signal is applied to the gate electrode, the drain electrode voltage will have a certain swing. The change of the drain electrode voltage will cause the electric field strength at the edge of the gate electrode to increase, resulting in unstable threshold voltage and easy self-oscillation. Summary of the invention

[0003] The purpose of the present application is to provide a semiconductor device and a method for preparing the semiconductor device, which can improve the stability of the device and reduce self-oscillation.

[0004] In order to achieve the above object, the present invention is implemented by the following scheme:

[0005] In a first aspect, the present invention provides a semiconductor device, comprising:

[0006] substrate;

[0007] A semiconductor epitaxial layer, the semiconductor epitaxial layer comprising a first channel layer, a first barrier layer, a second channel layer and a second barrier layer stacked in sequence on the substrate;

[0008] an electrode layer, the electrode layer comprising a source electrode, a gate electrode and a drain electrode, the source electrode, the gate electrode and the drain electrode being arranged at intervals on a side of the second barrier layer away from the substrate;

[0009] a source field plate, the source field plate being arranged on a side of the second barrier layer away from the substrate and between the gate electrode and the drain electrode;

[0010] A conductive block, wherein the conductive block is disposed between the first channel layer and the first barrier layer;

[0011] A first two-dimensional electron gas is formed between the first channel layer and the first barrier layer, a second two-dimensional electron gas is formed between the second channel layer and the second barrier layer in the active region of the semiconductor epitaxial layer, the first two-dimensional electron gas is insulated from the drain electrode, and the conductive block is electrically connected to the source electrode through the first two-dimensional electron gas.

[0012] In an optional embodiment, the projection of the conductive block on the substrate is located between the projection of the gate electrode on the substrate and the projection of the drain electrode on the substrate, and the projection of the conductive block on the substrate is spaced apart from the projection of the drain electrode on the substrate.

[0013] In an optional embodiment, a distance L1 between a projection of the conductive block on the substrate and a projection of the drain electrode on the substrate is greater than or equal to half a distance L2 between a projection of the source field plate on the substrate and a projection of the drain electrode on the substrate.

[0014] In an optional embodiment, a distance between a surface of the conductive block on one side away from the substrate and the second channel layer is smaller than a thickness of the first barrier layer;

[0015] A distance between a surface of the conductive block on one side close to the substrate and the substrate is smaller than a thickness of the first channel layer.

[0016] In an optional embodiment, the projection of the conductive block on the substrate is rectangular, curved or sawtooth-shaped.

[0017] In an optional implementation, two ends of the conductive block extend out of the active region, and the first two-dimensional electron gas is located outside the active region.

[0018] In an optional embodiment, the semiconductor epitaxial layer also includes a cap layer arranged on the second barrier layer away from the substrate, the source electrode, the gate electrode and the drain electrode are arranged on a surface of the cap layer away from the substrate, and the source field plate is arranged on a side of the cap layer away from the substrate.

[0019] In an optional implementation, a dielectric layer is further disposed between the source field plate and a surface of the cap layer on a side away from the substrate.

[0020] In an optional embodiment, both the first barrier layer and the second barrier layer are AlGaN layers, and the Al component content of the first barrier layer is less than the Al component content of the second barrier layer.

[0021] In a second aspect, the present invention provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device as described in the above embodiment, and the preparation method comprises:

[0022] providing a carrier;

[0023] sequentially growing a first channel layer, a first barrier layer, a second channel layer and a second barrier layer on the carrier;

[0024] A source electrode, a gate electrode and a drain electrode are arranged at intervals on a side of the second barrier layer away from the carrier;

[0025] A source field plate is disposed on a side of the second barrier layer away from the carrier, wherein the source field plate is located between the gate electrode and the drain electrode;

[0026] peeling off the carrier to expose the first channel layer;

[0027] Implanting ions between the first channel layer and the first barrier layer to form a conductive block;

[0028] bonding the first channel layer to a substrate;

[0029] A first two-dimensional electron gas is formed between the first channel layer and the first barrier layer, a second two-dimensional electron gas is formed between the second channel layer and the second barrier layer in the active region of the semiconductor epitaxial layer, the first two-dimensional electron gas is insulated from the drain electrode, and the conductive block is electrically connected to the source electrode through the first two-dimensional electron gas.

[0030] In an optional embodiment, the step of forming a conductive block by ion implantation between the first channel layer and the first barrier layer includes:

[0031] Performing an ion implantation on the surface of the first channel layer and patterning to form a first two-dimensional electron gas;

[0032] A secondary ion implantation is performed on the surface of the first channel layer to form a conductive block.

[0033] Through the above technical solution, the embodiment of the present invention sets a source field plate after the source electrode, gate electrode and drain electrode are prepared, and forms a conductive block between the first channel layer and the first barrier layer. A first two-dimensional electron gas is formed between the first channel layer and the first barrier layer, and a second two-dimensional electron gas is formed between the second channel layer and the second barrier layer in the active area of ​​the semiconductor epitaxial layer. The first two-dimensional electron gas is insulated from the drain electrode, and the conductive block is electrically connected to the source electrode through the first two-dimensional electron. Compared with the prior art, the embodiment of the present invention can shield the electric field lines originating from the epitaxy and the substrate, reduce the electric field strength at the gate electrode foot, avoid the phenomenon of unstable threshold voltage, improve the stability of the device, and reduce the self-oscillation phenomenon by additionally designing a conductive block.

[0034] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application at a first viewing angle;

[0037] Figure 2 A perspective view of a local structure of a semiconductor device provided by an embodiment of the present application at a second viewing angle;

[0038] Figure 3 A schematic diagram of the structure of a semiconductor device provided for other preferred embodiments of the present application;

[0039] Figures 4 to 9 A process step diagram of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0040] Fig.10 for Fig. 9 A structural diagram of step S6 from another perspective.

[0041] icon:

[0042] 100-semiconductor device; 110-substrate; 120-semiconductor epitaxial layer; 121-first channel layer; 122-first barrier layer; 123-second channel layer; 124-second barrier layer; 125-active region; 126-cap layer; 127-dielectric layer; 130-electrode layer; 131-source electrode; 132-drain electrode; 133-gate electrode; 140-source field plate; 150-conductive block; 160-first two-dimensional electron gas; 170-second two-dimensional electron gas. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0044] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0045] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0046] As disclosed in the background technology, the existing GaN-based RF power devices are unstable and prone to self-excitation in high-frequency and high-gain applications. Specifically, in current devices, a source field plate is usually set, and the source field plate can greatly increase the breakdown voltage of the device. If there is no source field plate, most of the drain electrode electric field lines are directly concentrated to the right side of the gate electrode. Because the gate electrode is very small, it is easy to cause breakdown failure. After adding the source field plate, the potential of the source field plate is zero, and most of the electric field lines will be concentrated on the source field plate, sharing the pressure of the gate electrode. However, the source field plate is located above the 2DEG, so some of the electric field lines passing through the epitaxy and the substrate cannot be effectively shielded, which will also cause the threshold voltage to be unstable and prone to self-oscillation.

[0047] In view of the above situation, the conventional treatment method is to debug through an external matching circuit to adjust the chip impedance to a suitable position, improve device stability, and reduce self-excitation. However, this method requires circuit-level design and debugging outside the chip, resulting in a large circuit area and low integration.

[0048] In addition, existing device substrates are usually fixed substrates, that is, the substrate used for growth and the substrate of the final device are usually of the same type. However, different application scenarios have different requirements for the substrate, which makes it difficult to meet usage needs.

[0049] In order to solve the above problems, an embodiment of the present invention provides a semiconductor device and a method for manufacturing a semiconductor device. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0050] See also Figure 1 and Figure 2The embodiment of the present invention provides a semiconductor device 100, which can improve the stability of the device, reduce self-oscillation, and reduce the difficulty of debugging the matching circuit.

[0051] The semiconductor device 100 provided in an embodiment of the present invention includes a substrate 110, a semiconductor epitaxial layer 120, an electrode layer 130, a source field plate 140 and a conductive block 150. The semiconductor epitaxial layer 120 can be epitaxially grown on the substrate 110, wherein the semiconductor epitaxial layer 120 includes a first channel layer 121, a first barrier layer 122, a second channel layer 123 and a second barrier layer 124 stacked in sequence on the substrate 110; the electrode layer 130 includes a source electrode 131, a gate electrode 133 and a drain electrode 132, and the source electrode 131, the gate electrode 133 and the drain electrode 132 are spaced apart and arranged in the second barrier layer 124 away from the substrate 110. one side; the source field plate 140 is arranged on the side of the second barrier layer 124 away from the substrate 110, and is located between the gate electrode 133 and the drain electrode 132; the conductive block 150 is arranged between the first channel layer 121 and the first barrier layer 122; wherein, a first two-dimensional electron gas 160 is formed between the first channel layer 121 and the first barrier layer 122, and a second two-dimensional electron gas 170 is formed between the second channel layer 123 and the second barrier layer 124 in the active region 125 of the semiconductor epitaxial layer 120, the first two-dimensional electron gas 160 is insulated from the drain electrode 132, and the conductive block 150 is electrically connected to the source electrode 131 through the first two-dimensional electron gas 160.

[0052] It should be noted that, in this embodiment, the second two-dimensional electron gas 170 is used to realize the conventional conductive function of the device, realize the electrical connection between the source electrode 131 and the drain electrode 132, and is controlled by the gate electrode 133. The first two-dimensional electron gas 160 is located below the second two-dimensional electron gas 170, and can realize the electrical connection between the source electrode 131 and the conductive block 150, and the second two-dimensional electron gas 170 is isolated from the drain electrode 132, which can avoid the drain electrode 132 being directly electrically connected to the source electrode 131. The source field plate 140 can greatly improve the breakdown voltage of the device. If there is no source field plate 140, most of the electric field lines of the drain electrode 132 are directly concentrated to the right side of the gate electrode 133. Because the gate electrode 133 is very small, it is easy to cause breakdown failure. After the source field plate 140 is added, the potential of the source field plate 140 is zero, and most of the electric field lines will be concentrated on the source field plate 140, sharing the pressure of the gate electrode 133. However, the source field plate 140 is located above the 2DEG, so some of the electric field lines passing through the epitaxy and the substrate 110 cannot be effectively shielded, which also leads to an unstable threshold voltage and prone to self-oscillation. In this embodiment, the additionally designed conductive block 150 is connected to the source electrode 131 through the first two-dimensional electron gas 160 formed between the first barrier layer 122 and the first channel layer 121, and cooperates with the source field plate 140 to reduce the electric field strength at the gate foot and reduce the influence of the voltage change of the drain electrode 132 on the electric field strength at the edge of the gate electrode 133, thereby improving the stability of the device and reducing self-oscillation.

[0053] It is worth noting that when the device is working, the source electrode 131 is GND, the gate electrode 133 is at a negative voltage, and the drain electrode 132 is at a positive voltage. Therefore, the potential difference between the gate and the drain is the largest, and a peak electric field will be formed at the gate foot. The source field plate 140 of a general device can shield the electric field lines in the upper half of the gate-drain, but cannot shield the electric field lines passing through the epitaxy and the substrate 110. Therefore, by providing a conductive block 150 between the first channel layer 121 and the first barrier layer 122, the electric field lines originating from the semiconductor epitaxial layer 120 and the substrate 110 can be shielded, thereby reducing the electric field strength at the gate foot. In order to avoid the conductive block 150 from being connected to the drain electrode 132, an additional isolation operation is required so that no two-dimensional electron gas is generated between the conductive block 150 and the drain electrode 132.

[0054] In some embodiments, the projection of the conductive block 150 on the substrate 110 is located between the projection of the gate electrode 133 on the substrate 110 and the projection of the drain electrode 132 on the substrate 110, and the projection of the conductive block 150 on the substrate 110 is spaced apart from the projection of the drain electrode 132 on the substrate 110. Specifically, if the conductive block 150 is too close to the drain electrode 132, the breakdown voltage will be reduced, so the conductive block 150 needs to be correspondingly disposed between the interval defined by the gate electrode 133 and the drain electrode 132, and spaced apart from the drain electrode 132.

[0055] Further, the distance L1 between the projection of the conductive block 150 on the substrate 110 and the projection of the drain electrode 132 on the substrate 110 is greater than or equal to half of the distance L2 between the projection of the source field plate 140 on the substrate 110 and the projection of the drain electrode 132 on the substrate 110. Specifically, the side of the projection of the conductive block 150 on the substrate 110 away from the drain electrode 132 does not exceed the side of the projection of the gate electrode 133 on the substrate 110 close to the drain electrode 132, so the distance between the projection of the conductive block 150 and the projection of the drain electrode 132 is greater than or equal to 0. The side of the projection of the conductive block 150 on the substrate 110 close to the drain electrode 132 does not exceed the center line of the projection gap between the source field plate 140 and the drain electrode 132, that is, the distance between the projection of the conductive block 150 and the projection of the drain electrode 132 is greater than half of the projection spacing between the source field plate 140 and the drain electrode 132, which can effectively shield the electric field lines while avoiding reducing the breakdown voltage.

[0056] It should be noted that, in this embodiment, the width of the conductive block 150 may be preferably slightly smaller than the width of the source field plate 140 . If the conductive block 150 is too large, the parasitic effect will increase, while if it is too small, the shielding effect will deteriorate.

[0057] In some embodiments, the distance between the side surface of the conductive block 150 away from the substrate 110 and the second channel layer 123 is less than the thickness of the first barrier layer 122; the distance between the side surface of the conductive block 150 close to the substrate 110 and the substrate 110 is less than the thickness of the first channel layer 121. Specifically, the conductive block 150 needs to extend to the interface between the first channel layer 121 and the second channel layer 123 to ensure connection with the first two-dimensional electron gas 160. In addition, the thickness of the conductive block 150 is less than or equal to the sum of the thickness of the first channel layer 121 and the first barrier layer 122. Preferably, the thickness of the conductive block 150 is equal to the sum of the thickness of the first channel layer 121 and the first barrier layer 122, that is, the two side surfaces of the conductive block 150 are respectively bonded to the second channel layer 123 and the substrate 110, ensuring sufficient thickness to shield the electric field lines.

[0058] In some embodiments, the projection of the conductive block 150 on the substrate 110 is rectangular, curved or sawtooth. Preferably, the conductive block 150 has a three-dimensional shape, which can be a long strip, and the projection on the substrate 110 is a long rectangular strip, so as to achieve better shielding effect.

[0059] In some embodiments, two ends of the conductive block 150 extend out of the active region 125, and the first two-dimensional electron gas 160 is located outside the active region 125. Specifically, the conductive block 150 may be parallel to the gate, and two ends of the conductive block 150 in a direction perpendicular to the gate-drain direction extend out of positions corresponding to the edge of the active region 125. The first two-dimensional electron gas 160 is connected to two ends of the conductive block 150, and may be located outside the active region 125 after patterning, so that no two-dimensional electron gas is generated below the active region 125, thereby minimizing parasitic capacitance caused by the first two-dimensional electron gas 160.

[0060] Of course, in other preferred embodiments of the present invention, the first two-dimensional electron gas 160 may also extend to the active region 125 to achieve a better electrical connection effect.

[0061] In some embodiments, the first barrier layer 122 and the second barrier layer 124 are both AlGaN layers, and the Al component content of the first barrier layer 122 is less than the Al component content of the second barrier layer 124. Specifically, the substrate 110 can be Si, SiC, diamond and other materials, and the first channel layer 121 and the second channel layer 123 can both be GaN layers. Since the second barrier layer 124 is used to form the two-dimensional electron gas required for the actual operation of the device, high density and high mobility will be pursued, while the first barrier layer 122 only needs to be able to form a layer of conductive two-dimensional electron gas, so the Al component content of the second barrier layer 124 is higher, while the Al component content of the first barrier layer 122 is lower. Preferably, the Al component content of the second barrier layer 124 is between 15% and 30%, which can ensure the actual working performance of the device.

[0062] In some embodiments, the semiconductor epitaxial layer 120 further includes a cap layer 126 disposed on the second barrier layer 124 away from the substrate 110, the source electrode 131, the gate electrode 133 and the drain electrode 132 are disposed on a surface of the cap layer 126 away from the substrate 110, and the source field plate 140 is disposed on a side of the cap layer 126 away from the substrate 110. Specifically, the cap layer 126 may be a GaN layer, which is grown on the surface of the second barrier layer 124, the source electrode 131, the gate electrode 133 and the drain electrode 132 are disposed on the surface of the cap layer 126, and the epitaxial layer below the source electrode 131 and the drain electrode 132 is ohmicized by ion implantation or a high-temperature ohmic process, and the specific process may refer to the existing GaN power device.

[0063] See also Figure 3 In some embodiments, a dielectric layer 127 is further disposed between the source field plate 140 and the surface of the cap layer 126 away from the substrate 110. Specifically, the dielectric layer 127 may be SiN, SiO2 or air, and in this embodiment may be a SiN layer, which can protect the epitaxial material.

[0064] The embodiment of the present invention further provides a method for preparing a semiconductor device 100, which is used to prepare the semiconductor device 100 as described above. The method comprises:

[0065] S1: Provide a vector.

[0066] See also Figure 4 Specifically, a carrier for epitaxial growth is first provided, the material of the carrier can be consistent with the subsequent substrate 110 material, or can be other materials that are conducive to epitaxial growth. In addition, the carrier needs to be conducive to the subsequent stripping action.

[0067] S2: sequentially growing a first channel layer 121 , a first barrier layer 122 , a second channel layer 123 and a second barrier layer 124 on a carrier.

[0068] See also Figure 5 Specifically, a first channel layer 121, a first barrier layer 122, a second channel layer 123 and a second barrier layer 124 are sequentially deposited on the surface of the carrier by an epitaxial growth process, such as a chemical vapor deposition or physical vapor deposition process, wherein the first channel layer 121 and the second channel layer 123 are both GaN layers, and the first barrier layer 122 and the second barrier layer 124 can be AlGaN layers. The Al content of the second barrier layer 124 can be higher by changing the process parameters. The purpose of the first barrier layer 122 is to connect the conductive block 150 to the source electrode 131, and the purpose of the second barrier layer 124 is to provide a two-dimensional electron gas connected between the source and the drain.

[0069] After the deposition of the second barrier layer 124 is completed, a cap layer 126 may be deposited on the second barrier layer 124 to complete the epitaxial process.

[0070] S3: The source electrode 131 , the gate electrode 133 and the drain electrode 132 are arranged at intervals on the side of the second barrier layer 124 away from the carrier.

[0071] See also Figure 6 Specifically, ion implantation can be performed first from the surface of the side away from the substrate 110 to destroy the lattice of the non-channel region so that no two-dimensional electron gas is generated in the non-channel region, that is, the active region 125 is delineated and no two-dimensional electron gas is generated outside the active region 125. Then, a gate electrode 133, a source electrode 131 and a drain electrode 132 are arranged on the surface of the cap layer 126, all of which are metal electrodes.

[0072] S4: a source field plate 140 is disposed on a side of the second barrier layer 124 away from the carrier.

[0073] See also Figure 7, wherein the source field plate 140 is located between the gate electrode 133 and the drain electrode 132. After the electrode layer 130 is prepared, the insulating dielectric layer 127 can be covered, and then the source field plate 140 is set, and finally the insulating dielectric material is covered again to complete the front process of the device.

[0074] S5 : peeling off the carrier to expose the first channel layer 121 .

[0075] See also Figure 8 Specifically, the carrier is peeled off through a peeling process. Of course, the carrier can also be removed by grinding.

[0076] S6 : forming a conductive block 150 by ion implantation between the first channel layer 121 and the first barrier layer 122 .

[0077] See also Fig. 9 and Fig.10 Specifically, an ion implantation is performed from the surface originally in contact with the substrate 110, that is, the surface exposed by the first channel layer 121, so that no two-dimensional electron gas is generated in the active region 125 between the first channel layer 121 and the first barrier layer 122, and the first two-dimensional electron gas 160 is patterned at the same time, so that the first two-dimensional electron gas 160 can be connected to the source and isolated from the drain (wherein the patterning is to define the region with or without two-dimensional electron gas). Then, a secondary ion implantation, that is, a large dose of ion implantation, is performed on the surface of the first channel layer 121 to form a conductive block 150, which can be connected to the source through the first two-dimensional electron gas 160.

[0078] S7 : bonding the first channel layer 121 to the substrate 110 .

[0079] Please continue to see Figure 1 Specifically, the epitaxial structure can be transplanted onto different substrate 110 materials, such as Si, SiC, diamond, etc., by bonding as needed.

[0080] A first two-dimensional electron gas 160 is formed between the first channel layer 121 and the first barrier layer 122 , a second two-dimensional electron gas 170 is formed between the second channel layer 123 and the second barrier layer 124 in the active region 125 of the semiconductor epitaxial layer 120 , the first two-dimensional electron gas 160 is insulated from the drain electrode 132 , and the conductive block 150 is electrically connected to the source electrode 131 through the first two-dimensional electron gas 160 .

[0081] Through the above technical solution, after the source electrode 131, the gate electrode 133 and the drain electrode 132 are prepared, the source field plate 140 is arranged in the embodiment of the present invention, and the conductive block 150 is formed between the first channel layer 121 and the first barrier layer 122. Among them, a first two-dimensional electron gas 160 is formed between the first channel layer 121 and the first barrier layer 122, and a second two-dimensional electron gas 170 is formed between the second channel layer 123 and the second barrier layer 124 in the active region 125 of the semiconductor epitaxial layer 120. The first two-dimensional electron gas 160 is insulated from the drain electrode 132, and the conductive block 150 is electrically connected to the source electrode 131 through the first two-dimensional electron. Compared with the prior art, the embodiment of the present invention can shield the electric field lines originating from the epitaxy and the substrate 110, reduce the electric field strength at the gate foot of the gate electrode 133, avoid the phenomenon of unstable threshold voltage, improve the stability of the device, and reduce the self-oscillation phenomenon by additionally designing the conductive block 150.

[0082] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: A substrate (110); A semiconductor epitaxial layer (120), the semiconductor epitaxial layer (120) comprising a first channel layer (121), a first barrier layer (122), a second channel layer (123) and a second barrier layer (124) which are sequentially stacked on the substrate (110); an electrode layer (130), the electrode layer (130) comprising a source electrode (131), a gate electrode (133) and a drain electrode (132), the source electrode (131), the gate electrode (133) and the drain electrode (132) being arranged at intervals on a side of the second barrier layer (124) away from the substrate (110); A source field plate (140), the source field plate (140) being arranged on a side of the second barrier layer (124) away from the substrate (110) and located between the gate electrode (133) and the drain electrode (132); A conductive block (150), the conductive block (150) being arranged between the first channel layer (121) and the first barrier layer (122); A first two-dimensional electron gas (160) is formed between the first channel layer (121) and the first barrier layer (122), a second two-dimensional electron gas (170) is formed between the second channel layer (123) and the second barrier layer (124) in the active region (125) of the semiconductor epitaxial layer (120), the first two-dimensional electron gas (160) is insulated from the drain electrode (132), and the conductive block (150) is electrically connected to the source electrode (131) through the first two-dimensional electron gas (160).

2. The semiconductor device according to claim 1, wherein: The projection of the conductive block (150) on the substrate (110) is located between the projection of the gate electrode (133) on the substrate (110) and the projection of the drain electrode (132) on the substrate (110), and the projection of the conductive block (150) on the substrate (110) is spaced apart from the projection of the drain electrode (132) on the substrate (110).

3. The semiconductor device according to claim 2, characterized in that A distance L1 between a projection of the conductive block (150) on the substrate (110) and a projection of the drain electrode (132) on the substrate (110) is greater than or equal to half a distance L2 between a projection of the source field plate (140) on the substrate (110) and a projection of the drain electrode (132) on the substrate (110).

4. The semiconductor device according to claim 1, wherein: The distance between a surface of the conductive block (150) on one side away from the substrate (110) and the second channel layer (123) is smaller than the thickness of the first barrier layer (122); The distance between a surface of one side of the conductive block (150) close to the substrate (110) and the substrate (110) is smaller than the thickness of the first channel layer (121).

5. The semiconductor device according to claim 1, wherein: The projection of the conductive block (150) on the substrate (110) is rectangular, curved or sawtooth-shaped.

6. The semiconductor device according to claim 1, wherein: Two ends of the conductive block (150) extend out of the active region (125), and the first two-dimensional electron gas (160) is located outside the active region (125).

7. The semiconductor device according to claim 1, wherein: The semiconductor epitaxial layer (120) further comprises a cap layer (126) arranged on the second barrier layer (124) away from the substrate (110); the source electrode (131), the gate electrode (133) and the drain electrode (132) are arranged on a side surface of the cap layer (126) away from the substrate (110); the source field plate (140) is arranged on a side of the cap layer (126) away from the substrate (110); and a dielectric layer (127) is further arranged between the source field plate (140) and a side surface of the cap layer (126) away from the substrate (110).

8. The semiconductor device according to claim 1, wherein: The first barrier layer (122) and the second barrier layer (124) are both AlGaN layers, and the Al component content of the first barrier layer (122) is less than the Al component content of the second barrier layer (124).

9. A method for preparing a semiconductor device, for preparing the semiconductor device as claimed in claim 1, characterized in that: The preparation method comprises: providing a carrier; Growing a first channel layer (121), a first barrier layer (122), a second channel layer (123) and a second barrier layer (124) in sequence on the carrier; A source electrode (131), a gate electrode (133) and a drain electrode (132) are arranged at intervals on a side of the second barrier layer (124) away from the carrier; A source field plate (140) is arranged on a side of the second barrier layer (124) away from the carrier, wherein the source field plate (140) is located between the gate electrode (133) and the drain electrode (132); peeling off the carrier to expose the first channel layer (121); Ion implantation is performed between the first channel layer (121) and the first barrier layer (122) to form a conductive block (150); Bonding the first channel layer (121) to a substrate (110); A first two-dimensional electron gas (160) is formed between the first channel layer (121) and the first barrier layer (122), a second two-dimensional electron gas (170) is formed between the second channel layer (123) and the second barrier layer (124) in the active region (125) of the semiconductor epitaxial layer (120), the first two-dimensional electron gas (160) is insulated from the drain electrode (132), and the conductive block (150) is electrically connected to the source electrode (131) through the first two-dimensional electron gas (160).

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The step of forming a conductive block (150) by ion implantation between the first channel layer (121) and the first barrier layer (122) comprises: Performing an ion implantation on the surface of the first channel layer (121) and patterning a first two-dimensional electron gas (160); Secondary ion implantation is performed on the surface of the first channel layer (121) to form a conductive block (150).

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