Circuit for increasing common-mode transient immunity of edge modulation and demodulation digital isolator

Abstract

The invention discloses a circuit for increasing common-mode transient immunity of a digital isolator for edge modulation and demodulation. The circuit comprises a transmitting end TX and a receiving end RX, the transmitting end TX comprises a negative common-mode voltage change rate detection circuit, the negative common-mode voltage change rate detection circuit is composed of a transistor MN11, a transistor MN12, a transistor MN13, a transistor MN14 and a fifth resistor R5, and the output ends of the transistor MN11 and the transistor MN12 are connected with the control ends of the transistor MN13 and the transistor MN14. The output end of the transistor MN13, the output end of the transistor MN14 and the fifth resistor R5 are connected with the grounding end GND1 of the transmitting end TX; the receiving end RX comprises a latch, a fully differential amplifier, an envelope comparator and a forward common-mode voltage change rate detection circuit; the forward common-mode voltage change rate detection circuit is composed of a transistor MN5, a transistor MN6, a transistor MN7, a transistor MN8 and a sixth resistor R6, the control ends of the transistor MN5 and the transistor MN6 are connected with the output end of the transmitting end TX, and the output ends of the transistor MN5 and the transistor MN6 are connected with the control ends of the transistor MN7 and the transistor MN8. And the output end of the transistor MN7, the output end of the transistor MN8 and the sixth resistor R6 are connected with the grounding end GND2 of the receiving end RX.

Description

Technical Field

[0001] The present application belongs to the technical field of edge modulation and demodulation digital isolators, and in particular refers to a circuit for increasing the common-mode transient immunity of edge modulation and demodulation digital isolators. Background Art

[0002] Since there are two completely independent grounds inside the capacitively isolated digital isolator, the voltage difference between the two grounds changes transiently in actual applications. If the transient change rate of the voltage difference between the two grounds exceeds a certain limit value, it will destroy the normal transmission of digital signals. This limit value is the common-mode transient immunity of the digital isolator, which is an important performance parameter of digital isolator products.

[0003] Common-mode transient immunity indicates the ability of the isolation circuit to suppress the high-speed transient signal from passing through the isolation layer and destroying the output state, and also reflects the sensitivity of the isolation circuit to the interference of fast transient signals. A higher common-mode transient immunity index means that the isolation circuit or isolation device can ensure that the output (OUT) does not have errors when the common-mode voltage with a higher rise or fall rate impacts the isolation barrier under its limited test conditions. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the present application provides a circuit for increasing the common-mode transient immunity of an edge-modulated digital isolator, which can improve the common-mode transient immunity of the digital isolator.

[0005] The present invention provides a circuit for increasing the common-mode transient immunity of an edge-modulated digital isolator, the circuit for increasing the common-mode transient immunity of an edge-modulated digital isolator comprising: a transmitting end TX and a receiving end RX, the transmitting end TX is connected to the receiving end RX, the transmitting end TX sends a voltage signal to the receiving end RX;

[0006] Wherein, the transmitting end TX includes a negative common-mode voltage change rate detection circuit, which is composed of a transistor MN11, a transistor MN12, a transistor MN13, a transistor MN14 and a fifth resistor R5, the output ends of the transistor MN11 and the transistor MN12 are connected to the control ends of the transistor MN13 and the transistor MN14, and the output end of the transistor MN13, the output end of the transistor MN14 and the fifth resistor R5 are connected to the ground end GND1 of the transmitting end TX;

[0007] The receiving end RX includes a latch, a fully differential amplifier, an envelope comparator and a positive common mode voltage change rate detection circuit;

[0008] The latch latches the voltage signal received by the receiving end RX; the input end of the fully differential amplifier is connected to the output end of the latch, and the fully differential amplifier amplifies the voltage signal latched by the latch; the input end of the envelope comparator is connected to the output end of the fully differential amplifier, and the envelope comparator compares the output voltage of the fully differential amplifier and outputs a corresponding high level signal or a low level signal;

[0009] The forward common-mode voltage change rate detection circuit is composed of a transistor MN5, a transistor MN6, a transistor MN7, a transistor MN8 and a sixth resistor R6, the control ends of the transistor MN5 and the transistor MN6 are connected to the output end of the transmitting end TX, the output ends of the transistor MN5 and the transistor MN6 are connected to the control ends of the transistor MN7 and the transistor MN8, and the output end of the transistor MN7, the output end of the transistor MN8 and the sixth resistor R6 are connected to the ground end GND2 of the receiving end RX.

[0010] According to the circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator provided in the present application, the transistor MN5, the transistor MN6, the transistor MN7, the transistor MN8, the transistor MN11, the transistor MN12, the transistor MN13 and the transistor MN14 are all NMOS transistors.

[0011] According to the circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator provided in the present application, the input voltage VDD1 of the transmitter TX and the ground terminal GND1 and the input voltage VDD2 of the receiver RX and the ground terminal GND2 are different.

[0012] According to the circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator provided in the present application, the transmitting end TX also includes a drive output unit; the drive output unit is composed of a transistor MP1, a transistor MP2, a transistor MN9 and a transistor MN10;

[0013] The gate of the transistor MP1 is connected to the upper circuit, the source of the transistor MP1 is connected to the input voltage VDD1 of the transmitting terminal TX, and the drain of the transistor MP1 outputs the voltage INA_TX;

[0014] The gate of the transistor MP2 is connected to the upper circuit, the source of the transistor MP2 is connected to the input voltage VDD1 of the transmitting terminal TX, and the drain of the transistor MP2 outputs the voltage INB_TX;

[0015] The gate of the transistor MN9 is connected to the upper circuit, the source of the transistor MN9 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN9 is connected to the drain of the transistor MP1;

[0016] The gate of the transistor MN10 is connected to the upper circuit, the source of the transistor MN10 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN10 is connected to the drain of the transistor MP2;

[0017] The transistor MP1 and the transistor MP2 are PMOS transistors; the transistor MN9 and the transistor MN10 are NMOS transistors.

[0018] According to the circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator provided by the present application, in the negative common-mode voltage change rate detection circuit, the gate of the transistor MN11 is connected to the output voltage INA_TX, the source of the transistor MN11 is connected to one end of the fifth resistor R5, and the drain of the transistor MN11 is connected to the input voltage VDD1 of the transmitting end TX;

[0019] The gate of the transistor MN12 is connected to the output voltage INB_TX, the source of the transistor MN12 is connected to one end of the fifth resistor R5, and the drain of the transistor MN12 is connected to the input voltage VDD1 of the transmitting end TX;

[0020] The other end of the fifth resistor R5 is connected to the ground terminal GND1 of the transmitting terminal TX;

[0021] The connection node between the fifth resistor R5 and the source of the transistor MN11 and the source of the transistor MN12 is connected to the gates of the transistor MN13 and the transistor MN14;

[0022] The source of the transistor MN13 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN13 is connected to the output voltage INA_TX;

[0023] The source of the transistor MN14 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN14 is connected to the output voltage INB_TX.

[0024] According to the circuit for increasing the common-mode transient immunity of the edge modulation and demodulation digital isolator provided in the present application, a first high-voltage resistant capacitor C1 and a second high-voltage resistant capacitor C2 are further connected between the transmitting end TX and the receiving end RX;

[0025] One end of the first high-voltage-resistant capacitor C1 is connected to the output voltage INA_TX of the transmitting end TX, and the other end of the first high-voltage-resistant capacitor C1 is connected to the first input end of the receiving end RX and inputs the voltage INA_RX;

[0026] One end of the second high voltage resistant capacitor C2 is connected to the output voltage INB_TX of the transmitting end TX, and the other end of the second high voltage resistant capacitor C2 is connected to the second input end of the receiving end RX and inputs the voltage INB_RX.

[0027] According to the circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator provided in the present application, in the forward common-mode voltage change rate detection circuit, the gate of the transistor MN5 is connected to the input voltage INA_RX, the source of the transistor MN5 is connected to one end of the sixth resistor R6, and the drain of the transistor MN5 is connected to the input voltage VDD2 of the receiving end RX;

[0028] The gate of the transistor MN6 is connected to the input voltage INB_RX, the source of the transistor MN6 is connected to one end of the sixth resistor R6, and the drain of the transistor MN6 is connected to the input voltage VDD2 of the receiving end RX;

[0029] The other end of the sixth resistor R6 is connected to the ground terminal GND2 of the receiving terminal RX;

[0030] The connection node between the sixth resistor R6 and the source of the transistor MN5 and the source of the transistor MN6 is connected to the gates of the transistor MN7 and the transistor MN8;

[0031] The source of the transistor MN7 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN7 is connected to the input voltage INA_RX;

[0032] The source of the transistor MN8 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN8 is connected to the input voltage INB_RX.

[0033] According to the circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator provided in the present application, the latch is composed of a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4;

[0034] The gate of the transistor MN1 is connected to the input voltage INB_RX, the source of the transistor MN1 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN1 is connected to one end of the fourth resistor R4 and one end of the first resistor R1;

[0035] The gate of the transistor MN2 is connected to the input voltage INA_RX, the source of the transistor MN2 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN2 is connected to one end of the third resistor R3 and one end of the second resistor R2;

[0036] The other end of the first resistor R1 is connected to the other end of the second resistor R2, the electrical node where the first resistor R1 and the second resistor R2 are connected is also connected to the input voltage VDD2 of the receiving end RX, the other end of the third resistor R3 is connected to the gate of the transistor MN1, and the other end of the fourth resistor R4 is connected to the gate of the transistor MN2;

[0037] The output signal of the connection node between the drain of the transistor MN1 and the first resistor R1 is INN_AMP, and the output signal of the connection node between the drain of the transistor MN2 and the second resistor R2 is INP_AMP;

[0038] The gate of the transistor MN3 is connected to the output signal INP_AMP, the source of the transistor MN3 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN4;

[0039] The gate of the transistor MN4 is connected to the output signal INN_AMP, the source of the transistor MN4 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN3;

[0040] The transistor MN1 , the transistor MN2 , the transistor MN3 , and the transistor MN4 are all NMOS transistors.

[0041] According to the circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator provided in the present application, the first input end of the fully differential amplifier is connected to the output signal INP_AMP, and the second input end of the fully differential amplifier is connected to the output signal INN_AMP.

[0042] According to the circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator provided in the present application, the first input end of the envelope comparator is connected to the first output end of the fully differential amplifier, the second input end of the envelope comparator is connected to the second output end of the fully differential amplifier, and the output end of the envelope comparator outputs the output signal of the edge-modulated digital isolator.

[0043] The beneficial effects of the present invention are as follows: the present application provides a circuit for increasing the common-mode transient immunity of an edge-modulated digital isolator, wherein a group of positive common-mode voltage change rate detection circuits and a group of negative common-mode voltage change rate detection circuits are added to the transmitting end TX and the receiving end RX, respectively. When the change rate of the common-mode voltage or common-mode current in the edge-modulated digital isolator circuit exceeds a set threshold value, the positive common-mode voltage change rate detection circuit or the negative common-mode voltage change rate detection circuit is turned on, thereby discharging the common-mode current, reducing the impact on the input signal of the amplifier of the receiving end RX, or reducing the impact on the driver of the transmitting end TX, thereby ensuring normal signal transmission. Furthermore, since the response speed of the positive common-mode voltage change rate detection circuit and the negative common-mode voltage change rate detection circuit is much higher than that of the modulation and demodulation path, during the change of the common-mode voltage or the common-mode current in the circuit, the output signal of the positive common-mode voltage change rate detection circuit or the negative common-mode voltage change rate detection circuit takes effect first, thereby preventing the output of the edge-modulated digital isolator circuit from changing, maintaining the output of the edge-modulated digital isolator circuit unchanged, and effectively improving the common-mode transient immunity of the digital isolator. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0045] Figure 1 The present application provides a circuit for increasing the common-mode transient immunity of an edge-modulated digital isolator. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0047] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0048] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0049] The present invention will now be further described with reference to the accompanying drawings and specific implementation methods.

[0050] Figure 1 The present application provides a circuit for increasing the common-mode transient immunity of an edge-modulated digital isolator.

[0051] like Figure 1 As shown, the circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator provided in the present application mainly includes a transmitter TX and a receiver RX, wherein the transmitter TX is connected to the receiver RX, and the transmitter TX sends a voltage signal to the receiver RX. The receiver RX processes the voltage signal sent by the transmitter TX and outputs a corresponding output (VOUT).

[0052] Among them, the transmitting end TX includes a negative common-mode voltage change rate detection circuit, which is composed of a transistor MN11, a transistor MN12, a transistor MN13, a transistor MN14 and a fifth resistor R5. The output ends of the transistor MN11 and the transistor MN12 are connected to the control ends of the transistor MN13 and the transistor MN14, and the output end of the transistor MN13, the output end of the transistor MN14 and the fifth resistor R5 are connected to the ground end GND1 of the transmitting end TX.

[0053] The receiving end RX includes a latch, a fully differential amplifier AMP, an envelope comparator COMP and a positive common mode voltage change rate detection circuit.

[0054] The latch latches the voltage signal received by the receiving end RX. The input end of the fully differential amplifier AMP is connected to the output end of the latch, and the fully differential amplifier AMP amplifies the voltage signal latched by the latch. The input end of the envelope comparator COMP is connected to the output end of the fully differential amplifier AMP, and the envelope comparator COMP compares the output voltage of the fully differential amplifier AMP and outputs a corresponding high level signal or a low level signal.

[0055] The forward common-mode voltage change rate detection circuit is composed of a transistor MN5, a transistor MN6, a transistor MN7, a transistor MN8 and a sixth resistor R6, the control ends of the transistor MN5 and the transistor MN6 are connected to the output end of the transmitting end TX, the output ends of the transistor MN5 and the transistor MN6 are connected to the control ends of the transistor MN7 and the transistor MN8, and the output end of the transistor MN7, the output end of the transistor MN8 and the sixth resistor R6 are connected to the ground end GND2 of the receiving end RX.

[0056] The input voltage VDD1 of the transmitter TX and the ground terminal GND1 are different from the input voltage VDD2 of the receiver RX and the ground terminal GND2, that is, the transmitter TX belongs to the VDD1-GND1 voltage domain, and the receiver RX belongs to the VDD2-GND2 voltage domain.

[0057] When a high common-mode voltage change rate or common-mode current change rate appears in the circuit of the edge-modulated digital isolator, including when the ground terminal GND1 of the transmitting end TX suddenly increases relative to the ground terminal GND2 of the receiving end RX, a positive common-mode voltage change occurs; or when the ground terminal GND1 of the transmitting end TX suddenly decreases relative to the ground terminal GND2 of the receiving end RX, a negative common-mode voltage change occurs; because the response speed of the positive common-mode voltage change rate detection circuit and the negative common-mode voltage change rate detection circuit is much higher than the response speed of the modulation and demodulation main path, the output signal of the positive common-mode voltage change rate detection circuit or the negative common-mode voltage change rate detection circuit takes effect first, thereby preventing the output of the edge-modulated digital isolator circuit from changing and maintaining the output (VOUT) of the edge-modulated digital isolator circuit unchanged.

[0058] In this embodiment, the transistor MN5 , the transistor MN6 , the transistor MN7 , the transistor MN8 , the transistor MN11 , the transistor MN12 , the transistor MN13 and the transistor MN14 are all NMOS transistors.

[0059] like Figure 1 As shown, the transmitting end TX also includes a driving output unit; the driving output unit is composed of a transistor MP1, a transistor MP2, a transistor MN9 and a transistor MN10.

[0060] The gate of the transistor MP1 is connected to an upper circuit, the source of the transistor MP1 is connected to an input voltage VDD1 of the transmitting terminal TX, and the drain of the transistor MP1 outputs a voltage INA_TX.

[0061] The gate of the transistor MP2 is connected to an upper circuit, the source of the transistor MP2 is connected to the input voltage VDD1 of the transmitting end TX, and the drain of the transistor MP2 outputs a voltage INB_TX.

[0062] The gate of the transistor MN9 is connected to the upper circuit, the source of the transistor MN9 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN9 is connected to the drain of the transistor MP1.

[0063] The gate of the transistor MN10 is connected to the upper circuit, the source of the transistor MN10 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN10 is connected to the drain of the transistor MP2.

[0064] The transistor MP1 and the transistor MP2 are PMOS transistors; the transistor MN9 and the transistor MN10 are NMOS transistors.

[0065] In the negative common-mode voltage change rate detection circuit, the gate of the transistor MN11 is connected to the output voltage INA_TX, the source of the transistor MN11 is connected to one end of the fifth resistor R5, and the drain of the transistor MN11 is connected to the input voltage VDD1 of the transmitter TX.

[0066] The gate of the transistor MN12 is connected to the output voltage INB_TX, the source of the transistor MN12 is connected to one end of the fifth resistor R5, and the drain of the transistor MN12 is connected to the input voltage VDD1 of the transmitting end TX.

[0067] The other end of the fifth resistor R5 is connected to the ground terminal GND1 of the transmitting terminal TX.

[0068] The connection node between the fifth resistor R5 and the source of the transistor MN11 and the source of the transistor MN12 is connected to the gates of the transistor MN13 and the transistor MN14.

[0069] The source of the transistor MN13 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN13 is connected to the output voltage INA_TX.

[0070] The source of the transistor MN14 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN14 is connected to the output voltage INB_TX.

[0071] like Figure 1 As shown, a first high voltage resistant capacitor C1 and a second high voltage resistant capacitor C2 are also connected between the transmitting end TX and the receiving end RX. One end of the first high voltage resistant capacitor C1 is connected to the output voltage INA_TX of the transmitting end TX, and the other end of the first high voltage resistant capacitor C1 is connected to the first input end of the receiving end RX and inputs the voltage INA_RX.

[0072] One end of the second high voltage resistant capacitor C2 is connected to the output voltage INB_TX of the transmitting end TX, and the other end of the second high voltage resistant capacitor C2 is connected to the second input end of the receiving end RX and inputs the voltage INB_RX.

[0073] The voltage difference between the ground terminal GND1 of the transmitting terminal TX and the ground terminal GND2 of the receiving terminal RX is mainly applied to the first high voltage capacitor C1 and the second high voltage capacitor C2. The driving output unit is mainly used to drive the first high voltage capacitor C1 and the second high voltage capacitor C2.

[0074] Specifically, in the forward common-mode voltage change rate detection circuit, the gate of the transistor MN5 is connected to the input voltage INA_RX, the source of the transistor MN5 is connected to one end of the sixth resistor R6, and the drain of the transistor MN5 is connected to the input voltage VDD2 of the receiving end RX.

[0075] The gate of the transistor MN6 is connected to the input voltage INB_RX, the source of the transistor MN6 is connected to one end of the sixth resistor R6, and the drain of the transistor MN6 is connected to the input voltage VDD2 of the receiving end RX.

[0076] The other end of the sixth resistor R6 is connected to the ground terminal GND2 of the receiving terminal RX.

[0077] The connection node between the sixth resistor R6 and the source of the transistor MN5 and the source of the transistor MN6 is connected to the gates of the transistor MN7 and the transistor MN8.

[0078] The source of the transistor MN7 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN7 is connected to the input voltage INA_RX.

[0079] The source of the transistor MN8 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN8 is connected to the input voltage INB_RX.

[0080] like Figure 1 As shown, the latch is composed of a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4;

[0081] The gate of the transistor MN1 is connected to the input voltage INB_RX, the source of the transistor MN1 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN1 is connected to one end of the fourth resistor R4 and one end of the first resistor R1;

[0082] The gate of the transistor MN2 is connected to the input voltage INA_RX, the source of the transistor MN2 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN2 is connected to one end of the third resistor R3 and one end of the second resistor R2;

[0083] The other end of the first resistor R1 is connected to the other end of the second resistor R2, the electrical node where the first resistor R1 and the second resistor R2 are connected is also connected to the input voltage VDD2 of the receiving end RX, the other end of the third resistor R3 is connected to the gate of the transistor MN1, and the other end of the fourth resistor R4 is connected to the gate of the transistor MN2;

[0084] The output signal of the connection node between the drain of the transistor MN1 and the first resistor R1 is INN_AMP, and the output signal of the connection node between the drain of the transistor MN2 and the second resistor R2 is INP_AMP;

[0085] The gate of the transistor MN3 is connected to the output signal INP_AMP, the source of the transistor MN3 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN4;

[0086] The gate of the transistor MN4 is connected to the output signal INN_AMP, the source of the transistor MN4 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN3;

[0087] The current flowing through the source of the transistor MN1 and the current flowing through the source of the transistor MN2 together constitute a current source I1, and the current source I1 flows into the ground terminal GND2 of the receiving terminal RX. The current flowing through the source of the transistor MN3 and the current flowing through the source of the transistor MN4 together constitute a current source I2, and the current source I2 flows into the ground terminal GND2 of the receiving terminal RX.

[0088] In this embodiment, the transistor MN1 , the transistor MN2 , the transistor MN3 , and the transistor MN4 are all NMOS transistors.

[0089] A first input terminal of the fully differential amplifier AMP is connected to the output signal INP_AMP, and a second input terminal of the fully differential amplifier is connected to the output signal INN_AMP.

[0090] The first input end of the envelope comparator COMP is connected to the first output end of the fully differential amplifier AMP, the second input end of the envelope comparator COMP is connected to the second output end of the fully differential amplifier AMP, and the output end of the envelope comparator COMP outputs the output signal (VOUT) of the edge modulated and demodulated digital isolator.

[0091] The working principle of the edge modulation and demodulation digital isolator circuit provided in this embodiment is as follows:

[0092] When the voltage of the ground terminal GND1 of the transmitting terminal TX suddenly increases relative to the voltage of the ground terminal GND2 of the receiving terminal RX, that is, when a positive common-mode voltage change is generated, the common-mode current is injected from the transmitting terminal TX into the receiving terminal RX through the first high-voltage resistant capacitor C1 and the second high-voltage resistant capacitor C2, and the voltages of the input voltage INA_RX and the input voltage INB_RX increase at the same time. When the common-mode change rate exceeds the preset value, the transistor MN5 and the transistor MN6 are turned on, and the conduction current flows through the sixth resistor R6, generating a voltage drop on the sixth resistor R6, thereby increasing the gate voltage of the transistor MN7 and the transistor MN8, and turning on the transistor MN7 and the transistor MN8, and the common-mode current is discharged to the ground terminal GND2 of the receiving terminal RX through the transistor MN7 and the transistor MN8, thereby preventing the main path output of the fully differential amplifier AMP and the envelope comparator COMP from changing, reducing the impact on the subsequent circuit, and ensuring the normal transmission of the signal in the edge modulation and demodulation digital isolator circuit.

[0093] When there is no positive common-mode voltage change, or the positive common-mode voltage change is small and does not exceed the preset value, the transistor MN5, the transistor MN6, the transistor MN7 and the transistor MN8 are all in the cut-off state, and the transistor MN5, the transistor MN6, the transistor MN7 and the transistor MN8 will not affect the normal modulation and demodulation function of the edge modulation and demodulation digital isolator circuit.

[0094] During the period when the positive common-mode voltage changes, the negative common-mode voltage change rate detection circuit formed by the transistor MN11, the transistor MN12, the transistor MN13 and the transistor MN14 is in a cut-off state, and the negative common-mode voltage change rate detection circuit will not affect the normal modulation and demodulation function of the edge modulation and demodulation digital isolator circuit.

[0095] When the voltage of the ground terminal GND1 of the transmitting end TX suddenly decreases relative to the voltage of the ground terminal GND2 of the receiving end RX, that is, when a negative common-mode voltage change occurs, the common-mode current passes through the first high-voltage resistant capacitor C1 and the second high-voltage resistant capacitor C2, and is injected from the receiving end RX into the transmitting end TX. Since the transistors MP1, MP2, MN9 and MN10 in the driving output unit are all in the on state, the output voltages INA_TX and INB_TX increase at the same time. When the common-mode change rate exceeds a preset value, the transistor MN11 and the transistor MN12 are turned on, and the conduction current flows through the fifth resistor R5, generating a voltage drop on the fifth resistor R5, thereby increasing the gate voltage of the transistor MN13 and the transistor MN14, and turning on the transistor MN13 and the transistor MN14, and the common-mode current is discharged to the ground terminal GND1 of the transmitting end TX through the transistor MN13 and the transistor MN14, thereby preventing the main path output of the fully differential amplifier AMP and the envelope comparator COMP from changing, reducing the impact on subsequent circuits, and ensuring normal transmission of signals in the edge-modulated digital isolator circuit.

[0096] When there is no negative common-mode voltage change, or the negative common-mode voltage change is small and does not exceed the preset value, the transistor MN11, the transistor MN12, the transistor MN13 and the transistor MN14 are all in the cut-off state, and the transistor MN11, the transistor MN12, the transistor MN13 and the transistor MN14 will not affect the normal modulation and demodulation function of the edge modulation and demodulation digital isolator circuit.

[0097] During the period when the negative common-mode voltage changes, the positive common-mode voltage change rate detection circuit composed of the transistor MN5, the transistor MN6, the transistor MN7 and the transistor MN8 is in a cut-off state, and the positive common-mode voltage change rate detection circuit will not affect the normal modulation and demodulation function of the edge modulation and demodulation digital isolator circuit.

[0098] The present application provides a circuit for increasing the common-mode transient immunity of an edge-modulated digital isolator. A group of positive common-mode voltage change rate detection circuits and a group of negative common-mode voltage change rate detection circuits are added to a transmitting end TX and a receiving end RX, respectively. When the change rate of the common-mode voltage or common-mode current in the edge-modulated digital isolator circuit exceeds a set threshold, the positive common-mode voltage change rate detection circuit or the negative common-mode voltage change rate detection circuit is turned on, thereby discharging the common-mode current, reducing the impact on the input signal of the amplifier of the receiving end RX, or reducing the impact on the driver of the transmitting end TX, thereby ensuring normal signal transmission. Furthermore, since the response speed of the positive common-mode voltage change rate detection circuit and the negative common-mode voltage change rate detection circuit is much higher than that of the modulation and demodulation path, during the change of the common-mode voltage or the common-mode current in the circuit, the output signal of the positive common-mode voltage change rate detection circuit or the negative common-mode voltage change rate detection circuit takes effect first, thereby preventing the output of the edge-modulated digital isolator circuit from changing, maintaining the output of the edge-modulated digital isolator circuit unchanged, and effectively improving the common-mode transient immunity of the digital isolator.

[0099] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the attached claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention. Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or terminal device including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0100] The above is a detailed introduction to a circuit for increasing the common-mode transient immunity of a digital isolator for edge modulation and demodulation provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A circuit for increasing the common-mode transient immunity of an edge-modulated digital isolator, characterized in that: The circuit for increasing the common-mode transient immunity of the edge-modulated digital isolator comprises: a transmitting end TX and a receiving end RX, wherein the transmitting end TX is connected to the receiving end RX, and the transmitting end TX sends a voltage signal to the receiving end RX; Wherein, the transmitting end TX includes a negative common-mode voltage change rate detection circuit, which is composed of a transistor MN11, a transistor MN12, a transistor MN13, a transistor MN14 and a fifth resistor R5, the output ends of the transistor MN11 and the transistor MN12 are connected to the control ends of the transistor MN13 and the transistor MN14, and the output end of the transistor MN13, the output end of the transistor MN14 and the fifth resistor R5 are connected to the ground end GND1 of the transmitting end TX; The receiving end RX includes a latch, a fully differential amplifier, an envelope comparator and a positive common mode voltage change rate detection circuit; The latch latches the voltage signal received by the receiving end RX; the input end of the fully differential amplifier is connected to the output end of the latch, and the fully differential amplifier amplifies the voltage signal latched by the latch; the input end of the envelope comparator is connected to the output end of the fully differential amplifier, and the envelope comparator compares the output voltage of the fully differential amplifier and outputs a corresponding high level signal or a low level signal; The forward common-mode voltage change rate detection circuit is composed of a transistor MN5, a transistor MN6, a transistor MN7, a transistor MN8 and a sixth resistor R6, the control ends of the transistor MN5 and the transistor MN6 are connected to the output end of the transmitting end TX, the output ends of the transistor MN5 and the transistor MN6 are connected to the control ends of the transistor MN7 and the transistor MN8, and the output end of the transistor MN7, the output end of the transistor MN8 and the sixth resistor R6 are connected to the ground end GND2 of the receiving end RX.

2. The circuit for increasing the common mode transient immunity of the edge modulation and demodulation digital isolator according to claim 1, characterized in that: The transistor MN5 , the transistor MN6 , the transistor MN7 , the transistor MN8 , the transistor MN11 , the transistor MN12 , the transistor MN13 , and the transistor MN14 are all NMOS transistors.

3. The circuit for increasing the common mode transient immunity of the edge modulation and demodulation digital isolator according to claim 1, characterized in that: The input voltage VDD1 of the transmitting terminal TX and the ground terminal GND1 are different from the input voltage VDD2 of the receiving terminal RX and the ground terminal GND2.

4. The circuit for increasing the common mode transient immunity of the edge modulation and demodulation digital isolator according to claim 1, characterized in that: The transmitting end TX also includes a driving output unit; the driving output unit is composed of a transistor MP1, a transistor MP2, a transistor MN9 and a transistor MN10; The gate of the transistor MP1 is connected to the upper circuit, the source of the transistor MP1 is connected to the input voltage VDD1 of the transmitting terminal TX, and the drain of the transistor MP1 outputs the voltage INA_TX; The gate of the transistor MP2 is connected to the upper circuit, the source of the transistor MP2 is connected to the input voltage VDD1 of the transmitting terminal TX, and the drain of the transistor MP2 outputs the voltage INB_TX; The gate of the transistor MN9 is connected to the upper circuit, the source of the transistor MN9 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN9 is connected to the drain of the transistor MP1; The gate of the transistor MN10 is connected to the upper circuit, the source of the transistor MN10 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN10 is connected to the drain of the transistor MP2; The transistor MP1 and the transistor MP2 are PMOS transistors; the transistor MN9 and the transistor MN10 are NMOS transistors.

5. The circuit for increasing the common mode transient immunity of the edge modulation and demodulation digital isolator according to claim 4, characterized in that: In the negative common-mode voltage change rate detection circuit, the gate of the transistor MN11 is connected to the output voltage INA_TX, the source of the transistor MN11 is connected to one end of the fifth resistor R5, and the drain of the transistor MN11 is connected to the input voltage VDD1 of the transmitting end TX; The gate of the transistor MN12 is connected to the output voltage INB_TX, the source of the transistor MN12 is connected to one end of the fifth resistor R5, and the drain of the transistor MN12 is connected to the input voltage VDD1 of the transmitting end TX; The other end of the fifth resistor R5 is connected to the ground terminal GND1 of the transmitting terminal TX; The connection node between the fifth resistor R5 and the source of the transistor MN11 and the source of the transistor MN12 is connected to the gates of the transistor MN13 and the transistor MN14; The source of the transistor MN13 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN13 is connected to the output voltage INA_TX; The source of the transistor MN14 is connected to the ground terminal GND1 of the transmitting terminal TX, and the drain of the transistor MN14 is connected to the output voltage INB_TX.

6. The circuit for increasing the common mode transient immunity of the edge modulation and demodulation digital isolator according to claim 5, characterized in that: A first high voltage resistant capacitor C1 and a second high voltage resistant capacitor C2 are also connected between the transmitting end TX and the receiving end RX; One end of the first high-voltage-resistant capacitor C1 is connected to the output voltage INA_TX of the transmitting end TX, and the other end of the first high-voltage-resistant capacitor C1 is connected to the first input end of the receiving end RX and inputs the voltage INA_RX; One end of the second high voltage resistant capacitor C2 is connected to the output voltage INB_TX of the transmitting end TX, and the other end of the second high voltage resistant capacitor C2 is connected to the second input end of the receiving end RX and inputs the voltage INB_RX.

7. The circuit for increasing the common mode transient immunity of the edge modulation and demodulation digital isolator according to claim 6, characterized in that: In the positive common-mode voltage change rate detection circuit, the gate of the transistor MN5 is connected to the input voltage INA_RX, the source of the transistor MN5 is connected to one end of the sixth resistor R6, and the drain of the transistor MN5 is connected to the input voltage VDD2 of the receiving end RX; The gate of the transistor MN6 is connected to the input voltage INB_RX, the source of the transistor MN6 is connected to one end of the sixth resistor R6, and the drain of the transistor MN6 is connected to the input voltage VDD2 of the receiving end RX; The other end of the sixth resistor R6 is connected to the ground terminal GND2 of the receiving terminal RX; The connection node between the sixth resistor R6 and the source of the transistor MN5 and the source of the transistor MN6 is connected to the gates of the transistor MN7 and the transistor MN8; The source of the transistor MN7 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN7 is connected to the input voltage INA_RX; The source of the transistor MN8 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN8 is connected to the input voltage INB_RX.

8. The circuit for increasing the common mode transient immunity of the edge modulation and demodulation digital isolator according to claim 7, characterized in that: The latch is composed of a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; The gate of the transistor MN1 is connected to the input voltage INB_RX, the source of the transistor MN1 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN1 is connected to one end of the fourth resistor R4 and one end of the first resistor R1; The gate of the transistor MN2 is connected to the input voltage INA_RX, the source of the transistor MN2 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN2 is connected to one end of the third resistor R3 and one end of the second resistor R2; The other end of the first resistor R1 is connected to the other end of the second resistor R2, the electrical node where the first resistor R1 and the second resistor R2 are connected is also connected to the input voltage VDD2 of the receiving end RX, the other end of the third resistor R3 is connected to the gate of the transistor MN1, and the other end of the fourth resistor R4 is connected to the gate of the transistor MN2; The output signal of the connection node between the drain of the transistor MN1 and the first resistor R1 is INN_AMP, and the output signal of the connection node between the drain of the transistor MN2 and the second resistor R2 is INP_AMP; The gate of the transistor MN3 is connected to the output signal INP_AMP, the source of the transistor MN3 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN4; The gate of the transistor MN4 is connected to the output signal INN_AMP, the source of the transistor MN4 is connected to the ground terminal GND2 of the receiving terminal RX, and the drain of the transistor MN3 is connected to the gate of the transistor MN3; The transistor MN1 , the transistor MN2 , the transistor MN3 , and the transistor MN4 are all NMOS transistors.

9. The circuit for increasing the common mode transient immunity of the edge modulation and demodulation digital isolator according to claim 8, characterized in that: The first input terminal of the fully differential amplifier is connected to the output signal INP_AMP, and the second input terminal of the fully differential amplifier is connected to the output signal INN_AMP.

10. The circuit for increasing the common mode transient immunity of the edge modulation and demodulation digital isolator according to claim 9, characterized in that: The first input end of the envelope comparator is connected to the first output end of the fully differential amplifier, the second input end of the envelope comparator is connected to the second output end of the fully differential amplifier, and the output end of the envelope comparator outputs the output signal of the edge modulated and demodulated digital isolator.

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