Large-scale parallel channel time-frequency diagram real-time generation method based on FPGA

Abstract

The invention discloses an FPGA (Field Programmable Gate Array)-based large-scale parallel channel time-frequency diagram real-time generation method, which is applied to an FPGA-based large-scale parallel channel time-frequency diagram real-time generation system, and the FPGA-based large-scale parallel channel time-frequency diagram real-time generation system comprises a ping-pong structure-based sliding overlapping module, a primary rearrangement module and a secondary rearrangement module, a ping-pong structure comprises a ping-pong branch and a ping-pong branch, and the FPGA-based large-scale parallel channel time-frequency diagram real-time generation method comprises the following steps: a ping-pong structure comprises a ping-pong branch and a ping-pong branch. According to the FPGA-based large-scale parallel channel time-frequency diagram real-time generation method, the problem of FPGA resource limitation of large-scale channel parallel processing and the problem of processing real-time performance are solved through a sliding overlapping module with a ping-pong structure, a first-stage rearrangement module and a second-stage rearrangement module; real-time generation and processing of the time-frequency diagram of a large-scale parallel channel can be realized on a single-chip FPGA (Field Programmable Gate Array).

Description

Technical Field

[0001] The invention belongs to the field of channelized processing, and in particular relates to a method for real-time generation of large-scale parallel channel time-frequency diagrams based on FPGA. Background Art

[0002] In the recent development and engineering construction of intelligent spectrum sensing technology, people have gradually realized that the performance of feature carriers has a huge impact on the results of intelligent judgment. Therefore, in recent years, the preprocessing technology of feature carriers has become a hot topic in the field. The preprocessing technology of spectrum sensing has developed to form a general theoretical framework, that is, digital channelization processing of intermediate frequency broadband data, and then feature extraction of each channel. The feature carrier is generally in the form of power spectrum. Among them, digital channelization processing can bring signal-to-noise ratio gain and effectively improve the detection granularity. With the development of FPGA technology, broadband large-scale channelized digital receiver products have appeared in the field. Secondly, the power spectrum can effectively reflect the energy frequency distribution characteristics of the signal. The carrier information can be better analyzed by reasoning about the power spectrum. Based on the engineering application of multi-channel parallel power spectrum generation technology in FPGA, the engineering construction of intelligent spectrum sensing technology in the field has been promoted. Among them, FPGA digital channelization technology is relatively mature and stable, but the selection and generation processing technology of feature carriers still need to be improved.

[0003] In the prior art, Figure 1 The parallel channel power spectrum generation algorithm structure shown in the figure first performs serial-to-parallel conversion through the serial channel interleaving data stream to make the IQ data of each channel in a parallel form; secondly, based on the principle of the Welch power spectrum estimation algorithm, the step sliding windowing process is implemented through the FIFO to achieve the windowing effect of the segmented overlapping data stream; thirdly, the power spectrum estimation is realized through the maximum hold and sliding smoothing process, and the power spectrum of all channels is normalized; finally, the parallel-to-serial conversion process is performed to form a serial panoramic high-resolution power spectrum data stream output; however, there are the following problems:

[0004] 1. As the number of channels for parallel processing continues to increase, the use of Figure 1 The structure will cause the number of sliding windowing, short-time Fourier transform (STFT), and smoothing modules to increase exponentially, and there will be FPGA timing divergence problems when processing a large number of channels in parallel. Therefore, this structure cannot meet the indicator requirements for the number of processing channels;

[0005] 2. In the application scenario of feature representation of anti-interception signals, the power spectrum can only represent the distribution relationship between energy and frequency, and does not carry information on time. The amount of information supporting back-end identification and judgment is small. Therefore, there is a performance bottleneck in detecting the power spectrum as a feature carrier. The capture of short bursts and frequency hopping signals is insufficient, and the adaptability requirements for carrier types in the industry cannot be met.

[0006] 3. In the application scenario of feature representation of weak signals, the carrier-to-noise ratio performance of the weak signal itself is low. When the power spectrum is used as the feature carrier, the distribution shape of the signal is less different from the background noise, and the distribution characteristics of the noise are maintained in the passband, which may easily lead to the back-end being unable to correctly detect the signal, or lead to missed detection and false detection of multiple signals in the passband. Summary of the invention

[0007] The purpose of the present invention is to solve the problem raised in the background technology and to propose a method for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA.

[0008] To achieve the above object, the technical solution adopted by the present invention is:

[0009] The present invention proposes a method for real-time generation of a time-frequency diagram of a large-scale parallel channel based on FPGA, which is applied to a real-time generation system of a time-frequency diagram of a large-scale parallel channel based on FPGA. The real-time generation system of a time-frequency diagram of a large-scale parallel channel based on FPGA includes a sliding overlapping module, a primary rearrangement module and a secondary rearrangement module based on a ping-pong structure, a short-time Fourier transform module and a normalization color adjustment module. The ping-pong structure includes a ping branch and a pong branch. The real-time generation method of a time-frequency diagram of a large-scale parallel channel based on FPGA includes:

[0010] Obtain n-channel channelized IQ data and continuously input them into the sliding overlap module in real time, and each channelized IQ data includes a preset number of IQ data sampling points, and the IQ data sampling points of the n-channel channelized IQ data are input at the same time in a time-sharing manner in the form of p channels in parallel and n / p clocks per clock;

[0011] The sliding overlap module performs sliding overlap on the continuously input n-channel channelized IQ data according to the step d based on the ping-pong structure, and outputs the m IQ data samples of each n-channel channelized IQ data in the form of ping-pong branch loop output with an overlap ratio of (md) / m, and each branch loop outputs the m IQ data samples of the n-channel channelized IQ data, and the m IQ data samples of the n-channel channelized IQ data are output in time-sharing in the form of p-channel parallel and n / p clocks;

[0012] The first-level rearrangement module performs ping-pong branch loop writing on the m IQ data samples of each n-channel channelized IQ data generated by the sliding overlap module, and rearranges and reads out the m IQ data samples of the n-channel channelized IQ data written by each branch, and each branch of the first-level rearrangement module reads out the continuous m IQ data samples of each p-channel channelized IQ data in a time-sharing form of n / p batches, and transmits the continuous m IQ data samples of each p-channel channelized IQ data to the p-channel parallel short-time Fourier transform module in the form of the data stream;

[0013] The short-time Fourier transform module processes the continuous m IQ data sample points of each batch of p-channel channelized IQ data in p-channel parallel, and for each channel of channelized IQ data, the continuous m IQ data sample points are sequentially windowed, short-time Fourier transformed, dB operated and FFT shift processed, and s spectral lines of the effective bandwidth part are retained, where s is m / 2, and the short-time Fourier transform module cyclically outputs the s spectral lines of the n-channel j times and inputs them into the secondary rearrangement module;

[0014] The secondary rearrangement module writes the s spectral lines of the n-channel output by the short-time Fourier transform module in a ping-pong branch cycle every j times, and rearranges and reads the s spectral lines of the n-channel written j times by each branch. Each branch of the secondary rearrangement module outputs the j×s-dimensional time-frequency spectrum of the n-channel to the p-channel parallel normalization color adjustment module in the form of n / p batches of s spectral lines for each p-channel in a continuous j-time manner;

[0015] The normalized color adjustment module searches for the maximum value of spectral line energy for j×s spectral lines in each n-channel during the process of the short-time Fourier transform module inputting the spectral lines into the secondary rearrangement module, normalizes the corresponding j×s spectral lines in the n-channel output of the secondary rearrangement module with the searched maximum spectral line energy, performs grayscale mapping on the normalized result in p-way parallel form to obtain a grayscale image data stream, and finally maps the grayscale image data stream into an RGB time-frequency image.

[0016] Preferably, the first-level rearrangement module includes a C0 group of DDR read-write controllers and a C1 group of DDR read-write controllers, and the second-level rearrangement module includes a C2 group of DDR read-write controllers and a C3 group of DDR read-write controllers, and each group of DDR read-write controllers corresponds to controlling multiple cascaded DDR cache particles, and each group of DDR read-write controllers acts as a ping-pong branch or a pong branch.

[0017] Preferably, the sliding overlap module performs sliding overlap on the continuously input n-channelized IQ data according to the step d based on the ping-pong structure, including:

[0018] The output of each branch of the sliding overlap module is taken as a group of samples, and a group of samples includes m IQ data samples of n-channel IQ data, and the i-th IQ data sample of each channel of the n-channel IQ data in each group of samples is taken as a data, and the value of i is [1, m], then a group of samples includes m data;

[0019] In the process of outputting the first group of sample points, when the dth data of the first group of sample points is output, the sliding overlap module simultaneously outputs the second group of sample points, and uses the d+1th data to the mth data of the first group of sample points as the first md data of the second group of sample points, and then uses the m+1th data to the m+dth data of the input continuous n-channel channelized IQ data as the last d data of the second group of sample points;

[0020] Similarly, in the process of outputting the second group of sample points, when the dth data of the second group of sample points is output, the sliding overlap module simultaneously outputs the third group of sample points, and the operation is repeated repeatedly, and there are md cross-overlapping data between each two adjacent groups of sample points;

[0021] Each group of samples is m consecutive IQ data samples of n-channel channelized IQ data;

[0022] The sliding overlap is a process in which the sliding overlap module outputs the current set of sample points while ping-pong-outputting the next set of sample points in parallel, and the overlap ratio performance of the two sets of output data is (md) / m, which is called a sliding overlap.

[0023] Preferably, the first-level rearrangement module performs ping-pong branch loop writing on the m IQ data samples of each n-channel channelized IQ data generated by the sliding overlap module, and rearranges and reads out the m IQ data samples of the n-channel channelized IQ data written by each branch, and each branch of the first-level rearrangement module reads out in a time-sharing form of n / p batches of continuous m IQ data samples of each p-channel channelized IQ data, and transmits the continuous m IQ data samples of each p-channel channelized IQ data to the p-channel parallel short-time Fourier transform module in the form of the data stream, including:

[0024] The DDR read / write controllers of group C0 write the first set of sample points output by the sliding overlap module for caching, and the DDR read / write controllers of group C1 write the second set of sample points output by the sliding overlap module for caching;

[0025] When the C1 group DDR read / write controller is writing the second group of sample points, the C0 group DDR read / write controller reads out the first group of sample points cached therein, and then the C0 group DDR read / write controller writes the third group of sample points output by the sliding overlap module for cache;

[0026] When the DDR read / write controller of group C0 is writing the third group of sample points, the DDR read / write controller of group C1 reads out the second group of sample points cached therein, and the operation is repeated repeatedly;

[0027] When reading out the samples in its cache, each group of DDR read-write controllers reads out the samples in n / p batches in p-way parallel form through offset address reading, and each batch reads out m consecutive IQ data samples of p-way channelized IQ data and inputs them into the short-time Fourier transform module in the form of a ping-pong pipeline.

[0028] Preferably, the short-time Fourier transform module processes the continuous m IQ data samples of each batch of p-channel channelized IQ data in p-channel parallel, and for each channel of channelized IQ data, the continuous m IQ data samples are sequentially windowed, short-time Fourier transformed, dB operated and FFTshift processed, and s spectral lines of the effective bandwidth part are retained, where s is m / 2, and the short-time Fourier transform module cyclically outputs the s spectral lines of the n-channel j times, including:

[0029] In the short-time Fourier transform module, for the sample points read out by each group of DDR read-write controllers, and the continuous m IQ data sample points of each channel of channelized IQ data in each batch, windowing and short-time Fourier transform are performed in sequence to obtain serial frequency domain IQ data corresponding to the continuous m IQ data sample points;

[0030] The frequency domain IQ data is processed by dB operation and FFT shift in turn to obtain s spectral lines of the effective bandwidth part, and the short-time Fourier transform module periodically outputs j times the s spectral lines of n channels in p-channel parallel form in n / p batches.

[0031] Preferably, the secondary rearrangement module writes the s spectral lines of the n-channel output by the short-time Fourier transform module in a ping-pong branch cycle every j times, and rearranges and reads out the s spectral lines of the n-channel written j times by each branch, including:

[0032] The s spectral lines of the j-th n-channel output by the short-time Fourier transform module are taken as a group of spectral lines, and the C2 group DDR read-write controller writes a group of spectral lines for cache, and the C3 group DDR read-write controller writes a group of spectral lines for cache;

[0033] When the C3 group DDR read / write controller is writing a group of spectrum lines, the C2 group DDR read / write controller reads out a group of spectrum lines cached therein, and then the C2 group DDR read / write controller rewrites a group of spectrum lines for cache;

[0034] When the DDR read / write controller of group C2 rewrites a group of spectrum lines, the DDR read / write controller of group C3 reads out a group of spectrum lines cached in it, and the operation is repeated repeatedly;

[0035] When writing a group of spectrum lines, each group of DDR read / write controllers writes j times in succession, and each time writes s spectrum lines of n channels in n / p batches in p-channel parallel form, and writes s spectrum lines of p channels in one batch;

[0036] When reading out a group of spectral lines, each group of DDR read-write controllers first reads out the j×s spectral lines of a p-channel, then reads out the j×s spectral lines of the next p-channel, until all the j×s spectral lines of n / p batches of p-channels are read out to complete the reading of a group of spectral lines.

[0037] Preferably, in the normalization color adjustment module, for the C2 group of DDR read / write controllers or the C3 group of DDR read / write controllers, the energy of the s spectral lines of the j-th n-channel input to each group of DDR read / write controllers is searched for the maximum value, and the searched maximum value is used to normalize the j×s spectral lines of the n-channel output of the corresponding group of DDR read / write controllers, and during the normalization process, the j×s spectral lines of the p-channel output of each group of DDR read / write controllers are normalized in parallel;

[0038] The spectral line energies of j×s spectral lines of p channels in each batch after normalization are gray-scale mapped in parallel to obtain the corresponding gray-scale image data stream;

[0039] The grayscale image data stream corresponding to the j×s spectral lines of the p-channels in each batch is mapped into an RGB time-frequency image.

[0040] Preferably, a first-in-first-out module is provided between the first-level rearrangement module and the short-time Fourier transform module, between the short-time Fourier transform module and the second-level rearrangement module, between the second-level rearrangement module and the normalization color adjustment module, and after the normalization color adjustment module to realize cross-clock conversion.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] This FPGA-based large-scale parallel channel time-frequency diagram real-time generation method solves the FPGA resource limitation problem of large-scale channel parallel processing and the real-time processing problem through a sliding overlap module, a first-level rearrangement module and a second-level rearrangement module with a ping-pong structure, and can realize the real-time generation and processing of large-scale parallel channel time-frequency diagrams on a single FPGA.

[0043] In this method, each channel outputs a time-frequency diagram, that is, the time-frequency diagram is used as a carrier. The time-frequency diagram covers information in three dimensions: time, frequency, and energy. The carrier type of the signal can be reflected on the time-frequency diagram, and the short burst and frequency hopping signals can be effectively represented, which can greatly support the carrier type adaptability of the intelligent spectrum sensing system.

[0044] Based on the normalized color adjustment module in this method, weak signals with low carrier-to-noise ratio can still be recognized in the image. Compared with the contrast power spectrum carrier in the prior art, it can greatly improve the weak signal detection capability of the intelligent spectrum sensing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A structure diagram of a parallel channel power spectrum generation algorithm in the prior art;

[0046] Figure 2 It is a module block diagram of the real-time generation method of large-scale parallel channel time-frequency diagram based on FPGA of the present invention;

[0047] Figure 3 It is a working schematic diagram of the sliding overlapping module of the present invention;

[0048] Figure 4 It is a working schematic diagram of the primary rearrangement module of the present invention;

[0049] Figure 5 It is a working schematic diagram of the short-time Fourier transform module of the present invention;

[0050] Figure 6 It is a working schematic diagram of the secondary rearrangement module of the present invention;

[0051] Figure 7 This is a working schematic diagram of the normalized color adjustment module of the present invention;

[0052] Figure 8 A schematic diagram of a channelized time-frequency diagram of a frequency hopping signal generated by the present invention;

[0053] Fig. 9 The present invention processes and generates a communication signal with a carrier-to-noise ratio less than 3dB in time-frequency distribution. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0055] like Figure 2-Figure 7As shown, a method for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA is provided. The method for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA is applied to a system for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA. The system for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA includes: a sliding overlapping module, a primary rearrangement module and a secondary rearrangement module based on a ping-pong structure, a short-time Fourier transform module and a normalized color adjustment module. The ping-pong structure includes a ping branch and a pong branch, wherein the sliding overlapping module, the primary rearrangement module and the secondary rearrangement module all include a ping branch and a pong branch (i.e., two branches), the primary rearrangement module includes a C0 group DDR read-write controller and a C1 group DDR read-write controller (i.e., the ping branch and the pong branch in the primary rearrangement module), the secondary rearrangement module includes a C2 group DDR read-write controller and a C3 group DDR read-write controller (i.e., the ping branch and the pong branch in the secondary rearrangement module), and each group of DDR read-write controllers corresponds to controlling multiple cascaded DDR cache particles, and each group of DDR read-write controllers serves as a ping branch or a pong branch.

[0056] A method for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA includes:

[0057] Step 1: Obtain n-channel channelized IQ data and continuously input them into the sliding overlap module in real time, and each channel of channelized IQ data includes a preset number of IQ data sampling points (wherein the number of IQ data sampling points included in each channel of channelized IQ data is not limited), and in the form of p channels in parallel per clock and divided into n / p clocks, the IQ data sampling points of the n-channel channelized IQ data are input at the same time in a time-sharing manner;

[0058] In this embodiment, n is 8192, m is 1024, p is 16, n / p is 512, d is 768, s is 512, and j is 512, but the values ​​of these symbols are not limited and can be set to other values. Taking n-channel channelized IQ data as an example, the IQ data stream with a channelized sampling rate of 160ksps per channel, the n-channel channelized IQ data stream is continuously input into the sliding overlap module in real time (that is, the same n-channel channelized IQ data stream continuously inputs the sliding overlap module, and the input timing of the sliding overlap module is as follows: Figure 3 Figure (2) shows the input timing of n-channel (8192-channel) channelized IQ data, in which p-channel (16-channel) channels are parallel and divided into n / p clocks (512 clocks) per clock, and the IQ data sampling point input of n-channel (8192-channel) channels at the same time is realized in time-sharing mode; Figure 3-Figure 7In the figure, 8192 channels (i.e., n channels) of channelized data are sequentially represented by digital numbers 0, 1, 2, ... 8191, 1024 (i.e., m) IQ data sample points are sequentially represented by digital numbers 0, 1, 2, ... 1023, 512 (i.e., s) spectral lines are sequentially represented by digital numbers 0, 1, 2, ... 511, and 512 times (i.e., j times) are sequentially represented by digital numbers 0, 1, 2, ... 511.

[0059] Step 2, a sliding overlap module performs sliding overlap on the continuously input n-channel channelized IQ data according to a step d based on a ping-pong structure, and outputs an overlap ratio of (md) / m within m IQ data samples of each n-channel channelized IQ data in the form of a ping-pong branch loop output, and each branch loop outputs m IQ data samples of n-channel channelized IQ data, and the m IQ data samples of n-channel channelized IQ data are output in time-sharing in the form of p-channel parallel and n / p clocks.

[0060] Step 2.1, the sliding overlap module performs sliding overlap on the continuously input n-channel IQ data, and after sliding overlap, cyclically outputs through each branch (such as Figure 3 Figure (1) in the figure is the output process of the sliding overlap module), the output of each branch of the sliding overlap module is taken as a group of samples, and a group of samples contains m IQ data samples of n-channel IQ data, and the i-th IQ data sample of each channel of the n-channel IQ data in each group of samples is taken as a data, and the value of i is [1, m] (the value of i in this embodiment is [1, 1024]), then a group of samples contains m data;

[0061] It should be noted that, in the present embodiment, each branch in the sliding overlapping module outputs m (1024) IQ data samples of n-channels (8192-channels) of channelized IQ data, and the ping branch and the pong branch output the samples cyclically over time, and each branch outputs m (1024) IQ data samples of n-channels (8192-channels) of channelized IQ data (i.e., a total of n×m (8192×1024) IQ data samples) as a group of samples, and the i-th IQ data sample of each channel in the n-channels (8192-channels) of channelized IQ data as a data (e.g., the first IQ data sample of each channel in the 8192-channel channelized IQ data is taken as a data, then one data contains n IQ data samples (i.e., 8192 IQ data samples)), then a group of samples contains m (1024) data.

[0062] Step 2.2: Figure 3Figure (3) in FIG. 1 is the output timing of the sliding overlap module. In the process of outputting the first group of samples, when the d-th data of the first group of samples is output, the sliding overlap module simultaneously outputs the second group of samples, and uses the d+1-th data to the m-th data of the first group of samples as the first md data of the second group of samples, and then uses the m+1-th data to the m+d-th data of the input continuous n-channel channelized IQ data as the last d data of the second group of samples;

[0063] In this embodiment, it should be noted that when one branch of the sliding overlap module outputs the dth data (768th data) of the first group of samples (the first group of samples is m IQ data samples of n-channel channelized IQ data), the other branch of the sliding overlap module simultaneously outputs the second group of samples, and uses the d+1th data to the mth data (769th data to the 1024th data) of the first group of samples as the first md data (first 256 data) of the second group of samples, and then uses the m+1th data to the m+dth data (1024+1th data to the 1024+768th data) of the input continuous n-channel (8192-channel) channelized IQ data as the last d (768) data of the second group of samples;

[0064] Similarly, in the process of outputting the second group of sample points, when the dth data of the second group of sample points is output, the sliding overlap module simultaneously outputs the third group of sample points, and uses the d+1th data to the mth data of the second group of sample points as the first md data of the third group of sample points, and then uses the m+d+1th data to the m+2dth data of the input continuous n-channel channelized IQ data as the last d data of the third group of sample points, and outputs multiple groups of sample points in a ping-pong pipeline in a reciprocating manner, and there are md data of cross-over overlap between each two adjacent groups of sample points;

[0065] Each group of samples is m consecutive IQ data samples of n-channel IQ data (i.e., 1024 consecutive IQ data samples of 8192-channel IQ data);

[0066] The sliding overlap is a process in which the sliding overlap module outputs the current group of sample points while ping-pong-outputting the next group of sample points in parallel (that is, when one branch outputs the d-th data, it starts to output the other branch at the same time), and the overlap ratio performance of the two groups of output data is achieved (md) / m (the overlap ratio in this embodiment is 1 / 4, and other values ​​can be set by setting m and d).

[0067] Step 3, the first-level rearrangement module performs ping-pong branch loop writing for each n-channel IQ data generated by the sliding overlap module, and rearranges and reads out the n-channel IQ data samples written by each branch. Each branch of the first-level rearrangement module reads out each p-channel IQ data in a time-sharing form of continuous m IQ data samples n / p batches (e.g. Figure 4 Figure (1) in the figure is the output process of the first-level rearrangement module), and transmits m consecutive IQ data samples of each p-channel channelized IQ data to the p-channel parallel short-time Fourier transform module in the form of the data stream, including:

[0068] (It should be noted first that the C0 group DDR read / write controller and the C1 group DDR read / write controller serve as the ping branch and pong branch of the first-level rearrangement module respectively);

[0069] The DDR read / write controllers of group C0 write the first set of sample points output by the sliding overlap module for caching, and the DDR read / write controllers of group C1 write the second set of sample points output by the sliding overlap module for caching;

[0070] When the C1 group DDR read / write controller is writing the second group of sample points, the C0 group DDR read / write controller reads out the first group of sample points cached therein, and then the C0 group DDR read / write controller writes the third group of sample points output by the sliding overlap module for cache;

[0071] When the DDR read / write controller of group C0 is writing the third group of sample points, the DDR read / write controller of group C1 reads out the second group of sample points cached therein, and the operation is repeated repeatedly;

[0072] In the process of reading out the samples in its cache, each group of DDR read-write controllers reads out the samples in its cache in n / p batches in the form of p-way parallel (i.e., reading out the samples in 512 batches in the form of 16-way parallel), and reads out the continuous m IQ data samples of p-way channelized IQ data in each batch (i.e., reads out the continuous 1024 IQ data samples of 16-way channelized IQ data in each batch), and inputs them into the short-time Fourier transform module in the form of a ping-pong pipeline, wherein the output timing of the first-level rearrangement module is as follows: Figure 4 As shown in Figure (2) in .

[0073] Step 4, the short-time Fourier transform module processes the continuous m IQ data samples of each batch of p-channel channelized IQ data in p-channel parallel. For each channel of channelized IQ data, the continuous m IQ data samples are sequentially windowed, short-time Fourier transformed, dB operated and FFTshift processed, and s spectral lines of the effective bandwidth part are retained, where s is m / 2 (set according to actual needs), and the short-time Fourier transform module cyclically outputs the s spectral lines of the n-channel j times and inputs them into the secondary rearrangement module, including:

[0074] like Figure 5 FIG. (1) shows the working process of the short-time Fourier transform module. In the short-time Fourier transform module, for the sample points read out by each group of DDR read / write controllers (i.e., the sample points read out by the C0 group of DDR read / write controllers and the C1 group of DDR read / write controllers), and the continuous m IQ data sample points of each channel of the channelized IQ data in each batch, windowing and short-time Fourier transform (STFT) are performed in sequence to obtain serial frequency domain IQ data corresponding to the continuous m IQ data sample points;

[0075] The frequency domain IQ data is processed by dB operation and FFT shift in sequence to obtain s spectral lines of the effective bandwidth part, and the short-time Fourier transform module periodically outputs j times in the form of p-channel parallel output in n / p batches of s spectral lines of n channels to the secondary rearrangement module (that is, the short-time Fourier transform module continuously outputs 512 times in the form of 16-channel parallel output in 512 batches of 512 spectral lines of 8192 channels, and the value of j is not limited and can be set according to specific design requirements). At this time, the average bandwidth of the transmission is reduced by four times, where Figure 5 Figure (2) is the output timing of the short-time Fourier transform module, and the time slice j in the figure is j times. After the dB operation, the data representation form of Q7 is adopted, that is, the fixed-point signed number form of 9-bit integer and 7-bit decimal, which can represent the dB domain dynamic range of -256 to 255, meeting the requirements of most scenarios. At this time, the transmission bit width of each spectral line is 16 bits.

[0076] Step 5, the secondary rearrangement module writes the s spectral lines of the n-channel output by the short-time Fourier transform module in a ping-pong branch cycle every j times, and rearranges and reads out the s spectral lines of the n-channel output by each branch j times. Each branch of the secondary rearrangement module reads the s spectral lines of each p-channel for j consecutive times in a time-sharing form of n / p batches (such as Figure 6 Figure (1) in the figure shows the output process of the secondary rearrangement module), outputting the j×s-dimensional time-frequency spectrum of n channels to p-channel parallel normalized color adjustment modules, including:

[0077] (It should be noted first that the C2 group DDR read / write controller and the C3 group DDR read / write controller serve as the ping branch and pong branch of the secondary rearrangement module respectively);

[0078] The s spectral lines of the j-th n-channel output by the short-time Fourier transform module are taken as a group of spectral lines, and the C2 group DDR read-write controller writes a group of spectral lines for cache, and the C3 group DDR read-write controller writes a group of spectral lines for cache;

[0079] When the C3 group DDR read / write controller is writing a group of spectrum lines, the C2 group DDR read / write controller reads out a group of spectrum lines cached therein, and then the C2 group DDR read / write controller rewrites a group of spectrum lines for cache;

[0080] When the DDR read / write controller of group C2 rewrites a group of spectrum lines, the DDR read / write controller of group C3 reads out a group of spectrum lines cached in it, and the operation is repeated repeatedly;

[0081] Each group of DDR read / write controllers writes a group of spectrum lines j times in succession, and each time writes s spectrum lines of n-channel channels in n / p batches in the form of p-channel parallel, and writes s spectrum lines of p-channel channels in a batch (i.e., when writing a group of spectrum lines, the C2 group of DDR read / write controllers or the C3 group of DDR read / write controllers writes s spectrum lines of n-channel channels in n / p batches in the form of p-channel parallel j times in succession (i.e., writes 512 spectrum lines of 8192-channel channels in 512 batches in the form of 16-channel parallel 512 times in succession), and writes s spectrum lines of p-channel channels in a batch (i.e., writes 512 spectrum lines of 16-channel channels in a batch));

[0082] When reading a group of spectrum lines, each group of DDR read-write controllers first reads out the j×s spectrum lines of a p-channel, and then reads out the j×s spectrum lines of the next p-channel, until all the j×s spectrum lines of n / p batches of p-channels are read out to complete the reading of a group of spectrum lines (that is, when the C2 group of DDR read-write controllers or the C3 group of DDR read-write controllers read out a group of 512×512 spectrum lines of 16 channels, and then reads out the 512×512 spectrum lines of the next 16 channels). Lines are read out until all 512×512 spectral lines of 16 channels in 512 batches are read out to complete the reading of a group of spectral lines), wherein j×s spectral lines constitute a time-frequency diagram of j×s spectral lines (i.e., 512×512 spectral lines constitute a time-frequency spectrum of 512×512 dimensions), and the time-frequency spectrum of j×s dimensions of p channels in each batch is input to a p-channel parallel normalized color adjustment module (i.e., the time-frequency spectrum of 512×512 dimensions of 16 channels in each batch is input to a 16-channel parallel normalized color adjustment module), wherein Figure 6 Figure (2) in FIG. 1 is the output timing of the secondary rearrangement module.

[0083] Step 6: Figure 7 The figure shows a schematic diagram of the normalized color adjustment module. In the process of the short-time Fourier transform module inputting the spectrum line into the secondary rearrangement module, the normalized color adjustment module searches for the maximum value of the spectrum line energy for each n-channel j×s spectrum line, and normalizes the corresponding n-channel j×s spectrum lines output by the secondary rearrangement module with the searched maximum spectrum line energy, and then performs grayscale mapping on the normalized result in the form of p-way parallel to obtain a grayscale image data stream, and finally maps the grayscale image data stream into an RGB time-frequency image (in Figure 2 RGB color), including:

[0084] In the normalization color adjustment module, for the C2 group of DDR read-write controllers or the C3 group of DDR read-write controllers, the energy of the s spectral lines of the j-th n-channel input to each group of DDR read-write controllers is searched for the maximum value, and the searched maximum value is used to normalize the j×s spectral lines of the output n-channels of the corresponding group of DDR read-write controllers (that is, the spectral line energy of each spectral line in the j×s-dimensional time-frequency spectrum of the n-channels) (so that the spectral line energy value of each spectral line is expressed as a floating point number between 0 and 1), and during the normalization process, the j×s spectral lines of the p-channels in each batch output by each group of DDR read-write controllers are normalized in parallel;

[0085] The spectral line energies of j×s spectral lines of p channels in each batch after normalization are gray-scale mapped in parallel (so that each floating point number is mapped to an integer range of 0 to 767) to obtain a corresponding grayscale image data stream;

[0086] Map the grayscale image data stream corresponding to the j×s spectral lines of each batch of p channels into an RGB time-frequency image (i.e. Figure 7 RGB mapping in); wherein, in the process of mapping the grayscale image data stream into the RGB time-frequency graph, when the grayscale value is less than or equal to 255, let G and B be 0, and R be mapped from 1 to 255 at equal intervals; when the grayscale value is greater than 255 and less than or equal to 511, let R be 255, B be 0, and G be mapped from 1 to 255 at equal intervals; when the grayscale is greater than 511, let R and G be 255, and B be mapped from 1 to 255 at equal intervals, and then p-channel j×s root spectrum lines form a p-channel parallel time-sharing RGB time-frequency graph (that is, 16-channel channel 512×512 root spectrum lines form a 16-channel parallel time-sharing RGB time-frequency graph).

[0087] It should be noted that a first-in-first-out module (FIFO) is provided between the first-level rearrangement module and the short-time Fourier transform module, between the short-time Fourier transform module and the second-level rearrangement module, between the second-level rearrangement module and the normalization color adjustment module, and after the normalization color adjustment module to realize cross-clock conversion, and each FIFO has p channels (i.e., 16 channels in this embodiment); among them, the FIFO between the short-time Fourier transform module and the second-level rearrangement module, the output of the short-time Fourier transform module first passes through the FIFO, and then is input into the second-level rearrangement module, and in the process of being input into the second-level rearrangement module, an extreme value search is performed.

[0088] like Figure 8 , which is a schematic diagram of a channelized frequency-frequency diagram of a frequency-hopping signal;

[0089] like Fig. 9 As shown, it is the time-frequency distribution of a communication signal with a carrier-to-noise ratio less than 3dB.

[0090] This FPGA-based large-scale parallel channel time-frequency diagram real-time generation method solves the FPGA resource limitation problem of large-scale channel parallel processing and the real-time processing problem through a sliding overlapping module, a first-level rearrangement module and a second-level rearrangement module with a ping-pong structure, and can realize the real-time generation and processing of time-frequency diagrams of large-scale parallel channels on a single FPGA; in this method, each channel outputs a time-frequency diagram, that is, the time-frequency diagram is used as a carrier. The time-frequency diagram covers information in three dimensions of time, frequency and energy. The carrier type of the signal can be reflected on the time-frequency diagram, and the effective representation of short bursts and frequency hopping signals can be achieved, which can greatly support the carrier type adaptability of the intelligent spectrum sensing system; in this method, based on the normalized color adjustment module, the weak signal with a low carrier-to-noise ratio still has the image recognition, which can greatly improve the weak signal detection capability of the intelligent spectrum sensing system compared with the contrast power spectrum carrier in the prior art.

[0091] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for real-time generation of large-scale parallel channel time-frequency diagrams based on FPGA, characterized in that: The FPGA-based large-scale parallel channel time-frequency diagram real-time generation method is applied to the FPGA-based large-scale parallel channel time-frequency diagram real-time generation system, the FPGA-based large-scale parallel channel time-frequency diagram real-time generation system includes a sliding overlap module based on a ping-pong structure, a primary rearrangement module and a secondary rearrangement module, as well as a short-time Fourier transform module and a normalized color adjustment module, the ping-pong structure includes a ping branch and a pong branch, wherein the FPGA-based large-scale parallel channel time-frequency diagram real-time generation method includes: Obtain n-channel channelized IQ data and continuously input them into the sliding overlap module in real time, and each channelized IQ data includes a preset number of IQ data sampling points, and the IQ data sampling points of the n-channel channelized IQ data are input at the same time in a time-sharing manner in the form of p channels in parallel and n / p clocks per clock; The sliding overlap module performs sliding overlap on the continuously input n-channel channelized IQ data according to the step d based on the ping-pong structure, and outputs the m IQ data samples of each n-channel channelized IQ data in the form of ping-pong branch loop output with an overlap ratio of (md) / m, and each branch loop outputs the m IQ data samples of the n-channel channelized IQ data, and the m IQ data samples of the n-channel channelized IQ data are output in time-sharing in the form of p-channel parallel and n / p clocks; The first-level rearrangement module performs ping-pong branch loop writing on the m IQ data samples of each n-channel channelized IQ data generated by the sliding overlap module, and rearranges and reads out the m IQ data samples of the n-channel channelized IQ data written by each branch, and each branch of the first-level rearrangement module reads out the continuous m IQ data samples of each p-channel channelized IQ data in a time-sharing form of n / p batches, and transmits the continuous m IQ data samples of each p-channel channelized IQ data to the p-channel parallel short-time Fourier transform module in the form of the data stream; The short-time Fourier transform module processes the continuous m IQ data sample points of each batch of p-channel channelized IQ data in p-channel parallel, and for each channel of channelized IQ data, the continuous m IQ data sample points are sequentially windowed, short-time Fourier transformed, dB operated and FFT shift processed, and s spectral lines of the effective bandwidth part are retained, where s is m / 2, and the short-time Fourier transform module cyclically outputs the s spectral lines of the n-channel j times and inputs them into the secondary rearrangement module; The secondary rearrangement module writes the s spectral lines of the n-channel output by the short-time Fourier transform module in a ping-pong branch cycle every j times, and rearranges and reads the s spectral lines of the n-channel written j times by each branch. Each branch of the secondary rearrangement module outputs the j×s-dimensional time-frequency spectrum of the n-channel to the p-channel parallel normalization color adjustment module in the form of n / p batches of s spectral lines for each p-channel in a continuous j-time manner; The normalized color adjustment module searches for the maximum value of spectral line energy for j×s spectral lines in each n-channel during the process of the short-time Fourier transform module inputting the spectral lines into the secondary rearrangement module, normalizes the corresponding j×s spectral lines in the n-channel output of the secondary rearrangement module with the searched maximum spectral line energy, performs grayscale mapping on the normalized result in p-way parallel form to obtain a grayscale image data stream, and finally maps the grayscale image data stream into an RGB time-frequency image.

2. The method for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA as claimed in claim 1, characterized in that: The first-level rearrangement module includes C0 group DDR read-write controller and C1 group DDR read-write controller, and the second-level rearrangement module includes C2 group DDR read-write controller and C3 group DDR read-write controller, and each group of DDR read-write controller corresponds to controlling multiple cascaded DDR cache particles, and each group of DDR read-write controller acts as a ping-pong branch or a pong branch.

3. The method for real-time generation of large-scale parallel channel time-frequency diagrams based on FPGA as claimed in claim 2, characterized in that: The sliding overlap module performs sliding overlap on the continuously input n-channel channelized IQ data according to the step d based on the ping-pong structure, including: The output of each branch of the sliding overlap module is taken as a group of samples, and a group of samples includes m IQ data samples of n-channel IQ data, and the i-th IQ data sample of each channel of the n-channel IQ data in each group of samples is taken as a data, and the value of i is [1, m], then a group of samples includes m data; In the process of outputting the first group of sample points, when the dth data of the first group of sample points is output, the sliding overlap module simultaneously outputs the second group of sample points, and uses the d+1th data to the mth data of the first group of sample points as the first md data of the second group of sample points, and then uses the m+1th data to the m+dth data of the input continuous n-channel channelized IQ data as the last d data of the second group of sample points; Similarly, in the process of outputting the second group of sample points, when the dth data of the second group of sample points is output, the sliding overlap module simultaneously outputs the third group of sample points, and the operation is repeated repeatedly, and there are md cross-overlapping data between each two adjacent groups of sample points; Each group of samples is m consecutive IQ data samples of n-channel channelized IQ data; The sliding overlap is a process in which the sliding overlap module outputs the current set of sample points while ping-pong-outputting the next set of sample points in parallel, and the overlap ratio performance of the two sets of output data is (md) / m, which is called a sliding overlap.

4. The method for real-time generation of large-scale parallel channel time-frequency diagrams based on FPGA as claimed in claim 3, characterized in that: The first-level rearrangement module performs ping-pong branch loop writing on the m IQ data samples of each n-channel IQ data generated by the sliding overlap module, and rearranges and reads out the m IQ data samples of the n-channel IQ data written by each branch, and each branch of the first-level rearrangement module reads out the continuous m IQ data samples of each p-channel IQ data in a time-sharing form of n / p batches, and transmits the continuous m IQ data samples of each p-channel IQ data to the p-channel parallel short-time Fourier transform module in the form of the data stream, including: The DDR read / write controllers of group C0 write the first set of sample points output by the sliding overlap module for caching, and the DDR read / write controllers of group C1 write the second set of sample points output by the sliding overlap module for caching; When the C1 group DDR read / write controller is writing the second group of sample points, the C0 group DDR read / write controller reads out the first group of sample points cached therein, and then the C0 group DDR read / write controller writes the third group of sample points output by the sliding overlap module for cache; When the DDR read / write controller of group C0 is writing the third group of sample points, the DDR read / write controller of group C1 reads out the second group of sample points cached therein, and the operation is repeated repeatedly; When reading out the samples in its cache, each group of DDR read-write controllers reads out the samples in n / p batches in p-way parallel form through offset address reading, and each batch reads out m consecutive IQ data samples of p-way channelized IQ data and inputs them into the short-time Fourier transform module in the form of a ping-pong pipeline.

5. The method for real-time generation of large-scale parallel channel time-frequency diagrams based on FPGA as claimed in claim 4, characterized in that: The short-time Fourier transform module processes the continuous m IQ data samples of each batch of p-channel channelized IQ data in p-channel parallel, and for each channelized IQ data, the continuous m IQ data samples are sequentially windowed, short-time Fourier transformed, dB operated and FFT shift processed, and s spectral lines of the effective bandwidth part are retained, where s is m / 2, and the short-time Fourier transform module cyclically outputs the s spectral lines of the n-channel j times, including: In the short-time Fourier transform module, for the sample points read out by each group of DDR read-write controllers, and the continuous m IQ data sample points of each channel of channelized IQ data in each batch, windowing and short-time Fourier transform are performed in sequence to obtain serial frequency domain IQ data corresponding to the continuous m IQ data sample points; The frequency domain IQ data is processed by dB operation and FFT shift in turn to obtain s spectral lines of the effective bandwidth part, and the short-time Fourier transform module periodically outputs j times the s spectral lines of n channels in p-channel parallel form in n / p batches.

6. The method for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA as claimed in claim 2, characterized in that: The secondary rearrangement module writes the s spectral lines of the n-channel output by the short-time Fourier transform module in a ping-pong branch cycle every j times, and rearranges and reads the s spectral lines of the n-channel written j times by each branch, including: The s spectral lines of the j-th n-channel output by the short-time Fourier transform module are taken as a group of spectral lines, and the C2 group DDR read-write controller writes a group of spectral lines for cache, and the C3 group DDR read-write controller writes a group of spectral lines for cache; When the C3 group DDR read / write controller is writing a group of spectrum lines, the C2 group DDR read / write controller reads out a group of spectrum lines cached therein, and then the C2 group DDR read / write controller rewrites a group of spectrum lines for cache; When the DDR read / write controller of group C2 rewrites a group of spectrum lines, the DDR read / write controller of group C3 reads out a group of spectrum lines cached in it, and the operation is repeated repeatedly; When writing a group of spectrum lines, each group of DDR read / write controllers writes j times in succession, and each time writes s spectrum lines of n channels in n / p batches in p-channel parallel form, and writes s spectrum lines of p channels in one batch; When reading out a group of spectral lines, each group of DDR read-write controllers first reads out the j×s spectral lines of a p-channel, then reads out the j×s spectral lines of the next p-channel, until all the j×s spectral lines of n / p batches of p-channels are read out to complete the reading of a group of spectral lines.

7. The method for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA as claimed in claim 6, characterized in that: In the normalization color adjustment module, for the C2 group of DDR read / write controllers or the C3 group of DDR read / write controllers, the energy of the s spectral lines of the j-th n-channel input to each group of DDR read / write controllers is searched for the maximum value, and the searched maximum value is used to normalize the j×s spectral lines of the n-channel output of the corresponding group of DDR read / write controllers, and during the normalization process, the j×s spectral lines of the p-channel output of each group of DDR read / write controllers are normalized in parallel; The spectral line energies of j×s spectral lines of p channels in each batch after normalization are gray-scale mapped in parallel to obtain the corresponding gray-scale image data stream; The grayscale image data stream corresponding to the j×s spectral lines of the p-channels in each batch is mapped into an RGB time-frequency image.

8. The method for real-time generation of time-frequency diagrams of large-scale parallel channels based on FPGA as claimed in claim 1, characterized in that: A first-in-first-out module is provided between the first-level rearrangement module and the short-time Fourier transform module, between the short-time Fourier transform module and the second-level rearrangement module, between the second-level rearrangement module and the normalization color adjustment module, and after the normalization color adjustment module to realize cross-clock conversion.

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