Power management integrated circuit and power management system

Abstract

A power management integrated circuit and a power management system. The power management integrated circuit is soldered on a printed circuit board, including a first output stage circuit and a second output stage circuit; in a separate configuration, first and second current inflow pins of the first and second output stage circuits are soldered to first and second inflow printed conductors which are not directly electrically connected, and first and second current outflow pins of the first and second output stage circuits are soldered to first and second outflow printed conductors which are not directly electrically connected; in a combined configuration, the first and second current inflow pins are both soldered to a common inflow printed conductor and are electrically connected, and the first and second current outflow pins are both soldered to a common outflow printed conductor and are electrically connected, so that the first and second elements are connected in parallel, and the first and second output stage circuits are combined into a combined output stage circuit, for generating a common output power.

Description

TECHNICAL FIELD

[0001] The present invention relates to a power management integrated circuit and a power management system, and more particularly, to a power management integrated circuit and a power management system which can save printed circuit board space and meet different power requirements at the same time. BACKGROUND

[0002] FIG. 1A With FIG. 1B is a circuit block diagram showing a known power management system. The conventional power management system 10 includes a power management integrated circuit 11 (11') and a printed circuit board 12 (12'). The power management integrated circuit 11 (11') is in the form of an integrated circuit package and becomes a product. When the power management system 10 needs to provide different combinations of different output power as different platform applications, the power management integrated circuit 11 (11') and the printed circuit board 12 (12') are required to have substantially the same appearance and circuit layout so as to facilitate production and reduce manufacturing cost. Therefore, the power management system 10 is arranged as shown in FIG. 1A With FIG. 1B the layout design of the power management system 10 shown in

[0003] As shown in FIG. 1A With FIG. 1B When the power management system 10 needs to provide two different power or a single power for two different platforms, the production process of the power management integrated circuit 11 (11') and the printed circuit board 12 (12') needs to pay extra cost in space layout to obtain application flexibility.

[0004] In the platform as shown in FIG. 1A the power management system 10 includes the power management integrated circuit 11 and the printed circuit board 12. The power management system 10 provides a first output power and a second output power; wherein the first output power includes a first output voltage Voutl and a first output current Ioutl; wherein the second output power includes a second output voltage Vout2 and a second output current Iout2. For example, the upper limit of the first output current Ioutl is 7A, and the upper limit of the second output current Iout2 is 3A. On the other hand, in the platform as shown in FIG. 1B the power management system 10 provides an output power; wherein the output power includes an output voltage Vout and an output current Iout. For example, the upper limit of the output current Iout is 10A. That is, the power management system 10 having substantially the same appearance and circuit layout can provide different power combinations for two different platforms.

[0005] As shown in FIG. 1AAs shown, the power management system 10 platform requires two output power supplies. For example, the first output power supply has an output voltage Vout1 and needs to provide an output current Iout1 with a maximum limit of 7A, while the second output power supply has an output voltage Vout2 and needs to provide an output current Iout2 with a maximum limit of 3A. FIG. 1B The power management system platform shown only requires one output power supply. For example, the output power supply has an output voltage Vout and needs to provide an output current Iout with a maximum of 10A.

[0006] like FIG. 1A As shown, the power management integrated circuit 11 includes a buck converter circuit 101a and a buck converter circuit 101b, used to provide a first output power supply and a second output power supply, respectively; and as FIG. 1B As shown, the power management integrated circuit 11' includes a buck converter 101c for providing output power. To meet the above conditions while maintaining a similar arrangement and layout of other circuits in power management integrated circuits 11 and 11', and similar arrangement of other circuits and lines in printed circuit boards 12 and 12', the traditional method is to place the smaller buck converter 101a in space reserved for a larger buck converter 101c. This allows it to meet applications with an output current limit of 7A and also an output current limit of 10A. FIG. 1A As shown. However, this creates a problem: it requires reserving unused space to accommodate applications with a maximum capacity of 10A, such as... FIG. 1A As shown. However, when the power management system 10 only needs to provide output power, having an output voltage Vout and an output current Iout with a maximum limit of 10A, then only a single buck circuit 101c is required, such as... FIG. 1B As shown, while FIG. 1A The space for placing the step-down circuit 101b is completely unusable and becomes idle space, which increases the space cost of the entire integrated circuit and printed circuit board.

[0007] In view of the deficiencies in the prior art, the present invention proposes a power management integrated circuit and a power management system that can save printed circuit board space and simultaneously meet different power requirements. Summary of the Invention

[0008] In one aspect, the present application provides a power management integrated circuit (PMIC) to be soldered on a printed circuit board (PCB), the PMIC comprising: a first output stage circuit; and a second output stage circuit; wherein in a discrete configuration, a first current-in flow pin of the first output stage circuit and a second current-in flow pin of the second output stage circuit are soldered to a first current-in printed trace and a second current-in printed trace of the PCB, respectively, which are not directly electrically connected to each other, a first current-out flow pin of the first output stage circuit and a second current-out flow pin of the second output stage circuit are soldered to a first current-out printed trace and a second current-out printed trace of the PCB, respectively, which are not directly electrically connected to each other, and a first element and a second element are used to generate a first output power corresponding to the first current-out flow pin and a second output power corresponding to the second current-out flow pin from a first input power corresponding to the first current-in flow pin and a second input power corresponding to the second current-in flow pin, respectively, a current upper limit of the first output power and the second output power being a first maximum output current and a second maximum output current, respectively; wherein in a combined configuration, the first current-in flow pin and the second current-in flow pin are soldered to a common current-in printed trace of the PCB to be electrically connected, and the first current-out flow pin and the second current-out flow pin are soldered to a common current-out printed trace of the PCB to be electrically connected, so that the first element and the second element are connected in parallel, and the first output stage circuit and the second output stage circuit are combined into a combined output stage circuit to generate a common output power, wherein a current upper limit of the common output power is a sum of the first maximum output current and the second maximum output current; wherein a first current-in flow end and a first current-out flow end of the first element correspond to the first current-in flow pin and the first current-out flow pin, respectively, and a second current-in flow end and a second current-out flow end of the second element correspond to the second current-in flow pin and the second current-out flow pin, respectively.

[0009] In another aspect, the present application provides a power management system, comprising a power management integrated circuit and a printed circuit board, wherein the power management integrated circuit is soldered on the printed circuit board, the power management integrated circuit comprises: a first output stage circuit; and a second output stage circuit; wherein in a split configuration, a first current flow-in pin of the first output stage circuit and a second current flow-in pin of the second output stage circuit are soldered to a first flow-in printed trace and a second flow-in printed trace of the printed circuit board, which are not directly electrically connected to each other, a first current flow-out pin of the first output stage circuit and a second current flow-out pin of the second output stage circuit are soldered to a first flow-out printed trace and a second flow-out printed trace of the printed circuit board, which are not directly electrically connected to each other, and a first element and a second element are used to generate a first output power corresponding to the first current flow-out pin and a second output power corresponding to the second current flow-out pin according to a first input power corresponding to the first current flow-in pin and a second input power corresponding to the second current flow-in pin, respectively, a current upper limit of the first output power and the second output power is a first maximum output current and a second maximum output current, respectively; wherein in a combined configuration, the first current flow-in pin and the second current flow-in pin are both soldered to a common flow-in printed trace of the printed circuit board and are electrically connected, the first current flow-out pin and the second current flow-out pin are both soldered to a common flow-out printed trace of the printed circuit board and are electrically connected, so that the first element and the second element are connected in parallel, and the first output stage circuit and the second output stage circuit are combined into a combined output stage circuit to generate a common output power, wherein a current upper limit of the common output power is a sum of the first maximum output current and the second maximum output current; wherein a first current flow-in end and a first current flow-out end of the first element correspond to the first current flow-in pin and the first current flow-out pin, a second current flow-in end and a second current flow-out end of the second element correspond to the second current flow-in pin and the second current flow-out pin.

[0010] In an embodiment, the common flow-in printed trace and the common flow-out printed trace are both located below the integrated circuit and between the integrated circuit and the printed circuit board.

[0011] In an embodiment, the common flow-in printed trace and / or the common flow-out printed trace are located on the uppermost layer of the printed circuit board.

[0012] In an embodiment, the first current flow-in pin and the second current flow-in pin are located on the same plane, so that the common flow-in printed trace is located on the uppermost layer of the printed circuit board, and / or the first current flow-out pin and the second current flow-out pin are located on the same plane, so that the common flow-out printed trace is located on the uppermost layer of the printed circuit board.

[0013] In one embodiment, the first current flow-in pin and the second current flow-in pin are located at two sides of the integrated circuit in a width direction and are aligned with each other in a length direction, such that the common flow-in printed conductor is located at the uppermost layer of the printed circuit board, and / or the first current flow-out pin and the second current flow-out pin are located at two sides of the integrated circuit in the width direction and are aligned with each other in the length direction, such that the common flow-out printed conductor is located at the uppermost layer of the printed circuit board.

[0014] In one embodiment, the common flow-in printed conductor is aligned with the first current flow-in pin and the second current flow-in pin in the length direction, and / or the common flow-out printed conductor is aligned with the first current flow-out pin and the second current flow-out pin in the length direction.

[0015] In one embodiment, the first output stage circuit and the second output stage circuit are linear power conversion circuits, wherein: in the discrete configuration, the first element and the second element correspond to a first transistor and a second transistor, respectively, to generate the first output power supply and the second output power supply in a linear regulation manner according to a first feedback signal and a second feedback signal of the first output power supply and the second output power supply; and in the merged configuration, the first element and the second element are connected in parallel as a common transistor to generate the common output power supply in a linear regulation manner according to a common feedback signal of the common output power supply.

[0016] In one embodiment, the first output stage circuit and the second output stage circuit are switching output stage circuits, wherein: in the discrete configuration, the first element and the second element correspond to include an upper bridge switch and a lower bridge switch of the switching output stage circuit, a driving circuit and / or a current detection circuit to drive the upper bridge switch or the lower bridge switch and to control switching of a first inductor and a second inductor corresponding to the first output power supply and the second output power supply, respectively, according to a first feedback signal and a second feedback signal of the first output power supply and the second output power supply, to generate the first output power supply and the second output power supply; and in the merged configuration, the first element and the second element control switching of an inductor corresponding to the common output power supply according to a common feedback signal of the common output power supply, to generate the common output power supply.

[0017] In one embodiment, in the discrete configuration, the first current-in pin and the first current-out pin are electrically connected to a first input voltage and a first switching node through the first current-in printed conductor and the first current-out printed conductor, the second current-in pin and the second current-out pin are electrically connected to a second output voltage and a second switching node through the second current-in printed conductor and the second current-out printed conductor; and in the merged configuration, the first current-in pin and the first current-out pin are electrically connected to a common input voltage and a common switching node through the common current-in printed conductor and the common current-out printed conductor, the second current-in pin and the second current-out pin are electrically connected to the common input voltage and the common switching node through the common current-in printed conductor and the common current-out printed conductor.

[0018] The power management integrated circuit of the present application can save printed circuit board space and meet different power requirements at the same time.

[0019] The purposes, technical contents, features and effects of the present application are described in detail below through specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0020] FIG. 1A With FIG. 1B is a circuit block diagram showing a known power management system.

[0021] FIG. 2A With FIG. 2B is a circuit block diagram showing a power management system according to an embodiment of the present application.

[0022] FIG. 3A With FIG. 3B is a bottom view showing a power management system according to an embodiment of the present application.

[0023] FIG. 4A With FIG. 4B is a cross-sectional view taken along line A-A and line B-B, respectively, of the embodiment shown in FIG. 3A

[0024] FIG. 4C With FIG. 4D is a cross-sectional view taken along line A-A and line B-B, respectively, of the embodiment shown in FIG. 3B

[0025] FIG. 5A With FIG. 5B is a bottom view showing a power management system according to another embodiment of the present application.

[0026] FIG. 6 is a circuit schematic diagram showing a power management integrated circuit according to an embodiment of the present application.​​

[0027] FIG. 7 is a circuit diagram showing a power management integrated circuit according to another embodiment of the present application.

[0028] Explanation of symbols in the drawings

[0029] 10, 20: power management system

[0030] 11, 11', 21, 21': power management integrated circuit

[0031] 12, 12', 22, 22': printed circuit board

[0032] 101a, 101b, 101c: step-down circuit

[0033] 201a: first output stage circuit

[0034] 201b: second output stage circuit

[0035] 203: control circuit

[0036] DU1, DU2, DL1, DL2: drive circuit

[0037] L, L1, L2: inductor

[0038] LX1, LX2: switching node

[0039] Pboot1, Pboot2: drive pin

[0040] Pgnd: ground pin

[0041] Psw1, Pvout1: first current outflow pin

[0042] Psw2, Pvout2: second current outflow pin

[0043] Pvin1: first current inflow pin

[0044] Pvin2: second current inflow pin

[0045] Q1: first transistor

[0046] Q2: second transistor

[0047] QL1, QL2: lower bridge switch

[0048] QU1, QU2: upper bridge switch

[0049] Tin1: first inflow printed conductor

[0050] Tin2: second inflow printed conductor

[0051] Tins: common in-printed conductor

[0052] Tout1: first out-printed conductor

[0053] Tout2: second out-printed conductor

[0054] Touts: common out-printed conductor

[0055] Tsw1, Tsw2: current out terminal

[0056] Tvin1, Tvin2: current in terminal

[0057] Vout: (common) output power supply

[0058] Vout1: first output power supply

[0059] Vout2: second output power supply DETAILED DESCRIPTION

[0060] The drawings in the present disclosure are schematic and mainly intended to represent the coupling relationship between circuits and the relationship between signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale.

[0061] FIG. 2A and FIG. 2B is a circuit block diagram showing a power management system according to an embodiment of the present disclosure. As shown in FIG. 2A and FIG. 2B The power management system 20 of the present disclosure includes a power management integrated circuit 21 (21') and a printed circuit board 22 (22'). The power management integrated circuit 21 (21') is in the form of an integrated circuit package and includes a first output stage circuit 201a and a second output stage circuit 201b. The first output stage circuit 201a includes first components and the second output stage circuit 201b includes second components. The first output stage circuit 201a and the second output stage circuit 201b are integrated in the power management integrated circuit 21 (21'). FIG. 2A represents a discrete configuration, and FIG. 2B represents a combined configuration. In the discrete configuration shown in FIG. 2A The first output stage circuit 201a is coupled to a switching node LX1 through one end of an inductor L1, and the other end of the inductor L1 is coupled to a first output power supply Vout1. The second output stage circuit 201b is coupled to a switching node LX2 through an inductor L2, and the other end of the inductor L2 is coupled to a second output power supply Vout2. In the combined configuration, the switching nodes LX1 and LX2 are coupled through PCB conductors to form a switching node LX, which is further coupled to the inductor L.

[0062] FIG. 3A andFIG. 3B is a bottom view of a power management system according to an embodiment of the present application. FIG. 4A With FIG. 4B is a bottom view of a power management system according to an embodiment of the present application. FIG. 3A In the embodiment shown, cross-sectional views taken along lines A-A and B-B, respectively. FIG. 4C With FIG. 4D is a bottom view of a power management system according to an embodiment of the present application. FIG. 3B In the embodiment shown, cross-sectional views taken along lines A-A and B-B, respectively. FIG. 3A and FIG. 4A With FIG. 4B represents a discrete configuration, while FIG. 3B and FIG. 4C With FIG. 4D represents a combined configuration. In the embodiment shown, the first output stage circuit 201a and the second output stage circuit 201b are switching output stage circuits.

[0063] As FIG. 3A and FIG. 4A With FIG. 4B In the discrete configuration, the first current of the first output stage circuit 201a flows into the pin Pvinl and the second current of the second output stage circuit 201b flows into the pin Pvin2, which are respectively soldered to the first input printed conductor Tinl and the second input printed conductor Tin2 of the printed circuit board 22 that are not directly electrically connected to each other, while the first current of the first output stage circuit 201a flows out of the pin Pswl and the second current of the second output stage circuit 201b flows out of the pin Psw2, which are respectively soldered to the first output printed conductor Toutl and the second output printed conductor Tout2 of the printed circuit board 22 that are not directly electrically connected to each other. The first element and the second element are respectively used to generate the first output power Voutl and the second output power Vout2 according to the first input power and the second input power, and the current upper limit of the first output power Voutl and the second output power Vout2 is respectively the first maximum output current and the second maximum output current.

[0064] As FIG. 3B and FIG. 4C With FIG. 4DAs shown, in the merged configuration, the first current inflow pin Pvin1 of the first output stage circuit 201a and the second current inflow pin Pvin2 of the second output stage circuit 201b are both soldered to the common inflow printed conductor Tins of the printed circuit board 22' and electrically connected. The first current outflow pin Psw1 of the first output stage circuit 201a and the second current outflow pin Psw2 of the second output stage circuit 201b are both soldered to the common outflow printed conductor Touts of the printed circuit board 22' and electrically connected. This allows the first and second components to be connected in parallel, thereby merging the first output stage circuit 201a and the second output stage circuit 201b into a merged output stage circuit to generate a common output power supply Vout. The upper limit of the common output power supply current is the sum of the first maximum output current and the second maximum output current. Please refer to... FIG. 6 The current inflow terminal Tvin1 and the current outflow terminal Tsw1 of the first element correspond to the first current inflow pin Pvin1 and the first current outflow pin Psw1, respectively. The current inflow terminal Tvin2 and the current outflow terminal Tsw2 of the second element correspond to the second current inflow pin Pvin2 and the second current outflow pin Psw2, respectively.

[0065] like FIG. 3B and FIG. 4C and FIG. 4D As shown, in the merged configuration, the first current inflow pin Pvin1 and the second current inflow pin Pvin2 are located on the same plane, such that the common inflow printed conductor Tins is located on the top layer of the printed circuit board 22', and / or, the first current outflow pin Psw1 and the second current outflow pin Psw2 are located on the same plane, such that the common outflow printed conductor Touts is located on the top layer of the printed circuit board 22'.

[0066] like FIG. 3B As shown, in the merged configuration, the first current inflow pin Pvin1 and the second current inflow pin Pvin2 are located on both sides of the integrated circuit 21' in the width direction and are aligned with each other in the length direction, so that the common inflow printed conductor Tins is located on the top layer of the printed circuit board 22', and / or, the first current outflow pin Psw1 and the second current outflow pin Psw2 are located on both sides of the integrated circuit 21' in the width direction and are aligned with each other in the length direction, so that the common outflow printed conductor Touts is located on the top layer of the printed circuit board 22'.

[0067] like FIG. 3BAs shown, the common in-printed trace Tins is aligned in length with the first current in-pin Pvinl and the second current in-pin Pvin2, and / or, the common out-printed trace Touts is aligned in length with the first current out-pin Pswl and the second current out-pin Psw2.

[0068] In FIG. 3A and FIG. 4A with FIG. 4B As shown in the split configuration, the first current in-pin Pvinl and the first current out-pin Pswl are electrically connected to the first input voltage and the first switching node through the first in-printed trace Tinl and the first out-printed trace Toutl, while the second current in-pin Pvin2 and the second current out-pin Psw2 are electrically connected to the second input voltage and the second switching node through the second in-printed trace Tin2 and the second out-printed trace Tout2.

[0069] In FIG. 3B and FIG. 4C with FIG. 4D As shown in the merged configuration, the first current in-pin Pvinl and the first current out-pin Pswl are electrically connected to the common input voltage and the common switching node through the common in-printed trace Tins and the common out-printed trace Touts, while the second current in-pin Pvin2 and the second current out-pin Psw2 are electrically connected to the common input voltage and the common switching node through the common in-printed trace Tins and the common out-printed trace Touts. In one embodiment, the boot pins Pbootl, Pboot2 can also be coupled through the common printed traces.

[0070] As FIG. 3B and FIG. 4C with FIG. 4D As shown in the merged configuration, the first element and the second element control the switching of the corresponding inductors L according to the common feedback signal of the common output power supply Vout to generate the common output power supply Vout.

[0071] FIG. 4A with FIG. 4B are respectively shown FIG. 3A cross-sectional views taken along lines A-A and B-B. FIG. 4B with FIG. 4D are respectively shown FIG. 3B cross-sectional views taken along lines A-A and B-B. As FIG. 3A-FIG. 3B with FIG. 4A-FIG. 4D As shown, the integrated circuit 21 (21') is soldered on the printed circuit board 22 (22'). As FIG. 4C with FIG. 4DAs shown, the common inflow printed conductors Tins and the common outflow printed conductors Touts are both located below the integrated circuit 21 and between the integrated circuit 21 and the printed circuit board 22. The common inflow printed conductors Tins and / or the common outflow printed conductors Touts are located on the top layer of the printed circuit board 22.

[0072] FIG. 5A and FIG. 5B This is a bottom view of a power management system according to another embodiment of the present invention. In this embodiment, the first output stage circuit 201a and the second output stage circuit 201b are, for example, linear power conversion circuits. This embodiment and... FIG. 3A and FIG. 3B The embodiment is similar, except that this embodiment does not have inductors L1 and L2, and the first current outflow pin is Pvout1, and the second current outflow pin is Pvout2. The remaining components are similar. FIG. 3A and FIG. 3B Therefore, its detailed description is omitted.

[0073] FIG. 6 This is a circuit diagram of a power management integrated circuit according to an embodiment of the present invention. In this embodiment, the first output stage circuit 201a and the second output stage circuit 201b are switching output stage circuits. In this embodiment, as... FIG. 6 As shown, the first and second components can respectively correspond to the upper bridge switches QU1, QU2 and lower bridge switches QL1, QL2, including the switching output stage circuit, to drive the drive circuits DU1, DU2, DL1, DL2 and / or the current detection circuit (not shown). The control circuit 203 generates operation signals to the drive circuits DU1, DL1, DU2, and DL2. FIG. 6 As shown, one end of the lower bridge switch QL1 is coupled to the upper bridge switch QU1 at the current outflow terminal Tsw1, and the other end of the lower bridge switch QL1 is coupled to the ground pin Pgnd. FIG. 6 As shown, in the discrete configuration, the first element and the second element are used to control the switching of the corresponding inductors L1 and L2 according to the first feedback signal and the second feedback signal of the first output power supply Vout1 and the second output power supply Vout2, respectively, so as to generate the first output power supply Vout1 and the second output power supply Vout2.

[0074] FIG. 7 This is a circuit diagram of a power management integrated circuit according to another embodiment of the present invention. In this embodiment, the first output stage circuit 201a and the second output stage circuit 201b are linear power conversion circuits. In this embodiment, as... FIG. 7 As shown, the first element and the second element can be a first transistor Q1 and a second transistor Q2. For example... FIG. 7As shown, in the discrete configuration, the first transistor Q1 and the second transistor Q2 generate the first output power Vout1 and the second output power Vout2 in a linear regulation manner according to the first feedback signal and the second feedback signal of the first output power Vout1 and the second output power Vout2, respectively.

[0075] As shown, in the discrete configuration, the first transistor Q1 and the second transistor Q2 generate the first output power Vout1 and the second output power Vout2 in a linear regulation manner according to the first feedback signal and the second feedback signal of the first output power Vout1 and the second output power Vout2, respectively. FIG. 5A With FIG. 5B As shown, in the discrete configuration, the first transistor Q1 and the second transistor Q2 generate the first output power Vout1 and the second output power Vout2 in a linear regulation manner according to the first feedback signal and the second feedback signal of the first output power Vout1 and the second output power Vout2, respectively.

[0076] As mentioned above, the present application can save the printed circuit board space and meet different power requirements at the same time by coupling, for example, soldering the first current inflow pin and the second current inflow pin to the common inflow printed conductor of the printed circuit board and coupling, for example, soldering the first current outflow pin and the second current outflow pin to the common outflow printed conductor of the printed circuit board.

[0077] The above has been described with respect to the preferred embodiments of the present application, but the above description is only to make those skilled in the art easily understand the content of the present application, and is not intended to limit the broadest scope of the present application. The described embodiments are not limited to separate applications, but can be combined, for example, two or more embodiments can be combined, and part of the components in one embodiment can be used to replace the corresponding components in another embodiment. In addition, those skilled in the art can think of various equivalent changes and various combinations under the same spirit of the present application, for example, the present application refers to "processing or operating or generating an output result according to a signal", which is not limited to the signal itself, but also includes, if necessary, voltage-current conversion, current-voltage conversion, and / or proportional conversion, etc., and then processing or operating to generate an output result according to the converted signal. Therefore, those skilled in the art can think of various equivalent changes and various combinations under the same spirit of the present application, and the combination methods are various, which are not listed one by one here. Therefore, the scope of the present application should cover all the above and other equivalent changes.

Claims

1. A power management integrated circuit (IC) to be soldered to a printed circuit board (PCB), the power management IC comprising: a first output stage circuit; and a second output stage circuit; wherein in a discrete configuration, a first current flow-in pin of the first output stage circuit and a second current flow-in pin of the second output stage circuit are soldered to a first current flow-in printed trace and a second current flow-in printed trace, respectively, of the PCB that are not directly electrically connected to each other, a first current flow-out pin of the first output stage circuit and a second current flow-out pin of the second output stage circuit are soldered to a first current flow-out printed trace and a second current flow-out printed trace, respectively, of the PCB that are not directly electrically connected to each other, and a first element and a second element are respectively configured to generate a first output power corresponding to the first current flow-out pin and a second output power corresponding to the second current flow-out pin from a first input power corresponding to the first current flow-in pin and a second input power corresponding to the second current flow-in pin, the first output power and the second output power having a current upper limit of a first maximum output current and a second maximum output current, respectively; wherein in a combined configuration, the first current flow-in pin and the second current flow-in pin are both soldered to a common current flow-in printed trace of the PCB to be electrically connected, the first current flow-out pin and the second current flow-out pin are both soldered to a common current flow-out printed trace of the PCB to be electrically connected, such that the first element and the second element are connected in parallel, and such that the first output stage circuit and the second output stage circuit are combined into a combined output stage circuit to generate a common output power having a current upper limit of a sum of the first maximum output current and the second maximum output current; wherein a first current flow-in terminal and a first current flow-out terminal of the first element correspond to the first current flow-in pin and the first current flow-out pin, and a second current flow-in terminal and a second current flow-out terminal of the second element correspond to the second current flow-in pin and the second current flow-out pin.

2. The power management integrated circuit of claim 1, wherein, The common current flow-in printed trace and the common current flow-out printed trace are both located below the IC and between the IC and the PCB.

3. The power management integrated circuit of claim 2, wherein, The common current flow-in printed trace and / or the common current flow-out printed trace are located at a topmost layer of the PCB.

4. The power management integrated circuit of claim 3, wherein, The first current flow-in pin and the second current flow-in pin are located on a same plane such that the common current flow-in printed trace is located at a topmost layer of the PCB, and / or the first current flow-out pin and the second current flow-out pin are located on a same plane such that the common current flow-out printed trace is located at a topmost layer of the PCB.

5. The power management integrated circuit of claim 4, wherein, the first current inflow pin and the second current inflow pin are located at two sides of the integrated circuit in a width direction and are aligned with each other in a length direction, so that the common inflow printed conductor is located at the uppermost layer of the printed circuit board, and / or the first current outflow pin and the second current outflow pin are located at two sides of the integrated circuit in the width direction and are aligned with each other in the length direction, so that the common outflow printed conductor is located at the uppermost layer of the printed circuit board.

6. The power management integrated circuit of claim 5, wherein, the first current inflow pin and the second current inflow pin are located at two sides of the integrated circuit in a width direction and are aligned with each other in a length direction, so that the common inflow printed conductor is located at the uppermost layer of the printed circuit board, and / or the first current outflow pin and the second current outflow pin are located at two sides of the integrated circuit in the width direction and are aligned with each other in the length direction, so that the common outflow printed conductor is located at the uppermost layer of the printed circuit board.

7. The power management integrated circuit of claim 1, wherein, the first output stage circuit and the second output stage circuit are linear power conversion circuits, wherein: in the separate configuration, the first element and the second element correspond to a first transistor and a second transistor, respectively, to generate the first output power supply and the second output power supply in a linear regulation manner according to a first feedback signal and a second feedback signal of the first output power supply and the second output power supply; and in the combined configuration, the first element and the second element are connected in parallel as a common transistor to generate the common output power supply in a linear regulation manner according to a common feedback signal of the common output power supply.

8. The power management integrated circuit of claim 1, wherein, the first output stage circuit and the second output stage circuit are switching output stage circuits, wherein: in the separate configuration, the first element and the second element correspond to include an upper bridge switch and a lower bridge switch of the switching output stage circuit, a driving circuit and / or a current detection circuit to drive the upper bridge switch or the lower bridge switch, and to control switching of a corresponding first inductor and a second inductor according to a first feedback signal and a second feedback signal of the first output power supply and the second output power supply, respectively, to generate the first output power supply and the second output power supply; and in the combined configuration, the first element and the second element control switching of a corresponding inductor according to a common feedback signal of the common output power supply to generate the common output power supply.

9. The power management integrated circuit of claim 8, wherein: in the separate configuration, the first current inflow pin and the first current outflow pin are connected to a first input voltage and a first switching node through the first inflow printed conductor and the first outflow printed conductor, and the second current inflow pin and the second current outflow pin are connected to a second output voltage and a second switching node through the second inflow printed conductor and the second outflow printed conductor; and In the merged configuration, the first current-in and the first current-out pins are electrically connected to a common input voltage and a common switching node through the common current-in and the common current-out printed conductors, respectively, and the second current-in and the second current-out pins are electrically connected to the common input voltage and the common switching node through the common current-in and the common current-out printed conductors, respectively.

10. A power management system comprising the power management integrated circuit and the printed circuit board as claimed in any one of claims 1 to 9.

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