Semiconductor device and forming method thereof

Abstract

A memory cell structure includes a transistor structure and a capacitor structure, where the capacitor structure includes a hydrogen absorbing layer. The hydrogen absorbing layer absorbs hydrogen, which prevents or reduces the likelihood that hydrogen diffuses into the underlying metal oxide channel of the transistor structure. In this manner, the hydrogen absorbing layer minimizes and / or reduces the likelihood of hydrogen contamination in the metal oxide channel, which may enable the memory cell structure to achieve low current leakage and reduce data corruption and / or failure of the memory cell structure, among others.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same. Background Art

[0002] Memory devices are used in a variety of applications. Memory devices are composed of a plurality of memory cells that are typically arranged in an array of rows and columns. One type of memory cell includes a dynamic random access memory (DRAM) cell. In certain applications, a DRAM cell-based memory device may be selected over other types of memory cell-based memory devices because DRAM cells have lower cost, smaller area, and the ability to store larger amounts of data relative to other types of memory cells, such as static random access memory (SRAM) cells or other types of memory cells. Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device. The semiconductor device includes a plurality of back-end dielectric layers. The semiconductor device includes a memory cell structure located in the plurality of back-end dielectric layers, including: a transistor structure; a capacitor structure located above the transistor structure, including: a first bottom electrode layer, a second bottom electrode layer located above the first bottom electrode layer, a hydrogen absorption layer located between the first bottom electrode layer and the second bottom electrode layer, a dielectric layer located above the second bottom electrode layer, and a top electrode layer located above the dielectric layer.

[0004] An embodiment of the present invention provides a semiconductor device. The semiconductor device includes a plurality of back-end dielectric layers. The semiconductor device includes a memory cell structure located in the plurality of back-end dielectric layers, including: a transistor structure, a capacitor structure located above the transistor structure, including: a bottom electrode layer, a dielectric layer located above the bottom electrode layer, a first top electrode layer located above the dielectric layer, a second top electrode layer located above the first top electrode layer, and a hydrogen absorption layer located between the first top electrode layer and the second top electrode layer.

[0005] An embodiment of the present invention provides a method. The method includes forming a gate structure of a transistor structure included in a memory cell structure of a semiconductor device. The method includes forming a gate dielectric layer of the transistor structure above the gate structure. The method includes forming a channel layer of the transistor structure on the gate dielectric layer. The method includes forming a plurality of source / drain regions of the transistor structure on the channel layer. The method includes forming a source / drain interconnection structure of the memory cell structure on a source / drain region in a plurality of source / drain regions. The method includes forming a bottom electrode of a capacitor structure included in the memory cell structure on the source / drain interconnection structure. The method includes forming a hydrogen absorption layer of the capacitor structure above the bottom electrode. The method includes forming a top electrode of the capacitor structure above the hydrogen absorption layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented.

[0008] FIG. 2A to FIG. 2C is a diagram of an example semiconductor device described herein.

[0009] FIG. 3A to FIG. 3C is a graph of examples of parameters associated with a memory cell structure including a hydrogen gettering layer as described herein.

[0010] 4A to 4T is a diagram of an example implementation of a memory cell structure forming a semiconductor device described herein.

[0011] FIG. 5A to FIG. 5C is a diagram of an example semiconductor device described herein.

[0012] 6A to 6F is a diagram of an example implementation of a memory cell structure forming a semiconductor device described herein.

[0013] FIG. 7A to FIG. 7C is a diagram of an example semiconductor device described herein.

[0014] FIG. 8A to FIG. 8O is a diagram of an example implementation of a memory cell structure forming a semiconductor device described herein.

[0015] 9A to 9C is a diagram of an example semiconductor device described herein.

[0016] FIG. 10A to FIG. 10F is a diagram of an example implementation of a memory cell structure forming a semiconductor device described herein.

[0017] Fig.11 is a diagram of example components of the apparatus described herein.

[0018] Fig.12 is a flow chart of an example process associated with forming the memory cell structure described herein.

[0019] FIG. 13A to FIG. 13C is a diagram of an example semiconductor device described herein.

[0020] FIG. 14A to FIG. 14H is a diagram of an example implementation of a memory cell structure forming a semiconductor device described herein. DETAILED DESCRIPTION

[0021] The following disclosure provides different embodiments or examples for implementing each feature of the provided target. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the disclosure. Of course, these are only examples and are not limiting. Other components, materials, values, steps, arrangements, etc. are also considered. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0022] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0023] A dynamic random access memory (DRAM) memory cell is a volatile memory cell that typically includes a transistor in series with a capacitor. This may be referred to as a one-transistor-one-capacitor (1T-1C) DRAM cell. The capacitor in a 1T-1C DRAM cell acts as a memory device by selectively storing charge. The capacitor may be charged via the transistor, and the amount of charge stored in the capacitor may be sensed by discharging the charge stored in the capacitor. The logic value (e.g., a 1 value or a 0 value) stored by the 1T-1C DRAM cell may correspond to the amount of charge stored by the capacitor.

[0024] In some cases, the transistors of the 1T-1C DRAM cell may include a metal oxide channel (e.g., a channel layer including a metal oxide material). The use of a metal oxide channel can reduce current leakage in the 1T-1C DRAM cell relative to an elemental semiconductor channel or a III-V compound semiconductor channel, which can improve charge retention in the capacitor of the 1T-1C DRAM cell (and thus improve data retention). However, metal oxide materials are very susceptible to hydrogen contamination. If hydrogen diffuses into the metal oxide channel of the 1T-1C DRAM cell, the carrier concentration in the metal oxide channel will increase. The increased carrier concentration can cause an increase in the off current leakage of the 1T-1C DRAM cell, an increase in positive bias temperature instability (PBTI), and / or an increase in negative bias temperature instability (NBTI). Additionally and / or alternatively, hydrogen contamination in the metal oxide channel can increase the charge carrier concentration to the extent that the 1T-1C DRAM cell falls into a normally-on configuration, rendering the 1T-1C DRAM cell inoperable.

[0025] In some embodiments described herein, a memory cell structure (e.g., a 1T-1C DRAM cell or another type of memory cell structure) includes a transistor structure and a capacitor structure, wherein the capacitor structure includes a hydrogen absorbing layer. The hydrogen absorbing layer absorbs hydrogen, such as atmospheric hydrogen and / or hydrogen used in various types of deposition processes, such as plasma enhanced chemical vapor deposition (PE-CVD) and atomic layer deposition (ALD). The hydrogen absorbing layer absorbs hydrogen, which prevents or reduces the likelihood of hydrogen diffusion into the metal oxide channel underlying the transistor structure. In this way, the hydrogen absorbing layer minimizes and / or reduces the likelihood of hydrogen contamination in the metal oxide channel, which can enable the memory cell structure to achieve low current leakage and reduce the likelihood of data corruption and / or memory cell structure failure, among other things.

[0026] Figure 1 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown, the example environment 100 may include a plurality of semiconductor processing tools 102-112 and a wafer / die transport tool 114. The plurality of semiconductor processing tools 102-112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, and / or another type of semiconductor processing tool. The tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, among other examples.

[0027] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a high density plasma CVD (HDP-CVD) tool, a sub-atmospheric pressure CVD (SACVD) tool, a low pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, deposition tool 102 includes an epitaxial tool configured to form layers and / or regions of a device through epitaxial growth. In some embodiments, example environment 100 includes multiple types of deposition tools 102.

[0028] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep ultraviolet (EUV) source, an extreme ultraviolet (EUV) source, an X-ray source, an electron beam (e-beam) source, and / or the like). The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from the mask to the photoresist layer. This pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, and so on. In some implementations, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0029] The developing tool 106 is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the photoresist layer. The pattern is formed by removing unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer.

[0030] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, etc. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0031] The planarization tool 110 is a semiconductor processing tool capable of polishing or flattening the layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or flattens a layer or surface of a deposited or plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free-abrasive polishing) to polish or flatten the surface of the semiconductor device. The planarization tool 110 may utilize abrasives and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head may rotate at different rotational axes to remove material and flatten any irregular topography of the semiconductor device, thereby making the semiconductor device flat or planar.

[0032] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion thereof with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, etc.) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0033] The wafer / die transporter 114 includes a mobile robot, a robotic arm, a tram or rail car, an overhead crane transport (OHT) system, an automatic material handling system (AMHS), and / or is configured to transfer substrates and / or semiconductor devices between semiconductor processing tools 102-112, which is configured to transfer substrates and / or semiconductor devices between processing chambers of the same semiconductor processing tool, and / or is configured to transfer substrates and / or semiconductor devices to and from other locations, such as wafer racks, storage rooms, etc. In some embodiments, the wafer / die transporter 114 can be a program device configured to travel a specific path and / or can operate semi-autonomously or autonomously. In some embodiments, the example environment 100 includes multiple wafer / die transporters 114.

[0034] For example, the wafer / die transfer tool 114 may be included in a cluster tool or another type of tool that includes multiple process chambers, and may be configured to transfer substrates and / or semiconductor devices between multiple process chambers, to transfer substrates and / or semiconductor devices between a process chamber and a buffer, to transfer substrates and / or semiconductor devices between a process chamber and an interface tool such as an equipment front end module (EFEM), and / or to transfer substrates and / or semiconductor devices between a process chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), etc. In some embodiments, the wafer / die transfer tool 114 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidations, and / or deposits), a deposition process chamber (e.g., a process chamber for depositing different types of materials, a process chamber for performing different types of deposition operations). In these embodiments, the wafer / die transfer tool 114 is configured to transfer substrates and / or semiconductor devices between processing chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) of the processing chambers and / or between processing operations in the deposition tool 102, as described herein.

[0035] In some embodiments, one or more of the semiconductor processing tools 102-112 may perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-112 may form a gate structure of a transistor structure included in a memory cell structure of a semiconductor device; a gate dielectric layer of the transistor structure may be formed above the gate structure; a channel layer of the transistor structure may be formed on the gate dielectric layer; multiple source / drain regions of the transistor structure may be formed on the channel layer; a source / drain interconnect structure of the memory cell structure may be formed on the source / drain regions of the multiple source / drain regions; a bottom electrode of a capacitor structure included in the memory cell structure may be formed on the source / drain interconnect structure; a hydrogen absorption layer of the capacitor structure may be formed above the bottom electrode; and / or a top electrode of the capacitor structure may be formed above the hydrogen absorption layer, and so on. One or more of the semiconductor processing tools 102-112 may perform other semiconductor processing operations described herein, such as in combination with 4A to 4T , 6A to 6F , FIG. 8A to FIG. 8O , FIG. 10A to FIG. 10F , Fig.12 and / or Figure 13.

[0036] Figure 1 The number and arrangement of devices shown are provided as one or more examples. In practice, there may be more than Figure 1 Additional devices, fewer devices, different devices, or differently arranged devices as shown in . In addition, Figure 1 Two or more devices shown in the figure may be implemented in a single device, or in a single device. Figure 1 The illustrated apparatus may be implemented as multiple distributed apparatuses. Additionally or alternatively, one set of apparatuses (eg, one or more apparatuses) of the example environment 100 may perform one or more functions described as being performed by another set of apparatuses of the example environment 100.

[0037] FIG. 2A to FIG. 2C is a diagram of an example semiconductor device 200 described herein. Specifically, Figure 2A FIG. 2 shows a top view of a back-end-of-line (BEOL) region of a semiconductor device 200 . Figure 2B Shown along Figure 2A Cross-sectional view of the BEOL region in section AA. Figure 2C Shown along Figure 2A BB in FIG. 1 is a cross-sectional view of the BEOL region of the semiconductor device 200. The semiconductor device 200 includes an example of a semiconductor device, such as a semiconductor memory component, an image sensor component (e.g., a complementary metal oxide semiconductor (CMOS) image sensor (CIS) component), a semiconductor logic component (e.g., a processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP)), an input / output device, an application specific integrated circuit (ASIC), or another type of semiconductor device. In some embodiments, the semiconductor device 200 includes a front end of line (FEOL) region that includes integrated circuits connected to the BEOL region of the semiconductor device 200.

[0038] like Figure 2A As shown, semiconductor device 200 may include a memory array including a plurality of memory cell structures 202. The memory array may be included in one or more back-end process dielectric layers (e.g., BEOL dielectric layers) in BEOL. Memory cell structures 202 may include volatile memory structures, such as DRAM memory structures and / or another type of volatile memory structures.

[0039] The memory cell structure 202 in the memory array may include a gate structure 204, a channel layer 206 above the gate structure 204, and a plurality of source / drain regions 208 and 210 above the channel layer 206. The gate structure 204, the channel layer 206, and the source / drain regions 208 and 210 may correspond to transistor structures of the memory cell structure 202. The source / drain region used herein may refer to a source region, a drain region, or both a source region and a drain region, depending on the context. The memory cell structure 202 may also include an interconnect structure 212 above the source / drain region 208, an interconnect structure 214 above the source / drain region 210, a capacitor structure 216 above the interconnect structure 214, and a bit line conductive structure 218 thereon. The interconnect structure 212 may electrically couple the transistor of the memory cell structure 202 with the bit line conductive structure 218, and the interconnect structure 214 may electrically couple the transistor of the memory cell structure 202 with the capacitor structure 216. Capacitor structure 216 may be configured to selectively store charge of memory cell structure 202, such that memory cell structure 202 can store one or more logic values ​​based on the amount of charge stored in capacitor structure 216. Capacitor structure 216 may be referred to as a charge-based programmable memory cell of memory cell structure 202.

[0040] like Figure 2A As further shown, one or more bit line conductive structures 218 in the memory array can extend in a first direction (e.g., the x-direction) in the semiconductor device 200. One or more gate structures 204 in the memory array can extend in a second direction (e.g., the y-direction) in the semiconductor device 200 that is approximately orthogonal to the first direction. This enables the gate structure 204 to span across multiple memory cell structures 202 in the memory array, and enables a single bit line conductive structure 218 to span across multiple memory cell structures 202 in the memory array. Therefore, the memory cell structures 202 in the memory array can be arranged in a grid, and each is electrically coupled to a single gate structure 204 and a bit line conductive structure 218, which enables each memory cell structure 202 in the memory array to be accessed through a specific combination of the gate structure 204 and the bit line conductive structure 218.

[0041] In some implementations, one or more channel layers 206 in the memory array may extend in a first direction in the semiconductor device 200 and may span across multiple memory cell structures 202. The source / drain regions 208 and the source / drain regions 210 may extend along a second direction. In some embodiments, each memory cell structure 202 may include its own set of source / drain regions 208 and 210 and a single channel layer 206 coupled to the source / drain regions 208 and 210. Thus, the memory cell structure 202 may be referred to as a single-channel memory cell structure. The source / drain regions 208 and 210 may be included directly above and / or within the periphery of the gate structure 204.

[0042] In some embodiments, dielectric layers 220 and 222 may be included to provide electrical isolation between source / drain regions 208 and / or 210. Dielectric layer 220 may provide electrical isolation along the x-direction between adjacent source / drain regions 208 and / or 210. Dielectric layer 222 may provide electrical isolation along the y-direction between two or more source / drain regions 208 and / or between two or more source / drain regions 210.

[0043] Figure 2B shows a memory cell structure 202 along Figure 2A The cross-sectional view along section AA is shown. The cross-sectional view along section AA includes the interconnect structure 214 and the capacitor structure 216 of the memory cell structure 202 .

[0044] like Figure 2B As shown, the memory cell structure 202 may be included in one or more back-end layers of the semiconductor device 200. The back-end dielectric layer (e.g., BEOL layer or BEOL dielectric layer) may include a dielectric layer 224, which includes a gate structure 204 of the memory cell structure 202. The dielectric layer 224 may include one or more layers, such as a passivation layer 226, an etch stop layer (ESL) 228, and / or an isolation layer 230. The gate structure 204 may include one or more liner layers 232 and 234 located between a gate electrode 236 of the gate structure 204 and the dielectric layer 224.

[0045] The passivation layer 226 may include one or more high dielectric constant (high-k) dielectric materials to provide etch selectivity relative to the isolation layer 230. Examples of high-k dielectric materials include dielectric materials having a dielectric constant greater than the dielectric constant of silicon oxide (approximately 3.6), such as silicon oxynitride (SiON). x ) and / or silicon nitride (Si x N y ) etc. The ESL 228 may include aluminum oxide (AlO x ), aluminum nitride (AlN x) and / or another suitable ESL material. The isolation layer 230 may include one or more low dielectric constant (low-k) dielectric materials, such as silicon oxide (SiO x ), fluorine-doped silicate glass (FSG) and / or another low-k dielectric material.

[0046] The gate electrode 236 may include polysilicon (e.g., polysilicon), one or more conductive materials such as tungsten (W) and / or aluminum (Al), one or more high-k materials, and / or combinations thereof. The liner 232 and / or 234 may include an adhesion liner (e.g., included to facilitate adhesion between the gate electrode 236 and the dielectric layer 224), a barrier layer (e.g., included to reduce or minimize diffusion of the material of the gate electrode 236 into the dielectric layer 224), and / or another type of liner. Examples of materials for the liner 232 and / or 234 include tantalum nitride (TaN) and / or titanium nitride (TiN), among others.

[0047] Gate dielectric layer 238 may be included on and / or over gate structure 204. Gate dielectric layer 238 may be included on dielectric layer 224. Gate dielectric layer 238 may include one or more dielectric materials, such as hafnium oxide (HfO2, etc.). x ), silicon oxide (SiO2 etc. x ), alumina (Al2O3 etc. x O y )、Zirconium oxide (Zr x O y ), titanium oxide (Ti x O y )) and / or silicon oxynitride (SiON), etc.

[0048] Channel layer 206 may be included on and / or above gate dielectric layer 238. In this manner, gate dielectric layer 238 is located between gate structure 204 and channel layer 206. Channel layer 206 may include one or more metal oxide materials or metal oxide semiconductor materials. In some embodiments, channel layer 206 is an n-type channel including tin oxide (SnO x , such as SnO2), indium oxide (In x O y , such as In2O3), zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO or IGZO), and / or other n-type metal oxide materials. In some embodiments, the channel layer 206 is a p-type channel, which includes nickel oxide (NiO), copper oxide (Cu x O, such as Cu2O), copper aluminum oxide (CuAlO x , such as CuAlO2), copper gallium oxide. (CuGaO x Such as CuGaO2), copper indium oxide (CuInOx Such as CuInO2), strontium cuprate (SrCu x O y Such as SrCu2O2), tin oxide (SnO) and / or another p-type metal oxide material.

[0049] Semiconductor device 200 may include additional back-end dielectric layers, such as dielectric layer 220 above channel layer 206. Dielectric layer 220 may include one or more layers, such as isolation layer 240, ESL 242, and source / drain regions 208 and 210 of memory cell structure 202 may be included in dielectric layer 220. Source / drain regions 208 and 210 may each include one or more liner layers 246 and / or 248, and source / drain regions 208 and 210 may be included on and / or over channel layer 206. Source / drain regions 208 and 210 may be electrically coupled to channel layer 206 such that current is selectively allowed to flow between source / drain regions 208 and 210 through channel layer 206.

[0050] Isolation layers 240 and 244 may each include one or more low-k dielectric materials, such as silicon oxide (SiO x ), FSG and / or another low-k dielectric material. The ESL 242 may include aluminum oxide (AlO x ), aluminum nitride (AlN x ) and / or another suitable ESL material.

[0051] One or more liners 246 and / or 248 of the source / drain regions 208 and / or 210 may include a barrier liner to prevent material from migrating from the electrode 250 into the surrounding dielectric layer 220, an adhesion layer to promote adhesion between the electrode 250 and the surrounding dielectric layer 220, and / or another type of liner. Examples of materials for the electrode 250 of the source / drain regions 208 and / or 210 include polysilicon, copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), and / or aluminum (Al), among others. Examples of liners 246 and / or 248 include tantalum nitride (TaN), titanium nitride (TiN), indium tin oxide (ITO), and / or another suitable liner, among others.

[0052] The gate structure 204, the gate dielectric layer 238, the channel layer 206, and the source / drain regions 208 and 210 may correspond to the transistor structure 252 of the memory cell structure 202. The gate structure 204 of the transistor structure 252 may be included below the channel layer 206 (e.g., in the z-direction in the semiconductor device 200) and below the source / drain regions 208 and 210. Therefore, the gate structure 204 may be referred to as a bottom gate.

[0053] The transistor structure 252 can be electrically coupled to the capacitor structure 216 over the transistor structure 252 via the interconnect structure 214. The transistor structure 252 can be configured to selectively control access to the capacitor structure 216. For example, the transistor structure 252 can be activated to enable charge to be provided to the capacitor structure 216 via the transistor structure 252. As another example, the transistor structure 252 can be deactivated to enable charge to be stored (e.g., retained) in the capacitor structure 216. As another example, the transistor structure 252 can be activated to perform a "read" operation, in which the charge stored in the capacitor structure 216 is discharged through the transistor structure 252 and measured.

[0054] In some embodiments, the memory cell structure 202 can be physically and / or electrically coupled to a word line conductive structure (not shown) below the transistor structure 252. The word line conductive structure can also be referred to as an access line conductive structure, and includes, among other examples, a select line conductive structure, an address line conductive structure, and / or a row line conductive structure. The word line conductive structure can be configured to selectively provide a voltage or current to the gate structure 204 of the transistor structure 252 for performing an access operation associated with the memory cell structure 202.

[0055] The interconnect structure 214 may be included in one or more back-end dielectric layers, such as the passivation layer 254 and / or the isolation layer 256 over the passivation layer 254. The interconnect structure 214 may be included on the source / drain region 210 and may be electrically and / or physically coupled to the source / drain region 210.

[0056] The passivation layer 254 may include one or more high-k dielectric materials, such as silicon oxynitride (SiON). x ) and / or silicon nitride (Si x N y ) etc. The isolation layer 256 may include one or more low-k dielectric materials, such as silicon oxide (SiO x ), FSG and / or another low-k dielectric material.

[0057] The interconnect structure 214 may include a through hole, a plug, a trench, a dual damascene structure, and / or another type of conductive structure. The interconnect structure 214 may include one or more liners 258 and an electrode 260. The electrode 260 may include one or more conductive materials, such as copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au), and / or silver (Ag). One or more liners 258 may be included between the electrode 260 and the passivation layer 254 and / or the isolation layer 256. The one or more liners 258 may include a barrier liner to prevent material from migrating from the electrode 260 to the passivation layer 254 and / or the isolation layer 256, an adhesion layer to promote adhesion between the electrode 260 and the passivation layer 254 and / or the isolation layer 256, and / or another type of liner. Examples of materials included in the liner 258 include tantalum nitride (TaN), titanium nitride (TiN), and / or another suitable liner.

[0058] The capacitor structure 216 may include a deep trench capacitor (DTC) having a relatively high aspect ratio between the height of the capacitor structure 216 and the width or critical dimension (CD) of the capacitor structure 216. Alternatively, the capacitor structure 216 may include a planar capacitor and / or another type of capacitor structure. The bottom surface of the capacitor structure 216 may be electrically and / or physically coupled to the interconnect structure 214. The capacitor structure 216 may include one or more back-end dielectric layers of the semiconductor device 200, such as the ESL 262, the passivation layer 264, and / or the isolation layer 266.

[0059] The ESL 262 may include aluminum oxide (AlO x ), aluminum nitride (AlN x ) and / or another suitable ESL material. The passivation layer 264 may include one or more high-k dielectric materials, such as silicon oxynitride (SiON) x ) and / or silicon nitride (Si x N y ) etc. The isolation layer 266 may include a low-k dielectric material such as silicon oxide (SiO x ), FSG and / or another low-k dielectric material.

[0060] Capacitor structure 216 may include a bottom electrode 268 on and / or over the sidewalls and bottom surface of capacitor structure 216. Bottom electrode 268 may include a first bottom electrode layer 268a and a second bottom electrode layer 268b. First bottom electrode layer 268a and second bottom electrode layer 268b may each include a conductive (or semiconductor) material, such as tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), aluminum (Al), polysilicon, and / or other suitable materials.

[0061] Capacitor structure 216 may also include a hydrogen absorbing layer 270 between first bottom electrode layer 268a and second bottom electrode layer 268b. Thus, hydrogen absorbing layer 270 may be included on and / or over first bottom electrode layer 268a, and second bottom electrode layer 268b may be included on and / or over hydrogen absorbing layer 270. Hydrogen absorbing layer 270 may conform to the contour of the deep trench capacitor structure of capacitor structure 216. The hydrogen absorbing layer may include a metal oxide material (or metal oxide semiconductor material) that easily absorbs hydrogen (H). Examples of metal oxide materials may include indium oxide (In2O3). x O y Such as In2O3, titanium oxide (TiO x Such as TiO2, ITO, indium tin oxide (ITO), cerium oxide, zinc oxide (CeO x ), zinc oxide (ZnO) and / or indium gallium zinc oxide (IGZO).

[0062] The metal oxide material of the hydrogen absorbing layer 270 may absorb and retain hydrogen before the hydrogen diffuses downward into the metal oxide material of the channel layer 206. At least some of the back-end dielectric layers (and / or other layers) may be deposited using a deposition technique in which hydrogen is used as a carrier gas and / or purge gas, resulting in difficulty in regulating the hydrogen content in the semiconductor device 200. In addition, the metal layers of the capacitor structure 216, the interconnect structure 214, and / or the source / drain region 210 may generally have a low hydrogen migration energy, allowing hydrogen to quickly diffuse through these structures and into the channel layer 206. Thermal treatment operations of the semiconductor device 200 may further promote the diffusion of hydrogen downward into the channel layer 206. The hydrogen may ionize and combine with oxygen in the metal oxide material of the channel to form oxygen-hydrogen (OH) bonds.

[0063] On the contrary, the hydrogen absorbing layer 270 can absorb hydrogen before the hydrogen diffuses downward into the metal oxide material of the channel layer 206. Specifically, the metal oxide material of the hydrogen absorbing layer 270 captures free electrons in the surrounding area and combines the free electrons with ionized hydrogen to generate free electrons, so that the ionized hydrogen remains fixed in the hydrogen absorbing layer 270. The chemical reaction of absorbing ionized hydrogen in the hydrogen absorbing layer 270 can be expressed as:

[0064] MO x +H + +e - →M(OH) x

[0065] Where M refers to the metal component of the metal oxide material. Thus, the hydrogen absorbing layer 270 may be deposited as a metal oxide layer and may subsequently include one or more metal hydroxide materials (e.g., In(OH) x、Ti(OH) x 、Zn(OH) x ).

[0066] In some embodiments, the thickness of the hydrogen absorbing layer 270 is included in the range of about 1 nanometer to about 100 nanometers. If the thickness of the hydrogen absorbing layer 270 is less than about 1 nanometer, the hydrogen absorbing layer 270 may not provide sufficient hydrogen absorption, resulting in an increased amount of hydrogen diffusion in the channel layer 206. When the hydrogen absorbing layer 270 is greater than about 100 nanometers, the hydrogen absorbing layer 270 may occupy a large amount of volume of the capacitor structure 216, thereby reducing the available volume of the electrodes of the capacitor structure 216. This may increase the resistivity of the capacitor structure 216 and reduce the capacitance of the capacitor structure 216. If the thickness of the hydrogen absorbing layer 270 is included in the range of about 1 nanometer to about 100 nanometers, a sufficient amount of hydrogen absorption can be achieved, and a sufficiently low resistance and a sufficiently high capacitance can be achieved for the capacitor structure 216. However, other values ​​of the thickness of the hydrogen absorbing layer 270 and ranges other than about 1 nanometer to about 100 nanometers are also within the scope of the present disclosure.

[0067] Capacitor structure 216 may also include dielectric layer 272 on and / or over bottom electrode 268 (e.g., on and / or over second bottom electrode layer 268b). Dielectric layer 272 may include a high-k dielectric material that enables high capacitance of capacitor structure 216. Examples of high-k dielectric materials that may be included in dielectric layer 272 of capacitor structure 216 include zirconium oxide (ZrO x , such as ZrO2), hafnium oxide (HfO x , such as HfO2), hafnium zirconium oxide (HZO), zirconium aluminum oxide (ZAO), silicon-doped hafnium oxide (HSO) and / or other high-k dielectric materials. Separating the bottom electrode 268 into a first bottom electrode layer 268a and a second bottom electrode layer 268b enables the hydrogen absorbing layer 270 to be formed such that the hydrogen absorbing layer 270 is not in direct contact with the dielectric layer 272, which may otherwise cause the hydrogen absorbing layer 270 to be in direct contact with the dielectric layer 272, which may cause a reverse reaction between the high-k material of the dielectric layer 272 and the hydrogen absorbing layer 270. In this way, forming the hydrogen absorbing layer 270 such that the hydrogen absorbing layer 270 is not in direct contact with the dielectric layer 272 can achieve low surface roughness of the layers of the capacitor structure 216, which can enable the capacitor structure 216 to achieve high capacitance values ​​and / or low resistance.

[0068] Top electrode 274 may be included on and / or over dielectric layer 272. Top electrode 274 may include a conductive (or semiconductor) material such as tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), aluminum (Al), polysilicon, and / or other suitable materials.

[0069] Figure 2C shows a memory cell structure 202 along Figure 2A Another cross-sectional view along the cross-sectional plane BB is shown. The cross-sectional view along the cross-sectional plane BB includes the interconnect structure 212 and the bit line conductive structure 218 of the memory cell structure 202 .

[0070] like Figure 2C As shown, the source / drain region 208 can be electrically and / or physically coupled to the interconnect structure 212. The interconnect structure 212 can be included in the passivation layer 254 above the source / drain region 208. The interconnect structure 212 can electrically couple the source / drain region 208 to the bit line conductive structure 218 above the interconnect structure 212. The interconnect structure 212 can include one or more liner layers 258 and an electrode 260. The electrode 260 can include one or more conductive structural materials, such as copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au) and / or silver (Ag), etc. One or more liner layers 258 can be included between the electrode 260 and the passivation layer 254 and / or the isolation layer 256. Examples of materials included in the liner layer 258 include tantalum nitride (TaN), titanium nitride (TiN) and / or another suitable liner layer, etc.

[0071] The bit line conductive structure 218 may also be referred to as a column line conductive structure. The bit line conductive structure 218 may be located on and / or above the interconnect structure 212 and may be configured to selectively receive current from the capacitor structure 216 or provide current to the capacitor structure 216 through the transistor structure 252. The bit line conductive structure 218 may include one or more conductive materials, such as copper (Cu), cobalt (Co), ruthenium (Ru), titanium (Ti), tungsten (W), gold (Au) and / or silver (Ag), among other examples.

[0072] As mentioned above, FIG. 2A to FIG. 2C Other examples can be found in the FIG. 2A to FIG. 2C Different than described.

[0073] FIG. 3A to FIG. 3C is a graph of examples of parameters associated with a memory cell structure including the hydrogen absorbing layer 270 described herein. Figure 3A An example 300 of threshold voltage (Vts) 302 as a function of gate length (Lg) of transistor structure 252 included in a memory cell structure is shown. Figure 3AAs shown, data graph 306 corresponds to a memory cell structure including a hydrogen absorbing layer 270, wherein the hydrogen absorbing layer 270 has a first thickness. Data graph 308 corresponds to another memory cell structure including another hydrogen absorbing layer 270 having a second thickness. The first thickness may be greater than the second thickness. As shown in data graphs 306 and 308, a hydrogen absorbing layer 270 having a greater thickness is generally capable of achieving a greater threshold voltage 302 for the same gate length 304. This may be due to the hydrogen absorbing layer 270 having a greater thickness being able to better absorb hydrogen that would otherwise contaminate the channel layer of the memory cell structure and reduce the threshold voltage 302.

[0074] Example 310 of reduced threshold voltage (Vts) 302 as a function of stress time 312 of a memory cell structure. Figure 3B As shown, data group 314 corresponds to a memory cell structure including hydrogen absorbing layer 270, and data group 316 corresponds to another memory cell structure not including hydrogen absorbing layer 270. Due to the hydrogen diffusion barrier of hydrogen absorbing layer 270, the impact of NBTI on the memory cell structure can be reduced and / or minimized. In the absence of hydrogen absorbing layer 270, as the stress time 312 increases, hydrogen diffusion can cause a decrease in the threshold voltage, as shown in data group 316.

[0075] Figure 3C An example 318 of hydrogen concentration 320 as a function of horizontal position 322 of channel layer 206 in transistor structure 252 along multiple memory cell structures is shown. Data graphs 324-330 may correspond to increasing thickness of hydrogen absorbing layer 270, respectively. Figure 3C As shown, the hydrogen concentration 320 may generally decrease as the thickness of the hydrogen absorbing layer 270 increases.

[0076] As mentioned above, FIG. 3A to FIG. 3C Other examples can be found in the FIG. 3A to FIG. 3C Different than described.

[0077] 4A to 4T is a diagram of an example implementation 400 of a memory cell structure 202 that forms a semiconductor device 200 described herein. In some implementations, in combination with 4A to 4T One or more of the processing operations may be performed using one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114. In some embodiments, in combination with 4A to 4T One or more of the described processing operations may be performed using another semiconductor processing tool not shown.

[0078] Steering Figure 4A , which can be performed after the front-end processing of the semiconductor device 200 4A to 4TThus, the memory cell structure 202 may be formed in a back-end region (eg, BEOL region) of the semiconductor device 200. Figure 4A As shown, a dielectric layer 224 may be formed. The deposition tool 102 may use CVD technology, PVD technology, ALD technology, or a combination of the above. Figure 1 The dielectric layer 224 is deposited using another deposition technique and / or a deposition technique in addition to the deposition techniques described above. In some embodiments, depositing the dielectric layer 224 includes depositing a passivation layer 226, depositing an ESL 228 on the passivation layer 226, and depositing an isolation layer 230 on the ESL 228.

[0079] like Figure 4B and Figure 4C As shown, the gate structure 204 of the transistor structure 252 of the memory cell structure 202 may be formed on the dielectric layer 224. The gate structure 204 may extend in the y direction of the semiconductor device 200, such as Figure 4B The dielectric layer 224 can electrically isolate adjacent gate structures 204 in the semiconductor device 200. Figure 4C As shown, forming gate structure 204 may include forming liner 232 and / or 234 in the recess in dielectric layer 224 , and forming gate electrode 236 on and / or over liner 232 and / or 234 .

[0080] The grooves can be formed in the dielectric layer 224 and / or through the dielectric layer 224 (e.g., formed in the passivation layer 226, the ESL 228, and the isolation layer 230 and / or through the dielectric layer 224). In some embodiments, the pattern in the photoresist layer is used to form the grooves in the dielectric layer 224. In these embodiments, the deposition tool 102 is used to form the photoresist layer on the dielectric layer 224. The exposure tool 104 exposes the photoresist to a radiation source to pattern the photoresist layer. The development tool 106 develops and removes portions of the photoresist layer to reveal the pattern. The etching tool 108 etches into the dielectric layer 224 based on the pattern to form the grooves. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, the photoresist removal tool can remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to forming grooves based on a pattern.

[0081] To form the gate structure 204 in the recess, the deposition tool 102 and / or the electroplating tool 112 may be used to form the gate structure 204 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, or a combination thereof. Figure 1 Another deposition technique described, and / or different from the above combination Figure 1 The described deposition technique deposits gate electrode 236 on and / or over liner 232 and / or 234 in the recess. In some embodiments, a seed layer is first deposited on liner 232 and / or 234, and gate electrode 236 is deposited on the seed layer, wherein the seed layer promotes adhesion between liner 232 and / or 234 and gate electrode 236. In some embodiments, planarization tool 110 is used to planarize liner 232 and / or 234 and / or gate electrode 236.

[0082] like Figure 4D and 4E As shown, multiple layers may be formed on and / or over dielectric layer 224 and on and / or over gate structure 204. For example, gate dielectric layer 238 may be formed on and / or over dielectric layer 224 and gate structure 204. As another example, channel layer 206 may be formed on and / or over gate dielectric layer 238. Deposition tool 102 may use CVD techniques, PVD techniques, ALD techniques, oxidation techniques, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above in combination Figure 1 The gate dielectric layer 238 may be deposited using a deposition technique other than the deposition techniques described above. The planarization tool 110 may be used to planarize the gate dielectric layer 238. The deposition tool 102 may be used to use a CVD technique, a PVD technique, an ALD technique, an oxidation technique, another deposition technique described above, and / or a combination thereof. Figure 1 The channel layer 206 can be deposited using a deposition technique other than the deposition techniques described above. In some embodiments, the planarization tool 110 can be used to planarize the channel layer 206 .

[0083] like Figure 4F and Figure 4G As shown, dielectric layers 220 and 222 may be formed. Deposition tool 102 may be used to deposit dielectric layers using CVD techniques, PVD techniques, ALD techniques, oxidation techniques, or a combination of the above. Figure 1 Another deposition technique described and / or in addition to the above in combination Figure 1 In some embodiments, the dielectric layers 220 and 222 are deposited using a deposition technique other than that described above. In some embodiments, the planarization tool 110 can be used to planarize the dielectric layers 220 and 222. In some embodiments, depositing the dielectric layer 220 includes depositing the isolation layer 240, depositing the ESL 242 on the isolation layer 240, and depositing the isolation layer 244 on the ESL 242.

[0084] like Figure 4F and Figure 4G As shown, the source / drain regions 208 and 210 of the memory cell structure 202 may be formed in the dielectric layer 220. The source / drain regions 208 and 210 may extend along the y direction in the semiconductor device 200, such as Figure 4F The dielectric layer 220 can electrically isolate adjacent source / drain regions 208 and 210 in the x-direction in the semiconductor device 200. The dielectric layer 222 can electrically isolate adjacent source / drain regions 208 and adjacent source / drain regions 210 in the y-direction. Figure 4G As shown, forming source / drain regions 208 or 210 may include forming liner 246 and / or 248 in the recess in dielectric layer 220 , and forming electrode 250 on and / or over liner 246 and / or 248 .

[0085] Recesses for source / drain regions 208 and 210 of transistor structures 252 of memory cell structure 202 may be formed above gate structure 204 and in and / or through dielectric layer 220. In this manner, source / drain regions 208 and source / drain regions 210 may be located in channel layer 206 above gate structure 204. Recesses may be formed in and / or through isolation layer 240, ESL 242, and isolation layer 244. In some embodiments, a pattern in a photoresist layer on dielectric layer 220 is used to form recesses in dielectric layer 220. In these embodiments, deposition tool 102 is used to form a photoresist layer on dielectric layer 220. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops and removes portions of the photoresist layer to reveal the pattern. The etching tool 108 etches into the dielectric layer 220 based on the pattern to form the grooves. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, the photoresist removal tool can remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to form the grooves based on the pattern.

[0086] To form the source / drain region 208 or the source / drain region 210 in the recess of the dielectric layer 220, the deposition tool 102 and / or the electroplating tool 112 may be used to deposit the liner layer 246 and / or 248, for example, using CVD technology, PVD technology, ALD technology, electroplating technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique described above and / or in addition to the above in combination Figure 1 The liner 246 may be disposed on the channel layer 206 directly above the gate structure 204. The deposition tool 102 and / or the electroplating tool 112 may use CVD technology, PVD technology, ALD technology, electroplating technology, epitaxial technology, or a combination of the above. Figure 1 Another deposition technique described above and / or in addition to the above in combination Figure 1Electrode 250 is deposited on and / or over liner 246 and / or 248 in the recess using a deposition technique other than that described above. In some embodiments, a seed layer is first deposited on liner 246 and / or 248, and electrode 250 is deposited on the seed layer, wherein the seed layer promotes adhesion between liner 246 and / or 248 and electrode 250. In some embodiments, planarization tool 110 is used to planarize liner 246 and / or 248 and / or electrode 250.

[0087] like Figure 4H and 4I As shown, an interconnect structure 212 (e.g., source / drain contacts, source / drain interconnect structures) of the memory cell structure 202 may be formed on and / or over the source / drain region 208. The interconnect structure 212 may be bonded to the source / drain region 208 such that the interconnect structure 212 is physically and / or electrically coupled to the source / drain region 208. Fig. 4I As shown, the interconnect structure 212 may be formed in a passivation layer 254 overlying the dielectric layer 220. The interconnect structure 212 may be formed in a recess in the passivation layer 254.

[0088] Passivation layer 254 of the back-end region of semiconductor device 200 may be deposited on and / or over dielectric layer 220. Deposition tool 102 may be used to deposit a passivation layer 254 on and / or over dielectric layer 220 using CVD techniques, PVD techniques, ALD techniques, oxidation techniques, or a combination of the above. Figure 1 Another deposition technique described above and / or in addition to the above in combination Figure 1 The passivation layer 254 may be deposited using a deposition technique other than the described deposition techniques. In some implementations, the planarization tool 110 may be used to planarize the passivation layer 254 .

[0089] In some embodiments, the pattern in the photoresist layer is used to form a groove in the passivation layer 254 above the source / drain region 208. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the passivation layer 254. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch into the passivation layer 254 based on the pattern to form the groove. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, the photoresist removal tool can remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to form grooves based on the pattern.

[0090] The deposition tool 102 and / or the electroplating tool 112 can be used to deposit the interconnect structure 212 in the groove. For example, the deposition tool 102 and / or the electroplating tool 112 can be used to deposit the interconnect structure 212 in the groove using CVD technology, PVD technology, ALD technology, electroplating technology, oxidation technology, a combination of the above, Figure 1 Another deposition technique described, and / or in addition to the above combined Figure 1 The liner 258 of the interconnect structure 212 is deposited in the recess using a deposition technique other than the deposition technique described above. As another example, the deposition tool 102 and / or the electroplating tool 112 may use CVD technology, PVD technology, ALD technology, electroplating technology, a combination of the above, Figure 1 Another deposition technique described above and / or in addition to the above combination Figure 1 The electrode 260 of the interconnect structure 212 may be deposited on the liner 258 in the recess using a deposition technique other than the deposition techniques described above. In some embodiments, the planarization tool 110 may be used to planarize the interconnect structure 212. In some embodiments, a seed layer is deposited in the interconnect structure 212. The recess is formed before forming the electrode 260 to promote adhesion between the liner 258 and the electrode 260.

[0091] like Figure 4J and 4K As shown, the bit line conductive structure 218 of the memory cell structure 202 can be formed above the interconnect structure 212, so that the bit line conductive structure 218 is located above the transistor structure 252. The bit line conductive structure 218 can fall on the interconnect structure 212. The interconnect structure 212 couples the interconnect structure 212 with the bit line conductive structure 218. In this way, the interconnect structure 212 electrically couples the transistor structure 252 with the bit line conductive structure 218. The bit line conductive structure 218 can extend in the x-direction in the semiconductor device 200.

[0092] The deposition tool 102 and / or the electroplating tool 112 may be used to utilize CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above in combination Figure 1 The bit line conductive structure 218 is deposited using a deposition technique other than the above-described deposition techniques. In some embodiments, the planarization tool 110 is used to planarize the bit line conductive structure 218 .

[0093] like Figure 4L and 4M As shown, the interconnect structure 214 (e.g., source / drain contact, source / drain interconnect structure) of the memory cell structure 202 can be formed on and / or above the source / drain region 210. The interconnect structure 214 can be bonded to the source / drain region 210 so that the interconnect structure 214 is physically and / or electrically coupled to the source / drain region 210. Figure 4M As shown, interconnect structure 214 may be formed in passivation layer 254 and interconnect structure 214 may be formed in isolation layer 256 over passivation layer 254. Interconnect structure 214 may be formed in recesses in passivation layer 254 and isolation layer 256.

[0094] Isolation layer 256 of the back-end region of semiconductor device 200 may be deposited on and / or over passivation layer 254. Deposition tool 102 may be used to deposit a passivation layer 254 using CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique described above and / or in addition to the above in combination Figure 1 The isolation layer 256 may be deposited using a deposition technique other than the described deposition techniques. In some embodiments, the planarization tool 110 may be used to planarize the isolation layer 256 .

[0095] In some embodiments, the pattern in the photoresist layer is used to form grooves in the passivation layer 254 and in the isolation layer 256 above the source / drain region 210. In these embodiments, the deposition tool 102 can be used to form the photoresist layer on the isolation layer 256. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch into the passivation layer 254 and the isolation layer 256 based on the pattern to form grooves. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, the photoresist removal tool can remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to form grooves based on a pattern.

[0096] The deposition tool 102 and / or the electroplating tool 112 can be used to deposit the interconnect structure 214 in the recess. For example, the deposition tool 102 and / or the electroplating tool 112 can be used to deposit the interconnect structure 214 in the recess using CVD technology, PVD technology, ALD technology, electroplating technology, oxidation technology, a combination of the above, Figure 1 Another deposition technique described, and / or in addition to the above combined Figure 1 The liner 258 of the interconnect structure 214 is deposited in the recess using a deposition technique other than the deposition technique described above. As another example, the deposition tool 102 and / or the electroplating tool 112 may use CVD technology, PVD technology, ALD technology, electroplating technology, a combination of the above, Figure 1 Another deposition technique described above and / or in addition to the above in combination Figure 1The electrode 260 of the interconnect structure 214 may be deposited on the liner 258 in the recess by a deposition technique other than the deposition techniques described above. In some embodiments, the planarization tool 110 may be used to planarize the interconnect structure 214. In some embodiments, a seed layer is deposited in the recess in the interconnect structure 214 before forming the electrode 260 to promote adhesion between the liner 258 and the electrode 260.

[0097] like Figure 4N As shown, the capacitor structure 216 of the memory cell structure 202 may be formed above the interconnect structure 214 of the memory cell structure 202. The capacitor structure 216 may be electrically coupled to the transistor structure 252 through the interconnect structure 214. FIG. 4O to FIG. 4T Example operations for forming capacitor structure 216 are shown.

[0098] like Fig.4O As shown, ESL 262 may be formed on and / or over isolation layer 256. Passivation layer 264 may be formed on and / or over ESL 262. Isolation layer 266 may be formed on and / or over passivation layer 264. Deposition tool 102 may be used to deposit a plurality of substrates using CVD techniques, PVD techniques, ALD techniques, oxidation techniques, or a combination of the above. Figure 1 Another deposition technique described above, and / or different from the above combined Figure 1 The described deposition techniques are used to deposit ESL 262 , passivation layer 264 , and / or isolation layer 266 . In some embodiments, planarization tool 110 is used to planarize ESL 262 , passivation layer 264 , and / or isolation layer 266 .

[0099] like Fig.4O As further shown, recess 402 is formed through ESL 262, passivation layer 264, and / or isolation layer 266. Recess 402 may be formed over interconnect structure 214 such that a top surface of interconnect structure 214 is exposed through recess 402.

[0100] In some embodiments, the pattern in the photoresist layer is used to form a groove 402 in the ESL 262, the passivation layer 264, and / or the isolation layer 266 above and onto the interconnect structure 214. In these embodiments, the deposition tool 102 can use the exposure tool 104 to form the photoresist layer on the isolation layer 266. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to reveal the pattern. The etching tool 108 can be used to etch into the ESL 262, the passivation layer 264, and / or the isolation layer 266 based on the pattern to form the groove 402. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. In some embodiments, the photoresist removal tool can remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to form the groove 402 based on the pattern.

[0101] like Figure 4P As shown, the first bottom electrode layer 268a of the bottom electrode 268 of the capacitor structure 216 can be formed in the groove 402. Specifically, the first bottom electrode layer 268a can be conformally deposited on the sidewalls and bottom surface of the groove 402, so that the first bottom electrode layer 268a conforms to the shape or contour of the groove 402. The bottom surface of the groove 402 can correspond to the top surface of the interconnect structure 214. Therefore, the first bottom electrode layer 268a is deposited on the top surface of the interconnect structure 214. The deposition tool 102 and / or the electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Another deposition technique described, and / or different from the above combination Figure 1 The first bottom electrode layer 268a is deposited using the described deposition techniques.

[0102] like Figure 4Q As shown, hydrogen absorbing layer 270 of capacitor structure 216 can be formed on and / or over first bottom electrode layer 268a. Specifically, hydrogen absorbing layer 270 can be conformally deposited over the sidewalls and over the bottom surface of recess 402, so that hydrogen absorbing layer 270 conforms to the shape or contour of recess 402. Deposition tool 102 and / or electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique and / or other than as described above in combination Figure 1 The hydrogen gettering layer 270 may be deposited using a deposition technique other than the one described above.

[0103] like Figure 4RAs shown, second bottom electrode layer 268b of bottom electrode 268 of capacitor structure 216 may be formed on and / or over hydrogen absorbing layer 270 in recess 402. Specifically, second bottom electrode layer 268b may be conformally deposited over the sidewalls and bottom surface of recess 402 such that second bottom electrode layer 268b conforms to the shape or contour of recess 402. Deposition tool 102 and / or electroplating tool 112 may be used to deposit the second bottom electrode layer 268b using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Another deposition technique described and / or in addition to the above in combination Figure 1 The second bottom electrode layer 268b may be deposited using a deposition technique other than the ones described above.

[0104] like Figure 4S As shown, dielectric layer 272 of capacitor structure 216 can be formed on and / or over second bottom electrode layer 268b. Specifically, dielectric layer 272 can be conformally deposited over the sidewalls and over the bottom surface of recess 402 so that dielectric layer 272 conforms to the shape or contour of recess 402. Deposition tool 102 and / or electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 The dielectric layer 272 is deposited by a deposition technique other than that described above.

[0105] like Figure 4T As shown, top electrode 274 of capacitor structure 216 may be formed on and / or over dielectric layer 272 in recess 402. Specifically, top electrode 274 may be deposited to fill the remaining volume in capacitor structure 216. Deposition tool 102 and / or electroplating tool 112 may be used to deposit the top electrode 274 using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, or a combination of the above. Figure 1 Another deposition technique described and / or in addition to the above in combination Figure 1 The top electrode 274 may be deposited using a deposition technique other than those described.

[0106] In some embodiments, the planarization tool 110 may be used to planarize the first bottom electrode layer 268a, the second bottom electrode layer 268b, the hydrogen absorbing layer 270, the dielectric layer 272, and / or the top electrode 274. In some embodiments, the first bottom electrode layer 268a, the second bottom electrode layer 268b, the hydrogen absorbing layer 270, the dielectric layer 272, and / or the top electrode 274 are deposited over the top surface of the isolation layer 266, and the planarization tool 110 is used to remove excess material from the top surface of the isolation layer 266.

[0107] After forming the capacitor structure 216, subsequent semiconductor processing operations may be performed to form layers and / or structures in the semiconductor device 200. For example, additional dielectric layers and / or additional metallization layers may be formed over the capacitor structure 216. The semiconductor processing operations may involve the use of hydrogen (e.g., as a carrier gas, as a purge gas, as an element of a deposited material) and / or thermal processing, any of which may cause hydrogen to diffuse downward into the memory cell structure into the capacitor structure 216, however, the hydrogen absorbing layer 270 in the capacitor structure 216 instead absorbs the hydrogen, thereby blocking, minimizing, and / or reducing the likelihood of hydrogen diffusion through the capacitor structure 216 and into the transistor structure 252. In this manner, the hydrogen absorbing layer 270 of the capacitor structure 216 may minimize and / or reduce the likelihood of contamination of the channel layer 206, which may minimize and / or reduce the likelihood of performance degradation and / or failure of the memory cell structure 202.

[0108] As mentioned above, 4A to 4T Other examples can be found in the 4A to 4T Different than described.

[0109] FIG. 5A to FIG. 5C is a diagram of an example semiconductor device 500 described herein. FIG. 5A to FIG. 5C As shown, semiconductor device 500 may include a memory array including a plurality of memory cell structures 502. The memory array may be included in one or more back-end dielectric layers (e.g., BEOL dielectric layers) in a BEOL region of semiconductor device 500. Memory cell structures 502 may include volatile memory structures, such as DRAM memory structures and / or another type of volatile memory structures.

[0110] like FIG. 5A to FIG. 5C As shown, the memory cell structure 502 may include a combination and arrangement of parts 204-276 similar to the memory cell structure 202. However, in the memory cell structure 502, the hydrogen absorbing layer 270 is included between the first top electrode layer 274a and the second top electrode layer 274b. Therefore, the capacitor structure 216 of the memory cell structure 502 may include the bottom electrode 268, the dielectric layer 272 between the bottom electrode 268 and the first top electrode layer 274a, and the hydrogen absorbing layer 270 between the first top electrode layer 274a and the second top electrode layer 274b.

[0111] As shown in the memory cell structure 202, including the hydrogen absorbing layer 270 between the first bottom electrode layer 268a and the second bottom electrode layer 268b provides a large radius area across which the hydrogen absorbing layer 270 can absorb hydrogen in the semiconductor device 200. As shown in the memory cell structure 502, including the hydrogen absorbing layer 270 between the first top electrode layer 274a and the second top electrode layer 274b provides flexibility in the thickness of the hydrogen absorbing layer 270 and enables the thickness of the hydrogen absorbing layer 270 to be reduced. The size of the hydrogen absorbing layer 270 is determined based on the aspect ratio of the capacitor structure 216.

[0112] As mentioned above, FIG. 5A to FIG. 5C Other examples can be found in the FIG. 5A to FIG. 5C Different than described.

[0113] 6A to 6F is a diagram of an example implementation 600 of a memory cell structure 502 that forms a semiconductor device 500 described herein. In some implementations, in combination with 6A to 6F One or more of the described processing operations may be performed using one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114. In some embodiments, the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 may be used in conjunction with the semiconductor processing tools 102-112. 6A to 6F One or more of the processing operations described uses Figure 1 The method may be performed by another semiconductor processing tool not shown.

[0114] like Fig. 6A As shown, the combination can be performed FIG. 4A to FIG. 4M One or more semiconductor processing operations are described to form components 204-214 and 218-266 of memory cell structure 502 of semiconductor device 500. Fig. 6A As further shown, recess 602 is formed through ESL 262, passivation layer 264, and / or isolation layer 266. Recess 602 may be formed over interconnect structure 214 such that a top surface of interconnect structure 214 is exposed through recess 602.

[0115] like Figure 6B As shown, the bottom electrode 268 of the capacitor structure 216 of the memory cell structure 502 can be formed in the groove 602. Specifically, the bottom electrode 268 can be conformally deposited on the sidewalls and bottom surface of the groove 602 of the memory cell structure 502. The bottom electrode 268 conforms to the shape or contour of the groove 602. The bottom surface of the groove 602 can correspond to the top surface of the interconnect structure 214. Therefore, the deposition tool 102 and / or the electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, and the above-described related Figure 1 Another deposition technique related to, and / or in addition to the above Figure 1The bottom electrode 268 may be deposited using a deposition technique other than the deposition techniques described above.

[0116] like Figure 6C As shown, dielectric layer 272 of capacitor structure 216 of memory cell structure 502 can be formed on and / or over bottom electrode 268. Specifically, dielectric layer 272 can be conformally deposited over the sidewalls of recess 602 and over the bottom surface such that dielectric layer 272 conforms to the shape or contour of recess 602. Deposition tool 102 and / or plating tool 112 can be used to deposit dielectric layer 272 using CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique described above, and / or in addition to the above Figure 1 The dielectric layer 272 may be deposited using a deposition technique other than those described.

[0117] like Fig.6D As shown, first top electrode layer 274a of top electrode 274 of capacitor structure 216 may be formed on and / or over dielectric layer 272 in recess 602. Specifically, first top electrode layer 274a may be formed on and / or over dielectric layer 272 in recess 602. First top electrode layer 274a may be conformally deposited on the sidewalls and bottom surface of recess 602 so that first top electrode layer 274a conforms to the shape or contour of recess 602. Deposition tool 102 and / or electroplating tool 112 may be used using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Another deposition technique and / or other than the above combination described Figure 1 The first top electrode layer 274a is formed by the described deposition techniques.

[0118] like Fig. 6E As shown, hydrogen absorbing layer 270 of capacitor structure 216 of memory cell structure 502 can be formed on and / or above first top electrode layer 274a. Specifically, hydrogen absorbing layer 270 can be conformally deposited on the sidewalls and bottom surface of recess 602 so that hydrogen absorbing layer 270 conforms to the shape or contour of recess 602. Deposition tool 102 and / or electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique as described above and / or a combination of Figure 1 The hydrogen absorbing layer 270 is deposited using deposition techniques other than those described.

[0119] like Fig. 6FAs shown, second top electrode layer 274b of top electrode 274 of capacitor structure 216 can be formed on and / or over hydrogen absorbing layer 270 in recess 602. Specifically, second top electrode layer 274b can be deposited to fill the remaining volume in recess 602. Deposition tool 102 and / or electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, a combination of the above Figure 1 Another deposition technique described, and / or a different one from the above combination Figure 1 The second top electrode layer 274b is deposited using the described deposition techniques.

[0120] In some embodiments, the planarization tool 110 may be used to planarize the bottom electrode 268, the hydrogen absorbing layer 270, the dielectric layer 272, the first top electrode layer 274a, and / or the second top electrode layer 274b. In some embodiments, the bottom electrode 268, the hydrogen absorbing layer 270, the dielectric layer 272, the first top electrode layer 274a, and / or the second top electrode layer 274b are deposited over the top surface of the isolation layer 266, and the planarization tool 110 is used to remove excess material from the top surface of the isolation layer 266.

[0121] After forming the capacitor structure 216, subsequent semiconductor processing operations may be performed to form layers and / or structures in the semiconductor device 500. For example, additional dielectric layers and / or additional metallization layers may be formed over the capacitor structure 216. The semiconductor processing operations may involve the use of hydrogen (e.g., as a carrier gas, as a purge gas, as an element of a deposited material) and / or thermal processing, any of which may cause hydrogen to diffuse downward into the memory cell structure 502 and contaminate the channel layer 206 of the transistor structure 252, which may result in performance degradation and / or failure of the memory cell structure 502. However, the hydrogen absorbing layer 270 in the capacitor structure 216 absorbs hydrogen, thereby blocking, minimizing and / or reducing the likelihood of hydrogen diffusing through the capacitor structure 216 and into the transistor structure 252. In this manner, the hydrogen absorbing layer 270 of the capacitor structure 216 may minimize and / or reduce the likelihood of hydrogen diffusing through the capacitor structure 216 and into the channel layer 206 of the transistor structure 252, which may minimize and / or reduce the likelihood of performance degradation and / or failure of the memory cell structure 502.

[0122] As mentioned above, 6A to 6F Other examples can be found in the 6A to 6F Different than described.

[0123] FIG. 7A to FIG. 7C is a diagram of an example semiconductor device 700 described herein. FIG. 7A to FIG. 7CAs shown, a semiconductor device 700 may include a memory array including a plurality of memory cell structures 702. The memory array may be included in one or more back-end dielectric layers (e.g., BEOL dielectric layers) in a BEOL region of the semiconductor device. The memory cell structures 702 may include volatile memory structures, such as DRAM memory structures and / or another type of volatile memory structures.

[0124] like FIG. 7A to FIG. 7C As shown, the memory cell structure 702 may include a combination and arrangement of components 204-276 similar to the memory cell structure 202. However, in the memory cell structure 702, the transistor structure 252 includes a dual-channel transistor structure as opposed to a single-channel transistor structure. Specifically, Figure 7B As shown, the source / drain region 210 coupled to the capacitor structure 216 through the interconnect structure 214 can be located directly above the gate structure 204, and the memory cell structure 702 can also include a plurality of source / drain regions 208a and 208b located above and adjacent to opposite sides of the gate structure 204. Therefore, the first channel in the channel layer 206 of the transistor structure 252 is located between the source / drain region 208a and the source / drain region 210, and the second channel in the channel layer 206 of the transistor structure 252 is located between the source / drain region 208b and the source / drain region 210. The source / drain regions 208a and 208b can each be electrically coupled and / or electrically coupled. or physically coupled to the same bit line conductive structure 218, or can be electrically coupled and / or physically coupled to different bit line conductive structures 218.

[0125] The dual channel configuration of transistor structure 252 of memory cell structure 702 enables memory cell structure 702 to achieve increased on-current (e.g., approximately twice the on-current) relative to memory cell structure 202. Memory cell structure 202 may provide reduced manufacturing complexity and increased memory cell density relative to memory cell structure 702.

[0126] As mentioned above, FIG. 7A to FIG. 7C Other examples can be found in the FIG. 7A to FIG. 7C Different than described.

[0127] FIG. 8A to FIG. 8O is a diagram of an example implementation 800 of a memory cell structure 702 that forms a semiconductor device 700 described herein. In some implementations, in combination with FIG. 8A to FIG. 8O One or more of the described processing operations may be performed using one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114. FIG. 8A to FIG. 8O One or more of the processing operations described may use Figure 1 The method may be performed by another semiconductor processing tool not shown.

[0128] like Fig. 8A and Figure 8B As shown, combined Fig. 8A and Figure 8B One or more semiconductor processing operations described include: performing FIG. 4A to FIG. 4G The semiconductor device 700 may be formed by a process to form the parts 204-210, 220-252 of the memory cell structure 702. However, additional semiconductor processing operations may be performed to form a plurality of source / drain regions 208, including a source / drain region 208a above the gate structure 204 in the memory cell structure 702 and a source / drain region 208b above the gate structure 204. The source / drain region 208a may be formed adjacent to a first side of the gate structure 204, and the source / drain region 208b may be formed adjacent to a portion of the side of the gate structure 204 opposite to the first side. The source / drain region 210 may be formed directly above the gate structure 204, such that a first channel is formed in the channel layer 206 between the source / drain region 208a and the source / drain region 210, and a second channel is formed in the channel layer 206 between the source / drain region 208b and the source / drain region 210. Thus, the transistor structure 252 is a dual-channel transistor structure.

[0129] like Figure 8C and Fig.8D As shown, interconnect structure 212 of memory cell structure 702 may be formed on and / or over source / drain regions 208 a and 208 b such that interconnect structure 212 is physically and / or electrically coupled to source / drain regions 208 a and 208 b .

[0130] like Fig. 8E and Figure 8F As shown, the bit line conductive structure 218 of the memory cell structure 702 can be formed above the interconnect structure 212, so that the bit line conductive structure 218 is located above the transistor structure 252. The bit line conductive structure 218 can fall on the interconnect structure 212, so that the interconnect structure 212 is coupled to the bit line conductive structure 218. In this way, the interconnect structure 212 electrically couples the transistor structure 252 with the bit line conductive structure 218 through the source / drain regions 208a and 208b. Alternatively, the source / drain regions 208a and 208b can each be electrically coupled to a different bit line conductive structure 218. The bit line conductive structure 218 can extend in the x-direction in the semiconductor device 200.

[0131] like FIG. 8G to FIG. 8O As shown, combined FIG. 8G to FIG. 8O One or more semiconductor processing operations described herein. Figures 4L to 4TThe process for forming the features 214, 216, and 256-274 of the memory cell structure 702 of the semiconductor device 700 includes forming the hydrogen absorption layer 270 in the recess 802 in which the capacitor structure 216 is formed.

[0132] After forming the capacitor structure 216, subsequent semiconductor processing operations may be performed to form layers and / or structures in the semiconductor device 700. For example, additional dielectric layers and / or additional metallization layers may be formed over the capacitor structure 216. The semiconductor processing operations may involve the use of hydrogen (e.g., as a carrier gas, as a purge gas, as an element of a deposited material) and / or thermal processing, any of which may cause hydrogen to diffuse downward into the memory cell structure 702 and contaminate the channel layer 206 of the transistor structure 252, which may result in performance degradation and / or failure of the memory cell structure 702. However, the hydrogen absorbing layer 270 in the capacitor structure 216 absorbs hydrogen, thereby blocking, minimizing and / or reducing the likelihood of hydrogen diffusing through the capacitor structure 216 and into the transistor structure 252. In this manner, the hydrogen absorbing layer 270 of the capacitor structure 216 may minimize and / or reduce the likelihood of hydrogen diffusing through the capacitor structure 216 and into the channel layer 206 of the transistor structure 252, which may minimize and / or reduce the likelihood of performance degradation and / or failure of the memory cell structure 702.

[0133] As mentioned above, FIG. 8A to FIG. 8O are provided as examples. Other examples can be found in the FIG. 8A to FIG. 8O Different than described.

[0134] 9A to 9C is a diagram of an example semiconductor device 900 described herein. 9A to 9C As shown, a semiconductor device 900 may include a memory array including a plurality of memory cell structures 902. The memory array may be included in one or more back-end dielectric layers (e.g., BEOL dielectric layers) in a BEOL region of the semiconductor device 900. The memory cell structures 902 may include volatile memory structures, such as DRAM memory structures and / or another type of volatile memory structures.

[0135] like 9A to 9C As shown, the memory cell structure 902 may include a combination and arrangement of parts 204-276b similar to the memory cell structure 502. However, in the memory cell structure 902, the transistor structure 252 includes a dual-channel transistor structure as opposed to a single-channel transistor structure. Specifically, as shown in FIG. Fig. 9BAs shown, the source / drain region 210 coupled to the capacitor structure 216 through the interconnect structure 214 may be located directly above the gate structure 204, and the memory cell structure 902 may further include a plurality of source / drain regions 208a and 208b located above and adjacent to opposite sides of the gate structure 204. Therefore, a first channel in the channel layer 206 of the transistor structure 252 is located between the source / drain region 208a and the source / drain region 210, and a second channel in the channel layer 206 of the transistor structure 252 is located between the source / drain region 208b and the source / drain region 210. The source / drain regions 208a and 208b may each be electrically coupled and / or electrically coupled, or physically coupled to the same bit line conductive structure 218, or may be electrically coupled and / or physically coupled to different bit line conductive structures 218.

[0136] The dual channel configuration of transistor structure 252 of memory cell structure 902 enables memory cell structure 902 to achieve increased on-current (e.g., approximately twice the on-current) relative to memory cell structure 502. However, memory cell structure 502 may provide reduced manufacturing complexity and increased memory cell density relative to memory cell structure 902.

[0137] As mentioned above, 9A to 9C Other examples can be found in the 9A to 9C Different than described.

[0138] FIG. 10A to FIG. 10F is a diagram of an example implementation 1000 of a memory cell structure 902 that forms a semiconductor device 900 described herein. In some implementations, in combination with FIG. 10A to FIG. 10F One or more of the described processing operations may be performed using one or more of the semiconductor processing tools 102-112 and / or the wafer / die transfer tool 114. FIG. 10A to FIG. 10F One or more of the processing operations described may use Figure 1 The method may be performed by another semiconductor processing tool not shown.

[0139] like Fig. 10A As shown, the combination can be performed FIG. 4A to FIG. 4M and / or FIG. 8A to FIG. 8H One or more semiconductor processing operations are described to form components 204-214 and 218-266 of memory cell structure 902 of semiconductor device 900. Fig. 10A As further shown, recess 1002 is formed through ESL 262, passivation layer 264, and / or isolation layer 266. Recess 1002 may be formed over interconnect structure 214 such that a top surface of interconnect structure 214 is exposed through recess 1002.

[0140] like Fig. 10B As shown, the bottom electrode 268 of the capacitor structure 216 of the memory cell structure 902 can be formed in the groove 1002. Specifically, the bottom electrode 268 can be conformally deposited on the sidewalls and bottom surface of the memory cell structure 902, so that the bottom electrode 268 conforms to the shape or contour of the groove 1002. The bottom surface of the groove 1002 can correspond to the top surface of the interconnect structure 214. Therefore, the deposition tool 102 and / or the electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, and the like described above. Figure 1 Another deposition technique and / or in addition to the above Figure 1 The bottom electrode 268 may be deposited using a deposition technique other than the deposition techniques described above.

[0141] like Fig. 10C As shown, dielectric layer 272 of capacitor structure 216 of memory cell structure 902 can be formed on and / or over bottom electrode 268. Specifically, dielectric layer 272 can be conformally deposited over the sidewalls and the bottom surface of recess 1002, so that dielectric layer 272 conforms to the shape or contour of recess 1002. Deposition tool 102 and / or electroplating tool 112 can be used to utilize CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique described above, and / or in addition to the above combined Figure 1 The dielectric layer 272 may be deposited using a deposition technique other than those described.

[0142] like Fig. 10D As shown, first top electrode layer 274a of top electrode 274 of capacitor structure 216 can be formed on and / or over dielectric layer 272 in recess 1002. Specifically, first top electrode layer 274a can be conformally deposited on the sidewalls and bottom surface of recess 1002 so that first top electrode layer 274a conforms to the shape or contour of recess 1002. Deposition tool 102 and / or electroplating tool 112 can use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Another deposition technique and / or other than the above combination described Figure 1 The first top electrode layer 274a is deposited using the deposition techniques described above.

[0143] like Fig. 10EAs shown, hydrogen absorbing layer 270 of capacitor structure 216 of memory cell structure 902 can be formed on and / or above first top electrode layer 274a. Specifically, hydrogen absorbing layer 270 can be conformally deposited on the sidewalls and the bottom surface of recess 1002, so that hydrogen absorbing layer 270 conforms to the shape or contour of recess 1002. Deposition tool 102 and / or electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique described and / or in combination with the above Figure 1 Various other deposition techniques are described to deposit the second bottom electrode layer 268b.

[0144] like Fig.10F As shown, second top electrode layer 274b of top electrode 274 of capacitor structure 216 may be formed on and / or over hydrogen absorbing layer 270 in recess 1002. Specifically, second top electrode layer 274b may be deposited to fill the remaining volume in recess 1002. Deposition tool 102 and / or electroplating tool 112 may be used to deposit the second top electrode layer 274b using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Another deposition technique described, and / or a different one from the above combination Figure 1 The second top electrode layer 274b is deposited using the described deposition techniques.

[0145] In some embodiments, the planarization tool 110 may be used to planarize the bottom electrode 268, the hydrogen absorbing layer 270, the dielectric layer 272, the first top electrode layer 274a, and / or the second top electrode layer 274b. In some embodiments, the bottom electrode 268, the hydrogen absorbing layer 270, the dielectric layer 272, the first top electrode layer 274a, and / or the second top electrode layer 274b are deposited over the top surface of the isolation layer 266, and the planarization tool 110 is used to remove excess material from the top surface of the isolation layer 266.

[0146] After forming the capacitor structure 216, subsequent semiconductor processing operations may be performed to form layers and / or structures in the semiconductor device 900. For example, additional dielectric layers and / or additional metallization layers may be formed over the capacitor structure 216. The semiconductor processing operations may involve the use of hydrogen (e.g., as a carrier gas, as a purge gas, as an element of a deposited material) and / or thermal processing, any of which may cause hydrogen to diffuse downward into the memory cell structure 902 and contaminate the channel layer 206 of the transistor structure 252, which may result in performance degradation and / or failure of the memory cell structure 902. However, the hydrogen absorbing layer 270 in the capacitor structure 216 absorbs hydrogen, thereby blocking, minimizing and / or reducing the likelihood of hydrogen diffusing through the capacitor structure 216 and into the transistor structure 252. In this manner, the hydrogen absorbing layer 270 of the capacitor structure 216 may minimize and / or reduce the likelihood of hydrogen diffusing through the capacitor structure 216 and into the channel layer 206 of the transistor structure 252, which may minimize and / or reduce the likelihood of performance degradation and / or failure of the memory cell structure 902.

[0147] As mentioned above, FIG. 10A to FIG. 10F Other examples can be found in the FIG. 10A to FIG. 10F Different than described.

[0148] Fig.11 1 is a diagram of example components of apparatus 1100 described herein. In some embodiments, one or more of semiconductor processing tools 102-112 and / or wafer / die transport tool 114 may include one or more apparatus 1100 and / or one or more components of apparatus 1100. Fig.11 As shown, the device 1100 may include a bus 1110 , a processor 1120 , a memory 1130 , an input component 1140 , an output component 1150 , and / or a communication component 1160 .

[0149] The bus 1110 may include one or more components that enable wired and / or wireless communications between components of the device 1100. ... Fig.11 Two or more components of a computer programmable logic device are coupled together, for example, via operational coupling, communication coupling, electronic coupling, coupling and / or electrical coupling. For example, bus 1110 may include electrical connections (e.g., wires, traces and / or leads) and / or wireless buses. Processor 1120 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit and / or another type of processing unit. Processor 1120 may be implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor 1120 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0150] Memory 1130 may include volatile and / or non-volatile memory. For example, memory 1130 may include random access memory (RAM), read-only memory (ROM), a hard disk, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1130 may include internal memory (e.g., RAM, ROM, or hard disk) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 1130 may be a non-transitory computer-readable medium. Memory 1130 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of device 1100. In some implementations, memory 1130 may include one or more memories coupled, for example, via bus 1110 (e.g., communicatively coupled) to one or more processors (e.g., processor 1120). The communicative coupling between processor 1120 and memory 1130 may enable processor 1120 to read and / or process information stored in memory 1130 and / or store information in memory 1130.

[0151] Input component 1140 can enable device 1100 to receive input, such as user input and / or sensed input. For example, input component 1140 can include a touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope and / or actuator. Output component 1150 can enable device 1100 to provide output such as via a display, speaker and / or light emitting diode. Communication component 1160 can enable device 1100 to communicate with other devices via wired connection and / or wireless connection. For example, communication component 1160 can include a receiver, a transmitter, a transceiver, a modem, a network adapter and / or an antenna.

[0152] Device 1100 can perform one or more operations or processes described herein. For example, a non-temporary computer-readable medium (e.g., memory 1130) can store a set of instructions (e.g., one or more instructions or program codes) for execution by processor 1120. Processor 1120 can execute this group of instructions to perform one or more operations or processes described herein. In some implementations, execution of the group of instructions by one or more processors 1120 causes one or more processors 1120 and / or device 1100 to perform one or more operations or processes described herein. In some implementations, hard-wired circuits can be used to replace instructions or to perform one or more operations or processes described herein in combination with instructions. Additionally or alternatively, processor 1120 can be set to perform one or more operations or processes described herein. Therefore, the implementation described herein is not limited to any specific combination of hardware circuits and software.

[0153] Fig.11 The number and arrangement of components shown are provided as examples. Apparatus 1100 may include Fig.11 Additional components, fewer components, different components, or differently arranged components are shown. Additionally or alternatively, one or more components of the device 1100 may perform one or more functions described as being performed by another set of components of the device 1100.

[0154] Fig.12 1 is a flow chart of an example process 1200 associated with forming the memory cell structure described herein. In some implementations, one or more semiconductor processing tools (eg, one or more of the semiconductor processing tools 102-112) are used to perform Fig.12 Additionally or alternatively, Fig.12 One or more processing blocks of may be performed using one or more components of the apparatus 1100 , such as the processor 1120 , the memory 1130 , the input component 1140 , the output component 1150 , and / or the communication component 1160 .

[0155] like Fig.12 As shown, process 1200 may include forming a gate structure of a transistor structure included in a memory cell structure of a semiconductor device (block 1210). For example, one or more of semiconductor processing tools 102-112 may be used to form a memory cell structure (e.g., memory cell structure 202, memory cell structure 502, memory cell structure 702, memory cell structure 902) included in a semiconductor device (e.g., semiconductor device 200, semiconductor device 500, semiconductor device 700, semiconductor device 900) as described herein.

[0156] like Fig.12 As further shown, process 1200 may include forming a gate dielectric layer of a transistor structure over the gate structure (block 1220). For example, one or more of semiconductor processing tools 102-112 may be used to form gate dielectric layer 238 of transistor structure 252 over gate structure 204, as described herein.

[0157] like Fig.12 As further shown, process 1200 may include forming a channel layer of a transistor structure on the gate dielectric layer (block 1230). For example, one or more of semiconductor processing tools 102-112 may be used to form channel layer 206 of transistor structure 252 on gate dielectric layer 238, as described herein.

[0158] like Fig.12As further shown, process 1200 may include forming a plurality of source / drain regions of a transistor structure on the channel layer (block 1240). For example, one or more of semiconductor processing tools 102-112 may be used to form a plurality of source / drain regions 208 and 210 of transistor structure 252 on channel layer 206, as described herein.

[0159] like Fig.12 As further shown, the process 1200 may include forming a source / drain interconnect structure of a memory cell structure on a source / drain region of the plurality of source / drain regions (block 1250). For example, one or more of the semiconductor processing tools 102-112 may be used to form a source / drain interconnect structure of a memory cell structure (e.g., interconnect structure 214) on a source / drain region 210 of the plurality of source / drain regions, as described herein.

[0160] like Fig.12 As further shown, process 1200 may include forming a bottom electrode of a capacitor structure included in the memory cell structure on the source / drain interconnect structure (block 1260). For example, one or more of semiconductor processing tools 102-112 may be used to form a bottom electrode 268 of a capacitor structure 216 included in the memory cell structure on the source / drain interconnect structure, as described herein.

[0161] like Fig.12 As further shown, process 1200 may include forming a hydrogen absorbing layer of the capacitor structure over the bottom electrode (block 1270). For example, one or more of semiconductor processing tools 102-112 may be used to form hydrogen absorbing layer 270 of capacitor structure 216 over bottom electrode 268 as described herein.

[0162] like Fig.12 As further shown, process 1200 may include forming a top electrode of a capacitor structure over the hydrogen absorbing layer (block 1280). For example, one or more of semiconductor processing tools 102-112 may be used to form top electrode 274 of a capacitor structure over hydrogen absorbing layer 270 as described herein.

[0163] Process 1200 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0164] In a first embodiment, forming the bottom electrode 268 includes forming a first bottom electrode layer 268a of the bottom electrode 268 on the source / drain interconnect structure, wherein forming the hydrogen absorbing layer 270 includes forming the hydrogen absorbing layer 270 on the first bottom electrode layer 268a, wherein forming the bottom electrode 268 includes forming a second bottom electrode layer 268b of the bottom electrode 268 on the hydrogen absorbing layer 270, and wherein the process 1200 includes forming a high-k dielectric layer (e.g., dielectric layer 272) on the second bottom electrode layer 268b, and wherein forming the top electrode 274 includes forming the top electrode 274 on the high-k dielectric layer.

[0165] In the second embodiment, alone or in combination with the first embodiment, forming the hydrogen absorbing layer 270 includes forming the hydrogen absorbing layer 270 of a metal oxide material.

[0166] In the third embodiment, alone or in combination with one or more of the first and second embodiments, the hydrogen absorbing layer 270 absorbs hydrogen in the semiconductor device during formation of one or more subsequent layers of the semiconductor device.

[0167] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the metal oxide material comprises indium oxide (In x O y ), titanium oxide (TiO x ), indium oxide (TiO x ), indium oxide (In x O y ), indium oxide (TiO x ), tin oxide (ITO), cerium oxide (CeO x ), zinc oxide (ZnO) or indium gallium zinc oxide (IGZO).

[0168] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 1200 includes forming a high-k dielectric layer (e.g., dielectric layer 272) on the bottom electrode 268, wherein forming a top electrode 274 includes forming a first top electrode layer 274a of the top electrode 274 on the high-k dielectric layer, wherein forming a hydrogen absorption layer 270 includes forming a hydrogen absorption layer 270 on the first top electrode layer 274a, and wherein forming a top electrode 274 includes forming a second top electrode layer 274b of the top electrode 274 on the hydrogen absorption layer 270.

[0169] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, forming the hydrogen absorbing layer 270 includes forming the hydrogen absorbing layer 270 to a thickness comprised within a range of about 1 nanometer to about 100 nanometers.

[0170] although Fig.12An example block diagram of process 1200 is shown, but in some implementations, process 1200 includes Fig.12 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in process 1200. Additionally or alternatively, two or more blocks of process 1200 can be performed in parallel.

[0171] FIG. 13A to FIG. 13C is a diagram of an example semiconductor device 1300 described herein. FIG. 13A to FIG. 13C As shown, semiconductor device 1300 may include a memory array including a plurality of memory cell structures 1302. The memory array may be included in one or more back-end dielectric layers (e.g., BEOL dielectric layers) in a BEOL region of semiconductor device 1300. Memory cell structures 1302 may include volatile memory structures, such as DRAM memory structures and / or another type of volatile memory structures.

[0172] like FIG. 13A to FIG. 13C As shown, the memory cell structure 1302 may include a combination and arrangement of parts 204-276 similar to the memory cell structure 202. However, the memory cell structure 1302 includes multiple hydrogen absorption layers, including a hydrogen absorption layer 270a between the first bottom electrode 268a and the second bottom electrode 268b, and another hydrogen absorption layer 270b between the first top electrode layer 274a and the second top electrode layer 274b of the top electrode. Therefore, the capacitor structure 216 of the memory cell structure 1302 may include the first bottom electrode 268a, the first hydrogen absorption layer 270a on the first bottom electrode 268a, the second bottom electrode 268b on the first hydrogen absorption layer 270a, the dielectric layer 272 between the second bottom electrode layer 268b and the first top electrode layer 274a, and the hydrogen absorption layer 270b between the first top electrode layer 274a and the second top electrode layer 274b. Including multiple hydrogen absorption layers in the memory cell structure 1302 may further enhance hydrogen absorption in the capacitor structure 216 of the memory cell structure 1302.

[0173] As mentioned above, FIG. 13A to FIG. 13C Other examples can be found in the FIG. 13A to FIG. 13C Different than described.

[0174] FIG. 14A to FIG. 14H is a diagram of an example implementation 1400 of a memory cell structure 1302 that forms a semiconductor device 1300 described herein. In some implementations, in combination with FIG. 14A to FIG. 14H One or more of the described processing operations may be performed using one or more of the semiconductor processing tools 102-112 and / or the wafer / die transfer tool 114. FIG. 14A to FIG. 14HOne or more of the processing operations described may use Figure 1 The method may be performed by another semiconductor processing tool not shown.

[0175] like Fig.14A As shown, the combination can be performed FIG. 4A to FIG. 4M One or more semiconductor processing operations are described to form the components 204-214 and 218-266 of the memory cell structure 1302 of the semiconductor device 1300. Fig.14A As further shown, recess 1402 is formed through ESL 262, passivation layer 264, and / or isolation layer 266. Recess 1402 may be formed over interconnect structure 214 such that a top surface of interconnect structure 214 is exposed through recess 1402.

[0176] like Fig. 14B As shown, the first bottom electrode 268a of the capacitor structure 216 of the memory cell structure 1302 can be formed in the groove 1402. Specifically, the first bottom electrode 268a can be conformally deposited on the sidewalls and bottom surface of the groove 1402, so that the first bottom electrode 268a conforms to the shape or contour of the groove 1402. The bottom surface of the groove 1402 can correspond to the top surface of the interconnect structure 214. Therefore, the first bottom electrode 268a is deposited on the top surface of the interconnect structure 214. The deposition tool 102 and / or the electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Other techniques and / or combinations different from those described above Figure 1 The first bottom electrode 268a is deposited using the described deposition techniques.

[0177] like Fig. 14C As shown, hydrogen absorbing layer 270a of capacitor structure 216 of memory cell structure 1302 can be formed on and / or above first bottom electrode layer 268a. Specifically, hydrogen absorbing layer 270a can be conformally deposited on the sidewalls and bottom surface of recess 1402 so that hydrogen absorbing layer 270a conforms to the shape or contour of recess 1402. Deposition tool 102 and / or electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique and / or in addition to the above described in combination Figure 1 The hydrogen absorbing layer 270a may be deposited by other deposition techniques than those described above.

[0178] like Fig.14DAs shown, second bottom electrode layer 268b of bottom electrode 268 of capacitor structure 216 may be formed on and / or over hydrogen absorbing layer 270a in recess 1402. Deposition tool 102 and / or electroplating tool 112 may be used to deposit the bottom electrode 268b on the bottom electrode 268 of capacitor structure 216 using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Another deposition technique described and / or in addition to the above combined Figure 1 The second bottom electrode layer 268b may be deposited using a deposition technique other than the one described above.

[0179] like Fig.14E As shown, dielectric layer 272 of capacitor structure 216 of memory cell structure 1302 can be formed on and / or over second bottom electrode layer 268b. Specifically, dielectric layer 272 can be conformally deposited over the sidewalls and the bottom surface of recess 1402, such that dielectric layer 272 conforms to the shape or contour of recess 1402. Deposition tool 102 and / or electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 The dielectric layer 272 is deposited by a deposition technique other than that described above.

[0180] like Fig.14F As shown, first top electrode layer 274a of top electrode 274 of capacitor structure 216 can be formed on and / or over dielectric layer 272 in recess 1402. Specifically, first top electrode layer 274a can be conformally deposited on the sidewalls and bottom surface of recess 1402 so that first top electrode layer 274a conforms to the shape or contour of recess 1402. Deposition tool 102 and / or electroplating tool 112 can use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Another deposition technique and / or other than the above combination described Figure 1 The first top electrode layer 274a is formed by the deposition techniques described above.

[0181] like Figure 14G As shown, hydrogen absorbing layer 270b of capacitor structure 216 of memory cell structure 502 can be formed on and / or over first top electrode layer 274a. Specifically, hydrogen absorbing layer 270b can be conformally deposited over the sidewalls and bottom surface of recess 1402, so that hydrogen absorbing layer 270 conforms to the shape or contour of recess 1402. Deposition tool 102 and / or electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, oxidation technology, or a combination of the above. Figure 1 Another deposition technique described and / or in addition to the above in combination Figure 1The hydrogen gettering layer 270b may be deposited using a deposition technique other than that described above.

[0182] like Fig.14H As shown, second top electrode layer 274b of top electrode 274 of capacitor structure 216 can be formed on and / or over hydrogen absorbing layer 270b in recess 1402. Specifically, second top electrode layer 274b can be deposited to fill the remaining volume in recess 1402. Deposition tool 102 and / or electroplating tool 112 can be used to use CVD technology, PVD technology, ALD technology, electroplating technology, a combination of the above Figure 1 Another deposition technique described, and / or a different one from the above combination Figure 1 The second top electrode layer 274b is deposited using the described deposition techniques.

[0183] In some embodiments, the planarization tool 110 may be used to planarize the first bottom electrode 268a, the hydrogen absorbing layer 270a, the second bottom electrode 268b, the dielectric layer 272, the first top electrode layer 274a, the hydrogen absorbing layer 270b, and / or the second top electrode layer 274b. In some embodiments, the first bottom electrode 268a, the hydrogen absorbing layer 270a, the second bottom electrode 268b, the dielectric layer 272, the first top electrode layer 274a, the hydrogen absorbing layer 270b, and / or the second top electrode layer 274b are deposited over the top surface of the isolation layer 266, and the planarization tool 110 is used to remove excess material from the top surface of the isolation layer 266.

[0184] After forming the capacitor structure 216, subsequent semiconductor processing operations may be performed to form layers and / or structures in the semiconductor device 1300. For example, additional dielectric layers and / or additional metallization layers may be formed over the capacitor structure 216. The semiconductor processing operations may involve the use of hydrogen (e.g., as a carrier gas, as a purge gas, as an element of a deposited material) and / or thermal processing, either of which may cause hydrogen to diffuse downward into the memory cell structure 1302 and contaminate the channel layer 206 of the transistor structure 252, which may result in performance degradation and / or failure of the memory cell structure 1302. However, the hydrogen absorbing layers 270a and 270b in the capacitor structure 216 absorb hydrogen, thereby blocking, minimizing, and / or reducing the likelihood of hydrogen diffusing through the capacitor structure 216 and into the transistor structure 252. In this manner, the hydrogen absorbing layers 270a and 270b absorb hydrogen. The capacitor structure 216 may minimize and / or reduce the likelihood of contamination of the channel layer 206 , which may minimize and / or reduce the likelihood of performance degradation and / or failure of the memory cell structure 1302 .

[0185] As mentioned above, FIG. 14A to FIG. 14H Other examples can be found in the FIG. 14A to FIG. 14HDifferent than described.

[0186] As such, the memory cell structure includes a transistor structure and a capacitor structure, wherein the capacitor structure includes a hydrogen absorbing layer. The hydrogen absorbing layer absorbs hydrogen, such as atmospheric hydrogen and / or hydrogen used in various types of deposition processes. The hydrogen absorbing layer absorbs hydrogen, which prevents or reduces the likelihood of hydrogen diffusing into the metal oxide channel below the transistor structure. In this way, the hydrogen absorbing layer minimizes and / or reduces the likelihood of hydrogen contamination in the metal oxide channel, which can enable the memory cell structure to achieve low current leakage and reduce data corruption and / or failure of the memory cell structure, among other things.

[0187] As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a plurality of back-end dielectric layers. The semiconductor device includes a memory cell structure located in the plurality of back-end dielectric layers, including: a transistor structure; a capacitor structure located above the transistor structure, including: a first bottom electrode layer, a second bottom electrode layer located above the first bottom electrode layer, a hydrogen absorption layer located between the first bottom electrode layer and the second bottom electrode layer, a dielectric layer located above the second bottom electrode layer, and a top electrode layer located above the dielectric layer.

[0188] In some embodiments, the hydrogen absorbing layer includes one or more metal oxide materials.

[0189] In some embodiments, the hydrogen absorbing layer includes at least one of the following: indium oxide (In x O y ), titanium dioxide (TiO x ), indium tin oxide (ITO), cerium oxide (CeO x ), zinc oxide (ZnO), or indium gallium zinc oxide (IGZO).

[0190] In some embodiments, the thickness of the hydrogen absorbing layer is in a range from about 1 nm to about 100 nm.

[0191] In some embodiments, the capacitor structure comprises a deep trench capacitor structure; and wherein the hydrogen gettering layer conforms to a contour of the deep trench capacitor structure.

[0192] In some embodiments, the transistor structure includes a single-channel transistor structure, which includes: a gate structure; a channel layer located above the gate structure; a first source / drain region located on the channel layer and directly above the gate structure; and a second source / drain region located on the channel layer and directly above the gate structure.

[0193] In some embodiments, the transistor structure includes a dual-channel transistor structure, which includes: a gate structure; a channel layer located above the gate structure; a first source / drain region located on the channel layer and directly above the gate structure; a second source / drain region located on the channel layer above the gate structure, wherein the second source / drain region is adjacent to a first side of the gate structure; and a third source / drain region located on the channel layer above the gate structure, wherein the third source / drain region is adjacent to a second side of the gate structure opposite to the first side.

[0194] As described in more detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a plurality of back-end dielectric layers. The semiconductor device includes a memory cell structure located in the plurality of back-end dielectric layers, including: a transistor structure, a capacitor structure located above the transistor structure, including: a bottom electrode layer, a dielectric layer located above the bottom electrode layer, a first top electrode layer located above the dielectric layer, a second top electrode layer located above the first top electrode layer, and a hydrogen absorption layer located between the first top electrode layer and the second top electrode layer.

[0195] In some embodiments, the hydrogen absorbing layer includes one or more metal oxide materials.

[0196] In some embodiments, the hydrogen absorbing layer includes one or more metal hydroxide materials.

[0197] In some embodiments, the transistor structure includes a single-channel transistor structure, which includes: a gate structure; a channel layer located above the gate structure; a first source / drain region located on the channel layer and directly above the gate structure; and a second source / drain region located on the channel layer and directly above the gate structure.

[0198] In some embodiments, the transistor structure includes a dual-channel transistor structure, which includes: a gate structure; a channel layer located above the gate structure; a first source / drain region located on the channel layer and directly above the gate structure; a second source / drain region located on the channel layer above the gate structure, wherein the second source / drain region is adjacent to a first side of the gate structure; and a third source / drain region located on the channel layer above the gate structure, wherein the third source / drain region is adjacent to a second side of the gate structure opposite to the first side.

[0199] In some embodiments, the thickness of the hydrogen absorbing layer is in a range from about 1 nm to about 100 nm.

[0200] As described in more detail above, some embodiments described herein provide a method. The method includes forming a gate structure of a transistor structure included in a memory cell structure of a semiconductor device. The method includes forming a gate dielectric layer of the transistor structure above the gate structure. The method includes forming a channel layer of the transistor structure on the gate dielectric layer. The method includes forming a plurality of source / drain regions of the transistor structure on the channel layer. The method includes forming a source / drain interconnect structure of the memory cell structure on a source / drain region of the plurality of source / drain regions. The method includes forming a bottom electrode of a capacitor structure included in the memory cell structure on the source / drain interconnect structure. The method includes forming a hydrogen absorption layer of the capacitor structure above the bottom electrode. The method includes forming a top electrode of the capacitor structure above the hydrogen absorption layer.

[0201] In some embodiments, forming the bottom electrode includes: forming a first bottom electrode layer of the bottom electrode on the source / drain interconnect structure; wherein forming the hydrogen absorption layer includes: forming the hydrogen absorption layer on the first bottom electrode layer; wherein forming the bottom electrode includes: forming a second bottom electrode layer of the bottom electrode on the hydrogen absorption layer; wherein the method also includes: forming a high dielectric constant (high-k) dielectric layer on the second bottom electrode layer; and wherein forming the top electrode includes: forming the top electrode on the high dielectric constant dielectric layer.

[0202] In some embodiments, forming the hydrogen absorbing layer includes forming the hydrogen absorbing layer of a metal oxide material.

[0203] In some embodiments, the hydrogen absorbing layer absorbs hydrogen in the semiconductor device during formation of one or more subsequent layers of the semiconductor device.

[0204] In some embodiments, the metal oxide material comprises at least one of the following: indium oxide (In x O y ), titanium dioxide (TiO x ), indium tin oxide (ITO), cerium oxide (CeO x ), zinc oxide (ZnO), or indium gallium zinc oxide (IGZO).

[0205] In some embodiments, the method further includes: forming a high dielectric constant (high-k) dielectric layer on the bottom electrode, wherein forming the top electrode includes: forming a first top electrode layer of the top electrode on the high dielectric constant dielectric layer; wherein forming the hydrogen absorption layer includes: forming the hydrogen absorption layer on the first top electrode layer; and wherein forming the top electrode includes: forming a second top electrode layer of the top electrode on the hydrogen absorption layer.

[0206] In some embodiments, forming the hydrogen absorbing layer includes forming the hydrogen absorbing layer to a thickness ranging from about 1 nanometer to about 100 nanometers.

[0207] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: multiple back-end dielectric layers; as well as The memory cell structure is located in the plurality of back-end dielectric layers and includes: transistor structure; and A capacitor structure, located on the transistor structure, comprising: a first bottom electrode layer; a second bottom electrode layer, located above the first bottom electrode layer; a hydrogen absorption layer, located between the first bottom electrode layer and the second bottom electrode layer; a dielectric layer located above the second bottom electrode layer; and A top electrode layer is located above the dielectric layer.

2. The semiconductor device according to claim 1, wherein: The capacitor structure comprises a deep trench capacitor structure; and The hydrogen absorbing layer conforms to the contour of the deep trench capacitor structure.

3. The semiconductor device according to claim 1, wherein: The transistor structure comprises a single-channel transistor structure, and the single-channel transistor structure comprises: Gate structure; A channel layer, located above the gate structure; A first source / drain region, located on the channel layer and directly above the gate structure; and The second source / drain region is located on the channel layer and directly above the gate structure.

4. The semiconductor device according to claim 1, wherein: The transistor structure comprises a dual-channel transistor structure, and the dual-channel transistor structure comprises: Gate structure; A channel layer, located above the gate structure; A first source / drain region, located on the channel layer and directly above the gate structure; a second source / drain region located on the channel layer above the gate structure, wherein the second source / drain region is adjacent to the first side of the gate structure; and a third source / drain region located on the channel layer above the gate structure, The third source / drain region is adjacent to a second side of the gate structure opposite to the first side.

5. A semiconductor device, characterized in that: include: multiple back-end dielectric layers; as well as The memory cell structure is located in the plurality of back-end dielectric layers and includes: transistor structure; and A capacitor structure, located above the transistor structure, comprises: bottom electrode layer; a dielectric layer located above the bottom electrode layer; a first top electrode layer located above the dielectric layer; A second top electrode layer, located on the first top electrode layer; and The hydrogen absorption layer is located between the first top electrode layer and the second top electrode layer.

6. The semiconductor device according to claim 5, wherein: The hydrogen absorbing layer includes one or more metal hydroxide materials.

7. The semiconductor device according to claim 5, wherein: The thickness of the hydrogen absorbing layer is in a range from about 1 nm to about 100 nm.

8. A method for forming a semiconductor device, characterized in that: include: Forming a gate structure of a transistor structure included in a memory cell structure of a semiconductor device; forming a gate dielectric layer of the transistor structure above the gate structure; forming a channel layer of the transistor structure on the gate dielectric layer; forming a plurality of source / drain regions of the transistor structure on the channel layer; forming a source / drain interconnection structure of the memory cell structure on a source / drain region among the plurality of source / drain regions; forming a bottom electrode of a capacitor structure included in the memory cell structure on the source / drain interconnect structure; forming a hydrogen absorbing layer of the capacitor structure over the bottom electrode; as well as A top electrode of the capacitor structure is formed over the hydrogen absorbing layer.

9. The method according to claim 8, characterized in that Forming the hydrogen absorbing layer comprises: The hydrogen absorbing layer of a metal oxide material is formed.

10. The method according to claim 9, characterized in that The hydrogen absorbing layer absorbs hydrogen in the semiconductor device during formation of one or more subsequent layers of the semiconductor device.

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