Preparation method of device structure of SGT MOS transistor

Abstract

The invention provides a method for preparing a device structure of an SGT MOS transistor, and the method comprises the steps: sequentially forming a first thermal oxidation layer, an isolation layer and a groove oxidation layer on the surface of an epitaxial layer and the side wall of a first groove of the epitaxial layer, and carrying out the reduction of the thickness of the first thermal oxidation layer on the basis of meeting the thickness requirement of the oxidation layer on the side wall of the groove, therefore, the consumption of the epitaxial layer is reduced, and the pressure resistance of the SGT tube is improved. According to the SGT transistor manufacturing method, the first polycrystalline silicon layer is deposited in the groove formed by the groove oxide layer, the part, in the first groove, of the groove oxide layer is removed, due to the fact that the isolation layer is arranged, the inter-gate oxide layer on the surface of the protruding part of the first polycrystalline silicon layer can be generated according to the required thickness, and therefore the gate source capacitance of the SGT transistor is reduced. And depositing a second polycrystalline silicon layer and carrying out first ion implantation and second ion implantation on the epitaxial layer at the two sides of the first groove. And depositing an interlayer dielectric layer on the substrate to complete the preparation of the device structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a method for preparing a device structure of an SGT MOS tube. Background Art

[0002] SGT (Shielded Gate Trench) MOS tube is a new type of power semiconductor device, which has the advantages of small parasitic capacitance, fast switching speed, low power loss, etc. It is the mainstream power device in the current medium and low voltage application field. In the traditional process of preparing SGT tubes, according to the position relationship between the source polysilicon and the control polysilicon in the trench, it can be divided into an upper and lower structure and a left and right structure.

[0003] Compared with the upper and lower structure SGT tube, the left-right structure SGT tube has a simpler process flow, thus reducing the process cost. At the same time, the left-right structure SGT also avoids problems such as wafer warping caused by increased mechanical stress due to the HDP (High Density Plasma) filling process.

[0004] However, in the prior art, in the process of preparing the SGT tube with the left-right structure, the specific on-resistance (Rsp) and gate-source capacitance of the SGT tube are usually increased due to process limitations.

[0005] Therefore, providing a preparation method that can reduce the specific on-resistance and gate-source capacitance of SGT tubes has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a device structure preparation method and a cell structure of an SGT MOS tube, an SGT tube and an electronic device, which solves the problem that the prior art cannot effectively reduce the specific on-resistance and gate-source capacitance of the SGT tube due to process limitations.

[0007] In order to solve the above technical problems, the first technical solution of the present invention provides a method for preparing a device structure of an SGT MOS tube, which is used to prepare the device structure of the SGT tube, and the method comprises:

[0008] S1: providing a substrate;

[0009] S2: forming an epitaxial layer on the substrate;

[0010] S3: forming a first groove in a first region of the epitaxial layer;

[0011] S4: performing a thermal oxidation treatment on the surface of the epitaxial layer and the sidewall of the first groove to generate a first thermal oxide layer on the surface of the epitaxial layer and the sidewall of the first groove;

[0012] S5: sequentially depositing an isolation layer and a trench oxide layer on the surface of the epitaxial layer and the first thermal oxide layer on the sidewall of the first groove;

[0013] S6: depositing a first polysilicon layer in the first groove, wherein the first polysilicon layer is located on the trench oxide layer, and a top of the first polysilicon layer is flush with a surface of the epitaxial layer;

[0014] S7: removing the trench oxide layer on the surface of the epitaxial layer and a portion of the trench oxide layer in the first groove, so that the first polysilicon layer protrudes from the remaining trench oxide layer in the first groove; wherein the first polysilicon layer and the first thermal oxide layer and the remaining trench oxide layer on both sides thereof form a second groove and a third groove respectively;

[0015] S8: thermally oxidizing a portion of the first polysilicon layer protruding from the trench oxide layer to generate a second thermal oxide layer on a surface of the portion of the first polysilicon layer protruding from the trench oxide layer;

[0016] S9: removing the isolation layer on the surface of the epitaxial layer and a portion of the isolation layer in the first groove;

[0017] S10: depositing a second polysilicon layer in both the second groove and the third groove, and the top of the second polysilicon layer is flush with the surface of the epitaxial layer;

[0018] S11: performing a first ion implantation on the epitaxial layer at both sides of the first groove to form a well region in a second region of the epitaxial layer; and performing a second ion implantation on the well region to form a source region in a third region of the well region;

[0019] S12: depositing an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the source region, the second polysilicon layer, and the second thermal oxide layer.

[0020] Optionally, before thermally oxidizing the portion of the first polysilicon layer protruding from the trench oxide layer in S8, the method further includes:

[0021] S71: thinning the width of a portion of the first polysilicon layer protruding from the trench oxide layer, so that the width of the protruding portion of the first polysilicon layer is a first width.

[0022] Optionally, the step of thinning the width of the protruding portion of the first polysilicon layer in S71 specifically includes:

[0023] S711: Etching the lateral structure of the protruding portion of the first polysilicon layer to make the width of the protruding portion of the first polysilicon layer equal to a first width.

[0024] Optionally, the step of thinning the width of the protruding portion of the first polysilicon layer in S71 specifically includes:

[0025] S721: thermally oxidizing the protruding portion of the first polysilicon layer to generate a thermal oxide layer on the surface of the protruding portion of the first polysilicon layer;

[0026] S722: removing the thermal oxide layer on the surface of the protruding portion of the first polysilicon layer;

[0027] S723: repeating step S721 and step S722 to make the width of the protruding portion of the first polysilicon layer be the first width.

[0028] Optionally, thermally oxidizing a portion of the first polysilicon layer protruding from the trench oxide layer in S8 specifically includes:

[0029] S81: thermally oxidizing the protruding portion of the first polysilicon layer to completely oxidize the protruding portion of the first polysilicon layer.

[0030] Optionally, the thickness of the first thermal oxide layer ranges from 500 angstroms to 800 angstroms.

[0031] Optionally, before depositing the second polysilicon layer in S10, the method further includes:

[0032] S91: performing thermal annealing on the exposed first thermal oxide layer.

[0033] Optionally, the isolation layer includes at least any one of nitride, metal oxide, HfO2 and aluminum oxide.

[0034] Optionally, the trench oxide layer includes a TEOS oxide layer.

[0035] The second technical solution of the present invention provides a cellular structure of an SGT tube, the cellular structure comprising:

[0036] A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS tube provided by the first technical solution of the present invention;

[0037] A first contact hole, wherein the first contact hole penetrates the interlayer dielectric layer and is electrically connected to the source region and the well region;

[0038] A first metal connection layer is located on a surface of the first contact hole and a surface of the interlayer dielectric layer respectively.

[0039] The third technical solution of the present invention provides a cellular structure of an SGT tube, the cellular structure comprising:

[0040] A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS tube provided by the first technical solution of the present invention;

[0041] a second contact hole, the second contact hole penetrating the interlayer dielectric layer and electrically connected to the second polysilicon layer;

[0042] A second metal connection layer is located on a surface of the second contact hole and a surface of the interlayer dielectric layer respectively.

[0043] The fourth technical solution of the present invention provides an SGT pipe, comprising:

[0044] substrate;

[0045] A plurality of first cellular structures, wherein the first cellular structures are located on the surface of the substrate, and the first cellular structures include the cellular structure of the SGT tube provided by the second technical solution of the present invention;

[0046] a plurality of second cellular structures, wherein the second cellular structures are located on the surface of the substrate, and the second cellular structures include the cellular structure of the SGT tube provided by the third technical solution of the present invention;

[0047] A plurality of third cell structures, the third cell structures are located on the surface of the substrate, and the third cell structures include: a second device structure, the second device structure is manufactured by steps S1 to S6 in the device structure manufacturing method of the SGT MOS tube provided by the first technical solution of the present invention; a third contact hole, the third contact hole penetrates the interlayer dielectric layer and is electrically connected to the first polysilicon layer; a third metal connection layer, the third metal connection layer is respectively located on the surface of the third contact hole and the surface of the interlayer dielectric layer;

[0048] The first polysilicon layers in the first cell structure, the second cell structure and the third cell structure are connected to each other, and the second polysilicon layers in the first cell structure and the second cell structure are connected to each other;

[0049] The second metal connection layer in the second cell structure serves as the gate of the SGT tube, the third metal connection layer in the third cell structure serves as the source of the SGT tube, and the bottom edge of the substrate serves as the drain of the SGT tube.

[0050] A fifth technical solution of the present invention provides an electronic device, comprising the SGT tube provided by the fourth technical solution of the present invention.

[0051] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0052] In the device structure preparation method of the SGT MOS tube of the technical solution of the present invention, the isolation layer and the trench oxide layer are sequentially deposited on the first thermal oxide layer, so that the thickness of the first thermal oxide layer can be made very thin, which greatly reduces the consumption of the epitaxial layer by thermal oxidation in the process of forming the first thermal oxide layer, thereby improving the voltage resistance of the SGT tube, or under the same voltage resistance conditions, the thickness of the epitaxial layer with a thinner thickness or a higher doping ion concentration can be selected, thereby reducing the specific on-resistance of the SGT tube.

[0053] Since the isolation layer is provided, the preparation of the first thermal oxide layer and the second thermal oxide layer is completely separated, so the thickness of the second thermal oxide layer can be made very thick as required, thereby reducing the gate-source capacitance of the device structure, and further reducing the turn-on loss of the SGT tube. At the same time, the isolation layer can prevent oxygen from contacting the first thermal oxide layer during the process of preparing the second thermal oxide layer by thermal oxidation, thereby avoiding the first groove from being enlarged during the process of preparing the second thermal oxide layer.

[0054] Furthermore, before thermally oxidizing the portion of the first polysilicon layer protruding from the trench oxide layer, the width of the protruding portion of the first polysilicon layer is thinned or even completely oxidized to reduce the width of the interlayer in the middle of the second polysilicon layer, further reducing the size of the first groove, thereby further reducing the volume of the cellular structure composed of the device structure, and further reducing the specific on-resistance of the SGT tube.

[0055] Furthermore, before depositing the second polysilicon layer, the method further includes performing thermal annealing on the exposed first thermal oxide layer to repair the surface of the first thermal oxide layer, thereby optimizing the anti-leakage performance of the device structure.

[0056] Furthermore, the isolation layer includes at least any one of nitride, metal oxide, HfO2 and aluminum oxide, thereby improving the ability of the isolation layer to isolate oxygen and the pressure resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a flow chart of an embodiment of a cellular structure for preparing an SGT tube;

[0058] Figures 2 to 10 They are schematic diagrams of simplified cross-sectional structures corresponding to different stages in the preparation process of a cellular structure embodiment of an SGT tube;

[0059] Fig.11 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 1 ;

[0060] Figures 12 to 21They are respectively schematic diagrams of simplified cross-sectional structures corresponding to different preparation stages of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention;

[0061] Fig. 22 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 2 ;

[0062] Fig.23 yes Fig. 22 A simplified cross-sectional structural schematic diagram corresponding to the preparation process shown;

[0063] Fig.24 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 3 ;

[0064] Fig.25 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 4 ;

[0065] Fig.26 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 5 ;

[0066] Fig. 27 yes Fig.26 A simplified cross-sectional structural schematic diagram corresponding to the preparation process shown;

[0067] Fig.28 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 6 ;

[0068] Fig.29 It is a simplified cross-sectional structural schematic diagram of the cellular structure provided by the technical solution of the present invention;

[0069] Fig.30 It is a simplified cross-sectional structural schematic diagram of another cellular structure provided by the technical solution of the present invention;

[0070] Fig.31 It is a simplified cross-sectional structural schematic diagram of the SGT pipe provided by the technical solution of the present invention. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0072] As described in the background art, in the process of preparing the SGT tube with the left and right structures in the prior art, the specific on-resistance and gate-source capacitance of the SGT tube are usually increased due to process limitations.

[0073] in, Figure 1 The present invention is a flow chart of an embodiment of preparing a cellular structure of an SGT tube. Figures 2 to 10 They are schematic diagrams of simplified cross-sectional structures corresponding to different stages in the preparation process of a cellular structure embodiment of an SGT tube.

[0074] Please refer to Figures 1 to 10 An embodiment of preparing a cellular structure of an SGT tube specifically includes the following steps:

[0075] S100: providing a substrate.

[0076] S101: forming an epitaxial layer on a substrate.

[0077] S102: forming a first trench in a first region of the epitaxial layer.

[0078] S103: thermally oxidize the surface of the epitaxial layer 201 and the sidewalls of the first trench 204 to form a trench thermal oxide layer 203 on the surface of the epitaxial layer 201 and the sidewalls of the first trench 204. The thickness of the trench thermal oxide layer 203 is in the range of 5000 angstroms to 7000 angstroms, corresponding to Figure 2 .

[0079] S104: depositing a shielding gate polysilicon layer 205 in the first trench, wherein the shielding gate polysilicon layer 205 is located on the trench thermal oxide layer 203, and the top of the shielding gate polysilicon layer 205 is flush with the surface of the epitaxial layer 201, corresponding to Figure 3 .

[0080] S105: removing the trench thermal oxide layer 203 on the surface of the epitaxial layer 201 and a portion of the trench thermal oxide layer 203 in the first trench, so that the shield gate polysilicon layer 205 protrudes from the remaining trench thermal oxide layer 203 in the first trench. The protruding portion of the shield gate polysilicon layer 205 and the epitaxial layer 201 on both sides and the remaining trench thermal oxide layer 203 in the first trench 204 form a second trench 206 and a third trench 206, respectively, corresponding to Figure 4 .

[0081] S106: Perform thermal oxidation treatment on the epitaxial layer 201 on both sides of the first trench, the sidewalls of the second trench 206, the sidewalls of the third trench 206, and the top of the shielding gate polysilicon layer 205, so as to form a thermal oxide layer on the epitaxial layer 201 on both sides of the first trench 204, the sidewalls of the second trench 206, the sidewalls of the third trench 206, and the top of the shielding gate polysilicon layer 205. The thermal oxide layer on the epitaxial layer 201 on both sides of the first trench 204, the sidewalls of the second trench 206 close to the epitaxial layer 201, and the sidewalls of the third trench 206 close to the epitaxial layer 201 are used as gate oxide layer 207, and the thermal oxide layer on the surface of the protruding part of the shielding gate polysilicon layer 205 is used as an inter-gate oxide layer 208, corresponding to Figure 5 .

[0082] S107: Depositing a control gate polysilicon layer 209 in both the second trench 206 and the third trench 206, corresponding to Figure 6 .

[0083] S108: performing a first ion implantation on the epitaxial layer 201 on both sides of the first trench 204 to form a well region 210 in the second region of the epitaxial layer 201; and performing a second ion implantation on the well region 210 to form a source region 211 in the third region of the well region 210, corresponding to Figure 7 .

[0084] S109: depositing an interlayer dielectric layer 212 on the substrate, wherein the interlayer dielectric layer 212 covers the control gate polysilicon layer 209, the control gate polysilicon layer 209 and the intergate thermal oxide layer, corresponding to Figure 8 .

[0085] S1 1 0: forming a contact hole 213 on the interlayer dielectric layer 212, the contact hole 213 penetrates the interlayer dielectric layer 212 and is electrically connected to the control gate polysilicon layer 209, corresponding to Fig. 9 .

[0086] S1 1 1: depositing a metal connection layer 214 on the surface of the contact hole 213 and the surface of the interlayer dielectric layer 212, corresponding to Fig.10 .

[0087] The problem with this embodiment is that:

[0088] 1. Since the epitaxial layer 201 itself will be consumed in a certain proportion during the process of forming an oxide layer on the epitaxial layer 201 through the thermal oxidation process. Therefore, in step S103, a thermal oxide layer of 5000 angstroms to 7000 angstroms is generated on the surface of the epitaxial layer 201 and the sidewall of the first groove 204 through the thermal oxidation process, which will consume the epitaxial layer 201 over a large area, so that the size of the first groove 204 is continuously expanded to increase the volume of the cellular structure. Since the cellular structure is a substructure constituting the SGT tube, the increase in the volume of the cellular structure will reduce the density of the cellular structure in the SGT tube, thereby increasing the specific on-resistance of the SGT tube. At the same time, since the consumption of the epitaxial layer 201 in step S103 is relatively large, a thinner epitaxial layer 201 or an epitaxial layer 201 with a higher doping ion concentration cannot be used, thereby failing to reduce the turn-on loss of the SGT tube, thereby further increasing the specific on-resistance of the SGT tube.

[0089] 2. It is necessary to remove a portion of the trench thermal oxide layer 203 in the first trench 204 in step S105 before forming the gate oxide layer 207 in step S106. On the one hand, in the process of generating the gate oxide layer 207, the epitaxial layer 201 will be further consumed, thereby further expanding the size of the first trench 204, and further increasing the specific on-resistance of the SGT tube. On the other hand, in the process of generating the gate oxide layer 207, oxygen will also affect the remaining trench thermal oxide layer 203, thereby further increasing the specific on-resistance of the SGT tube.

[0090] 3. The industry has a relatively low requirement for the thickness of the gate oxide layer 207, and the thickness of the gate oxide layer 207 is generally between 500 angstroms and 1000 angstroms. In step S106, the gate oxide layer 207 and the inter-gate oxide layer 208 are generated simultaneously, so the thickness of the inter-gate oxide layer 208 is also between 500 angstroms and 1000 angstroms. The thickness of the inter-gate oxide layer 208 affects the gate-source capacitance of the cell structure, and the thinner the thickness of the inter-gate oxide layer 208, the greater the gate-source capacitance of the cell structure. The gate-source capacitance of the cellular structure will affect the conduction speed of the SGT tube, and the larger the gate-source capacitance of the cellular structure, the slower the conduction speed of the SGT tube. Therefore, the industry requires that the thickness of the gate oxide layer 208 be more than 1500 angstroms. Therefore, in this embodiment, the thickness of the gate oxide layer 208 is only 500 angstroms-1000 angstroms, which makes the gate-source capacitance of the cellular structure too large, thereby causing the conduction speed of the SGT tube to be too slow, and further causing the turn-on loss of the SGT tube to be too large.

[0091] In view of this, the first technical solution of the present invention provides a new method for preparing a device structure of an SGT MOS tube, which is used for preparing a device structure of an SGT tube.

[0092] in, Fig.11 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 1 . Figures 12 to 21 They are respectively schematic diagrams of simplified cross-sectional structures corresponding to different preparation stages of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention.

[0093] Please refer to Figures 11 to 21 The device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention comprises the following steps:

[0094] S1: Provide an N-type silicon substrate 10.

[0095] S2 : forming an epitaxial layer 20 on the N-type silicon substrate 10 .

[0096] S3: forming a first groove 30 in the first region of the epitaxial layer 20, corresponding to Fig.12 .

[0097] S4: thermally oxidizing the surface of the epitaxial layer 20 and the sidewall of the first groove 30 to form a first thermal oxide layer 40 on the surface of the epitaxial layer 20 and the sidewall of the first groove 30, corresponding to Fig.13 .

[0098] The thickness of the first thermal oxidation layer 40 is controlled by specific conditions such as the furnace tube temperature, process time and oxygen flow rate in the thermal oxidation process. The specific control method is a conventional technical means in this field and will not be repeated here.

[0099] S5: Sequentially depositing an isolation layer 50 and a trench oxide layer 60 on the surface of the epitaxial layer 20 and the first thermal oxide layer 40 on the sidewall of the first groove 30, corresponding to Fig.14 .

[0100] S6: depositing a first polysilicon layer 70 in the first groove 30, wherein the first polysilicon layer 70 is located on the trench oxide layer 60, and the top of the first polysilicon layer 70 is flush with the surface of the epitaxial layer 20, corresponding to Fig.15 .

[0101] S7: removing the trench oxide layer 60 on the surface of the epitaxial layer 20 and a portion of the trench oxide layer 60 in the first groove 30, so that the first polysilicon layer 70 protrudes from the remaining trench oxide layer 60 in the first groove 30; wherein the first polysilicon layer 70 and the first thermal oxide layer 40 and the remaining trench oxide layer 60 on both sides thereof form a second groove 90 and a third groove 90, respectively, corresponding to Fig.16 .

[0102] S8: thermally oxidizing the portion of the first polysilicon layer 70 protruding from the trench oxide layer 60 to form a second thermal oxide layer 80 on the surface of the portion of the first polysilicon layer 70 protruding from the trench oxide layer 60, corresponding to Fig.17 .

[0103] The thickness of the second thermal oxidation layer 80 is also controlled by specific conditions such as the furnace temperature, process time and oxygen flow rate in the thermal oxidation process. The specific control method is a conventional technical means in this field and will not be repeated here.

[0104] S9: removing the isolation layer 50 on the surface of the epitaxial layer 20 and a portion of the isolation layer 50 in the first groove 30, corresponding to Fig.18 .

[0105] S10: depositing a second polysilicon layer 100 in both the second groove and the third groove, and the top of the second polysilicon layer 100 is flush with the surface of the epitaxial layer 20, corresponding to Fig.19 .

[0106] S11: performing a first ion implantation on the epitaxial layer 20 on both sides of the first groove 30 to form a P-type well region 120 in the second region of the epitaxial layer 20; and performing a second ion implantation on the P-type well region 120 to form an N-type source region 110 in the third region of the P-type well region 120, corresponding to Fig. 20 .

[0107] S12: depositing an interlayer dielectric layer 130 on the N-type silicon substrate 10, wherein the interlayer dielectric layer 130 covers the source region, the second polysilicon layer 100 and the second thermal oxide layer 80, corresponding to Fig.21 .

[0108] Through the above technical means, the technical solution of the present invention can greatly reduce the specific on-resistance and turn-on loss of the SGT tube. The specific principle is as follows:

[0109] Since the prior art needs to generate a trench thermal oxide layer of 5000-7000 angstroms, the epitaxial layer 20 will be greatly consumed and the size of the first trench will be enlarged. Therefore, step S4 will be made very thin when generating the first thermal oxide layer 40, and the thickness can range from 500 angstroms to 800 angstroms, which is equivalent to the thickness requirement of the gate oxide layer in the prior art. The advantage of doing so is that, on the one hand, the loss of the epitaxial layer 20 is greatly reduced, and the expansion of the first groove 30 during the thermal oxidation process is reduced, thereby reducing the volume of the device structure and improving the withstand voltage performance of the SGT tube. Alternatively, under the premise of maintaining the same withstand voltage performance, the epitaxial layer 20 with a large thickness or a high doping ion concentration can be selected, thereby greatly reducing the specific on-resistance of the SGT tube. On the other hand, the first thermal oxide layer 40 can be used as the gate oxide layer of the prior art, which is equivalent to completing the gate oxide layer in advance, and the preparation of the gate oxide layer and the preparation of the inter-gate oxide layer are separated by the isolation layer 50, so that the thickness of the inter-gate oxide layer will not be affected by the thickness of the gate oxide layer.

[0110] At the same time, in order to make the trench oxide layer 60 meet the requirements of the device's withstand voltage and isolation, even if the thickness of the trench oxide layer 60 is between 5000 angstroms and 7000 angstroms. Step S5 first deposits the isolation layer 50 on the surface of the first thermal oxide layer 40 to completely isolate the first thermal oxide layer 40 from oxygen. The advantage of doing so is that, on the one hand, when the second thermal oxide layer 80 is prepared separately in the subsequent step S8, oxygen will not contact the first thermal oxide layer 40, thereby avoiding the consumption of the epitaxial layer 20, that is, avoiding the expansion of the first groove 30. On the other hand, there is no need to prepare the trench oxide layer 60 through a thermal oxidation process, but it can be directly prepared by chemical deposition or the like, so that the trench oxide layer 60 can be made very thick to meet the requirements of the device's withstand voltage and isolation, and will not affect the size of the epitaxial layer 20 and the first groove 30, so as to affect the specific on-resistance of the SGT tube.

[0111] Since the isolation layer 50 is provided, when preparing the second thermal oxide layer 80 in step S8, that is, the inter-gate oxide layer of the prior art, the corresponding thickness can be prepared as required, thereby avoiding the problem that the gate-source capacitance of the cell structure is too large due to the inter-gate oxide layer being too thin in the prior art, thereby improving the conduction speed of the SGT tube and further reducing the turn-on loss of the SGT tube. Since the turn-on loss of the SGT tube is positively correlated with the specific on-resistance of the SGT tube, the specific on-resistance of the SGT tube is also reduced.

[0112] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0113] in, Fig. 22 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 2 . Fig.23 yes Fig. 22 Schematic diagram of the simplified cross-sectional structure corresponding to the preparation process shown.

[0114] Please refer to Fig. 22 and Fig.23 As a specific implementation, before thermally oxidizing the portion of the first polysilicon layer 70 protruding from the trench oxide layer 60 in S8, the method further includes:

[0115] S71: thinning the width of a portion of the first polysilicon layer 70 protruding from the trench oxide layer 60 so that the width of the protruding portion of the first polysilicon layer 70 is a first width.

[0116] The specific size of the first width can be set according to demand, and even the protruding portion of the first polysilicon layer 70 can be completely oxidized during the thermal oxidation process, which is not limited here.

[0117] The beneficial effect of this embodiment is that: since the second thermal oxide layer 80 is thickened in step S8, before the second thermal oxide layer 80 is generated, the width of the protruding portion of the first polysilicon layer 70 is thinned, or even the protruding portion of the first polysilicon layer 70 is completely oxidized, so that the width of the isolation structure located in the middle of the second polysilicon layer 100 remains unchanged or even reduced compared with the prior art. The isolation structure is composed of the second thermal oxide layer 80, the protruding portion of the first polysilicon layer 70 and the second thermal oxide layer 80. If the width of the isolation structure is too large, it will occupy the space of the second polysilicon layer 100, thereby affecting the connection between the subsequent contact hole and the second polysilicon layer 100. Therefore, by thinning or even completely oxidizing the width of the protruding portion of the first polysilicon layer 70, it can ensure that the gate-source capacitance of the device structure is reduced while avoiding affecting the connection between the contact hole and the second polysilicon layer 100.

[0118] If the width of the isolation structure is reduced, the size of the first groove 30 can also be reduced in the design stage, thereby reducing the specific on-resistance of the SGT tube.

[0119] in, Fig.24 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 3 .

[0120] Please refer to Fig.23 and Fig.24 Specifically, in S71, the width of the protruding portion of the first polysilicon layer 70 is thinned, which specifically includes:

[0121] S711: etching the lateral structure of the protruding portion of the first polysilicon layer 70 so that the width of the protruding portion of the first polysilicon layer 70 is a first width.

[0122] In this embodiment, the width of the protruding portion of the first polysilicon layer 70 is directly thinned by etching. The etching method may include wet etching or dry etching. The specific implementation of wet etching or dry etching is a conventional technical method in the art and will not be described in detail here.

[0123] in, Fig.25 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 4 .

[0124] Please refer to Fig.23 and Fig.25 Specifically, in S71, the width of the protruding portion of the first polysilicon layer 70 is thinned, and specifically includes:

[0125] S721: thermally oxidizing the protruding portion of the first polysilicon layer 70 to generate a thermal oxide layer on the surface of the protruding portion of the first polysilicon layer 70;

[0126] S722: removing the thermal oxide layer on the surface of the protruding portion of the first polysilicon layer 70;

[0127] S723: repeating step S721 and step S722 to make the width of the protruding portion of the first polysilicon layer 70 equal to the first width.

[0128] Since a certain proportion of polysilicon will be lost during the thermal oxidation process, this embodiment performs oxidation and deoxidation on the protruding portion of the first polysilicon layer 70 for multiple times to reduce the width of the protruding portion of the first polysilicon layer 70 .

[0129] It should be noted that the process of thermally oxidizing the protruding portion of the first polysilicon layer 70 and the process of removing the resulting thermal oxidation layer are conventional technical means in the art and will not be elaborated herein.

[0130] in, Fig.26 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 5 . Fig. 27 yes Fig.26 Schematic diagram of the simplified cross-sectional structure corresponding to the preparation process shown.

[0131] Please refer to Fig.26 and Figure 7 As a specific implementation, thermal oxidation of the portion of the first polysilicon layer 70 protruding from the trench oxide layer 60 in S8 specifically includes:

[0132] S81 : thermally oxidizing the protruding portion of the first polysilicon layer 70 to completely oxidize the protruding portion of the first polysilicon layer 70 .

[0133] in, Fig.28 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is Figure 6 .

[0134] Please refer to Fig.28 As a specific implementation manner, before depositing the second polysilicon layer in S10, the method further includes:

[0135] S91: performing thermal annealing on the exposed first thermal oxide layer.

[0136] This embodiment has a beneficial effect in that thermal annealing can repair the surface of the first thermal oxide layer, thereby optimizing the anti-leakage performance of the device structure.

[0137] It should be noted that the thermal annealing process is a common technical means in this field and will not be described in detail here.

[0138] As a specific implementation, the thickness of the first thermal oxide layer ranges from 500 angstroms to 800 angstroms. The thickness of the isolation layer ranges from 200 angstroms to 2000 angstroms. The thickness of the trench oxide layer ranges from 1000 angstroms to 5000 angstroms. Of course, the specific thickness of the isolation layer and the specific thickness of the trench oxide layer can be selected according to the withstand voltage requirements of the device structure, and are not limited here.

[0139] Specifically, the isolation layer includes at least one of nitride, metal oxide, HfO2 and aluminum oxide. Of course, any high-K dielectric material with isolation function can be used as the isolation layer, which is not limited here.

[0140] As a specific implementation, the material of the trench oxide layer may specifically include a TEOS (tetraethyl orthosilicate) oxide layer. Of course, any oxide layer with an isolation function falls within the protection scope of the present invention and is not limited here.

[0141] As a specific implementation, the material of the substrate may include any one of silicon, germanium, silicon germanium or silicon carbide, which is not limited here.

[0142] It should be noted that if the substrate material used is a P-type silicon substrate, an N-type well region is generated through the first ion implantation in step S11 , and a P-type source region is generated through the second ion implantation in step S12 .

[0143] As a specific implementation, the size and location of the first region of the epitaxial layer in step S3, the second region of the epitaxial layer in step S11, and the third region of the P-type well region can be set as required, and are not limited here. For example, in step S3, a first groove is formed in the first region of the epitaxial layer, and the size of the first region here can be set according to the pre-designed opening diameter of the first groove.

[0144] As a specific implementation, the depth of etching the trench oxide layer in step S7 is usually 1 μm-1.5 μm. The specific depth is related to the thickness of the P-type well region generated in step S11 and is not limited here.

[0145] In summary, in the method for preparing the device structure of the SGT MOS tube provided by the embodiment of the present invention, in step S4, the first thermal oxide layer can be prepared to be very thin so as to be used as the gate oxide layer of the device structure. On the one hand, the loss of the epitaxial layer is greatly reduced, and the expansion of the first groove during the thermal oxidation process is reduced, thereby reducing the volume of the device structure and improving the voltage resistance of the SGT tube. Alternatively, under the premise of maintaining the same voltage resistance, the epitaxial layer with a large thickness or a high doping ion concentration can be selected, thereby greatly reducing the specific on-resistance of the SGT tube. On the other hand, the preparation of the gate oxide layer and the preparation of the inter-gate oxide layer are separated by the isolation layer, so that the thickness of the inter-gate oxide layer will not be affected by the thickness of the gate oxide layer.

[0146] In step S5, the isolation layer is first deposited on the surface of the first thermal oxide layer to completely isolate the first thermal oxide layer from oxygen. On the one hand, it ensures that when the second thermal oxide layer is prepared separately in the subsequent step S8, oxygen will not contact the first thermal oxide layer, thereby avoiding the consumption of the epitaxial layer, that is, avoiding the expansion of the first groove. On the other hand, there is no need to prepare the groove oxide layer through a thermal oxidation process, but it can be directly prepared by chemical deposition or the like, so that the groove oxide layer can be made very thick to meet the voltage resistance and isolation requirements of the device, and will not affect the size of the epitaxial layer and the first groove, so as to affect the specific on-resistance of the SGT tube.

[0147] Furthermore, before generating the second thermal oxide layer, the width of the protruding portion of the first polysilicon layer is thinned so that the width of the isolation structure located in the middle of the second polysilicon layer remains unchanged or even decreases compared with the prior art, thereby ensuring that the gate-source capacitance of the device structure is reduced while avoiding affecting the connection between the contact hole and the second polysilicon layer.

[0148] Furthermore, before depositing the second polysilicon layer in S10 , thermal annealing is performed on the exposed first thermal oxide layer to repair the surface of the first thermal oxide layer, thereby optimizing the anti-leakage performance of the device structure.

[0149] The device structure manufactured above is specifically a device component structure in each cellular structure in the SGT tube. The cellular structures in the SGT tube and the SGT tube structure are described below:

[0150] The second technical solution of the present invention provides a new cellular structure.

[0151] in, Fig.29 It is a simplified cross-sectional structural schematic diagram of the cellular structure provided by the technical solution of the present invention.

[0152] Please refer to Fig.29, the cellular structure provided by the technical solution of the present invention includes:

[0153] A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS tube provided by the previous technical solution;

[0154] A first contact hole 140 , wherein the first contact hole 140 penetrates the interlayer dielectric layer 130 and is electrically connected to the N-type source region 110 and the P-type well region 120 ;

[0155] The first metal connection layer 150 is located on the surface of the first contact hole 140 and the surface of the interlayer dielectric layer 130 respectively.

[0156] The third technical solution of the present invention also provides another new cellular structure.

[0157] in, Fig.30 It is a simplified cross-sectional structural schematic diagram of another cellular structure provided by the technical solution of the present invention.

[0158] Please refer to Fig.30 , the cellular structure provided by the technical solution of the present invention includes:

[0159] A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS tube according to any one of claims 1 to 9;

[0160] a second contact hole 160, wherein the second contact hole 160 penetrates the interlayer dielectric layer 130 and is electrically connected to the second polysilicon layer 100;

[0161] The second polysilicon layer 170 is located on the surface of the second contact hole 160 and the surface of the interlayer dielectric layer 130 respectively.

[0162] The fourth technical solution of the present invention also provides a new SGT pipe.

[0163] in, Fig.31 It is a simplified cross-sectional structural schematic diagram of the SGT pipe provided by the technical solution of the present invention.

[0164] Please refer to Fig.31 The SGT pipe provided by the technical solution of the present invention comprises:

[0165] N-type silicon substrate 10;

[0166] A plurality of first cellular structures 1, wherein the first cellular structures 1 are located on the surface of the N-type silicon substrate 10, and the first cellular structures 1 include the cellular structure of the SGT tube provided by the second technical solution of the present invention;

[0167] A plurality of second cellular structures 2, wherein the second cellular structures 2 are located on the surface of the N-type silicon substrate 10, and the second cellular structures 2 include the cellular structure of the SGT tube provided by the third technical solution of the present invention;

[0168] A plurality of third cell structures 3, the third cell structures 3 are located on the surface of the N-type silicon substrate 10, and the third cell structures 3 include: a second device structure, the second device structure is made by steps S1 to S6 in the device structure preparation method of the SGTMOS tube provided by the first technical solution of the present invention; a third contact hole 180, the third contact hole 180 penetrates the interlayer dielectric layer 130 and is electrically connected to the first polysilicon layer 70; a third metal connection layer 190, the third metal connection layer 190 is respectively located on the surface of the third contact hole 180 and the surface of the interlayer dielectric layer 130;

[0169] The first polysilicon layer 70 in the first cell structure 1, the second cell structure 2 and the third cell structure 3 are connected to each other, and the second polysilicon layer 100 in the first cell structure 1 and the second cell structure 2 are connected to each other;

[0170] The second polysilicon layer 170 in the second cell structure 2 serves as the gate of the SGT tube, the third metal connection layer 190 in the third cell structure 3 serves as the source of the SGT tube, and the bottom edge of the N-type silicon substrate 10 serves as the drain of the SGT tube.

[0171] Specifically, the first cell structure 1 is used as the source cell structure of the SGT tube, the second cell structure 2 is used as the control electrode structure of the SGT tube, and the third cell structure 3 is used as the source shield gate connection electrode structure of the SGT tube.

[0172] Of course, the N-type silicon substrate 10 may also be a P-type silicon substrate or other materials, and the types and concentrations of ions implanted in the first ion implantation and the second ion implantation may also change adaptively.

[0173] The fifth technical solution of the present invention further provides an electronic device, comprising the SGT tube provided by the fourth technical solution of the present invention.

[0174] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing a device structure of an SGT MOS tube, characterized in that: A device structure for preparing an SGT tube, the method comprising: S1: providing a substrate; S2: forming an epitaxial layer on the substrate; S3: forming a first groove in a first region of the epitaxial layer; S4: performing a thermal oxidation treatment on the surface of the epitaxial layer and the sidewall of the first groove to generate a first thermal oxide layer on the surface of the epitaxial layer and the sidewall of the first groove; S5: sequentially depositing an isolation layer and a trench oxide layer on the surface of the epitaxial layer and the first thermal oxide layer on the sidewall of the first groove; S6: depositing a first polysilicon layer in the first groove, wherein the first polysilicon layer is located on the trench oxide layer, and a top of the first polysilicon layer is flush with a surface of the epitaxial layer; S7: removing the trench oxide layer on the surface of the epitaxial layer and a portion of the trench oxide layer in the first groove, so that the first polysilicon layer protrudes from the remaining trench oxide layer in the first groove; wherein the first polysilicon layer and the first thermal oxide layer and the remaining trench oxide layer on both sides thereof form a second groove and a third groove respectively; S8: thermally oxidizing a portion of the first polysilicon layer protruding from the trench oxide layer to generate a second thermal oxide layer on a surface of the portion of the first polysilicon layer protruding from the trench oxide layer; S9: removing the isolation layer on the surface of the epitaxial layer and a portion of the isolation layer in the first groove; S10: depositing a second polysilicon layer in both the second groove and the third groove, and the top of the second polysilicon layer is flush with the surface of the epitaxial layer; S11: performing a first ion implantation on the epitaxial layer at both sides of the first groove to form a well region in a second region of the epitaxial layer; and performing a second ion implantation on the well region to form a source region in a third region of the well region; S12: depositing an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the source region, the second polysilicon layer, and the second thermal oxide layer.

2. The method for preparing the device structure of the SGT MOS tube according to claim 1, characterized in that: Before thermally oxidizing the portion of the first polysilicon layer protruding from the trench oxide layer in S8, the method further includes: S71: thinning the width of a portion of the first polysilicon layer protruding from the trench oxide layer, so that the width of the protruding portion of the first polysilicon layer is a first width.

3. The method for preparing the device structure of the SGT MOS tube according to claim 2, characterized in that: S71 thins the width of the protruding portion of the first polysilicon layer, specifically including: S711: Etching the lateral structure of the protruding portion of the first polysilicon layer to make the width of the protruding portion of the first polysilicon layer equal to a first width.

4. The method for preparing the device structure of the SGT MOS tube according to claim 2, characterized in that: S71 thins the width of the protruding portion of the first polysilicon layer, specifically including: S721: thermally oxidizing the protruding portion of the first polysilicon layer to generate a thermal oxide layer on the surface of the protruding portion of the first polysilicon layer; S722: removing the thermal oxide layer on the surface of the protruding portion of the first polysilicon layer; S723: repeating step S721 and step S722 to make the width of the protruding portion of the first polysilicon layer be the first width.

5. The method for preparing the device structure of the SGT MOS tube according to claim 2, characterized in that: S8 thermally oxidizes a portion of the first polysilicon layer protruding from the trench oxide layer, specifically comprising: S81: thermally oxidizing the protruding portion of the first polysilicon layer to completely oxidize the protruding portion of the first polysilicon layer.

6. The method for preparing the device structure of the SGT MOS tube according to claim 1, characterized in that: The thickness of the first thermal oxide layer ranges from 500 angstroms to 800 angstroms.

7. The method for preparing the device structure of the SGT MOS tube according to claim 1, characterized in that: Before depositing the second polysilicon layer in S10, the method further includes: S91: performing thermal annealing on the exposed first thermal oxide layer.

8. The method for preparing the device structure of the SGT MOS tube according to claim 1, characterized in that: The isolation layer includes at least any one of nitride, metal oxide, HfO2 and aluminum oxide.

9. The method for preparing the device structure of the SGT MOS tube according to claim 1, characterized in that: The trench oxide layer includes a TEOS oxide layer.

10. A cellular structure of an SGT tube, characterized in that: The cell structure includes: A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS tube according to any one of claims 1 to 9; A first contact hole, wherein the first contact hole penetrates the interlayer dielectric layer and is electrically connected to the source region and the well region; A first metal connection layer is located on a surface of the first contact hole and a surface of the interlayer dielectric layer respectively.

11. A cellular structure of an SGT tube, characterized in that: The cell structure includes: A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS tube according to any one of claims 1 to 9; a second contact hole, the second contact hole penetrating the interlayer dielectric layer and electrically connected to the second polysilicon layer; A second metal connection layer is located on a surface of the second contact hole and a surface of the interlayer dielectric layer respectively.

12. An SGT pipe, characterized in that: include: substrate; a plurality of first cellular structures, wherein the first cellular structures are located on a surface of the substrate, and the first cellular structures include the cellular structure of the SGT tube according to claim 10; a plurality of second cellular structures, wherein the second cellular structures are located on the surface of the substrate, and the second cellular structures include the cellular structure of the SGT tube according to claim 11; a plurality of third cell structures, the third cell structures being located on the surface of the substrate, the third cell structures comprising: a second device structure, the second device structure being manufactured by steps S1 to S6 in the method for manufacturing the device structure of the SGT MOS tube according to claim 1; a third contact hole, the third contact hole penetrating the interlayer dielectric layer and being electrically connected to the first polysilicon layer; a third metal connection layer, the third metal connection layer being respectively located on the surface of the third contact hole and the surface of the interlayer dielectric layer; The first polysilicon layers in the first cell structure, the second cell structure and the third cell structure are connected to each other, and the second polysilicon layers in the first cell structure and the second cell structure are connected to each other; The second metal connection layer in the second cell structure serves as the gate of the SGT tube, the third metal connection layer in the third cell structure serves as the source of the SGT tube, and the bottom edge of the substrate serves as the drain of the SGT tube.

13. An electronic device, characterized in that: include: The SGT pipe according to claim 12.

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