Device structure preparation method of SGT MOS tube

Abstract

The present invention provides a method for preparing a device structure of an SGT MOS tube, the method comprising: sequentially forming a first thermal oxide layer, an isolation layer, and a trench oxide layer on the surface of an epitaxial layer and on the sidewalls of a first groove of the epitaxial layer; thinning the thickness of the first thermal oxide layer while meeting the thickness requirements of the trench sidewall oxide layer to reduce consumption of the epitaxial layer, thereby improving the voltage resistance of the SGT tube; depositing a first polysilicon layer in a groove formed by the trench oxide layer, and removing a portion of the trench oxide layer in the first groove; because the isolation layer is provided, an inter-gate oxide layer on the surface of the protruding portion of the first polysilicon layer can be formed to the required thickness, thereby reducing the gate-source capacitance of the SGT tube; depositing a second polysilicon layer and performing a first ion implantation and a second ion implantation on the epitaxial layer on both sides of the first groove; depositing an interlayer dielectric layer on the substrate to complete the preparation of the device structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a method for preparing a device structure of an SGT MOS tube. Background Art

[0002] The shielded gate trench (SGT) MOS transistor is a new type of power semiconductor device. It boasts low parasitic capacitance, fast switching speed, and low power loss, making it a mainstream power device in low- and medium-voltage applications. Traditional SGT manufacturing processes categorize SGT transistors into top-bottom and left-right configurations, depending on the position of the source and control polysilicon within the trench.

[0003] Compared to the top-bottom SGT tube, the left-right SGT tube has a simpler process flow, thus reducing process costs. It also avoids issues such as wafer warpage caused by increased mechanical stress during the HDP (High Density Plasma) filling process.

[0004] However, in the prior art, in the process of preparing the SGT tube with the left-right structure, the specific on-resistance (Rsp) and gate-source capacitance of the SGT tube are usually increased due to process limitations.

[0005] Therefore, providing a preparation method that can reduce the specific on-resistance and gate-source capacitance of SGT tubes has become a technical problem that needs to be solved urgently in the industry. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a device structure preparation method and cell structure of an SGT MOS tube, an SGT tube and an electronic device, which solves the problem that the existing technology cannot effectively reduce the specific on-resistance and gate-source capacitance of the SGT tube due to process limitations.

[0007] To solve the above technical problems, the first technical solution of the present invention provides a method for preparing a device structure of an SGT MOS transistor, which is used to prepare the device structure of the SGT transistor. The method includes:

[0008] S1: providing a substrate;

[0009] S2: forming an epitaxial layer on the substrate;

[0010] S3: forming a first groove in a first region of the epitaxial layer;

[0011] S4: performing a thermal oxidation process on the surface of the epitaxial layer and the sidewalls of the first groove to form a first thermal oxide layer on the surface of the epitaxial layer and the sidewalls of the first groove;

[0012] S5: sequentially depositing an isolation layer and a trench oxide layer on the surface of the epitaxial layer and the first thermal oxide layer on the sidewall of the first groove;

[0013] S6: depositing a first polysilicon layer in the first groove, wherein the first polysilicon layer is located on the trench oxide layer, and a top of the first polysilicon layer is flush with a surface of the epitaxial layer;

[0014] S7: removing the trench oxide layer on the surface of the epitaxial layer and a portion of the trench oxide layer in the first groove, so that the first polysilicon layer protrudes from the remaining trench oxide layer in the first groove; wherein the first polysilicon layer and the first thermal oxide layer and the remaining trench oxide layer on both sides thereof form a second groove and a third groove respectively;

[0015] S8: thermally oxidizing a portion of the first polysilicon layer protruding from the trench oxide layer to form a second thermal oxide layer on a surface of the portion of the first polysilicon layer protruding from the trench oxide layer;

[0016] S9: removing the isolation layer on the surface of the epitaxial layer and a portion of the isolation layer in the first groove;

[0017] S10: depositing a second polysilicon layer in both the second groove and the third groove, with the top of the second polysilicon layer flush with the surface of the epitaxial layer;

[0018] S11: performing a first ion implantation on the epitaxial layer on both sides of the first groove to form a well region in the second region of the epitaxial layer; and performing a second ion implantation on the well region to form a source region in the third region of the well region;

[0019] S12: depositing an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the source region, the second polysilicon layer, and the second thermal oxide layer.

[0020] Optionally, before thermally oxidizing the portion of the first polysilicon layer protruding from the trench oxide layer in S8, the method further includes:

[0021] S71: thinning the width of a portion of the first polysilicon layer protruding from the trench oxide layer, so that the width of the protruding portion of the first polysilicon layer is a first width.

[0022] Optionally, the step of thinning the width of the protruding portion of the first polysilicon layer in S71 specifically includes:

[0023] S711: Etching the lateral structure of the protruding portion of the first polysilicon layer to make the width of the protruding portion of the first polysilicon layer be a first width.

[0024] Optionally, the step of thinning the width of the protruding portion of the first polysilicon layer in S71 specifically includes:

[0025] S721: thermally oxidizing the protruding portion of the first polysilicon layer to form a thermal oxide layer on the surface of the protruding portion of the first polysilicon layer;

[0026] S722: removing the thermal oxide layer on the surface of the protruding portion of the first polysilicon layer;

[0027] S723: repeating step S721 and step S722 to make the width of the protruding portion of the first polysilicon layer be the first width.

[0028] Optionally, thermally oxidizing a portion of the first polysilicon layer protruding from the trench oxide layer in S8 specifically includes:

[0029] S81: thermally oxidizing the protruding portion of the first polysilicon layer to completely oxidize the protruding portion of the first polysilicon layer.

[0030] Optionally, the thickness of the first thermal oxide layer ranges from 500 angstroms to 800 angstroms.

[0031] Optionally, before depositing the second polysilicon layer in S10, the method further includes:

[0032] S91: performing thermal annealing on the exposed first thermal oxide layer.

[0033] Optionally, the isolation layer includes at least any one of nitride, metal oxide, HfO2 and aluminum oxide.

[0034] Optionally, the trench oxide layer includes a TEOS oxide layer.

[0035] The second technical solution of the present invention provides a cellular structure of an SGT tube, the cellular structure comprising:

[0036] A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS transistor provided by the first technical solution of the present invention;

[0037] a first contact hole, wherein the first contact hole penetrates the interlayer dielectric layer and is electrically connected to the source region and the well region;

[0038] A first metal connection layer is located on a surface of the first contact hole and a surface of the interlayer dielectric layer.

[0039] The third technical solution of the present invention provides a cellular structure of an SGT tube, the cellular structure comprising:

[0040] A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS transistor provided by the first technical solution of the present invention;

[0041] a second contact hole, the second contact hole penetrating the interlayer dielectric layer and electrically connected to the second polysilicon layer;

[0042] A second metal connection layer is located on a surface of the second contact hole and a surface of the interlayer dielectric layer respectively.

[0043] A fourth technical solution of the present invention provides an SGT pipe, comprising:

[0044] substrate;

[0045] a plurality of first cellular structures, wherein the first cellular structures are located on a surface of the substrate, and the first cellular structures include the cellular structure of the SGT tube provided by the second technical solution of the present invention;

[0046] a plurality of second cellular structures, the second cellular structures being located on the surface of the substrate, the second cellular structures comprising the cellular structure of the SGT tube provided by the third technical solution of the present invention;

[0047] a plurality of third cellular structures, the third cellular structures being located on the surface of the substrate, the third cellular structures comprising: a second device structure, the second device structure being manufactured by steps S1 to S6 of the method for manufacturing the device structure of an SGT MOS transistor provided by the first technical solution of the present invention; a third contact hole, the third contact hole penetrating the interlayer dielectric layer and electrically connected to the first polysilicon layer; and a third metal connection layer, the third metal connection layer being respectively located on surfaces of the third contact hole and the interlayer dielectric layer;

[0048] The first polysilicon layers in the first cellular structure, the second cellular structure, and the third cellular structure are connected to each other, and the second polysilicon layers in the first cellular structure and the second cellular structure are connected to each other;

[0049] The second metal connection layer in the second cell structure serves as the gate of the SGT tube, the third metal connection layer in the third cell structure serves as the source of the SGT tube, and the bottom edge of the substrate serves as the drain of the SGT tube.

[0050] A fifth technical solution of the present invention provides an electronic device, comprising the SGT tube provided by the fourth technical solution of the present invention.

[0051] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0052] In the device structure fabrication method of an SGT MOS transistor according to the technical solution of the present invention, the isolation layer and the trench oxide layer are sequentially deposited on the first thermal oxide layer, so that the thickness of the first thermal oxide layer can be made very thin. This greatly reduces consumption of the epitaxial layer by thermal oxidation during the formation of the first thermal oxide layer, thereby improving the withstand voltage capability of the SGT transistor. Alternatively, under the same withstand voltage conditions, a thinner epitaxial layer thickness or a higher doping ion concentration can be selected, thereby reducing the specific on-resistance of the SGT transistor.

[0053] The isolation layer allows the first and second thermal oxide layers to be fabricated completely separately. Therefore, the thickness of the second thermal oxide layer can be made very thick as required, thereby reducing the gate-source capacitance of the device structure and, in turn, the turn-on loss of the SGT transistor. Furthermore, the isolation layer prevents oxygen from contacting the first thermal oxide layer during the thermal oxidation process, thereby preventing the first groove from expanding during the fabrication of the second thermal oxide layer.

[0054] Furthermore, before thermally oxidizing the portion of the first polysilicon layer protruding from the trench oxide layer, the width of the protruding portion of the first polysilicon layer is thinned or even completely oxidized to reduce the width of the interlayer in the middle of the second polysilicon layer, further reducing the size of the first groove, thereby further reducing the volume of the cellular structure composed of the device structure, and further reducing the specific on-resistance of the SGT tube.

[0055] Furthermore, before depositing the second polysilicon layer, the method further includes performing thermal annealing on the exposed first thermal oxide layer to repair the surface of the first thermal oxide layer, thereby optimizing the anti-leakage performance of the device structure.

[0056] Furthermore, the isolation layer includes at least any one of nitride, metal oxide, HfO2 and aluminum oxide, thereby improving the ability of the isolation layer to isolate oxygen and the pressure resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 is a flow chart of an embodiment of preparing a cellular structure of an SGT tube;

[0058] Figures 2 to 10 They are schematic diagrams of simplified cross-sectional structures corresponding to different stages in the preparation process of an embodiment of a cellular structure of an SGT tube;

[0059] Figure 11 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 1 ;

[0060] Figures 12 to 21They are respectively schematic diagrams of simplified cross-sectional structures corresponding to different preparation stages of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention;

[0061] Figure 22 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 2 ;

[0062] Figure 23 yes Figure 22 A simplified cross-sectional structural diagram corresponding to the preparation process shown;

[0063] Figure 24 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 3 ;

[0064] Figure 25 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 4 ;

[0065] Figure 26 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 5 ;

[0066] Figure 27 yes Figure 26 A simplified cross-sectional structural diagram corresponding to the preparation process shown;

[0067] Figure 28 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 6 ;

[0068] Figure 29 This is a simplified cross-sectional structural diagram of the cellular structure provided by the technical solution of the present invention;

[0069] Figure 30 This is a simplified cross-sectional structural diagram of another cellular structure provided by the technical solution of the present invention;

[0070] Figure 31 This is a simplified cross-sectional structural diagram of the SGT pipe provided by the technical solution of the present invention. DETAILED DESCRIPTION

[0071] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention, in conjunction with the accompanying drawings. It should be understood that the described embodiments are only some, and not all, of the embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are intended to fall within the scope of protection of the present invention. The terms "first," "second," "third," "fourth," and so on (if any) in the specification and claims of the present invention and in the accompanying drawings are used to distinguish similar items and are not necessarily intended to describe a specific order or precedence. It should be understood that such terms are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "including," "comprising," and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, product, or apparatus.

[0072] As described in the background art, in the prior art, the specific on-resistance and gate-source capacitance of the SGT tube are usually increased due to process limitations during the preparation of the left-right structure of the SGT tube.

[0073] in, Figure 1 The present invention is a flow chart of an embodiment of preparing a cellular structure of an SGT tube. Figures 2 to 10 Each of them is a schematic diagram of a simplified cross-sectional structure corresponding to different stages in the preparation process of an embodiment of the cellular structure of an SGT tube.

[0074] Please refer to Figures 1 to 10 An embodiment of preparing a cellular structure of an SGT tube specifically includes the following steps:

[0075] S100: providing a substrate.

[0076] S101: forming an epitaxial layer on a substrate.

[0077] S102: forming a first trench in a first region of the epitaxial layer.

[0078] S103: thermally oxidizing the surface of the epitaxial layer 201 and the sidewalls of the first trench 204 to form a trench thermal oxide layer 203 on the surface of the epitaxial layer 201 and the sidewalls of the first trench 204. The thickness of the trench thermal oxide layer 203 is in the range of 5000 angstroms to 7000 angstroms, corresponding to Figure 2 .

[0079] S104: depositing a shield gate polysilicon layer 205 in the first trench, wherein the shield gate polysilicon layer 205 is located on the trench thermal oxide layer 203, and the top of the shield gate polysilicon layer 205 is flush with the surface of the epitaxial layer 201, corresponding to Figure 3 .

[0080] S105: removing the trench thermal oxide layer 203 on the surface of the epitaxial layer 201 and a portion of the trench thermal oxide layer 203 in the first trench, so that the shield gate polysilicon layer 205 protrudes from the remaining trench thermal oxide layer 203 in the first trench. The protruding portion of the shield gate polysilicon layer 205 and the epitaxial layer 201 on both sides and the remaining trench thermal oxide layer 203 in the first trench 204 form a second trench 206 and a third trench 206, respectively, corresponding to Figure 4 .

[0081] S106: Performing thermal oxidation treatment on the epitaxial layer 201 on both sides of the first trench, the sidewalls of the second trench 206, the sidewalls of the third trench 206, and the top of the shielding gate polysilicon layer 205, so as to form a thermal oxide layer on the epitaxial layer 201 on both sides of the first trench 204, the sidewalls of the second trench 206, the sidewalls of the third trench 206, and the top of the shielding gate polysilicon layer 205. The thermal oxide layer on the epitaxial layer 201 on both sides of the first trench 204, the sidewalls of the second trench 206 close to the epitaxial layer 201, and the sidewalls of the third trench 206 close to the epitaxial layer 201 serve as the gate oxide layer 207, and the thermal oxide layer on the surface of the protruding portion of the shielding gate polysilicon layer 205 serves as the inter-gate oxide layer 208, corresponding to Figure 5 .

[0082] S107: depositing a control gate polysilicon layer 209 in both the second trench 206 and the third trench 206, corresponding to Figure 6 .

[0083] S108: performing a first ion implantation on the epitaxial layer 201 on both sides of the first trench 204 to form a well region 210 in the second region of the epitaxial layer 201; and performing a second ion implantation on the well region 210 to form a source region 211 in the third region of the well region 210, corresponding to Figure 7 .

[0084] S109: Depositing an interlayer dielectric layer 212 on the substrate, the interlayer dielectric layer 212 covers the control gate polysilicon layer 209, the control gate polysilicon layer 209 and the intergate thermal oxide layer, corresponding to Figure 8 .

[0085] S110: forming a contact hole 213 on the interlayer dielectric layer 212, wherein the contact hole 213 penetrates the interlayer dielectric layer 212 and is electrically connected to the control gate polysilicon layer 209. Figure 9 .

[0086] S111: Depositing a metal connection layer 214 on the surface of the contact hole 213 and the surface of the interlayer dielectric layer 212, corresponding to Figure 10 .

[0087] The problems with this embodiment are:

[0088] 1. Because the thermal oxidation process forms an oxide layer on the epitaxial layer 201, a certain percentage of the epitaxial layer 201 itself is consumed. Therefore, in step S103, a thermal oxidation process generates a 5000-7000 angstrom thick thermal oxide layer on the surface of the epitaxial layer 201 and the sidewalls of the first trench 204. This consumes a large area of ​​the epitaxial layer 201, causing the first trench 204 to continuously expand in size, thereby increasing the volume of the cellular structure. Since the cellular structure is a substructure of the SGT tube, the increase in the cellular structure volume reduces the density of the cellular structure in the SGT tube, thereby increasing the SGT tube's specific on-resistance. Furthermore, due to the high consumption of the epitaxial layer 201 in step S103, a thinner epitaxial layer 201 or an epitaxial layer 201 with a higher doping ion concentration cannot be used, thereby failing to reduce the SGT tube's turn-on loss and further increasing the SGT tube's specific on-resistance.

[0089] 2. A portion of the trench thermal oxide layer 203 within the first trench 204 must be removed in step S105 before the gate oxide layer 207 can be formed in step S106. On the one hand, the process of forming the gate oxide layer 207 further consumes the epitaxial layer 201, thereby further expanding the size of the first trench 204 and further increasing the specific on-resistance of the SGT transistor. On the other hand, during the process of forming the gate oxide layer 207, oxygen will also affect the remaining trench thermal oxide layer 203, further increasing the specific on-resistance of the SGT transistor.

[0090] 3. The industry has relatively low requirements for the thickness of the gate oxide layer 207, and the thickness of the gate oxide layer 207 is generally between 500 angstroms and 1000 angstroms. Furthermore, because the gate oxide layer 207 and the inter-gate oxide layer 208 are formed simultaneously in step S106, the thickness of the inter-gate oxide layer 208 is also between 500 angstroms and 1000 angstroms. The thickness of the inter-gate oxide layer 208 affects the gate-source capacitance of the cellular structure, and the thinner the inter-gate oxide layer 208, the greater the gate-source capacitance of the cellular structure. The gate-source capacitance of the cellular structure affects the conduction speed of the SGT tube. The larger the gate-source capacitance of the cellular structure, the slower the conduction speed of the SGT tube. Therefore, the industry requires that the thickness of the inter-gate oxide layer 208 be greater than 1500 angstroms. Therefore, in this embodiment, the thickness of the inter-gate oxide layer 208 is only 500 angstroms to 1000 angstroms, which makes the gate-source capacitance of the cellular structure too large, resulting in a too slow conduction speed of the SGT tube, and further resulting in excessive turn-on loss of the SGT tube.

[0091] In view of this, a first technical solution of the present invention provides a new method for preparing a device structure of an SGT MOS transistor, which is used to prepare the device structure of the SGT transistor.

[0092] in, Figure 11 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 1 . Figures 12 to 21 They are schematic diagrams of simplified cross-sectional structures corresponding to different preparation stages of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention.

[0093] Please refer to Figures 11 to 21 The method for preparing the device structure of the SGT MOS tube provided by the technical solution of the present invention comprises the following steps:

[0094] S1: Provide an N-type silicon substrate 10.

[0095] S2 : forming an epitaxial layer 20 on the N-type silicon substrate 10 .

[0096] S3: forming a first groove 30 in the first region of the epitaxial layer 20, corresponding to Figure 12 .

[0097] S4: thermally oxidizing the surface of the epitaxial layer 20 and the sidewall of the first groove 30 to form a first thermal oxide layer 40 on the surface of the epitaxial layer 20 and the sidewall of the first groove 30, corresponding to Figure 13 .

[0098] The thickness of the first thermal oxidation layer 40 is controlled by specific conditions such as the furnace tube temperature, process time, and oxygen flow rate in the thermal oxidation process. The specific control method is a conventional technical means in this field and will not be repeated here.

[0099] S5: Sequentially depositing an isolation layer 50 and a trench oxide layer 60 on the surface of the epitaxial layer 20 and the first thermal oxide layer 40 on the sidewall of the first groove 30, corresponding to Figure 14 .

[0100] S6: depositing a first polysilicon layer 70 in the first groove 30, wherein the first polysilicon layer 70 is located on the trench oxide layer 60, and the top of the first polysilicon layer 70 is flush with the surface of the epitaxial layer 20, corresponding to Figure 15 .

[0101] S7: removing the trench oxide layer 60 on the surface of the epitaxial layer 20 and a portion of the trench oxide layer 60 in the first groove 30, so that the first polysilicon layer 70 protrudes from the remaining trench oxide layer 60 in the first groove 30; wherein the first polysilicon layer 70 and the first thermal oxide layer 40 and the remaining trench oxide layer 60 on both sides thereof form a second groove 90 and a third groove 90, respectively, corresponding to Figure 16 .

[0102] S8: Thermally oxidizing the portion of the first polysilicon layer 70 protruding from the trench oxide layer 60 to form a second thermal oxide layer 80 on the surface of the portion of the first polysilicon layer 70 protruding from the trench oxide layer 60, corresponding to Figure 17 .

[0103] The thickness of the second thermal oxidation layer 80 is also controlled by specific conditions such as the furnace temperature, process time, and oxygen flow rate in the thermal oxidation process. The specific control method is a conventional technical means in this field and will not be repeated here.

[0104] S9: removing the isolation layer 50 on the surface of the epitaxial layer 20 and a portion of the isolation layer 50 in the first groove 30, corresponding to Figure 18 .

[0105] S10: depositing a second polysilicon layer 100 in both the second groove and the third groove, and the top of the second polysilicon layer 100 is flush with the surface of the epitaxial layer 20, corresponding to Figure 19 .

[0106] S11: performing a first ion implantation on the epitaxial layer 20 on both sides of the first groove 30 to form a P-type well region 120 in the second region of the epitaxial layer 20; and performing a second ion implantation on the P-type well region 120 to form an N-type source region 110 in the third region of the P-type well region 120, corresponding to Figure 20 .

[0107] S12: Depositing an interlayer dielectric layer 130 on the N-type silicon substrate 10, the interlayer dielectric layer 130 covers the source region, the second polysilicon layer 100 and the second thermal oxide layer 80, corresponding to Figure 21 .

[0108] Through the above technical means, the technical solution of the present invention can greatly reduce the specific on-resistance and turn-on loss of SGT tubes. The specific principle is as follows:

[0109] Because the existing technology requires the generation of a trench thermal oxide layer of 5000-7000 angstroms, the epitaxial layer 20 will be greatly damaged, and the size of the first trench will be expanded. Therefore, when generating the first thermal oxide layer 40 in step S4, the thickness will be made very thin, and the thickness can range from 500-800 angstroms, which is equivalent to the thickness requirement of the gate oxide layer in the existing technology. The advantages of doing so are: on the one hand, it greatly reduces the loss of the epitaxial layer 20 and reduces the expansion of the first groove 30 during the thermal oxidation process, thereby reducing the volume of the device structure and improving the voltage resistance of the SGT tube. Alternatively, while maintaining the same voltage resistance, the epitaxial layer 20 with a large thickness or a high doping ion concentration can be selected, thereby greatly reducing the specific on-resistance of the SGT tube. On the other hand, the first thermal oxide layer 40 can serve as the gate oxide layer of the existing technology, which is equivalent to completing the gate oxide layer in advance, and the preparation of the gate oxide layer and the preparation of the inter-gate oxide layer are separated by the isolation layer 50, so that the thickness of the inter-gate oxide layer is not affected by the thickness of the gate oxide layer.

[0110] At the same time, in order to make the trench oxide layer 60 meet the voltage resistance and isolation requirements of the device, even if the thickness of the trench oxide layer 60 is between 5000 angstroms and 7000 angstroms. Step S5 first deposits the isolation layer 50 on the surface of the first thermal oxide layer 40 to completely isolate the first thermal oxide layer 40 from oxygen. The advantage of doing so is that, on the one hand, when the second thermal oxide layer 80 is prepared separately in the subsequent step S8, oxygen will not come into contact with the first thermal oxide layer 40, thereby avoiding the consumption of the epitaxial layer 20, that is, avoiding the expansion of the first groove 30. On the other hand, there is no need to prepare the trench oxide layer 60 through a thermal oxidation process, but it can be prepared directly by chemical deposition or the like, so that the trench oxide layer 60 can be made very thick to meet the voltage resistance and isolation requirements of the device, and will not affect the size of the epitaxial layer 20 and the first groove 30, so as to affect the specific on-resistance of the SGT tube.

[0111] Because the isolation layer 50 is provided, the second thermal oxide layer 80 (i.e., the inter-gate oxide layer in the prior art) can be prepared in step S8 to a desired thickness. This avoids the problem of excessive gate-source capacitance in the cell structure caused by an overly thin inter-gate oxide layer, as is the case in the prior art. This improves the conduction speed of the SGT transistor and, in turn, reduces the turn-on loss of the SGT transistor. Furthermore, because the turn-on loss of the SGT transistor is positively correlated with the specific on-resistance of the SGT transistor, this also reduces the specific on-resistance of the SGT transistor.

[0112] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0113] in, Figure 22 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 2 . Figure 23 yes Figure 22 Schematic diagram of the simplified cross-sectional structure corresponding to the preparation process shown.

[0114] Please refer to Figure 22 and Figure 23 As a specific embodiment, before thermally oxidizing the portion of the first polysilicon layer 70 protruding from the trench oxide layer 60 in S8, the method further includes:

[0115] S71 : thinning the width of a portion of the first polysilicon layer 70 protruding from the trench oxide layer 60 , so that the width of the protruding portion of the first polysilicon layer 70 is a first width.

[0116] The specific size of the first width can be set according to needs, and even the protruding portion of the first polysilicon layer 70 can be completely oxidized during the thermal oxidation process, which is not limited here.

[0117] The beneficial effect of this embodiment is that: since the second thermal oxide layer 80 is thickened in step S8, before the second thermal oxide layer 80 is generated, the width of the protruding portion of the first polysilicon layer 70 is thinned, or even the protruding portion of the first polysilicon layer 70 is completely oxidized, so that the width of the isolation structure located in the middle of the second polysilicon layer 100 remains unchanged or even reduced compared with the prior art. The isolation structure is composed of the second thermal oxide layer 80, the protruding portion of the first polysilicon layer 70 and the second thermal oxide layer 80. If the width of the isolation structure is too large, it will occupy the space of the second polysilicon layer 100, thereby affecting the connection between the subsequent contact hole and the second polysilicon layer 100. Therefore, by thinning the width of the protruding portion of the first polysilicon layer 70 or even completely oxidizing it, it can ensure that the gate-source capacitance of the device structure is reduced while avoiding affecting the connection between the contact hole and the second polysilicon layer 100.

[0118] If the width of the isolation structure is reduced, the size of the first groove 30 can also be reduced during the design phase, thereby reducing the specific on-resistance of the SGT tube.

[0119] in, Figure 24 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 3 .

[0120] Please refer to Figure 23 and Figure 24 Specifically, in S71, the width of the protruding portion of the first polysilicon layer 70 is thinned, which specifically includes:

[0121] S711 : etching the lateral structure of the protruding portion of the first polysilicon layer 70 so that the width of the protruding portion of the first polysilicon layer 70 is a first width.

[0122] In this embodiment, the width of the protruding portion of the first polysilicon layer 70 is directly reduced by etching. The etching method may include wet etching or dry etching. The specific implementation of wet etching or dry etching is a conventional technical method in the art and will not be repeated here.

[0123] in, Figure 25 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 4 .

[0124] Please refer to Figure 23 and Figure 25 Specifically, in S71, the width of the protruding portion of the first polysilicon layer 70 is reduced, and specifically further includes:

[0125] S721: thermally oxidizing the protruding portion of the first polysilicon layer 70 to form a thermal oxide layer on the surface of the protruding portion of the first polysilicon layer 70;

[0126] S722: removing the thermal oxide layer on the surface of the protruding portion of the first polysilicon layer 70;

[0127] S723: repeating step S721 and step S722 to make the width of the protruding portion of the first polysilicon layer 70 be the first width.

[0128] Since a certain proportion of polysilicon will be lost during the thermal oxidation process, this embodiment performs multiple oxidation and deoxidation on the protruding portion of the first polysilicon layer 70 to reduce the width of the protruding portion of the first polysilicon layer 70 .

[0129] It should be noted that the process of thermally oxidizing the protruding portion of the first polysilicon layer 70 and the process of removing the resulting thermally oxidized layer are conventional technical means in this field and will not be described in detail here.

[0130] in, Figure 26 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 5 . Figure 27 yes Figure 26 Schematic diagram of the simplified cross-sectional structure corresponding to the preparation process shown.

[0131] Please refer to Figure 26 and Figure 7 As a specific embodiment, thermally oxidizing the portion of the first polysilicon layer 70 protruding from the trench oxide layer 60 in S8 specifically includes:

[0132] S81 : thermally oxidizing the protruding portion of the first polysilicon layer 70 to completely oxidize the protruding portion of the first polysilicon layer 70 .

[0133] in, Figure 28 The process of the device structure preparation method of the SGT MOS tube provided by the technical solution of the present invention is as follows Figure 6 .

[0134] Please refer to Figure 28 As a specific embodiment, before depositing the second polysilicon layer in S10, the method further includes:

[0135] S91: performing thermal annealing on the exposed first thermal oxide layer.

[0136] This embodiment has the beneficial effect that thermal annealing can repair the surface of the first thermal oxide layer, thereby optimizing the anti-leakage performance of the device structure.

[0137] It should be noted that the thermal annealing process is a common technical means in this field and will not be described in detail here.

[0138] As a specific embodiment, the thickness of the first thermal oxide layer ranges from 500 angstroms to 800 angstroms. The thickness of the isolation layer ranges from 200 angstroms to 2000 angstroms. The thickness of the trench oxide layer ranges from 1000 angstroms to 5000 angstroms. Of course, the specific thickness of the isolation layer and the specific thickness of the trench oxide layer can be selected according to the withstand voltage requirements of the device structure and are not limited here.

[0139] Specifically, the isolation layer includes at least one of nitride, metal oxide, HfO2 and aluminum oxide. Of course, any high-K dielectric material with isolation function can be used as the isolation layer, and this is not limited here.

[0140] As a specific embodiment, the material of the trench oxide layer may specifically include a TEOS (tetraethyl orthosilicate) oxide layer. Of course, any oxide layer with an isolation function falls within the scope of protection of the present invention and is not limited here.

[0141] As a specific embodiment, the material of the substrate may include any one of silicon, germanium, silicon germanium or silicon carbide, which is not limited here.

[0142] It should be noted that if the substrate material used is a P-type silicon substrate, an N-type well region is generated through the first ion implantation in step S11 , and a P-type source region is generated through the second ion implantation in step S12 .

[0143] As a specific embodiment, the size and location of the first region of the epitaxial layer in step S3, the second region of the epitaxial layer in step S11, and the third region of the P-type well region can be set as needed and are not limited herein. For example, in step S3, a first recess is formed in the first region of the epitaxial layer. The size of the first region can be set based on the pre-designed opening diameter of the first recess.

[0144] As a specific implementation, the depth of etching the trench oxide layer in step S7 is generally 1 μm-1.5 μm. The specific depth is related to the thickness of the P-type well region generated in step S11 and is not limited here.

[0145] In summary, in the method for preparing the device structure of an SGT MOS tube provided by an embodiment of the present invention, in step S4, the first thermal oxide layer can be prepared very thin to serve as the gate oxide layer of the device structure. On the one hand, the loss of the epitaxial layer is greatly reduced, and the expansion of the first groove during the thermal oxidation process is reduced, thereby reducing the volume of the device structure and improving the voltage resistance of the SGT tube. Alternatively, while maintaining the same voltage resistance, the epitaxial layer with a large thickness or a high doping ion concentration can be selected, thereby greatly reducing the specific on-resistance of the SGT tube. On the other hand, the preparation of the gate oxide layer and the preparation of the inter-gate oxide layer are separated by the isolation layer, so that the thickness of the inter-gate oxide layer is not affected by the thickness of the gate oxide layer.

[0146] In step S5, the isolation layer is first deposited on the surface of the first thermal oxide layer to completely isolate the first thermal oxide layer from oxygen. On the one hand, this ensures that when the second thermal oxide layer is separately prepared in the subsequent step S8, oxygen will not come into contact with the first thermal oxide layer, thereby avoiding consumption of the epitaxial layer, that is, avoiding the expansion of the first groove. On the other hand, there is no need to prepare the trench oxide layer through a thermal oxidation process, but it can be directly prepared through chemical deposition or other methods. This allows the trench oxide layer to be made very thick to meet the device's voltage resistance and isolation requirements, while not affecting the size of the epitaxial layer and the first groove, which would affect the SGT tube's specific on-resistance.

[0147] Furthermore, before generating the second thermal oxide layer, the width of the protruding portion of the first polysilicon layer is thinned so that the width of the isolation structure located in the middle of the second polysilicon layer remains unchanged or even decreases compared with the prior art, thereby ensuring that the gate-source capacitance of the device structure is reduced while avoiding affecting the connection between the contact hole and the second polysilicon layer.

[0148] Furthermore, before depositing the second polysilicon layer in S10 , thermal annealing is performed on the exposed first thermal oxide layer to repair the surface of the first thermal oxide layer, thereby optimizing the anti-leakage performance of the device structure.

[0149] The device structure manufactured above is specifically the device component structure in each cellular structure in the SGT tube. The following will describe each cellular structure in the SGT tube and the SGT tube structure:

[0150] The second technical solution of the present invention provides a new cellular structure.

[0151] in, Figure 29 It is a simplified cross-sectional structural diagram of the cellular structure provided by the technical solution of the present invention.

[0152] Please refer to Figure 29, the cellular structure provided by the technical solution of the present invention includes:

[0153] A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS transistor provided in the previous technical solution;

[0154] a first contact hole 140 , the first contact hole 140 penetrating the interlayer dielectric layer 130 and electrically connected to the N-type source region 110 and the P-type well region 120 ;

[0155] The first metal connection layer 150 is located on the surface of the first contact hole 140 and the surface of the interlayer dielectric layer 130 respectively.

[0156] The third technical solution of the present invention also provides another new cellular structure.

[0157] in, Figure 30 It is a simplified cross-sectional structural diagram of another cellular structure provided by the technical solution of the present invention.

[0158] Please refer to Figure 30 , the cellular structure provided by the technical solution of the present invention includes:

[0159] A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of the SGT MOS transistor;

[0160] a second contact hole 160 , the second contact hole 160 penetrating the interlayer dielectric layer 130 and electrically connected to the second polysilicon layer 100 ;

[0161] The second polysilicon layer 170 is located on the surface of the second contact hole 160 and the surface of the interlayer dielectric layer 130 respectively.

[0162] The fourth technical solution of the present invention further provides a new SGT pipe.

[0163] in, Figure 31 This is a simplified cross-sectional structural diagram of the SGT pipe provided by the technical solution of the present invention.

[0164] Please refer to Figure 31 The SGT pipe provided by the technical solution of the present invention includes:

[0165] N-type silicon substrate 10;

[0166] a plurality of first cellular structures 1, wherein the first cellular structures 1 are located on the surface of the N-type silicon substrate 10, and the first cellular structures 1 include the cellular structure of the SGT tube provided by the second technical solution of the present invention;

[0167] a plurality of second cellular structures 2, wherein the second cellular structures 2 are located on the surface of the N-type silicon substrate 10, and the second cellular structures 2 include the cellular structure of the SGT tube provided by the third technical solution of the present invention;

[0168] a plurality of third cellular structures 3, each located on a surface of the N-type silicon substrate 10, comprising: a second device structure, the second device structure being fabricated by steps S1 to S6 of the method for fabricating a device structure of the SGTMOS transistor provided by the first technical solution of the present invention; a third contact hole 180, the third contact hole 180 penetrating the interlayer dielectric layer 130 and electrically connected to the first polysilicon layer 70; and a third metal connection layer 190, the third metal connection layer 190 being respectively located on surfaces of the third contact hole 180 and the interlayer dielectric layer 130;

[0169] The first polysilicon layer 70 in the first cellular structure 1, the second cellular structure 2 and the third cellular structure 3 is connected to each other, and the second polysilicon layer 100 in the first cellular structure 1 and the second cellular structure 2 is connected to each other;

[0170] The second polysilicon layer 170 in the second cell structure 2 serves as the gate of the SGT tube, the third metal connection layer 190 in the third cell structure 3 serves as the source of the SGT tube, and the bottom edge of the N-type silicon substrate 10 serves as the drain of the SGT tube.

[0171] Specifically, the first cell structure 1 serves as the source cell structure of the SGT transistor, the second cell structure 2 serves as the control electrode structure of the SGT transistor, and the third cell structure 3 serves as the source shield gate connection electrode structure of the SGT transistor.

[0172] Of course, the N-type silicon substrate 10 may also be made of other materials such as a P-type silicon substrate, and the types and concentrations of ions implanted in the first ion implantation and the second ion implantation may also vary adaptively.

[0173] The fifth technical solution of the present invention further provides an electronic device, comprising the SGT tube provided by the fourth technical solution of the present invention.

[0174] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for preparing a device structure of an SGT MOS tube, characterized in that: A device structure for preparing an SGT tube, the method comprising: S1: providing a substrate; S2: forming an epitaxial layer on the substrate; S3: forming a first groove in a first region of the epitaxial layer; S4: performing a thermal oxidation treatment on the surface of the epitaxial layer, the sidewalls of the first groove, and the bottom of the first groove to form a first thermal oxide layer on the surface of the epitaxial layer, the sidewalls of the first groove, and the bottom of the first groove; S5: sequentially depositing an isolation layer and a trench oxide layer on the surface of the epitaxial layer, the sidewalls of the first groove, and the first thermal oxide layer on the bottom of the first groove; S6: depositing a first polysilicon layer in the first groove, wherein the first polysilicon layer is located on the trench oxide layer, and a top of the first polysilicon layer is flush with a surface of the epitaxial layer; S7: removing the trench oxide layer on the surface of the epitaxial layer and a portion of the trench oxide layer in the first groove, so that the first polysilicon layer protrudes from the remaining trench oxide layer in the first groove; wherein the first polysilicon layer and the first thermal oxide layer and the remaining trench oxide layer on both sides thereof form a second groove and a third groove respectively; S8: thermally oxidizing a portion of the first polysilicon layer protruding from the trench oxide layer to form a second thermal oxide layer on a surface of the portion of the first polysilicon layer protruding from the trench oxide layer; S9: removing the isolation layer on the surface of the epitaxial layer and a portion of the isolation layer in the first groove; S10: depositing a second polysilicon layer in both the second groove and the third groove, with the top of the second polysilicon layer flush with the surface of the epitaxial layer; S11: performing a first ion implantation on the epitaxial layer on both sides of the first groove to form a well region in the second region of the epitaxial layer; and performing a second ion implantation on the well region to form a source region in the third region of the well region; S12: depositing an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the source region, the second polysilicon layer, and the second thermal oxide layer.

2. The method for preparing the device structure of the SGT MOS transistor according to claim 1, characterized in that: Before thermally oxidizing the portion of the first polysilicon layer protruding from the trench oxide layer in S8, the method further includes: S71: thinning the width of a portion of the first polysilicon layer protruding from the trench oxide layer, so that the width of the protruding portion of the first polysilicon layer is a first width.

3. The method for preparing the device structure of the SGT MOS transistor according to claim 2, characterized in that: S71 thins the width of the protruding portion of the first polysilicon layer, specifically including: S711: Etching the lateral structure of the protruding portion of the first polysilicon layer to make the width of the protruding portion of the first polysilicon layer be a first width.

4. The method for preparing the device structure of the SGT MOS transistor according to claim 2, characterized in that: S71 thins the width of the protruding portion of the first polysilicon layer, specifically including: S721: thermally oxidizing the protruding portion of the first polysilicon layer to form a thermal oxide layer on the surface of the protruding portion of the first polysilicon layer; S722: removing the thermal oxide layer on the surface of the protruding portion of the first polysilicon layer; S723: repeating step S721 and step S722 to make the width of the protruding portion of the first polysilicon layer be the first width.

5. The method for preparing the device structure of the SGT MOS transistor according to claim 2, characterized in that: S8 thermally oxidizes a portion of the first polysilicon layer protruding from the trench oxide layer, specifically comprising: S81: thermally oxidizing the protruding portion of the first polysilicon layer to completely oxidize the protruding portion of the first polysilicon layer.

6. The method for preparing the device structure of the SGT MOS transistor according to claim 1, characterized in that: The thickness of the first thermal oxide layer ranges from 500 angstroms to 800 angstroms.

7. The method for preparing the device structure of the SGT MOS transistor according to claim 1, characterized in that: Before depositing the second polysilicon layer in S10, the method further includes: S91: performing thermal annealing on the exposed first thermal oxide layer.

8. The method for preparing the device structure of the SGT MOS transistor according to claim 1, characterized in that: The isolation layer includes at least any one of nitride, metal oxide, HfO2 and aluminum oxide.

9. The method for preparing the device structure of the SGT MOS transistor according to claim 1, characterized in that: The trench oxide layer includes a TEOS oxide layer.

10. A cellular structure of an SGT tube, characterized in that: The cellular structure includes: A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of an SGT MOS transistor according to any one of claims 1 to 9; a first contact hole, wherein the first contact hole penetrates the interlayer dielectric layer and is electrically connected to the source region and the well region; A first metal connection layer is located on a surface of the first contact hole and a surface of the interlayer dielectric layer.

11. A cellular structure of an SGT tube, characterized in that: The cellular structure includes: A first device structure, wherein the first device structure is manufactured by the device structure manufacturing method of an SGT MOS transistor according to any one of claims 1 to 9; a second contact hole, the second contact hole penetrating the interlayer dielectric layer and electrically connected to the second polysilicon layer; A second metal connection layer is located on a surface of the second contact hole and a surface of the interlayer dielectric layer respectively.

12. An SGT pipe, characterized in that: include: substrate; a plurality of first cellular structures, wherein the first cellular structures are located on a surface of the substrate, and the first cellular structures include the cellular structure of the SGT tube according to claim 10; a plurality of second cellular structures, the second cellular structures being located on the surface of the substrate, the second cellular structures comprising the cellular structure of the SGT tube according to claim 11; a plurality of third cellular structures, the third cellular structures being located on the surface of the substrate, the third cellular structures comprising: a second device structure, the second device structure being manufactured by steps S1 to S6 of the method for manufacturing a device structure of an SGT MOS transistor according to claim 1; a third contact hole, the third contact hole penetrating the interlayer dielectric layer and electrically connected to the first polysilicon layer; and a third metal connection layer, the third metal connection layer being respectively located on surfaces of the third contact hole and the interlayer dielectric layer; The first polysilicon layers in the first cellular structure, the second cellular structure, and the third cellular structure are connected to each other, and the second polysilicon layers in the first cellular structure and the second cellular structure are connected to each other; The second metal connection layer in the second cell structure serves as the gate of the SGT tube, the third metal connection layer in the third cell structure serves as the source of the SGT tube, and the bottom edge of the substrate serves as the drain of the SGT tube.

13. An electronic device, characterized in that: include: The SGT pipe according to claim 12.

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