Vertical power semiconductor device including SiC semiconductor body

Abstract

The invention relates to a vertical power semiconductor device including a SiC semiconductor body. A power semiconductor device is presented. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnection region electrically coupling the gate electrode of the gate structure and the gate pad of the gate pad region via a gate interconnect. The vertical power semiconductor device also includes a source electrode or an emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric including a first interface for the source electrode or the emitter electrode and a second interface for at least one of the gate electrode or the gate interconnect or the gate pad, and wherein a conduction band offset at the first interface is in a range from 1 eV to 2.5 eV.

Description

Technical Field

[0001] The present disclosure relates to a vertical power semiconductor device, and in particular to a vertical power semiconductor device including a SiC semiconductor body. Background Art

[0002] Technology development of new generation SiC power semiconductor devices (e.g., insulated gate field effect transistors (IGFETs), such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs)) aims to improve electrical device characteristics, such as short circuit withstand time. When improving the short circuit withstand time of SiC power semiconductor devices, various tradeoffs and challenges must be met.

[0003] There is a need to improve the short circuit current capability of SiC power semiconductor devices. Summary of the invention

[0004] Examples of the present disclosure relate to a vertical power semiconductor device. The vertical power semiconductor device includes: a silicon carbide SiC semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnect region, a gate electrode of the gate structure and a gate pad of the gate pad region are electrically coupled via a gate interconnect. The power semiconductor device also includes a source electrode or an emitter electrode. The power semiconductor device also includes: a first interlayer dielectric including a first interface for the source electrode or the emitter electrode and a second interface for at least one of the gate electrode or the gate interconnect or the gate pad. The value of the conduction band offset at the first interface is in the range from 1eV to 2.5eV.

[0005] Another example of the present disclosure relates to a vertical power semiconductor device. The vertical power semiconductor device includes: a silicon carbide SiC semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnect region, a gate electrode of the gate structure and a gate pad of the gate pad region being electrically coupled via a gate interconnect. The power semiconductor device also includes a source electrode or an emitter electrode. The power semiconductor device also includes: a first interlayer dielectric including a first interface for the source electrode or the emitter electrode and a second interface for at least one of the gate electrode or the gate interconnect or the gate pad. The value of the valence band offset at the second interface is in the range of from 1.0 eV to 2.5 eV.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of SiC power semiconductor devices and together with the description serve to explain the principles of the embodiments. Additional embodiments are described in the following detailed description and claims.

[0008] Figure 1 A view schematically and exemplarily showing a configuration example of a SiC power semiconductor device including a first interlayer dielectric including a first interface for a source electrode or an emitter electrode and a second interface for a gate electrode or a gate interconnect or a gate pad.

[0009] Figure 2 A partial cross-sectional view schematically and exemplarily showing a configuration example of a SiC power MOSFET including a trench gate structure.

[0010] Figure 3A and 3B A partial cross-sectional view and a top view schematically and exemplarily show an interconnection region of a configuration example of a SiC power MOSFET.

[0011] Figure 4A and 4B A top view and a partial cross-sectional view schematically and exemplarily show a gate pad region of a configuration example of a SiC power MOSFET.

[0012] Figure 5 An energy band diagram including the valence band energy Ev of a second interface between a first interlayer dielectric and one of a gate electrode or a gate interconnect or a gate pad is schematically and exemplarily shown. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific examples of processable semiconductor substrates are illustrated as diagrams. It should be understood that other examples may be used and structural or logical changes may be implemented without departing from the scope of the present disclosure. For example, features illustrated or described for one example can be used on other examples or used in conjunction with other examples to produce another example. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The accompanying drawings are not drawn to scale and are for illustration purposes only. If not otherwise indicated, corresponding elements are designated by the same reference numerals in different drawings.

[0014] The terms "having", "containing", "including", "comprising" and the like are open ended and indicate the presence of stated structures, elements or features but do not exclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0015] The term "electrically connected" may describe a permanent low resistance connection between electrically connected elements, such as direct contact between the elements involved or a low resistance connection via metal and / or heavily doped semiconductor materials. The term "electrically coupled" may include that one or more intervening elements suitable for signal and / or power transfer may be connected between the electrically coupled elements, such as elements that may be controlled to temporarily provide a low resistance connection in a first state and a high resistance electrical decoupling in a second state.

[0016] If two elements A and B are combined using "or", if not explicitly or implicitly defined otherwise, this should be understood to disclose all possible combinations, i.e. only A, only B and A and B. Alternative wordings for the same combination are "at least one of A and B" or "A and / or B". The same applies to combinations of more than two elements, if appropriately modified.

[0017] Ranges given for physical dimensions include the boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value (e.g., "at most" and "at least").

[0018] The main components of a layer or structure of a chemical compound or alloy are such elements whose atoms form said chemical compound or alloy.For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0019] The term “on” should not be interpreted as meaning only “directly on.” On the contrary, if an element is disposed “on another element” (for example, a layer is “on another layer” or “on a substrate”), another component (for example, another layer) may be disposed between the two elements (for example, if a layer is “on a substrate,” another layer may be disposed between the layer and the substrate).

[0020] An example configuration of a vertical power semiconductor device includes: a silicon carbide SiC semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnect region, a gate electrode of the gate structure and a gate pad of the gate pad region being electrically coupled via a gate interconnect. The vertical power semiconductor device also includes a source electrode or an emitter electrode. The power semiconductor device also includes: a first interlayer dielectric including a first interface for the source electrode or the emitter electrode and a second interface for at least one of the gate electrode or the gate interconnect or the gate pad. The value of the conduction band offset at the first interface may be in the range of 1eV to 2.5eV or from 1.5eV to 2.1eV.

[0021] For example, the power semiconductor device may be part of an integrated circuit, or may be a discrete semiconductor device or a semiconductor module. For example, the power semiconductor device may be or may include an insulated gate field effect transistor (IGFET), such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The power semiconductor device may be: a vertical power semiconductor device having a load current flowing between a first surface and a second surface opposite to the first surface. The vertical power semiconductor device may be configured to conduct a current exceeding 1A or exceeding 10A or exceeding 30A or exceeding 50A or exceeding 75A or even exceeding 100A, and may also be configured to block a voltage between load electrodes (e.g., between the collector and emitter on an IGBT, or between the drain and source of a MOSFET) in a range of hundreds or up to several thousand volts, such as 400V, 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV, 10kV. For example, the blocking voltage may correspond to a voltage level specified in a data sheet of the power semiconductor device.

[0022] The power semiconductor device may be based on a semiconductor body from a crystalline SiC semiconductor material having a band gap larger than that of silicon (i.e., larger than 1.12 eV). For example, the semiconductor material may be 2H-SiC (SiC in 2H polymorph), 6H-SIC or 15R-SiC. According to an example, the semiconductor material is silicon carbide in 4H polymorph (4H-SiC). The semiconductor body may include or consist of a semiconductor substrate having no semiconductor layer (e.g., a layer grown epitaxially), one or more than one semiconductor layer thereon.

[0023] For example, the first surface may be a front surface or top surface of the semiconductor body, and the second surface may be a back surface or rear surface of the semiconductor body. For example, the semiconductor body may be attached to a lead frame via the second surface. On the first surface of the semiconductor body, for example, bonding pads may be arranged, and bonding wires may be bonded on the bonding pads.

[0024] In order to achieve the desired current carrying capacity, a vertical SiC power semiconductor device can be designed by a plurality of transistor primitives connected in parallel. The transistor primitives connected in parallel may be, for example, transistor primitives formed in the shape of a strip or a strip segment. Of course, the transistor primitives can also have any other shape, such as a circle, an ellipse, a polygon (such as a hexagon or an octahedron). The transistor primitives are arranged in a transistor primitive region of a SiC semiconductor body. The transistor primitive region may be an active region, in which the emitter region of an IGBT (or the source region of a MOSFET) and the collector region of an IGBT (or the drain region of a MOSFET) are arranged relative to each other along a vertical direction. In the active region, for example, through a contact plug on the first surface of the SiC semiconductor body, a load current may enter or leave the semiconductor body of the power semiconductor device. The power semiconductor device may also include an edge termination region, which may include a termination structure. In a blocking mode of the power semiconductor device or in a reverse bias mode of the power semiconductor device, a blocking voltage between the transistor primitive region and the field-free region decreases laterally across the termination structure. The termination structure may have a higher or slightly lower voltage blocking capability than the transistor cell region. For example, the termination structure may include a junction termination extension (JTE) with or without lateral doping variation (VLD), one or more laterally separated guard rings, or any combination thereof.

[0025] For example, the gate structure may be a planar gate structure, or may be a trench gate structure. The gate structure may be strip-shaped. The gate structure may also have another layout or geometric shape in a plan view, such as a hexagon, a square, a circle, an ellipse. For example, via a gate interconnect, the gate electrode of the gate structure may be electrically connected to a gate pad in a gate pad region. The gate interconnect or a portion thereof may be arranged outside the transistor primitive region, for example, in an interconnect region, the interconnect region being arranged laterally between the transistor primitive region and the edge termination region. The gate interconnect may include one or more conductive materials, for example: a metal, a metal alloy, such as Cu, Au, AlCu, Ag or an alloy thereof; a metal compound, such as TiN; a highly doped semiconductor material, such as highly doped polysilicon. For example, the one or more conductive materials may form a layer stack. At least a portion of the gate interconnect may be a so-called gate runner, which merges with the gate pad. The gate pad and, for example, a first load electrode pad (for example, a source pad of a MOSFET or an emitter pad of an IGBT) may be part of a wiring region on a SiC semiconductor body. The wiring region may include one or more than one (e.g., two, three, four or even more) wiring levels. Each wiring level may be formed by a single conductive layer or a stack of conductive layers (e.g., (one or more) metal layers). For example, the wiring levels may be patterned in a lithographic manner. Between the stacked wiring levels, an interlayer dielectric structure may be arranged. (One or more) contact plugs and / or (one or more) contact lines may be formed in the openings of the interlayer dielectric structure to electrically connect the parts of different wiring levels (e.g., metal lines or contact regions) to each other. For example, the source electrode or emitter electrode may include one or more parts, such as a source or emitter pad, a source or emitter line (or source or emitter pad track) in an interconnect region, and a source or emitter trench filling material (e.g., n-doped polysilicon) in a trench structure below a gate pad. The one or more parts of the source electrode or emitter electrode are electrically connected and may be formed of different, partially different, or the same conductive materials. For example, the source pad or emitter pad and / or the source or emitter line of the source electrode or emitter electrode may be formed from one or more metals or metal alloys, and, for example, the source or emitter trench filling material under the gate pad may be formed from doped polysilicon (such as, highly doped n-type polysilicon).

[0026] The first interlayer dielectric may be arranged in at least one of the following regions: arranged in the transistor cell region, for example, directly above the gate electrode and directly below the source electrode or the emitter electrode; arranged in the gate interconnect region, for example, arranged laterally between the gate interconnect (such as the gate track) and the source or emitter line of the source electrode or the emitter electrode; arranged in the gate pad region, for example, arranged directly above the source or emitter trench filling material of the source electrode or the emitter electrode and arranged directly below the gate pad. Therefore, in at least one region of the transistor cell region, the interconnect region or the gate pad region, the first interface and the second interface of the first dielectric layer may face each other.

[0027] For example, the materials of the source electrode or emitter electrode at the first interface, the gate electrode and / or gate pad and / or gate interconnect at the second interface, the first interlayer dielectric between the first interface and the second interface, and the gate dielectric between the gate electrode and the SiC semiconductor body can be selected so that at normal operating temperature (e.g., less than 250° C.) and at a nominal positive gate voltage (e.g., 18 V), the first interlayer dielectric electrically isolates the gate electrode from the source electrode or emitter electrode, and the gate dielectric electrically isolates the gate electrode from the SiC semiconductor body. For this case, the overall gate-to-source leakage may be small, e.g., in the μA range or below. However, at higher temperatures, e.g., in the event of a short circuit, the conduction band offset of the first interface in the configuration examples described herein allows much higher thermal leakage current to flow between i) the gate electrode (and / or gate pad and / or gate interconnect) and the source electrode or emitter electrode than between ii) the gate electrode and the SiC semiconductor body. The leakage current through the first interlayer dielectric at high temperature can be generally the sum of the electron current from the source electrode or emitter electrode into the gate electrode (and / or gate pad and / or gate interconnect) and the hole current from the gate electrode (and / or gate pad and / or gate interconnect) into the source electrode or emitter electrode. Generally, the electron or hole current is dominant, depending on the corresponding band offset.

[0028] Once a certain critical temperature is exceeded, the increased leakage current between the gate electrode (and / or gate pad and / or gate interconnect) and the source electrode or emitter electrode can lead to a reduction in the gate potential in the transistor primitive region, thereby reducing the channel overdrive (gate to source voltage VGS minus threshold voltage VTH). This results in a self-limiting mechanism for saturation current. The configuration example described herein for reducing channel overdrive is similar to the operation of a thermistor (thermistor) with a negative temperature coefficient (NTC). It can be directly incorporated in the transistor primitive region, where the source electrode or emitter electrode is placed directly on top of the first interlayer dielectric, which isolates the gate electrode in an electrically isolated manner, and / or it can be incorporated in different passive device regions, such as between a metal source or emitter and a gate track (or interconnect) or between a gate pad in a gate pad region and a source or emitter trench filling material below the gate pad. In the configuration example described herein including a first interlayer dielectric having a low conduction band offset (for the source electrode or emitter electrode) compared to the conduction band offset of the gate dielectric (for the SiC semiconductor body), the original transistor primitive area design (e.g., MOS system) that governs the channel properties does not need to be modified to achieve the desired functionality, because the material of the gate dielectric is less relevant for achieving the technical effect of reducing channel overdrive, considering the leakage current flowing through the first interlayer dielectric. Therefore, the configuration example described herein can allow for increased short-circuit withstand without affecting the area-specific on-state resistance RonxA of the vertical power semiconductor device.

[0029] For example, a portion of the source electrode or the emitter electrode at the first interface may be made of aluminum, copper, titanium, nickel, molybdenum, tungsten, or an alloy thereof.

[0030] For example, a portion of the first interlayer dielectric at the first interface may be made of a high-k material.

[0031] For example, the high-k material may be aluminum oxide, zirconium oxide, aluminum nitride, hafnium oxide, yttrium oxide, silicon nitride oxide, silicon nitride or aluminum nitride.For example, the first interlayer dielectric may also include a layer stack of the above high-k materials.

[0032] For example, the gate structure may include a gate dielectric disposed between the gate electrode and the SiC semiconductor body. A portion of the gate dielectric at the channel interface for the SiC semiconductor body may be a high-k dielectric. In some other examples, a portion of the gate dielectric at the channel interface for the SiC semiconductor body may be an oxide, such as a thermal oxide such as thermal SiO2 or a deposited and annealed oxide. The portion of the gate dielectric may also include a layer stack of dielectric materials, such as a combination of oxides and high-k materials.

[0033] For example, the conduction band offset at the first interface of the first interlayer dielectric may be smaller than the conduction band offset at the channel interface. Thus, at a positive gate voltage (on-state), the onset of thermionic electron tunneling current between the source electrode or emitter electrode and the gate electrode occurs at a (much) lower threshold temperature than the onset of thermionic tunneling current between the gate electrode and the SiC semiconductor body. Thus, the MOS interface and the gate oxide are not altered or degraded by large leakage currents flowing from the gate electrode through the gate oxide into the semiconductor body.

[0034] For example, the gate structure may be a planar or trench gate structure. At least a portion of the second interface may be arranged in the transistor cell region. The portion of the second interface may be directly opposite to the first interface, ie, facing the first interface.

[0035] For example, at least a portion of the second interface is arranged in the interconnection region. The portion of the second interface may be directly opposite to the first interface.

[0036] For example, the portion of the second interface may be arranged directly opposite a portion of a source electrode or an emitter electrode having two edges on the bottom side that turn into each other at an angle equal to or less than 90°. This may allow the electric field strength to be locally enhanced at or around the interface between the source electrode or the emitter electrode and the interlayer dielectric. As a result, the thermally assisted electron tunneling current between the source electrode or the emitter electrode and the gate electrode may be increased even further in this region.

[0037] For example, at least a portion of the second interface of the first interlayer dielectric may be arranged in the interconnect region. The portion of the second interface may be directly opposite the first interface along the first lateral direction. A portion of the first interlayer dielectric may be arranged laterally between the source or emitter line of the source electrode or emitter electrode and the gate interconnect. Once a certain critical temperature is exceeded, the increased leakage current flowing along the first lateral direction between the gate interconnect and the source or emitter electrode may therefore lead to a reduction in the gate potential in the transistor primitive region, thereby reducing the channel overdrive.

[0038] For example, the gate interconnect may include a gate resistor having a gate resistance in a range from 5Ω to 20Ω.

[0039] For example, the vertical power semiconductor device may further include: a second interlayer dielectric including a first interface for a source electrode or an emitter electrode and a second interface for at least one of a gate electrode or a gate interconnect. The conduction band offset at the first interface of the second interlayer dielectric may be greater than the conduction band offset at the first interface of the first interlayer dielectric.

[0040] For example, the second interlayer dielectric may be or may include an oxide of silicon. For example, the oxide of silicon may include deposited SiO2 and / or thermal SiO2. Additionally or alternatively, for example, the second interlayer dielectric may be or may include a silicate glass, such as tetraethyl silicate (TEOS).

[0041] For example, the conduction band offset at the first interface of the second interlayer dielectric may be 0.5 eV to 1.5 eV greater than the conduction band offset at the first interface of the first interlayer dielectric. Thus, when a certain critical temperature is exceeded, the flow of increased electron leakage current is limited through the first interlayer dielectric.

[0042] Another configuration example of a vertical power semiconductor device includes: a silicon carbide SiC semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes: a transistor cell region including a gate structure; a gate pad region; and an interconnect region, a gate electrode of the gate structure and a gate pad of the gate pad region being electrically coupled via the gate interconnect. The vertical power semiconductor device also includes a source electrode or an emitter electrode. The vertical power semiconductor device also includes: a first interlayer dielectric including a first interface for the source electrode or the emitter electrode and a second interface for at least one of the gate electrode or the gate interconnect or the gate pad. The value of the valence band offset at the second interface may be in the range of from 1.0 eV to 2.5 eV or from 1.5 eV to 2.1 eV. Once a certain critical temperature is exceeded, the increased hole leakage current between the gate electrode (and / or the gate pad and / or the gate interconnect) and the source electrode or the emitter electrode may result in a reduction in the gate potential in the transistor cell region, thereby reducing the channel overdrive.

[0043] For example, the vertical power semiconductor device may further include: a second interlayer dielectric including a first interface for a source electrode or an emitter electrode and a second interface for at least one of a gate electrode or a gate interconnect. The valence band offset at the second interface of the second interlayer dielectric may be greater than the valence band offset at the second interface of the first interlayer dielectric.

[0044] For example, the second interlayer dielectric may be or may include an oxide of silicon. For example, the oxide of silicon may include deposited SiO2 and / or thermal SiO2. Additionally or alternatively, for example, the second interlayer dielectric may be or may include a silicate glass, such as tetraethyl silicate (TEOS).

[0045] For example, the value of the valence band offset at the second interface of the second interlayer dielectric can be 0.5 eV to 3.0 eV greater than the value of the valence band offset at the second interface of the first interlayer dielectric. Thus, when a certain critical temperature is exceeded, the increased hole leakage current flow is restricted through the first interlayer dielectric.

[0046] The examples and features described above and below may be combined.

[0047] Some of the above and following examples are described in conjunction with a silicon carbide substrate. Alternatively, a wide bandgap semiconductor substrate (e.g., a wide bandgap wafer) may be processed, for example, including a wide bandgap semiconductor material other than silicon carbide. The wide bandgap semiconductor wafer may have a bandgap larger than the bandgap of silicon (1.12 eV). For example, the wide bandgap semiconductor wafer may be a silicon carbide (SiC) wafer or a gallium arsenide (GaAs) wafer or a gallium nitride (GaN) wafer.

[0048] Further details and aspects are mentioned in connection with the examples described above or below.Processing a SiC semiconductor wafer for manufacturing a vertical power semiconductor device may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0049] The description and drawings illustrate only the principles of the present disclosure. In addition, all examples described herein are primarily intended to be used for illustrative purposes only to help readers understand the principles and concepts of the present disclosure contributed by (one or more) inventors to promote the art. All statements describing the principles, aspects and examples of the present disclosure and specific examples of the present disclosure herein are intended to include their equivalents.

[0050] In the following, another example of a field effect transistor FET is explained in conjunction with the accompanying drawings. The functional and structural details described for the above examples will be equally applicable to the exemplary embodiments illustrated in the accompanying drawings and further described below. In the illustrated examples, an n-channel FET is illustrated. However, the examples described herein may also be applied to p-channel devices, such as p-channel MOSFETs or p-channel IGBTs.

[0051] Details of the structure or functionality or technical benefits of the features described above are equally applicable to the following examples, and vice versa.

[0052] Figure 1 A portion of a power semiconductor device 100 configured as a planar or trench gate SiC power MOSFET is schematically and exemplarily illustrated.

[0053] The power semiconductor device 100 includes a first interlayer dielectric 120 including a first interface 1221 for a source electrode or emitter electrode 116 and a second interface 1222 for a gate electrode 1061 or a gate pad 112 or a gate interconnect 114 (such as a gate track or gate interconnect line). The schematic energy band diagram illustrates the conduction band energy Ec versus the direction x / y. The conduction band offset Φ B,0 Exists at the first interface 1221. The conduction band offset Φ B,0It can be in the range from 1 eV to 2.5 eV.

[0054] Figure 2 A partial cross-sectional view schematically and exemplarily shows a configuration example of a power semiconductor device 100 configured as a trench gate SiC power MOSFET. The SiC power MOSFET is a vertical power semiconductor device that also includes an edge termination region (not shown in the figure) that at least partially surrounds the transistor cell region 104. Figure 2 middle).

[0055] The gate structure 106 includes a gate electrode 1061, which is electrically isolated from the SiC semiconductor body 102 by a gate dielectric 1062 of the gate structure 106. The gate dielectric 1062 is adjacent to a channel region 113. The channel region 113 is defined by a portion of the p-doped body region 134, which is adjacent to the gate dielectric 1062 at a channel interface 121 with the gate structure 106. The gate structure 106 is configured as a trench gate structure 107. For example, the conductivity of the channel region 113 can be controlled by a potential applied to the gate electrode 1061, for example, by a field effect. For example, a positive voltage applied to the gate electrode 1061 can induce an n-type inversion channel, for example, in the channel region 113 adjacent to the gate dielectric 1062. The p-doped body region 134 may be electrically connected to the source electrode or emitter electrode 116 via the first surface 1031, for example, by a contact plug and / or a recessed contact of the source electrode or emitter electrode 116 on the top surface of the body region 114, wherein the recessed contact may extend into the SiC semiconductor body 102 and / or may be electrically connected to the body region 134 via the sidewall of the recessed contact (not shown). Figure 2 For example, the channel region 113 as part of the body region 134 may include partial compensation by n-type dopants for adjusting the threshold voltage VTH. For example, partial compensation may be achieved by oblique ion implantation through the sidewalls of the trench. The gate dielectric 1062 of the gate structure 106 is also connected to the n-type dopant. + The doped source region 136 is adjacent to n + The doped source region 136 is arranged between the p-doped body region 134 and the first surface 1031 .

[0056] At the bottom side of the gate structure 106, the gate dielectric 1062 may be adjacent to the p-doped diode region 124. The p-doped diode region 124 may include one or more sub-regions overlapping each other along the vertical direction y. Along the sidewall of the trench gate structure 107 opposite to the sidewall where the channel interface 121 is located, the p-doped diode region 124 may extend upward to the first surface 1031 (not shown). Figure 2). The gate dielectric 1062 of the gate structure 106 also adjoins an n-doped current extension zone 138, which is arranged between the p-doped body region 134 and the n-doped drift region 140. The n-doped drift region 140 has a lower doping concentration than the current extension zone 138. At the second surface 1032 of the SiC semiconductor body 102, the drift region 140 is electrically connected to the drain or collector electrode 126. Between the drift region 140 and the second surface 1032, further doped semiconductor regions may be arranged, for example a highly n-doped drift contact region or an n-doped field stop region.

[0057] The first interlayer dielectric 120 is arranged on top of the gate electrode 1061 with an intermediate second interface 1222. The source electrode or emitter electrode 116 is arranged on top of the first interlayer dielectric 120 with an intermediate first interface 1221. The conduction band offset at the first interface 1221 of the first interlayer dielectric 120 is greater than the conduction band offset at the channel interface 121.

[0058] Figure 3A The schematic cross-sectional view illustrates an interconnection region 110 of a configuration example of a vertical power semiconductor device 100, and Figure 3B yes Figure 3A Top view.

[0059] Reference Figure 3A , the second interface 1222 of the first interlayer dielectric 120 is arranged in the interconnection region 110. Along the first lateral direction x1, the second interface 1222 is arranged directly opposite to the first interface 1221. The first interlayer dielectric 120 is arranged laterally between the source or emitter line 1161 of the source electrode or emitter electrode 116 and the gate interconnect 114 (e.g., gate track 1141).

[0060] Reference Figure 3B In the top view of FIG. 1 , along the second lateral direction x2, the source or emitter line 1161 and the gate track 1141 extend in parallel. For example, the second lateral direction x2 may be parallel to an edge of a die including the SiC semiconductor body 102 and / or to an edge of a transistor cell region.

[0061] Figure 4A The top view of the gate pad region 108 is shown in FIG. Figure 4B A schematic cross-sectional view is taken along Figure 4A An exemplary view obtained along line AA'.

[0062] The gate pad 112 in the gate pad region 108 includes a first gate pad material 1121 (e.g., a first gate metal material) and a second gate pad material 1122. The first interlayer dielectric 120 adjoins the bottom side of the gate pad 112, i.e., the bottom side of the first gate pad material 1121, via a second interface 1222. Opposite to the second interface 1222, the first interface 1221 of the first interlayer dielectric 120 adjoins the source or emitter trench filling material 1162 (e.g., doped polysilicon). The source or emitter trench filling material 1162 is a part of the source or emitter electrode 116 and is electrically isolated from the doped region 1021 (e.g., p-well) of the SiC semiconductor body 102 via the trench isolation dielectric 128.

[0063] The power semiconductor device 100 further includes a second interlayer dielectric 1202, which includes a first interface 1231 for the source or emitter trench filling material 1162 and a second interface for the gate pad 112. The conduction band offset at the first interface 1231 of the second interlayer dielectric 1202 is greater than the conduction band offset at the first interface 1221 of the first interlayer dielectric 120. The third interlayer dielectric 1203 on the first surface 1031 of the SiC semiconductor body 102 electrically isolates the gate pad 112 from the SiC semiconductor body, and may also be arranged in other areas, such as in Figure 3A , 3B 1 and 12. In some examples, the first gate pad material 1221 can be replaced by the second gate pad material 1222, and vice versa.

[0064] In the above examples, the increased leakage current between the gate electrode (and / or gate pad and / or gate interconnect) and the source electrode or emitter electrode has been illustrated as a conduction band shift Φ at the first interface 1221. B,0 This can result in a reduction in the gate potential in the transistor primitive region, thereby reducing the channel overdrive (gate-to-source voltage VGS minus threshold voltage VTH). Figure 5 , Figure 5 As shown in the schematic energy band diagram of valence band energy Ev versus direction x / y, hole leakage current from the second interface 1222 of the gate electrode 1061 or the gate interconnect 114 or the gate pad 112 can also lead to a reduction in the gate potential in the transistor primitive region, thereby reducing the channel overdrive (gate-to-source voltage VGS minus threshold voltage VTH). The valence band offset Φ at the second interface 1222 B,1 The value of may be in the range from 1.0 eV to 2.5 eV.

[0065] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A vertical power semiconductor device (100), comprising: A silicon carbide (SiC) semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite to the first surface (1031), the SiC semiconductor body (102) comprising: a transistor cell region (104) comprising a gate structure (106); a gate pad region (108); and an interconnect region (110) electrically coupling a gate electrode (1061) of the gate structure (106) and a gate pad (112) of the gate pad region (108) via a gate interconnect (114); a source electrode or an emitter electrode (116); and A first interlayer dielectric (120) comprising a first interface (1221) for the source electrode or the emitter electrode (116) and a second interface (1222) for at least one of the gate electrode (1061) or the gate interconnect (114) or the gate pad (112), and wherein the conduction band offset (Φ) at the first interface (1221) is B,0 ) is in the range from 1 eV to 2.5 eV.

2. A vertical power semiconductor device (100) as claimed in the preceding claim, wherein a portion of the source electrode or emitter electrode (116) at the first interface (1121) is made of aluminum, copper, titanium, nickel, molybdenum, tungsten or alloys thereof.

3. The vertical power semiconductor device (100) according to any one of the preceding claims, wherein a portion of the first interlayer dielectric (120) at the first interface (1121) is made of a high-k material.

4. The vertical power semiconductor device (100) of the preceding claim, wherein the high-k material is aluminum oxide, zirconium oxide, aluminum nitride, hafnium oxide, yttrium oxide, silicon nitride oxide, silicon nitride or aluminum nitride.

5. A vertical power semiconductor device (100) as claimed in any one of the preceding claims, wherein the gate structure (106) comprises a gate dielectric (1062) arranged between the gate electrode (1061) and the SiC semiconductor body (102), and a portion of the gate dielectric (1062) at a channel interface (121) with the SiC semiconductor body (102) is a high-k dielectric.

6. The vertical power semiconductor device (100) according to any one of the preceding claims, wherein the conduction band offset (Φ B,0 ) is smaller than the conduction band offset at the channel interface (121).

7. A vertical power semiconductor device (100) as claimed in any of the preceding claims, wherein the gate structure (106) is a planar or trench gate structure (107), and at least a portion of the second interface (1222) is arranged in the transistor cell region (104), the portion of the second interface being directly opposite to the first interface (1221).

8. The vertical power semiconductor device (100) as claimed in any one of the preceding claims, wherein at least a portion of the second interface (1222) is arranged in the interconnection region (110), the portion of the second interface directly opposing the first interface (1221).

9. A vertical power semiconductor device (100) as claimed in any one of the preceding claims, wherein: The portion of the second interface (1222) is arranged to be directly opposite to a portion of the source electrode or emitter electrode (116), and the source electrode or emitter electrode (116) has two edges on the bottom side, and the two edges turn to each other at an angle equal to or less than 90°.

10. A vertical power semiconductor device (100) as claimed in any of the preceding claims, wherein at least a portion of the second interface (1222) of the first interlayer dielectric (120) is arranged in the interconnection region (110), the portion of the second interface (1222) being directly opposite to the first interface (1221) along a first lateral direction (x1), wherein a portion of the first interlayer dielectric (120) is arranged laterally between a source line or emitter line (1161) of the source electrode or emitter electrode (116) and the gate interconnect (114).

11. The vertical power semiconductor device (100) of any one of the preceding claims, wherein the gate interconnect (114) comprises a gate resistor having a gate resistance in the range from 5Ω to 20Ω.

12. The vertical power semiconductor device (100) according to any one of the preceding claims, further comprising: a second interlayer dielectric, comprising a first interface for the source electrode or the emitter electrode (116) and a second interface for at least one of the gate electrode (1061) or the gate interconnect (114) or the gate pad (112), and wherein the conduction band offset (Φ) at the first interface of the second interlayer dielectric B,0 ) is greater than the conduction band offset (Φ) at the first interface (1221) of the first interlayer dielectric (120) B,0 ).

13. The vertical power semiconductor device (100) of the preceding claim, wherein the second interlayer dielectric is an oxide of silicon.

14. A vertical power semiconductor device (100) as claimed in any one of the two preceding claims, wherein the conduction band offset (Φ B,0 ) is greater than the conduction band offset (Φ) at the first interface (1221) of the first interlayer dielectric (120) B,0 ) is 0.5eV to 1.5eV.

15. A vertical power semiconductor device (100), comprising: A silicon carbide (SiC) semiconductor body (102) having a first surface (1031) and a second surface (1032) opposite to the first surface (1031), the SiC semiconductor body (102) comprising: a transistor cell region (104) comprising a gate structure (106); a gate pad region (108); and an interconnect region (110) electrically coupling a gate electrode (1061) of the gate structure (106) and a gate pad (112) of the gate pad region (108) via a gate interconnect (114); a source electrode or an emitter electrode (116); and A first interlayer dielectric (120) comprising a first interface (1221) for the source electrode or the emitter electrode (116) and a second interface (1222) for at least one of the gate electrode (1061) or the gate interconnect (114) or the gate pad (112), and wherein the valence band offset (Φ) at the second interface (1222) is B,1 ) is in the range from 1 eV to 2.5 eV.

16. The vertical power semiconductor device (100) according to any one of the preceding claims, further comprising: a second interlayer dielectric, comprising a first interface for the source electrode or the emitter electrode (116) and a second interface for at least one of the gate electrode (1061) or the gate interconnect (114) or the gate pad (112), and wherein a valence band offset (Φ) at the second interface of the second interlayer dielectric B,1 ) is greater than the valence band offset (Φ) at the second interface (1222) of the first interlayer dielectric (120) B,1 ).

17. The vertical power semiconductor device (100) of the preceding claim, wherein the second interlayer dielectric is an oxide of silicon.

18. A vertical power semiconductor device (100) as claimed in any one of the two preceding claims, wherein the valence band offset (Φ B,1 ) is greater than the valence band offset (Φ) at the second interface (1222) of the first interlayer dielectric (120). B,1 ) value is 0.5eV to 3.0eV.

Images