Trench gate dual-control-electrode 4H-SiC composite transistor structure and preparation method thereof

Abstract

The invention discloses a trench gate dual-control electrode 4H-SiC composite transistor structure and a preparation method thereof. The structure is composed of an active region and a trench-junction terminal extension composite terminal region, wherein the active region is formed by connecting multi-cell structures in parallel; an n + source region and a p + region are separated, and double control electrodes are introduced to respectively control on and off of a VUMOS and a BJT which are connected in parallel, so that on resistance and loss of DCT are reduced, channel density is reduced, short-circuit tolerance time is prolonged, short-circuit resistance is improved, and influence of a body diode on device characteristics is eliminated; a p floating region with an arc-shaped side surface is formed at the bottom of the active region groove, and the edge of the p floating region wraps the corner of the groove, so that the electric field intensity in the gate oxide layer is reduced, and the problem that the gate oxide layer is easy to break down is solved; a trench-junction terminal extension composite terminal is adopted, so that the size of the terminal is reduced, high voltage withstanding efficiency is obtained, the requirements of actual application on the characteristics and reliability of a power MOSFET can be met, and the cost is low.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and in particular relates to a trench gate double control electrode 4H-SiC composite transistor structure and a preparation method thereof. Background Art

[0002] At present, 4H-SiC power MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor, Metal-Oxide Semiconductor Field-EffectTransistor, abbreviated as MOS) has been used as a power switch in the fields of new energy, photovoltaic inverters, power systems, etc. In comparison, due to the simple structure and process of planar gate power MOSFET, existing power MOSFETs mostly adopt planar gate MOSFET (abbreviated as VDMOS) structure, and set a carrier expansion layer above the n-drift region to reduce its on-resistance, but its on-resistance is still higher than that of trench gate MOSFET (abbreviated as VUMOS). In addition to setting a carrier expansion layer between the n-drift region and the p-body region to reduce the on-resistance, the existing VUMOS structure usually adds a medium-doped p-region just below the trench gate to suppress the high electric field strength at the trench corner.

[0003] Although the above-mentioned technical means are used to continuously improve the device structure, since VUMOS is essentially a unipolar device, it cannot produce conductivity modulation effect during conduction, and the on-resistance is still larger than that of bipolar devices (such as bipolar junction transistors BJT). In practical applications, existing VUMOS still has many disadvantages, such as the high electric field at the corner of the trench makes the gate oxide layer easy to break down; the short circuit withstand time is short, resulting in poor short circuit resistance; the anti-parallel body diode affects the device characteristics; the chip terminal size is large, the process is complex, and the cost is high, which cannot meet the application requirements of power switches. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a trench gate dual-control electrode 4H-SiC composite transistor structure and a preparation method. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In a first aspect, an embodiment of the present invention provides a trench gate dual-control electrode 4H-SiC composite transistor structure, which is composed of an active region formed by connecting a plurality of central cellular structures in parallel and a peripheral trench-junction terminal extension composite terminal region;

[0006] The cell structure comprises: an n buffer layer, an n-drift region, an n carrier expansion layer, a p body region and an n+ source region sequentially arranged on a 4H-SiC n+ substrate; an active region trench is arranged in the center of the cell structure, penetrating downward from the n+ source region to the n-drift region; a p floating region with an arc-shaped outer side is arranged below the active region trench, and its arc edge wraps the corner of the active region trench; the side and bottom surfaces of the active region trench are covered with a gate oxide layer, and the interior is filled with heavily doped polysilicon as a trench gate G; the n+ source region and the p body region on each side form a mesa structure, and a p+ region is arranged in the top layer area close to the outer edge of the p body region under the mesa structure on each side, and has a spacing with the n+ source region on the same side; a source electrode S is arranged on the surface of the n+ source region; a base electrode B is arranged on the surface of the p+ region; the surface of the active region trench is covered with a phosphorus silicon glass layer to isolate the trench gate G from the source electrode S; the 4H-SiC A drain D is provided on the back of the n+ substrate; the trench gate G and the base B are both control electrodes; the cell structure is symmetrical with the central trench gate G as the axis, which is equivalent to the parallel connection of VUMOS and BJT;

[0007] The trench-junction terminal extension composite terminal region is connected to the corresponding layer of the outermost cellular structure of the active region, and includes an n buffer layer, an n-drift region, an n carrier expansion layer, a p body region, and a drain D on the back side of the 4H-SiC n+ substrate, which are sequentially arranged on a 4H-SiC n+ substrate; its p body region, n carrier expansion layer and a part of the n-drift region form a mesa structure with the remaining part of the n-drift region as a terminal region trench, and a p-junction terminal extension region is arranged in a local area in the n-drift region at a corner below the terminal region trench, and the p-junction terminal extension region is arc-shaped near the side of the terminal region trench and wraps the corner of the terminal region trench.

[0008] In one embodiment of the present invention, for the trench-junction terminal extension composite terminal region and the outermost cell structure of the connected active region, a naturally formed longitudinal resistance region is present in the p-body region, n-carrier expansion layer and n-drift region of the trench sidewall of the terminal region.

[0009] In one embodiment of the present invention, in the trench gate dual-control electrode 4H-SiC composite transistor structure, the n-drift region of VUMOS is equivalent to the n-collector region of BJT, the p-body region of VUMOS is equivalent to the p-base region of BJT, the n+ source region of VUMOS is equivalent to the n+ emitter region of BJT, and the 4H-SiC n+ substrate of VUMOS is equivalent to the collector ohmic contact region of BJT; the source S of VUMOS is also the emitter E of BJT, and the drain D of VUMOS is also the collector C of BJT; the gate G and the base B respectively control the opening and closing of VUMOS and BJT.

[0010] In one embodiment of the present invention, when the trench gate dual control electrode 4H-SiC composite transistor is turned on, a gate voltage is applied to the trench gate G as a control electrode, and a base current is applied to the base B as another control electrode, thereby triggering VUMOS and BJT to turn on at the same time, so that the n-drift region produces a conductivity modulation effect, and the entire device operates in a bipolar mode.

[0011] In one embodiment of the present invention, in the cellular structure,

[0012] The width W of the active area trench TG The active area trench depth D TG 1.4~2μm;

[0013] The concentration N of the p floating region p 5×10 17 cm -3 ~6×10 17 cm -3 , the junction depth D of the p floating region p 0.6~0.7μm;

[0014] The width W of the n+ source region n+ is 5 to 7 μm; the thickness D of the n+ source region n+ is 0.3-0.5 μm; the distance S between the n+ source region and the p+ region B 3~5μm.

[0015] In one embodiment of the present invention, in the trench-junction termination extension composite termination region,

[0016] The depth of the terminal region trench is 1.7 to 2.5 μm; the concentration N of the p-junction terminal extension region is JTE 3.2×10 17 ~3.6×10 17 cm -3 ; The junction depth D of the p-junction terminal extension region JTE is 0.4 to 0.6 μm; the width W of the p-junction terminal extension region JTE 20~35μm.

[0017] In a second aspect, an embodiment of the present invention provides a method for preparing a trench gate dual-control electrode 4H-SiC composite transistor structure, the method comprising:

[0018] On a 4H-SiC n+ substrate, an n-buffer layer, an n-drift region, an n-carrier extension layer, a p-body region and an n+ source region are grown in sequence using an epitaxial process;

[0019] Etching both sides of the n+ source region by dry etching process to form a mesa structure of the n+ source region and the p-body region;

[0020] Using a dry etching process, the n+ source region is etched downward to the n-drift region to form an active region trench, and the edge p-body region is etched downward to the n-drift region to form a terminal region trench;

[0021] Performing multiple aluminum ion cover implantations on the active area trench to form a p-type floating area at the bottom of the active area trench, and making the outer side of the p-type floating area wrap around the corner of the active area trench in an arc shape;

[0022] Performing multiple aluminum ion covering implantations on the bottom of the termination region trench to form a p-junction termination extension region at the bottom of the termination region trench, and making the outer side of the p-junction termination extension region wrap around the corner of the termination region trench in an arc shape;

[0023] Aluminum ions are implanted into the outer surface edge region of the p-body region which is spaced apart from the n+ source region to form a p+ region, and high temperature annealing is performed;

[0024] Using thermal oxidation to prepare a gate oxide layer on the side and bottom of the active area trench, and then depositing polysilicon and heavily doping it to fill the active area trench to form a trench gate G;

[0025] An oxide film and a borophosphosilicate glass layer are deposited on the surface of the active area groove, and source and base metal contact holes are formed by photolithography; metal nickel is then deposited, and after high-temperature annealing, an ohmic contact of the source S is formed on the surface of the n+ source area, and an ohmic contact of the base B is formed on the surface of the p+ area; then the metal nickel layer on the surface of the borophosphosilicate glass is removed by a stripping process; and a gate welding hole is etched, and metal titanium, titanium nitride and aluminum-copper films are deposited in sequence, and then reverse etching is performed to form source, base and gate metal electrodes, and rapid annealing is performed to complete the preparation of surface metal electrodes;

[0026] Deposit silicon nitride film and perform photolithography to passivate the terminal area on the chip surface; then apply polyimide film, perform photolithography to form the surface source, gate and base area bonding area patterns, and perform imidization treatment to form the front terminal passivation and protection layer to complete the device surface passivation treatment;

[0027] The lower surface of the 4H-SiC n+ substrate is thinned, and metal titanium, nickel and silver are sputtered in sequence to prepare a drain electrode D, and then laser annealing is performed to reduce the ohmic contact resistance to complete the preparation of the back metal electrode.

[0028] In one embodiment of the present invention, multiple aluminum ion implantations are performed on the active area trench to form a p floating area at the bottom of the active area trench, and the outer side of the p floating area is formed in an arc shape to wrap around the corner of the active area trench, including:

[0029] On the upper surface of the current crystal, a 30-50 nm silicon dioxide covering film is deposited, a photoresist is applied as a masking film, and aluminum ion covering implantation is performed multiple times at room temperature on the bottom of the active area trench. By adjusting the implantation dose and energy, a p floating area is formed at the bottom of the active area trench, and the outer side of the p floating area is made to wrap the corner of the active area trench in an arc shape; wherein the concentration N of the p floating area p 5×10 17 cm -3 ~6×10 17 cm -3 , the junction depth D of the p floating region p It is 0.6~0.7μm.

[0030] In one embodiment of the present invention, multiple aluminum ion implantations are performed on the bottom of the termination region trench to form a p-junction termination extension region at the bottom of the termination region trench, and the outer side of the p-junction termination extension region is formed in an arc shape to wrap around the corner of the termination region trench, including:

[0031] The silicon dioxide covering film on the current crystal upper surface is removed, and a 30-50 nm silicon dioxide covering film is re-deposited, and a photoresist is applied as a masking film. The bottom of the terminal area trench is implanted with aluminum ions multiple times at room temperature, and the implantation dose and energy are adjusted at the same time to form a p-junction terminal extension area at the bottom of the terminal area trench, and the outer side of the p-junction terminal extension area is formed in an arc shape to wrap the corner of the terminal area trench; wherein the concentration N of the p-junction terminal extension area JTE 3.2×10 17 ~3.6×10 17 cm -3 ; The junction depth D of the p-junction terminal extension region JTE is 0.4 to 0.6 μm; the width W of the p-junction terminal extension region JTE 20~35μm.

[0032] In one embodiment of the present invention, aluminum ions are implanted into the outer surface edge region of the p-body region having a distance from the n+ source region to form the p+ region, including:

[0033] Remove the silicon dioxide covering film on the current crystal surface, re-deposit the silicon dioxide covering film and polysilicon masking film, etch the polysilicon in the outer surface edge area of ​​the p-body region with a spacing from the n+ source region to form a p+ region injection window, and then perform aluminum ion implantation at 500°C to form a p+ region;

[0034] The doping concentration of the p+ region after annealing is 3×10 19 ~5×10 19 cm -3 .

[0035] Beneficial effects of the present invention:

[0036] Compared with the existing trench gate 4H-SiC MOSFET (VUMOS) cell structure, the present invention proposes a trench gate dual control electrode 4H-SiC composite transistor structure, firstly, the n+ source region and the p+ ohmic contact region are separated, and a BJT connected in parallel with the VUMOS is introduced to form a dual control electrode, which controls the opening and closing of the VUMOS and the BJT respectively, so as to reduce the on-resistance and loss of the DCT, and at the same time reduce the channel density, so as to increase the short-circuit withstand time, improve the short-circuit resistance, and eliminate the influence of the body diode on the device characteristics; secondly, a p floating region with a side arc shape is formed at the bottom of the active area trench, so that the arc edge wraps the corner of the active area trench, so as to reduce the electric field strength in the gate oxide layer at the corner of the active area trench, thereby solving the problem that the gate oxide layer is easy to break down; in addition, a trench-junction terminal extension composite terminal (T-JTE) is adopted to reduce the terminal size and obtain a higher terminal breakdown voltage, so as to meet the requirements of practical applications for power MOSFET characteristics and reliability.

[0037] Furthermore, the manufacturing process of the trench gate dual-control electrode 4H-SiC composite transistor structure of the embodiment of the present invention is compatible with the existing VUMOS process. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of the existing 4H-SiC VUMOS cell structure;

[0039] Figure 2 It is the equivalent circuit diagram of the existing 4H-SiC VUMOS cell;

[0040] Figure 3 Schematic diagram of a trench gate dual control electrode 4H-SiC composite transistor (T-DCT) structure provided by an embodiment of the present invention;

[0041] Figure 4 is an equivalent circuit diagram of a 4H-SiC T-DCT cell according to an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the carrier transport trajectory in the initial stage of the opening of the existing 4H-SiC VUMOS cell;

[0043] Figure 6 is the control timing of the control signal applied to the two control electrodes of the 4H-SiC T-DCT according to the embodiment of the present invention;

[0044] Figure 7 Schematic diagram of carrier transport trajectory in the initial stage of opening of a 4H-SiC T-DCT cell according to an embodiment of the present invention;

[0045] Figure 8 is a comparison curve of breakdown characteristics between the 4H-SiC T-DCT cell of the embodiment of the present invention and the existing 4H-SiC VUMOS cell;

[0046] Fig. 9 is a comparison curve of the longitudinal electric field intensity distribution when the 4H-SiC T-DCT cell of the embodiment of the present invention and the existing 4H-SiC VUMOS cell are broken down;

[0047] Fig.10 4H-SiC T-DCT cell of the embodiment of the present invention and the conventional 4H-SiC VUMOS cell are compared in terms of on-state characteristics;

[0048] Fig.11 4H-SiC T-DCT cell of the present invention and the conventional 4H-SiC VUMOS cell are compared in terms of transfer characteristics;

[0049] Fig.12 is a graph showing the conduction characteristics of a 4H-SiC T-DCT according to an embodiment of the present invention at different base currents;

[0050] Fig.13 is a comparison curve of turn-on characteristics of the 4H-SiC T-DCT cell of the embodiment of the present invention and the existing 4H-SiC VUMOS cell under resistive load;

[0051] Fig.14 4H-SiC T-DCT cell according to the embodiment of the present invention and the conventional 4H-SiC VUMOS cell are compared in terms of turn-off characteristics under resistive load;

[0052] Fig.15 4 is a short-circuit characteristic comparison curve between the 4H-SiC T-DCT cell according to the embodiment of the present invention and the existing 4H-SiC VUMOS.

[0053] Fig.16 The 4H-SiC T-DCT cells of the embodiment of the present invention have different gate trench depths D TG The lower conduction characteristic comparison curve;

[0054] Fig.17a The 4H-SiC T-DCT cell of the embodiment of the present invention is subjected to different p-floating region concentrations N p The lower breakdown characteristic comparison curve;

[0055] Fig.17b The 4H-SiC T-DCT cell of the embodiment of the present invention is subjected to different p-floating region concentrations N p Comparison curve of longitudinal electric field intensity distribution during breakdown;

[0056] Fig.18a The 4H-SiC T-DCT cell of the embodiment of the present invention has different p-floating region junction depths D p The lower breakdown characteristic comparison curve;

[0057] Fig.18b The 4H-SiC T-DCT cell of the embodiment of the present invention has different p-floating region junction depths D p Comparison curve of electric field intensity distribution during breakdown;

[0058] Fig.19 The 4H-SiC T-DCT cell of the embodiment of the present invention has different n+ source region widths W. n+ The conduction characteristics comparison curve below;

[0059] Fig. 20 The 4H-SiC T-DCT cell of the embodiment of the present invention has different spacings S between the n+ source region and the p+ region. B The conduction characteristics comparison curve below;

[0060] Fig.21a is a comparison curve of the terminal breakdown characteristics and the active region breakdown characteristics of the 4H-SiC T-DCT according to the embodiment of the present invention;

[0061] Figure 21b is a lateral electric field intensity distribution curve of the terminal breakdown characteristic of the 4H-SiC T-DCT of the embodiment of the present invention;

[0062] Fig.22a is the concentration N of 4H-SiC T-DCT in different p-JTE regions in the embodiment of the present invention JTE The breakdown characteristic curve below;

[0063] Figure 22b is the concentration N of 4H-SiC T-DCT in different p-JTE regions in the embodiment of the present invention JTE Transverse electric field intensity distribution curve during down breakdown;

[0064] Fig.23a The 4H-SiC T-DCT of the embodiment of the present invention has different junction depths D in the p-JTE region. JTE The breakdown characteristic curve below.

[0065] Figure 23b The 4H-SiC T-DCT of the embodiment of the present invention has different junction depths D in the p-JTE region. JTE Electric field intensity distribution curve at breakdown;

[0066] Fig.24a The 4H-SiC T-DCT of the embodiment of the present invention has different p-JTE region widths W. JTE The breakdown characteristic curve below;

[0067] Figure 24b The 4H-SiC T-DCT of the embodiment of the present invention has different p-JTE region widths W. JTE Electric field intensity distribution curve at breakdown;

[0068] Fig.25 It is a schematic flow chart of a method for preparing a trench gate dual-control electrode 4H-SiC composite transistor structure provided by an embodiment of the present invention;

[0069] Figure 26a to Figure 26h It is a cross-sectional view of the key area of ​​the 4H-SiC T-DCT with T-JTE composite terminal of the present invention. DETAILED DESCRIPTION

[0070] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0071] Reference Figure 1 The existing 4H-SiC trench gate power MOSFET (hereinafter referred to as VUMOS) is a multi-cell parallel structure, and its cell structure is that on the 4H-SiC n+ substrate (see Figure 1 4H-SiC n+sub), and n buffer layers are arranged upward in sequence (see Figure 1 n buffer), n-drift region (see Figure 1 n-drift in), n-carrier extension layer (see Figure 1 nCSL in the p-body region (see Figure 1 p-body) and n+ source region (see Figure 1 A trench is provided in the center of the cell, and a p floating region is provided below the trench (see Figure 1 The side and bottom of the trench are filled with gate oxide layer, and the inside is filled with heavily doped polysilicon. A trench gate G is arranged on the polysilicon. An n+ source region is arranged in the p-body region on both sides near the trench side, and a p+ ohmic contact region in contact with the n+ source region is arranged outside the n+ source region (see Figure 1 The p+ on both sides of the upper middle part, the source S is set on the upper surface of the part of the n+ source region and the p+ ohmic contact region, and the drain D is set on the back of the n+ substrate. Each cell is symmetrical with the central trench gate as the axis.

[0072] Reference Figure 2, which is the equivalent circuit of the existing 4H-SiC VUMOS. It can be seen that in the existing VUMOS structure, the p+ ohmic contact region, the p-body region, the n-carrier expansion layer (CSL), the n-drift region, the n-buffer layer and the n+ substrate constitute a PIN body diode (parasitic diode), which is equivalent to the VUMOS and the PIN diode being anti-parallel, the drain D and the cathode K are shared, and the source S and the anode A are shared.

[0073] In practical applications, existing VUMOS still has many shortcomings. For example, the high electric field at the corner of the trench causes the gate oxide layer to easily break down; the short-circuit withstand time is short, resulting in poor short-circuit resistance; the anti-parallel body diode affects the device characteristics; the chip terminal is large in size, the process is complex, and the cost is high, which cannot meet the application requirements of power switches.

[0074] In order to solve the above problems, an embodiment of the present invention proposes a trench gate dual-control electrode 4H-SiC composite transistor structure and a preparation method.

[0075] In a first aspect, an embodiment of the present invention provides a trench gate dual control electrode 4H-SiC composite transistor (T-DCT for short), such as Figure 3 As shown, specifically including:

[0076] It is composed of an active region formed by connecting multiple cellular structures in parallel in the center and a composite terminal region of trench-junction terminal extensions in the periphery;

[0077] The cell structure comprises: an n buffer layer, an n-drift region, an n carrier expansion layer, a p body region and an n+ source region sequentially arranged on a 4H-SiC n+ substrate; an active region trench is arranged in the center of the cell structure, penetrating downward from the n+ source region to the n-drift region; a p floating region with an arc-shaped outer side is arranged below the active region trench, and its arc edge wraps the corner of the active region trench; the side and bottom surfaces of the active region trench are covered with a gate oxide layer, and the interior is filled with heavily doped polysilicon as a trench gate G; the n+ source region and the p body region on each side form a mesa structure, and a p+ region is arranged in the top layer area close to the outer edge of the p body region under the mesa structure on each side, and has a spacing with the n+ source region on the same side; a source electrode S is arranged on the surface of the n+ source region; a base electrode B is arranged on the surface of the p+ region; the surface of the active region trench is covered with a phosphorus silicon glass layer to isolate the trench gate G from the source electrode S; the 4H-SiC A drain D is provided on the back of the n+ substrate; the trench gate G and the base B are both control electrodes; the cell structure is symmetrical with the central trench gate G as the axis, which is equivalent to the parallel connection of VUMOS and BJT;

[0078] The trench-junction terminal extension composite terminal region is connected to the corresponding layer of the outermost cellular structure of the active region, and includes an n buffer layer, an n-drift region, an n carrier expansion layer, a p body region, and a drain D on the back side of the 4H-SiC n+ substrate, which are sequentially arranged on a 4H-SiC n+ substrate; its p body region, n carrier expansion layer and a part of the n-drift region form a mesa structure with the remaining part of the n-drift region as a terminal region trench, and a p-junction terminal extension region is arranged in a local area in the n-drift region at a corner below the terminal region trench, and the p-junction terminal extension region is arc-shaped near the side of the terminal region trench and wraps the corner of the terminal region trench.

[0079] The T-DCT provided in the embodiment of the present invention includes an active region and a trench-junction terminal extension composite terminal region. The active region is located in the center and includes a plurality of parallel cellular structures; the trench-junction terminal extension composite terminal region is located at the periphery, referred to as T-JTE, which is connected to the outermost cellular structure of the active region. For simplicity, Figure 3 Only the T-JTE and its connected outermost cellular structures are shown.

[0080] Figure 3 In the figure, the left side of the dotted line is the active area, taking only one cell structure as an example, and the right side of the dotted line is the terminal area, namely T-JTE. Among them, 4H-SiC n+sub represents 4H-SiC n+substrate; n buffer represents n buffer layer; n-drift represents n-drift region; CSL represents n carrier extension layer; p-body represents p body region; n+ represents n+ source region; p+ represents p+ region, namely p+ ohmic contact region; p below G represents p floating region; the p junction terminal extension region in T-JTE is referred to as p-JTE region. It can be seen that T-JTE and the connected cell structure are connected correspondingly to 4H-SiC n+substrate, n buffer layer, part of n-drift region, and drain D.

[0081] In the embodiment of the present invention, for the trench-junction terminal extension composite terminal region and the outermost cell structure of the connected active region, a naturally formed longitudinal resistance region is formed in the p-body region, n-carrier expansion layer and n-drift region of the trench sidewall of the terminal region. Figure 3 The three parts of the area above the right side of the middle dotted line are shown. This longitudinal resistance area can effectively prevent the side wall of the trench from failing due to current concentration after avalanche breakdown occurs.

[0082] Reference Figure 4, is the equivalent circuit of the T-DCT of the present invention. It can be seen that the T-DCT is equivalent to a VUMOS and a BJT connected in parallel. Among them, the n-drift region of the VUMOS is equivalent to the n-collector region of the BJT, the p-body region of the VUMOS is equivalent to the p-base region of the BJT, the n+source region of the VUMOS is equivalent to the n+emitter region of the BJT, and the 4H-SiC n+substrate of the VUMOS is equivalent to the collector ohmic contact region of the BJT; the source S of the VUMOS is also the emitter E of the BJT, and the drain D of the VUMOS is also the collector C of the BJT; the gate G and the base B respectively control the opening and closing of the VUMOS and the BJT.

[0083] As a preferred embodiment, in the cellular structure,

[0084] The width W of the active area trench TG The active area trench depth D TG 1.4~2μm;

[0085] The concentration N of the p floating region p 5×10 17 cm -3 ~6×10 17 cm -3 , the junction depth W of the p floating region p 0.5~0.7μm;

[0086] The width W of the n+ source region n+ is 5 to 7 μm; the thickness D of the n+ source region n+ is 0.3-0.5 μm; the distance S between the n+ source region and the p+ region B 3~5μm.

[0087] As a preferred embodiment, the trench-junction termination extends into the composite termination region,

[0088] The depth of the terminal region trench is 1.7 to 2.5 μm; the concentration N of the p-junction terminal extension region is JTE 3.2×10 17 ~3.6×10 17 cm -3 ; The junction depth D of the p-junction terminal extension region JTE is 0.4 to 0.6 μm; the width W of the p-junction terminal extension region JTE 20~35μm.

[0089] contrast Figure 1 and Figure 3Compared with the existing 4H-SiC VUMOS, the trench gate dual control electrode 4H-SiC composite transistor structure provided by the embodiment of the present invention is different in that a table structure is set on the surface of the p-body region and the n+ source region, the n+ source region is located in the upper part of the table structure, and the p+ ohmic contact region is set in the surface of the lower part of the table structure, so that the n+ source region is separated from the p+ ohmic contact region, and is respectively set as the source S and the base B. Therefore, the entire T-DCT is equivalent to the parallel connection of VUMOS and BJT. When the trench gate dual control electrode 4H-SiC composite transistor is turned on, a gate voltage is applied to the trench gate G as a control electrode, and a base current is applied to the base B as another control electrode, thereby triggering VUMOS and BJT to turn on at the same time, so that the n-drift region produces a conductivity modulation effect, and the entire device works in a bipolar mode. This not only improves the on-resistance of the device, but also reduces the channel density of the same chip area due to the increase in the width of the n+ source region and the distance between it and the p+ ohmic contact region, which can increase the short-circuit withstand time and improve the short-circuit resistance of the device. In addition, the separation of the p+ ohmic contact region and the n+ source region eliminates the PIN body diode existing in the existing 4H-SiC VUMOS, thereby avoiding the influence of the body diode on the device characteristics.

[0090] In summary, compared with the existing trench gate 4H-SiC MOSFET (VUMOS) cell structure, the present invention first separates the n+ source region and the p+ ohmic contact region, introduces a BJT in parallel with the VUMOS, forms a dual control electrode, and controls the opening and closing of the VUMOS and the BJT respectively, so as to reduce the on-resistance and loss of the DCT, and at the same time reduce the channel density to increase the short-circuit withstand time, improve the short-circuit resistance, and eliminate the influence of the body diode on the device characteristics; secondly, a p floating region with a side arc shape is formed at the bottom of the active area trench, so that the arc edge wraps the corner of the active area trench to reduce the electric field strength in the gate oxide layer at the corner of the active area trench, thereby solving the problem of easy breakdown of the gate oxide layer; in addition, a trench-junction terminal extension composite terminal (T-JTE) is adopted to reduce the terminal size and obtain high withstand voltage efficiency, so as to meet the requirements of practical applications for power MOSFET characteristics and reliability.

[0091] In order to facilitate understanding of the effect of the trench gate dual-control electrode 4H-SiC composite transistor structure proposed in the present invention, a comparative analysis is performed between the present invention and the existing 4H-SiC VUMOS, as follows:

[0092] 1) The working principle of the trench gate dual-control electrode 4H-SiC T-DCT of the present invention is significantly different from that of the existing VUMOS;

[0093] Reference Figure 5, is a schematic diagram of the carrier transport trajectory of the existing VUMOS at the initial stage of opening. It can be seen that when the gate-source voltage is greater than the threshold voltage (V G >V TH ), the drain-source voltage is greater than zero (V DS >0), at the beginning of VUMOS opening, an N channel will be formed on the surface of the p-body region along the side wall of the trench gate G, and the electrons in the n+ source region will vertically enter the n-carrier extension layer (n CSL) through the N channel and reach the n-drift region, and finally flow out from the drain to form a drain current. It can be seen that the drain current is only the electron current passing through the channel, and its working mode is also a unipolar working mode. During the conduction period, the n-drift region will not have a conductivity modulation effect, so it has a higher on-resistance.

[0094] Reference Figure 6 , is the control signal applied to the two control electrodes of the 4H-SiC T-DCT of the present invention. It can be seen that when the device is turned on, the gate G applies a positive voltage signal, and the base B applies a positive current peak signal; after turning on, the gate voltage remains unchanged, and the base current drops to the steady-state base current; when the device is turned off, the gate G applies a negative voltage signal, and the base B applies a negative current signal.

[0095] Reference Figure 7 , is a schematic diagram of the carrier transport trajectory of the T-DCT of the present invention at the initial stage of opening. It can be seen that the current distribution of the T-DCT of the present invention is significantly different from that of the existing VUMOS at the initial stage of opening. When the gate-source voltage is greater than the threshold voltage (V GS >V TH ), the base-emitter voltage is greater than the J2 junction (i.e., emitter junction) turn-on voltage (V BE >V TO )(The corresponding base current I B >0), drain-source voltage is greater than zero (V DS >0), two vertical N channels similar to VUMOS are formed along the surface of the p-body region on the side wall of the trench gate G. In addition to the fact that the N channel can conduct electron current, due to the positive bias voltage V applied by the base B BE Make the J2 junction (i.e., the emitter junction) forward biased, so the n+ source region (emitter region) will inject electrons into the p-body region (p-base region), and some of the electrons will recombine with some of the holes in the p-body region to form a hole current; the holes that have not recombinated will enter the n+ source region (emitter region) and flow out from the source (emitter); the electrons that have not recombinated will be swept into the n-drift region by the electric field of the reverse-biased J1 junction (i.e., the collector junction), drift, and then flow out from the collector to form a drain (collector) current. It can be seen that the current in the T-DCT has two parts, one is the electron current in the communication channel, and the other is the current through the BJT, including the electron current and the hole current; therefore, the T-DCT works in bipolar mode, and a conductivity modulation effect will occur during the conduction period, so the on-resistance is reduced.

[0096] 2) Taking the 2kV withstand voltage level as an example, compare and explain the relevant characteristics;

[0097] Reference Figure 8 , which is a comparison curve of the breakdown characteristics of the T-DCT of the present invention and the existing VUMOS. Since the breakdown mechanism of the two is the same, the external voltage is borne by the J1 junction formed by the p-body region and the n-drift region. Under the same longitudinal structural parameters and 10nA leakage current, the breakdown voltage of VUMOS is 2181V, and the breakdown voltage of DCT is 2228V. It can be seen that the breakdown voltage of the T-DCT of the present invention is slightly higher than that of VDMOS, and the breakdown voltages of both meet the 2kV withstand voltage level requirement.

[0098] Reference Fig. 9 , is a comparison curve of the electric field intensity distribution when the T-DCT cell of the present invention and the existing VUMOS cell are broken down. It can be seen that when the existing VUMOS cell is broken down, the electric field in the gate oxide layer is 6.39×10 6 V / cm, and when the T-DCT cell of the present invention breaks down, the electric field in the gate oxide layer is 2.68×10 6 V / cm, which is 58% lower than the electric field at the gate oxide layer of VDMOS, indicating that the T-DCT of the present invention can effectively reduce the electric field strength in the gate oxide layer at the bottom of the trench and prevent the gate oxide layer from breaking down.

[0099] Reference Fig.10 , which is a comparison curve of the on-state characteristics of the T-DCT cell of the present invention and the existing VUMOS cell. It can be seen that at the rated current of 60A, the on-resistances of the T-DCT of the present invention and the VUMOS are 7.1mΩ and 14.3mΩ respectively. The on-resistance of the T-DCT of the present invention is 50% lower than that of the VUMOS, and the saturation current is lower than that of the VUMOS, which is beneficial to improve the short-circuit tolerance capability.

[0100] Reference Fig.11 , is a transfer characteristic comparison curve between the T-DCT of the present invention and the existing VUMOS. It can be seen that VUMOS has a DS =20V, I D =50mA, the threshold voltage is 6.17V; while in the T-DCT of the present invention, when voltage is applied to both the G and B poles at the same time, the threshold voltage is 2.27V. This shows that adding the base electrode is beneficial to reducing the threshold voltage of the device.

[0101] Reference Fig.12 , is the T-DCT of the present invention at different base steady-state currents I B The conduction characteristic curve below. It can be seen that as I B Increase, the on-resistance R on The saturation current decreases slightly, but at the same time increases significantly. B When 3A is used, a lower Ron and saturation current I Dsat .

[0102] Reference Fig.13 , is the turn-on characteristic comparison curve of the T-DCT of the present invention and the existing VUMOS under resistive load. It can be seen that when the bus voltage V DD =1000V, gate resistance R G =2Ω, load resistance R L =16.6Ω, gate-source voltage V GS = When turned on under the condition of +18V, when the existing VUMOS is turned on, the rise time t r (i.e., voltage drop time) is 39.7ns; the T-DCT of the present invention has a voltage drop time of 39.7ns. DD =1000V, R G =2Ω、R L =16.6Ω,V GS = +18V, base trigger peak current I BP =7A and base steady-state current I B =When turned on under 2A condition, the rise time t r The t r It is reduced by 27.5%, which shows that the turn-on characteristic of T-DCT is better than that of VUMOS.

[0103] Reference Fig.14 , is the turn-off characteristic comparison curve of the T-DCT of the present invention and the existing VUMOS under resistive load. It can be seen that at V DD =1000V, I DS =60A, R G =2Ω、R L =16.6Ω、V GS = When the 60A current is turned off under the condition of -2V, the fall time t of the existing VUMOS f (i.e., voltage rise time) is 23.5ns; the T-DCT of the present invention has a voltage rise time of 23.5ns. DD =1000V, R G =2Ω、R L =16.6Ω,V GS =-2V, I BO = Turn off I under -5A condition DS =60A current, fall time t f The t f It is reduced by 21.3%, which shows that the turn-off characteristic of the T-DCT of the present invention is better than that of VUMOS.

[0104] Reference Fig.15, is a short-circuit characteristic comparison curve of the T-DCT of the present invention and the existing VUMOS when the bus voltage is 1000V. It can be seen that the short-circuit withstand time of the VUMOS is 3.6μs, while the short-circuit withstand time of the T-DCT of the present invention is 4.3μs, which is improved by 19.4%. This is because the T-DCT of the present invention has a lower saturation current and has the extraction of base negative current.

[0105] 4) Explanation of the influence trend of the key structural parameters of the DCT of the present invention on the characteristics;

[0106] Reference Fig.16 , is the T-DCT cell of the present invention at different gate trench depths (i.e., active area trench depths) D TG The conduction characteristic comparison curve below shows that as the gate trench depth D TG increases, the breakdown voltage decreases. TG When the thickness is 1.4 μm, the breakdown voltage is the highest.

[0107] Reference Fig.17a , is the T-DCT cell of the present invention at different p floating region concentrations N p Comparison curve of breakdown characteristics, see Fig.17b , is the T-DCT cell of the present invention at different p floating region concentrations N p The electric field strength comparison curve at the time of breakdown is shown in Figure 2. p As N increases, the breakdown voltage and the electric field strength in the gate oxide layer will decrease. p Take 6×10 17 cm -3 When , a higher breakdown voltage can be obtained, and the electric field strength in the gate oxide layer is close to the electric field strength in the depletion layer of the p floating region at the bottom of the trench, indicating that the p floating region at the bottom of the trench can effectively shield the high electric field in the gate oxide layer.

[0108] Reference Fig.18a , is the T-DCT cell of the present invention at different p floating region junction depths D p The breakdown characteristics comparison curve is shown below. Fig.18b , is the T-DCT cell of the present invention at different p floating region junction depths D p The electric field strength comparison curve at the breakdown is shown in Figure 2. p When D p When the thickness is 0.6 to 0.7 μm, a higher breakdown voltage can be obtained, and at the same time, the depletion layer of the p floating region will shield the high electric field in the gate oxide layer.

[0109] Reference Fig.19 , is the T-DCT of the present invention at different n+ source region widths W n+The conduction characteristic curve below. It can be seen that with the width W of the n+ source region n+ Increase, the on-resistance R on Slightly increased, while the saturation current I Dsat will be significantly reduced. n+ When 6μm is used, a lower R on and saturation current I Dsat .

[0110] Reference Fig. 20 , is the spacing S between the T-DCT cells of the present invention at different n+ source regions and p+ regions B The conduction characteristics comparison curve under the condition of B As S increases, the on-resistance increases slightly, while the saturation current decreases significantly. B When the value is 5μm or more, the saturation current I Dsat The decline has decreased.

[0111] Reference Fig.21a , is a comparison curve of the terminal breakdown characteristics of the T-DCT of the present invention and its active area breakdown characteristics. It can be seen that the T-DCT active area breakdown voltage is 2228V, the terminal breakdown voltage is 2148V, which meets the 2kV withstand voltage grade requirement, the withstand voltage efficiency reaches 96.4%, and the terminal size is very small.

[0112] Reference Figure 21b , is the lateral electric field intensity distribution curve of the terminal breakdown characteristic of the T-DCT of the present invention. It can be seen that the electric field intensity at the bottom of the active area trench is 2.8×10 6 V / cm, and the electric field strength at the bottom of the terminal trench is 2.1×10 6 V / cm, and the electric field strength at the end of the JTE region is 2.4×10 6 V / cm, indicating that the use of T-JTE terminals can effectively reduce the electric field strength of the terminals.

[0113] Reference Fig.22a , is the concentration N of T-DCT in different p-JTE regions of the present invention JTE The breakdown characteristic curve under Figure 22b , is the concentration N of T-DCT in different p-JTE regions of the present invention JTE The lateral electric field intensity distribution curve at breakdown. It can be seen that with the concentration N JTE As N increases, the breakdown voltage increases, the electric field at the bottom of the trench decreases, and the electric field at the end of the p-JTE region increases. JTE Take 3.2×10 17 cm -3 , the breakdown voltage is 2019V, which meets the 2kV withstand voltage requirement. JTEMore than 3.5×10 17 cm -3 , the electric field at the end of JTE increases and exceeds the electric field in the active area, causing it to break down first.

[0114] Reference Fig.23a , is the junction depth D of the T-DCT in different p-JTE regions of the present invention JTE The breakdown characteristic curve under Figure 23b , is the junction depth D of the T-DCT in different p-JTE regions of the present invention JTE The lateral electric field intensity distribution curve at the time of breakdown. It can be seen that with the junction depth D JTE When the junction depth of the p-JTE region is 0.4-0.6μm, the breakdown voltage meets the 2kV withstand voltage requirement.

[0115] Reference Fig.24a , is the width W of the T-DCT in different p-JTE regions of the present invention JTE The breakdown characteristic curve under Figure 24b , is the width W of the T-DCT in different p-JTE regions of the present invention JTE The electric field intensity distribution curve at the time of breakdown. It can be seen that with the width W of the p-JTE region JTE As the length of the JTE region is 15 to 30 μm, the 2 kV withstand voltage requirement is met.

[0116] In a second aspect, an embodiment of the present invention provides a method for preparing a trench gate dual-control electrode 4H-SiC composite transistor structure, such as Fig.25 As shown, the following steps may be included:

[0117] S1, on a 4H-SiC n+ substrate, using an epitaxial process, an n buffer layer, an n-drift region, an n carrier expansion layer, a p body region, and an n+ source region are grown in sequence;

[0118] Among them, the first choice is the crystal direction <0001> An n+ type 4H-SiC substrate is prepared, and the surface is corroded and cleaned in situ to obtain the desired 4H-SiC n+ substrate.

[0119] Then, an n buffer layer, an n-drift region, an n carrier expansion layer, a p body region and an n+ source region are sequentially grown on the 4H-SiC n+ substrate by using an epitaxial process. The thickness of each layer can be set as required.

[0120] Among them, the P body region and the n+ source region are both formed by an epitaxial process and are uniformly doped. By controlling the thickness and concentration of the epitaxial layer in the p body region, the channel length and threshold voltage can be precisely controlled.

[0121] In a preferred embodiment, the width W of the n+ source region is n+ is 5 to 7 μm; the thickness D of the n+ source region n+ 0.3~0.5μm;

[0122] The crystal structure obtained in this step is shown in Fig.26a shown.

[0123] S2, etching both sides of the n+ source region by dry etching process to form a mesa structure of the n+ source region and the p body region;

[0124] Specifically, a silicon dioxide masking film is deposited on the upper surface of the crystal obtained in S1, and both sides of the n+ source region on the upper surface of the crystal are dry-etched to form a mesa structure of the n+ source region and the p-body region, wherein the over-etching of the n+ source region is controlled within 10% of its depth.

[0125] The crystal structure obtained in this step is shown in Figure 26b As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0126] S3, using a dry etching process, etching the n+ source region downward to the n-drift region to form an active region trench, and etching the edge p-body region downward to the n-drift region to form a terminal region trench;

[0127] Specifically, S3 may include:

[0128] S31, remove the silicon dioxide film on the upper surface of the current crystal, re-deposit the silicon dioxide mask film, and perform a second dry etching on the upper surface of the crystal, including etching the n+ source region downward to the n-drift region to form an active region groove, and etching the edge p body region downward to the n-drift region to form a terminal region groove.

[0129] In a preferred embodiment, the width W of the active area trench is TG The active area trench depth D TG The depth of the terminal area groove is 1.7 to 2.5 μm;

[0130] S32, removing the silicon dioxide covering film on the upper surface of the current crystal, and performing NO / N2O nitridation treatment to remove the damage caused by surface etching to reduce the surface state.

[0131] It can be seen that the present invention only performs one NO / N2O nitridation treatment after all etching is completed, which can not only remove the damage caused by surface etching to reduce the interface state, but also simplify the process flow and reduce the cost.

[0132] The crystal structure obtained in this step is shown in Fig.26c shown.

[0133] S4, performing multiple aluminum ion cover implantation on the active area trench to form a p floating area at the bottom of the active area trench, and making the outer side of the p floating area wrap around the corner of the active area trench in an arc shape;

[0134] Specifically, a 30-50 nm silicon dioxide covering film is deposited on the upper surface of the current crystal, a photoresist is applied as a masking film, and aluminum ion covering implantation is performed multiple times at room temperature on the bottom of the active area trench, and a p floating area is formed at the bottom of the active area trench by adjusting the implantation dose and energy, and the outer side of the p floating area is made to wrap the corner of the active area trench in an arc shape;

[0135] In a preferred embodiment, the concentration N of the p floating region is p 5×10 17 cm -3 ~6×10 17 cm -3 , the junction depth D of the p floating region p It is 0.6~0.7μm.

[0136] The crystal structure obtained in this step is shown in Fig.26d As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0137] S5, performing multiple aluminum ion implantation on the bottom of the termination region trench to form a p-junction termination extension region at the bottom of the termination region trench, and making the outer side of the p-junction termination extension region wrap around the corner of the termination region trench in an arc shape;

[0138] Specifically, the silicon dioxide covering film on the upper surface of the current crystal is removed, a silicon dioxide covering film of 30 to 50 nm is re-deposited, a photoresist is applied as a masking film, and aluminum ion covering implantation is performed multiple times at room temperature on the bottom of the trench in the terminal area, while adjusting the implantation dose and energy to form a p-junction terminal extension area at the bottom of the trench in the terminal area, and the outer side of the p-junction terminal extension area is made to wrap the corner of the trench in the terminal area in an arc shape;

[0139] In a preferred embodiment, the concentration N of the p-junction terminal extension region is JTE 3.2×10 17 ~3.6×10 17 cm -3 ; The depth D of the p-junction terminal extension regionJTE is 0.4 to 0.6 μm; the width W of the p-junction terminal extension region JTE The p-junction terminal extension region is referred to as p-JTE region.

[0140] The crystal structure obtained in this step is shown in Fig.26e As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0141] S6, implanting aluminum ions into the outer surface edge region of the p-body region having a distance from the n+ source region to form a p+ region, and performing high temperature annealing;

[0142] Specifically, the silicon dioxide covering film on the current crystal upper surface is removed, and a 30-50nm silicon dioxide covering film and a polysilicon masking film are re-deposited, and polysilicon is etched at the outer surface edge area of ​​the p-body region with a spacing from the n+ source region to form a p+ region injection window, and then aluminum ions are implanted at 500°C to form a p+ region;

[0143] Wherein, the high temperature annealing is performed at 1700° C. In a preferred embodiment, the distance S between the n+ source region and the p+ region is B The doping concentration of the p+ region after high temperature annealing is 3×10 19 ~5×10 19 cm -3 , which belongs to high concentration injection.

[0144] The crystal structure obtained in this step is shown in Fig.26f As shown (for simplicity, the silicon dioxide film on the upper surface of the crystal is not shown).

[0145] S7, preparing a gate oxide layer on the side and bottom of the active area trench by thermal oxidation, and then depositing polysilicon and heavily doping it to fill the active area trench to form a trench gate G;

[0146] Specifically, S7 may include:

[0147] S71, removing the silicon dioxide covering film on the upper surface of the current crystal, and depositing a carbon film, and performing high temperature annealing at 1700° C. under the protection of the carbon film to activate impurities, eliminate damage caused by ion implantation, and prevent impurities from overflowing;

[0148] S72, after removing the carbon film and damage on the upper surface of the current crystal, high temperature thermal oxidation is performed at 1250°C to form a gate oxide layer on the side and bottom of the active area trench, and then polysilicon is deposited and heavily doped to fill the active area trench to form a polysilicon trench gate G; wherein the doping concentration is 5×10 19 cm -3 above;

[0149] The crystal structure obtained in this step is shown in Figure 26g shown.

[0150] S8, depositing an oxide film and a borophosphosilicate glass layer on the surface of the active area groove, and photolithography to form source and base metal contact holes; then depositing metal nickel, and after high-temperature annealing, forming an ohmic contact of the source S on the surface of the n+ source area, and forming an ohmic contact of the base B on the surface of the p+ area; then using a stripping process to remove the metal nickel layer on the surface of the borophosphosilicate glass; and etching a gate welding hole, depositing metal titanium, titanium nitride and aluminum copper film in sequence, and then reverse etching to form source, base and gate metal electrodes, and performing rapid annealing to complete the preparation of the surface metal electrode;

[0151] The high temperature annealing in this step is carried out at 1700°C. The obtained crystal structure is shown in Figure 26h shown.

[0152] S9, depositing silicon nitride film and photolithography to passivate the terminal area on the chip surface; then coating polyimide film, photolithography to form surface source, gate and base area bonding area patterns, and performing imidization treatment to form a front terminal passivation and protection layer to complete the device surface passivation treatment;

[0153] S10, thinning the lower surface of the 4H-SiC n+ substrate, and sputtering metal titanium, nickel, and silver in sequence to prepare a drain electrode D, and then performing laser annealing to reduce the ohmic contact resistance to complete the preparation of the back metal electrode.

[0154] Through the above steps, the trench gate dual-control electrode 4H-SiC composite transistor is completed.

[0155] The chips then need to be diced, packaged and tested.

[0156] The design features of the above process flow of the present invention are:

[0157] The P-body region and n+ source region in S1 are both formed by epitaxial process and are uniformly doped. By controlling the thickness and concentration of the epitaxial layer in the p-body region, the channel length and threshold voltage can be precisely controlled.

[0158] First, the p-body region mesa etching is performed (involving step S2), and then the active region trench etching and the terminal region trench etching are performed simultaneously (involving step S31), and after all etchings are completed, only one NO / N2O nitridation treatment is performed (involving step S32), which can not only remove the damage caused by surface etching to reduce the interface state, but also simplify the process flow and reduce the cost;

[0159] During all ion implantations (involving steps S4, S5, and S6), a 30-50 nm silicon dioxide capping film is used for implantation, which can not only avoid crystal damage caused by ion implantation, but also move the implantation peak concentration to the crystal surface;

[0160] After all ions are implanted, only one high temperature annealing treatment is performed under the protection of the carbon film (involving step S71), which can not only activate the impurities, eliminate the damage caused by ion implantation, and prevent the impurities from overflowing, but also simplify the process flow and reduce costs;

[0161] Aluminum ion implantation is performed multiple times on the bottom of the trench, and the implantation dose and energy are adjusted at the same time to form a p-floating region at the bottom of the active region trench or a p-junction terminal extension region at the bottom of the terminal region trench, and the outer side of the p-floating region or the p-junction terminal extension region is formed in an arc shape to wrap the corner of the active region trench or the terminal region trench. The electric field in the oxide layer at the corner of the trench can be significantly reduced to avoid the breakdown of the gate oxide layer at the corner of the active region trench or the breakdown at the corner of the terminal trench.

[0162] The over-etching of the n+ source region needs to be controlled within 10% of its depth to prevent the p-body region from being too thin and causing punch-through (involving step S2).

[0163] The device prepared by the method for preparing the trench gate dual-control electrode 4H-SiC composite transistor structure provided in the embodiment of the present invention can not only improve the contradiction between on-resistance and breakdown voltage, but also reduce the electric field strength in the gate oxide layer and increase the short-circuit withstand time, thereby improving the characteristics and reliability of the device. At the same time, the terminal area size is reduced and is compatible with the active area process, thereby reducing costs.

[0164] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the concept and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A trench gate dual-control electrode 4H-SiC composite transistor structure, characterized in that: It is composed of an active region formed by connecting multiple cellular structures in parallel in the center and a composite terminal region of trench-junction terminal extensions in the periphery; The cell structure comprises: an n buffer layer, an n-drift region, an n carrier expansion layer, a p body region and an n+ source region sequentially arranged on a 4H-SiC n+ substrate; an active region trench is arranged in the center of the cell structure, penetrating downward from the n+ source region to the n-drift region; a p floating region with an arc-shaped outer side is arranged below the active region trench, and its arc edge wraps the corner of the active region trench; the side and bottom surfaces of the active region trench are covered with a gate oxide layer, and the interior is filled with heavily doped polysilicon as a trench gate G; the n+ source region and the p body region on each side form a mesa structure, and a p+ region is arranged in the top layer area close to the outer edge of the p body region under the mesa structure on each side, and has a spacing with the n+ source region on the same side; a source electrode S is arranged on the surface of the n+ source region; a base electrode B is arranged on the surface of the p+ region; the surface of the active region trench is covered with a phosphorus silicon glass layer to isolate the trench gate G from the source electrode S; the 4H-SiC A drain D is provided on the back of the n+ substrate; the trench gate G and the base B are both control electrodes; the cell structure is symmetrical with the central trench gate G as the axis, which is equivalent to the parallel connection of VUMOS and BJT; The trench-junction terminal extension composite terminal region is connected to the corresponding layer of the outermost cellular structure of the active region, and includes an n buffer layer, an n-drift region, an n carrier expansion layer, a p body region, and a drain D on the back side of the 4H-SiC n+ substrate, which are sequentially arranged on a 4H-SiC n+ substrate; its p body region, n carrier expansion layer and a part of the n-drift region form a mesa structure with the remaining part of the n-drift region as a terminal region trench, and a p-junction terminal extension region is arranged in a local area in the n-drift region at a corner below the terminal region trench, and the p-junction terminal extension region is arc-shaped near the side of the terminal region trench and wraps the corner of the terminal region trench.

2. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that: For the trench-junction terminal extension composite terminal region and the outermost cell structure of the connected active region, a naturally formed longitudinal resistance region is present in the p-body region, the n-carrier expansion layer and the n-drift region of the trench sidewall of the terminal region.

3. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that: In the trench gate dual-control electrode 4H-SiC composite transistor structure, the n-drift region of VUMOS is equivalent to the n-collector region of BJT, the p-body region of VUMOS is equivalent to the p-base region of BJT, the n+ source region of VUMOS is equivalent to the n+ emitter region of BJT, and the 4H-SiC n+ substrate of VUMOS is equivalent to the collector ohmic contact region of BJT; the source S of VUMOS is also the emitter E of BJT, and the drain D of VUMOS is also the collector C of BJT; the gate G and the base B respectively control the opening and closing of VUMOS and BJT.

4. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that: When the trench gate dual control electrode 4H-SiC composite transistor is turned on, a gate voltage is applied to the trench gate G as a control electrode, and a base current is applied to the base B as another control electrode, thereby triggering VUMOS and BJT to turn on at the same time, so that the n-drift region produces a conductivity modulation effect, and the entire device works in a bipolar mode.

5. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that: In the cell structure, The width W of the active area trench TG The active area trench depth D TG 1.4~2μm; The concentration N of the p floating region p 5×10 17 cm -3 ~6×10 17 cm -3 , the junction depth D of the p floating region p 0.6~0.7μm; The width W of the n+ source region n+ is 5 to 7 μm; the thickness D of the n+ source region n+ is 0.3-0.5 μm; the distance S between the n+ source region and the p+ region B 3~5μm.

6. The trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 1, characterized in that: The trench-junction termination extends into the composite termination region, The depth of the terminal region trench is 1.7 to 2.5 μm; the concentration N of the p-junction terminal extension region is JTE 3.2×10 17 ~3.6×10 17 cm -3 ; The junction depth D of the p-junction terminal extension region JTE is 0.4 to 0.6 μm; the width W of the p-junction terminal extension region JTE 20~35μm.

7. A method for preparing a trench gate dual-control electrode 4H-SiC composite transistor structure, characterized in that: include: On a 4H-SiC n+ substrate, an n-buffer layer, an n-drift region, an n-carrier extension layer, a p-body region and an n+ source region are grown in sequence using an epitaxial process; Etching both sides of the n+ source region by dry etching process to form a mesa structure of the n+ source region and the p-body region; Using a dry etching process, the n+ source region is etched downward to the n-drift region to form an active region trench, and the edge p-body region is etched downward to the n-drift region to form a terminal region trench; Performing multiple aluminum ion cover implantations on the active area trench to form a p-type floating area at the bottom of the active area trench, and making the outer side of the p-type floating area wrap around the corner of the active area trench in an arc shape; Performing multiple aluminum ion covering implantations on the bottom of the termination region trench to form a p-junction termination extension region at the bottom of the termination region trench, and making the outer side of the p-junction termination extension region wrap around the corner of the termination region trench in an arc shape; Aluminum ions are implanted into the outer surface edge region of the p-body region which is spaced apart from the n+ source region to form a p+ region, and high temperature annealing is performed; Using thermal oxidation to prepare a gate oxide layer on the side and bottom of the active area trench, and then depositing polysilicon and heavily doping it to fill the active area trench to form a trench gate G; Depositing an oxide film and a borophosphosilicate glass layer on the surface of the active area trench, and photolithographically forming source and base metal contact holes; Then, metal nickel is deposited, and after high-temperature annealing, an ohmic contact of the source electrode S is formed on the surface of the n+ source region, and an ohmic contact of the base electrode B is formed on the surface of the p+ region; and then the metal nickel layer on the surface of the borophosphosilicate glass is removed by a stripping process; The gate welding hole is etched, and metal titanium, titanium nitride and aluminum copper films are deposited in sequence, and then the source, base and gate metal electrodes are formed by reverse etching, and rapid annealing is performed to complete the preparation of the surface metal electrode; Deposit silicon nitride film and perform photolithography to passivate the terminal area on the chip surface; then apply polyimide film, perform photolithography to form the surface source, gate and base area bonding area patterns, and perform imidization treatment to form the front terminal passivation and protection layer to complete the device surface passivation treatment; The lower surface of the 4H-SiC n+ substrate is thinned, and metal titanium, nickel and silver are sputtered in sequence to prepare a drain electrode D, and then laser annealing is performed to reduce the ohmic contact resistance to complete the preparation of the back metal electrode.

8. The method for preparing a trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 7, characterized in that: Performing multiple aluminum ion cover implantations on the active area trench to form a p floating area at the bottom of the active area trench, and making the outer side of the p floating area wrap around the corner of the active area trench in an arc shape, including: On the upper surface of the current crystal, a 30-50 nm silicon dioxide covering film is deposited, a photoresist is applied as a masking film, and aluminum ion covering implantation is performed multiple times at room temperature on the bottom of the active area trench. By adjusting the implantation dose and energy, a p floating area is formed at the bottom of the active area trench, and the outer side of the p floating area is made to wrap the corner of the active area trench in an arc shape; wherein the concentration N of the p floating area p 5×10 17 cm -3 ~6×10 17 cm -3 , the junction depth D of the p floating region p It is 0.6~0.7μm.

9. The method for preparing a trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 8, characterized in that: The bottom of the terminal region trench is covered with aluminum ions for multiple times to form a p-junction terminal extension region at the bottom of the terminal region trench, and the outer side of the p-junction terminal extension region is formed in an arc shape to wrap the corner of the terminal region trench, including: The silicon dioxide covering film on the current crystal upper surface is removed, and a 30-50 nm silicon dioxide covering film is re-deposited, and a photoresist is applied as a masking film. The bottom of the terminal area trench is implanted with aluminum ions multiple times at room temperature, and the implantation dose and energy are adjusted at the same time to form a p-junction terminal extension area at the bottom of the terminal area trench, and the outer side of the p-junction terminal extension area is formed in an arc shape to wrap the corner of the terminal area trench; wherein the concentration N of the p-junction terminal extension area JTE 3.2×10 17 ~3.6×10 17 cm -3 ; The junction depth D of the p-junction terminal extension region JTE is 0.4 to 0.6 μm; the width W of the p-junction terminal extension region JTE 20~35μm.

10. The method for preparing a trench gate dual-control electrode 4H-SiC composite transistor structure according to claim 9, characterized in that: Aluminum ions are implanted into the outer surface edge region of the p-body region having a spacing from the n+ source region to form a p+ region, including: Remove the silicon dioxide covering film on the current crystal surface, re-deposit the silicon dioxide covering film and polysilicon masking film, etch the polysilicon in the outer surface edge area of ​​the p-body region with a spacing from the n+ source region to form a p+ region injection window, and then perform aluminum ion implantation at 500°C to form a p+ region; The doping concentration of the p+ region after annealing is 3×10 19 ~5×10 19 cm -3 .

Images