A trench MOSFET device and its preparation method

Abstract

The present application provides a trench MOSFET device and a preparation method thereof, relating to the field of semiconductor technology, wherein the MOSFET device comprises: a substrate, an epitaxial layer, a well region layer and a MOSFET structure, wherein the doping concentration of the well region layer decreases in a direction away from the epitaxial layer, and the MOSFET structure comprises a source region, a trench gate, a source electrode, a drain electrode and a first carrier channel. The trench gate comprises a trench located in the epitaxial layer, and a gate located in the trench, with a gate dielectric layer filled between the gate and the trench. Thus, it can be seen that for the MOSFET device, the doping concentration of its well region layer decreases in a direction away from the epitaxial layer, and the region with a high doping concentration in the well region layer can form a good shielding effect, and the region with a low doping concentration can ensure the conduction characteristics of the device, thereby forming a good shielding effect while not affecting the conduction characteristics of the device, effectively solving the problem of rapid breakdown of the gate dielectric layer under high drain voltage.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a trench MOSFET device and a method for preparing the same. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] Integrated circuits are the primary structure for electronic devices to achieve their various functions, and they are crucial electronic components. In recent years, wide-bandgap semiconductor materials have demonstrated advantages in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. MOSFET devices fabricated from these materials exhibit superior electrical properties, overcoming the limitations of silicon-based materials in applications requiring high power, high voltage, high frequency, and high temperature. These materials represent a breakthrough path toward surpassing Moore's Law, and are therefore widely used in new energy fields (photovoltaics, energy storage, charging stations, electric vehicles, etc.).

[0004] However, in actual design and application, the high electric field in the drift region leads to a very high electric field on the gate dielectric layer. Especially for trench MOSFET devices, this problem is exacerbated at the trench corners, causing the gate dielectric layer to quickly break down under high drain voltages. The device has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit. Summary of the Invention

[0005] In view of this, the present application provides a trench MOSFET device and a method for manufacturing the same, the scheme is as follows:

[0006] A trench MOSFET device, comprising:

[0007] substrate;

[0008] an epitaxial layer, the epitaxial layer being located on the surface of the substrate;

[0009] a well region layer, the well region layer being located on a side of the epitaxial layer away from the substrate, and the doping concentration of the well region layer decreasing in a direction away from the epitaxial layer;

[0010] At least one MOSFET structure, the MOSFET structure comprising a source region, a trench gate, a source electrode, and a drain, the trench gate comprising a trench located on a side of the well region layer facing away from the epitaxial layer, a gate electrode located within the trench, and an interlayer dielectric layer filling the trench and covering the gate, with a gate dielectric layer further filling between the gate and the trench; the source region being located on a side of the well region layer facing away from the epitaxial layer and surrounding the trench, the source electrode being located on a side of the source region facing away from the epitaxial layer, and the drain being located on a side of the substrate facing away from the epitaxial layer;

[0011] The MOSFET structure further includes a first carrier channel, which is located between the trench gate and the epitaxial layer, and one end of the first carrier channel is connected to the trench, and the other end is connected to the epitaxial layer.

[0012] Optionally, the well region layer includes a first well region and a second well region arranged along a first direction, and the first direction is from the epitaxial layer to the well region layer;

[0013] The doping concentration of the second well region is lower than the doping concentration of the first well region, and the trench is located in the second well region.

[0014] Optionally, the method further comprises: a first diode structure, wherein a first diode structure is provided between two adjacent MOSFET structures in the at least one MOSFET structure, and the first diode structure comprises a carrier shielding layer and a second carrier channel;

[0015] The second carrier channel runs through the well region layer, the source region surrounds the second carrier channel, and the second carrier channel surrounds the carrier shielding layer; the carrier shielding layer extends into the second well region and is exposed on a side of the second well region facing away from the epitaxial layer, and the side of the carrier shielding layer facing away from the epitaxial layer is flush with a side of the second carrier channel facing away from the epitaxial layer.

[0016] Optionally, the carrier shielding layer extends along a second direction, the second direction is parallel to the plane where the well region layer is located, and the second carrier channel surrounds the carrier shielding layer.

[0017] Optionally, the carrier shielding layer includes a plurality of sub-shielding layers arranged along a second direction, and the second direction is parallel to the plane where the well region layer is located;

[0018] There are first gaps between the plurality of sub-shielding layers, and the second carrier channel surrounds the carrier shielding layer and fills the first gaps between the plurality of sub-shielding layers.

[0019] Optionally, the method further comprises: a second diode structure, wherein a second diode structure is provided between two adjacent MOSFET structures in the at least one MOSFET structure, and the second diode structure comprises a carrier shielding layer and a second carrier channel;

[0020] The carrier shielding layer extends into the second well region and is exposed on a side of the second well region facing away from the epitaxial layer; the carrier shielding layer includes a plurality of sub-shielding layers arranged along a second direction, with first gaps between the plurality of sub-shielding layers, and the second direction is parallel to the plane where the well region layer is located;

[0021] The second carrier channel runs through the well region layer, and the second carrier channel surrounds the portion of the carrier shielding layer located in the second well region, and the second carrier channel also fills the first gap between the multiple sub-shielding layers, and the source region surrounds the side of the second carrier channel facing away from the epitaxial layer and the side of the carrier shielding layer facing away from the epitaxial layer.

[0022] Optionally, the second carrier channel includes a plurality of channel regions arranged along the first direction, and the diameters of the plurality of channel regions gradually increase along the first direction;

[0023] The carrier shielding layer includes a plurality of shielding regions arranged along the first direction, and diameters of the plurality of shielding regions gradually increase along the first direction.

[0024] Optionally, the multiple channel regions include a first channel region, a second channel region, and a third channel region arranged along the first direction; the first channel region is located in the first well region, and the first channel region is exposed on a side of the first well region facing the epitaxial layer; the second channel region is located in the second well region, covering the first channel region; the third channel region extends in the second well region, covering the second channel region, and is exposed on a side of the second well region facing away from the epitaxial layer;

[0025] The diameter of the first channel region is smaller than that of the second channel region, and the diameter of the second channel region is smaller than that of the third channel region.

[0026] Optionally, the gate includes a first gate and a second gate;

[0027] The first gate includes a first sub-gate and a second sub-gate, the first sub-gate covers the sidewall of the trench, the second sub-gate covers the sidewall of the trench, and a second gap is formed between the first sub-gate and the second sub-gate, the second gap exposes the bottom of the trench, and the interlayer dielectric layer covers the first gate and fills the second gap;

[0028] The second gate covers the sidewall and bottom of the trench, is connected to the second gate of the adjacent MOSFET structure, and the interlayer dielectric layer covers the second gate.

[0029] Optionally, the gate is a fin-shaped gate.

[0030] A method for preparing a trench MOSFET device, comprising:

[0031] providing a substrate;

[0032] forming an epitaxial layer on the substrate;

[0033] forming a well region layer on a side of the epitaxial layer away from the substrate, wherein the doping concentration of the well region layer decreases in a direction away from the epitaxial layer;

[0034] forming at least one MOSFET structure, the MOSFET structure comprising a source region, a trench gate, a source electrode, and a drain, the trench gate comprising a trench located on a side of the well region layer facing away from the epitaxial layer, a gate electrode located within the trench, and an interlayer dielectric layer filling the trench and covering the gate, with a gate dielectric layer further filled between the gate and the trench; the source region being located on a side of the well region layer facing away from the epitaxial layer and surrounding the trench, the source electrode being located on a side of the source region facing away from the epitaxial layer, and the drain being located on a side of the substrate facing away from the epitaxial layer;

[0035] The MOSFET structure further includes a first carrier channel, which is located between the trench gate and the epitaxial layer, and one end of the first carrier channel is connected to the trench, and the other end is connected to the epitaxial layer.

[0036] Optionally, forming a well region layer on a side of the epitaxial layer facing away from the substrate includes:

[0037] forming a first well region and a second well region arranged along a first direction on a side of the epitaxial layer away from the substrate, wherein the first direction is from the epitaxial layer to the well region layer;

[0038] The doping concentration of the second well region is lower than the doping concentration of the first well region, and the trench is located in the second well region.

[0039] Optionally, the preparation method further comprises:

[0040] forming a first diode structure, wherein a first diode structure is provided between two adjacent MOSFET structures in the at least one MOSFET structure, and the first diode structure includes a carrier shielding layer and a second carrier channel;

[0041] The second carrier channel runs through the well region layer, the source region surrounds the second carrier channel, and the second carrier channel surrounds the carrier shielding layer; the carrier shielding layer extends into the second well region and is exposed on a side of the second well region facing away from the epitaxial layer, and the side of the carrier shielding layer facing away from the epitaxial layer is flush with a side of the second carrier channel facing away from the epitaxial layer.

[0042] Optionally, the preparation method further comprises:

[0043] forming a second diode structure, wherein a second diode structure is provided between two adjacent MOSFET structures in the at least one MOSFET structure, and the second diode structure includes a carrier shielding layer and a second carrier channel;

[0044] The carrier shielding layer extends into the second well region and is exposed on a side of the second well region facing away from the epitaxial layer; the carrier shielding layer includes a plurality of sub-shielding layers arranged along a second direction, with first gaps between the plurality of sub-shielding layers, and the second direction is parallel to the plane where the well region layer is located;

[0045] The second carrier channel runs through the well region layer, and the second carrier channel surrounds the portion of the carrier shielding layer located in the second well region, and the second carrier channel also fills the first gap between the multiple sub-shielding layers, and the source region surrounds the side of the second carrier channel facing away from the epitaxial layer and the side of the carrier shielding layer facing away from the epitaxial layer.

[0046] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0047] The MOSFET device includes: a substrate, an epitaxial layer, a well region layer, and at least one MOSFET structure, wherein the doping concentration of the well region layer decreases in the direction away from the epitaxial layer, and the MOSFET structure includes a source region, a trench gate, a source electrode, a drain electrode, and a first carrier channel. The trench gate includes a trench located on the side of the well region layer away from the epitaxial layer, and a gate electrode located in the trench, and a gate dielectric layer is filled between the gate electrode and the trench. It can be seen that for the MOSFET device, its trench gate is located in the well region layer, so that the groove corners of the trench gate can be wrapped by the well region layer, thereby effectively achieving electric field shielding at the trench gate through the well region layer, especially for the electric field shielding at the groove corners of the trench, which helps to suppress the problem of rapid breakdown of the gate dielectric layer of the trench gate under high drain voltage, thereby ensuring the reliability of the trench MOSFET device. In addition, the doping concentration of the well layer decreases in the direction away from the epitaxial layer. The area with high doping concentration in the well layer can form a good shielding effect, and the area with low doping concentration can ensure the conduction characteristics of the device. Then, the well layer can form a good shielding effect while not affecting the conduction characteristics of the device, effectively solving the problem of rapid breakdown of the gate dielectric layer of the trench gate under high drain voltage, thereby ensuring the reliability of the trench MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0049] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size, without affecting the efficacy and objectives that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0050] Figure 1 A schematic structural diagram of a trench MOSFET device provided in this application;

[0051] Figure 2 A schematic structural diagram of another trench MOSFET device provided in this application;

[0052] Figure 3-Figure 5 for Figure 2 Cross-sectional view along AA1;

[0053] Figure 6 A schematic structural diagram of another trench MOSFET device provided in this application;

[0054] Figure 7 for Figure 6 Cross-sectional view along BB1;

[0055] Figure 8 A schematic structural diagram of another trench MOSFET device provided in this application;

[0056] Figure 9 A schematic structural diagram of another trench MOSFET device provided in this application;

[0057] Figure 10 A schematic diagram of the cell layout of a trench MOSFET device provided in this application;

[0058] Figure 11 A schematic diagram of the cell layout of another trench MOSFET device provided in this application;

[0059] Figure 12 for Figure 10 and Figure 11 Cross-sectional view along CC1;

[0060] Figure 13 for Figure 10 and Figure 11 Cross-sectional view along DD1;

[0061] Figure 14 A flow chart of a method for preparing a trench MOSFET device provided in this application;

[0062] Figure 15 Schematic diagram of the process flow of Example 1;

[0063] Figure 16 This is a schematic diagram of the process flow of Example 2. DETAILED DESCRIPTION

[0064] The following will be combined with the accompanying drawings to clearly and completely describe the embodiments of this application. Obviously, the described embodiments are only embodiments of one area of ​​this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0065] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0066] As described in the background technology, for trench MOSFET devices, the high electric field in the drift region will cause a very high electric field on the gate dielectric layer, which in turn causes the gate dielectric layer to quickly break down under high drain voltage, especially at the trench corners. This makes the trench MOSFET poorly resistant to electrostatic effects in harsh environments and high-voltage spikes in circuits.

[0067] In addition, the parasitic diode (also called body diode) in the trench MOSFET device is a bipolar device with a minority carrier storage effect, a long reverse recovery time, and large switching losses.

[0068] Based on the above, the present application provides a trench MOSFET device, such as Figure 1 As shown, the MOSFET device includes:

[0069] Substrate 100 may be a wide bandgap substrate, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), aluminum nitride (AlN), or the like. Accordingly, the trench MOSFET device described herein may be a wide bandgap trench MOSFET device.

[0070] The epitaxial layer 200 is located on the surface of the substrate 100, specifically the upper surface of the substrate 100. It should be noted that the surface of the substrate 100 specifically refers to the upper surface of the substrate 100. It should be noted that the epitaxial layer 200 can be an N-type epitaxial layer.

[0071] The well region layer 300 is located on the side of the epitaxial layer 200 facing away from the substrate 100. The doping concentration of the well region layer 300 decreases as it moves away from the epitaxial layer 200. That is, the doping concentration of the well region layer 300 decreases in the direction from the epitaxial layer 200 toward the well region layer 300. The well region layer 300 may be a P-type doped well region.

[0072] At least one MOSFET structure 400 includes a source region 410, a trench gate 420, a source electrode 430, and a drain electrode 440. The trench gate 420 includes a trench 421 located on the side of the well layer 300 facing away from the epitaxial layer 200, a gate electrode 422 located in the trench 421, and an interlayer dielectric layer 426 filling the trench 421 and covering the gate electrode 422. A gate dielectric layer 423 is also filled between the gate electrode 422 and the trench 421. In other words, the trench gate 420 is located in the well layer 300 and is surrounded by the well layer 300. Then, the trench corners of the trench gate 420 can be covered by the well layer 300. The source region 410 is located on the side of the well layer 300 facing away from the epitaxial layer 200, surrounds the trench 421, and contacts the outer sidewalls of the trench 421. The source region 410 may be composed of a first source region 411 and a second source region 412 having different doping types. For example, the first source region 411 is an N-type doped source region that contacts the outer sidewalls of the trench 421, and the second source region 412 is a P-type doped source region. The source electrode 430 is located on the side of the source region 410 facing away from the epitaxial layer 200. Specifically, the source electrode 430 contacts the first source region 411 and also contacts the second source region 412. The drain electrode 440 is located on the side of the substrate 100 facing away from the epitaxial layer 200, that is, the drain electrode 440 is located on the lower surface of the substrate 100, with the lower surface of the substrate 100 facing the upper surface.

[0073] The MOSFET structure 400 further includes a first carrier channel 1, which is located between the trench gate 420 and the epitaxial layer 200. Specifically, one end of the first carrier channel 1 is connected to the trench 421, and the other end is connected to the epitaxial layer 200. When the MOSFET device is in operation, current flows through the first carrier channel 1.

[0074] From the above, it can be seen that for the trench MOSFET device provided in the present application, its trench gate 420 is located in the well region layer 300, so that the trench corners of the trench gate 420 can be wrapped by the well region layer 300, thereby effectively realizing electric field shielding at the trench gate 420 through the well region layer 300, especially for the electric field shielding at the trench corners of the trench 421, which helps to suppress the problem of rapid breakdown of the gate dielectric layer 423 of the trench gate 420 under high drain voltage, thereby ensuring the reliability of the trench MOSFET device.

[0075] It should be noted that when the well region layer 300 is used to achieve electric field shielding for the trench gate 420, the doping concentration of the well region layer 300 has an important influence on the effect of the electric field shielding. If the doping concentration is low, a good shielding effect cannot be formed, and if the doping concentration is too high, it will affect the conduction characteristics of the device, resulting in a significant degradation of the conduction characteristics of the device. To this end, the doping concentration of the well region layer 300 of the trench MOSFET device provided by the present application decreases in the direction away from the epitaxial layer 200. The high doping concentration area in the well region layer 300 can form a good shielding effect, and the low doping concentration area can ensure the conduction characteristics of the device. Then, the well region layer 300 can form a good shielding effect while not affecting the conduction characteristics of the device, effectively solving the problem of the gate dielectric layer 423 of the trench gate 420 being quickly broken down under high drain voltage, thereby ensuring the reliability of the trench MOSFET device.

[0076] Based on the above embodiments, in one embodiment of the present application, Figure 1 As shown, the well region layer 300 includes a first well region 310 and a second well region 320 arranged along a first direction, wherein the first direction is from the epitaxial layer 200 to the well region layer 300, that is, the first well region 310 and the second well region 320 are arranged along a direction away from the epitaxial layer 200, that is, the first well region 310 is located on a side close to the epitaxial layer 200, and the second well region 320 is located on a side away from the epitaxial layer 200.

[0077] The doping concentration of the second well region 320 is lower than the doping concentration of the first well region 310, and the groove 421 is located in the second well region 310, so that the area with low doping concentration in the well region layer 300 ensures the conduction characteristics of the device, and the area with high doping concentration forms a good shielding effect, so that the well region layer 300 can form a good shielding effect while not affecting the conduction characteristics of the device.

[0078] Based on the above embodiments, in one embodiment of the present application, Figure 2 As shown, the trench MOSFET device further includes a first diode structure 500. Specifically, for this trench MOSFET device, a first diode structure 500 is provided between two adjacent MOSFET structures 400 in the at least one MOSFET structure 400. The first diode structure 500 includes a carrier shielding layer 510 and a second carrier channel 2.

[0079] Specifically, the second carrier channel 2 of the first diode structure 500 is located in the well region layer 300 and penetrates the first well region 310 and the second well region 320. That is, the second carrier channel 2 penetrates the well region layer 300, and its upper and lower ends are respectively exposed on the upper and lower surfaces of the well region layer 300. The source region 410 surrounds the second carrier channel 2, that is, the source region 410 surrounds the end of the second carrier channel 2 exposed on the upper surface of the well region layer 300, and the second carrier channel 2 surrounds the carrier shielding layer 510. Specifically, the carrier shielding layer 510 extends into the second well region 320 and is exposed on the side of the second well region 320 facing away from the epitaxial layer 200. That is, the carrier shielding layer 510 extends into the second well region 320, and the side of the carrier shielding layer 510 facing away from the epitaxial layer 200 is flush with the side of the second carrier channel 2 facing away from the epitaxial layer 200.

[0080] As can be seen from the above, there is a first diode structure 500 between two adjacent MOSFET structures 400 in the at least one MOSFET structure 400, and the first diode structure 500 can form a high-speed freewheeling diode controlled by a PN junction. Since the high-speed freewheeling diode is a unipolar device, there is no minority carrier storage effect, and the reverse recovery time is short, thereby reducing the switching loss of the trench MOSFET device. Specifically, when the high-speed freewheeling diode formed by the first diode structure 500 is in a reverse withstand voltage state, the second carrier channel 2 will be pinched off by the surrounding source region 410, the carrier shielding layer 510 and the depletion region of the well layer 300. At this time, the high-speed freewheeling diode is in a closed state, thereby effectively avoiding the degradation problem of the withstand voltage blocking characteristics of the MOSFET device, thereby reducing the switching loss of the trench MOSFET device.

[0081] Furthermore, the first diode structure 500 includes a carrier-shielding layer 510. In the well layer 300, the second carrier channel 2 surrounds the carrier-shielding layer 510. In other words, the carrier-shielding layer 510 is embedded in the second carrier channel 2. As the name implies, the carrier-shielding layer 510 is a film layer that blocks carriers. Therefore, the presence of the carrier-shielding layer 510 can narrow the second carrier channel 2, thereby pinching off the second carrier channel 2 during reverse withstand voltage.

[0082] Based on the above embodiments, in one embodiment of the present application, Figure 3 As shown, the carrier shielding layer 510 extends along the second direction, which is parallel to the plane of the well region layer 300. The second carrier channel 2 surrounds the carrier shielding layer 510. That is, the carrier shielding layer 510 is a strip or a piece extending along the second direction, that is, the carrier shielding layer 510 can be an integrally formed structure.

[0083] In another embodiment of the present application, Figure 4 As shown, the carrier shielding layer 510 includes multiple sub-shielding layers 511 arranged along a second direction, which is parallel to the plane of the well region layer 300. A first gap is defined between the multiple sub-shielding layers 511. The second carrier channel 2 surrounds the carrier shielding layer 510 and also fills the first gap between the multiple sub-shielding layers 511. This embodiment differs from the previous embodiment in that the carrier shielding layer 510 is intermittently distributed, rather than being an integrally formed structure.

[0084] Based on the above two embodiments, it can be seen that for the trench MOSFET device provided in this application, the carrier shielding layer 510 can be an integrally formed structure or a discontinuously distributed structure. It can be flexibly selected based on the actual application scenario and is highly practical.

[0085] It should be noted that if the carrier shielding layer 510 is a discontinuous structure including a plurality of sub-shielding layers 511, each sub-shielding layer 511 may be rectangular (eg Figure 4 As shown), it can also be circular (as Figure 5 As shown), or other shapes, this application does not limit this, and the specific circumstances depend on the circumstances.

[0086] Based on the above embodiments, in one embodiment of the present application, Figure 6 and Figure 7 As shown, Figure 7 for Figure 6 In the cross-sectional view along BB1, the trench MOSFET device further includes a second diode structure 600, wherein, for this trench MOSFET device, there is a second diode structure 600 between two adjacent MOSFET structures 400 in the at least one MOSFET structure 400, and the second diode structure 600 includes a carrier shielding layer 610 and a second carrier channel 2.

[0087] Specifically, the carrier-shielding layer 610 of the second diode structure 600 extends into the second well region 320 and is exposed on the side of the second well region 320 facing away from the epitaxial layer 200. That is, the carrier-shielding layer 610 extends from the upper surface of the well region layer 300 into the second well region 320. Furthermore, the carrier-shielding layer 610 includes a plurality of sub-shielding layers 611 arranged along a second direction, with first gaps between the plurality of sub-shielding layers 611. The second direction is parallel to the plane of the well region layer 300.

[0088] The second carrier channel 2 of the second diode structure 600 penetrates the well region layer 300, surrounds the portion of the carrier shielding layer 610 located within the second well region 320, and further fills the first gaps between the plurality of sub-shielding layers 611. The source region 410 surrounds the side of the second carrier channel 2 facing away from the epitaxial layer and the side of the carrier shielding layer 610 facing away from the epitaxial layer 200. That is, the source region 410 surrounds the second carrier channel 2 and the portion of the carrier shielding layer 610 located on the upper surface of the well region layer 300. In other words, the second carrier channel 2 located on the upper surface of the well region layer 300 is surrounded by and in contact with the source region 410, and the carrier shielding layer 610 located on the upper surface of the well region layer 300 is surrounded by and in contact with the source region 410.

[0089] The difference between the second diode structure 600 described in this embodiment and the above-mentioned first diode structure 500 is that the portion of the second carrier channel 2 located in the well region layer 300 surrounds the portion of the carrier shielding layer 610 located in the second well region 320, and the second carrier channel 2 located on the upper surface of the well region layer 300 corresponds to the first gap between the multiple sub-shielding layers 611, that is, the carrier shielding layer 610 is wider, so that the second carrier channel 2 of the second diode structure 600 can be narrower, so as to further ensure that the second carrier channel 2 can be pinched off during reverse withstand voltage.

[0090] Based on the above embodiments, in one embodiment of the present application, Figure 2 As shown, the second carrier channel 2 includes a plurality of channel regions 21 arranged along the first direction, and the diameters of the plurality of channel regions 21 gradually increase along the first direction. The carrier shielding layer 510 includes a plurality of shielding regions 512 arranged along the first direction, and the diameters of the plurality of shielding regions 512 gradually increase in the first direction. In other words, the diameter of the second carrier channel 2 gradually decreases during the process of extending into the well region layer 300, and the diameter of the carrier shielding layer 510 gradually decreases during the process of extending into the well region layer 300, so that the second carrier channel 2 can be more easily pinched off during reverse withstand voltage.

[0091] Based on the above embodiments, in a specific embodiment of the present application, Figure 8As shown, the plurality of channel regions 21 include a first channel region 211, a second channel region 212, and a third channel region 213 arranged along a first direction. The first channel region 211 is located within the first well region 310 and is exposed on the side of the first well region 310 facing the epitaxial layer 200, i.e., one end of the first channel region 211 is exposed on the lower surface of the well region layer 300. The second channel region 212 is located within the second well region 320, covering the first channel region 211. The third channel region 213 extends within the second well region 320, covering the second channel region 212, and is exposed on the side of the second well region 320 facing away from the epitaxial layer 200, i.e., the second channel region 212 and the third channel region 213 penetrate the second well region 320, and the third channel region 213 is exposed on the upper surface of the well region layer 300.

[0092] Specifically, the diameter of the first channel region 211 is smaller than the diameter of the second channel region 212 , and the diameter of the second channel region 212 is smaller than the diameter of the third channel region 213 .

[0093] Accordingly, the carrier shielding layer 510 may include a first shielding region 5121 and a second shielding region 5122 arranged along the first direction, and a diameter of the first shielding region 5121 is smaller than a diameter of the second shielding region 5122 .

[0094] Alternatively, the carrier shielding layer 510 may include a first shielding region 5121, a second shielding region 5122, and a third shielding region 5123 arranged along the first direction, wherein the diameter of the first shielding region 5121 is smaller than the diameter of the second shielding region 5122, and the diameter of the second shielding region 5122 is smaller than the diameter of the third shielding region 5123. It should be noted that when the carrier shielding layer 510 includes three shielding regions arranged along the first direction, the corresponding diode structure may also be the second diode structure 600, such as Figure 9 As shown, the carrier shielding layer 610 may include a first shielding area 6121, a second shielding area 6122 and a third shielding area 6123 arranged along the first direction, the diameter of the first shielding area 6121 is smaller than the diameter of the second shielding area 6122, and the diameter of the second shielding area 6122 is smaller than the diameter of the third shielding area 6123.

[0095] Based on the above embodiments, in one embodiment of the present application, the layout of the trench MOSFET device can be a square cell layout, such as Figure 10 In another embodiment of the present application, the layout of the trench MOSFET device can be a hexagonal cell layout, such as Figure 11 However, this application does not limit this, and the specific circumstances will be determined.

[0096] Based on the above embodiments, in one embodiment of the present application, Figure 12 and Figure 13 As shown, Figure 12 for Figure 10 and Figure 11 Cross-sectional view along CC1, Figure 13 for Figure 10 and Figure 11 In the cross-sectional view along DD1, the gate 422 includes a first gate 424 and a second gate 425. The first gate 424 includes a first sub-gate 4241 and a second sub-gate 4242. The first sub-gate 4241 covers the sidewalls of the trench 421, and the second sub-gate 4242 also covers the sidewalls of the trench 421. A second gap is provided between the first sub-gate 4241 and the second sub-gate 4242, and the second gap exposes the bottom of the trench 421. The second gate 425 covers the sidewalls and bottom of the trench 421 and is used to connect to the second gate of the adjacent MOSFET structure, thereby achieving a connection between the adjacent MOSFET structures. It should be noted that, in this embodiment, the interlayer dielectric layer 426 covers the first gate 424 and fills the second gap, and the interlayer dielectric layer 426 covers the second gate 425, so that the interlayer dielectric layer 426 fills the trench 421 and covers the gate 42.

[0097] As can be seen from the above, the first gate 424 is composed of two separate gate structures, which can reduce the contact area between the gate 422 and the drain 440, thereby reducing the gate-drain capacitance of the trench MOSFET device and further improving the switching characteristics of the trench MOSFET device.

[0098] Optionally, in one embodiment of the present application, the gate 422 is a fin-shaped gate, but the present application does not limit this. In other embodiments of the present application, the gate 422 may also be a rectangular gate, etc., depending on the specific circumstances.

[0099] The present application also provides a method for preparing a trench MOSFET device, which is used to prepare the trench MOSFET device described in any of the above embodiments. Figure 14 As shown, the preparation method comprises:

[0100] S1: Provide a substrate 100. The substrate 100 may be a wide bandgap substrate, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), aluminum nitride (AlN), or the like. Accordingly, the trench MOSFET device described herein may be a wide bandgap trench MOSFET device.

[0101] S2 : forming an epitaxial layer 200 on the substrate 100 , specifically growing an N-type epitaxial layer 200 on the upper surface of the substrate 100 .

[0102] S3: A well region layer 300 is formed on the side of the epitaxial layer 200 facing away from the substrate 100. The doping concentration of the well region layer 300 decreases as it moves away from the epitaxial layer 200. That is, the doping concentration of the well region layer 300 decreases in the direction from the epitaxial layer 200 toward the well region layer 300. The well region layer 300 may be a P-type doped well region. It should be noted that the well region layer 300 may be formed by ion implantation or secondary epitaxial growth, depending on the specific circumstances.

[0103] S4: forming at least one MOSFET structure 400, the MOSFET structure 400 including a source region 410, a trench gate 420, a source 430, and a drain 440. The trench gate 420 includes a trench 421 located on the side of the well region layer 300 away from the epitaxial layer 200, a gate 422 located in the trench 421, and an interlayer dielectric layer 426 filling the trench 421 and covering the gate 422, and a gate dielectric layer 423 is further filled between the gate 422 and the trench 421, that is, the trench gate 420 is located in the well region layer 300 and is wrapped by the well region layer 300, and then the trench corner of the trench gate 420 can be wrapped by the well region layer 300. The source region 410 is located on the side of the well layer 300 facing away from the epitaxial layer 200, surrounds the trench 421, and contacts the outer sidewalls of the trench 421. The source region 410 may be composed of a first source region 411 and a second source region 412 having different doping types. For example, the first source region 411 is an N-type doped source region that contacts the outer sidewalls of the trench 421, and the second source region 412 is a P-type doped source region. The source electrode 430 is located on the side of the source region 410 facing away from the epitaxial layer 200. Specifically, the source electrode 430 contacts the first source region 411 and also contacts the second source region 412. The drain electrode 440 is located on the side of the substrate 100 facing away from the epitaxial layer 200, that is, the drain electrode 440 is located on the lower surface of the substrate 100, with the lower surface of the substrate 100 facing the upper surface.

[0104] The MOSFET structure 400 further includes a first carrier channel 1, which is located between the trench gate 420 and the epitaxial layer 200. Specifically, one end of the first carrier channel 1 is connected to the trench 421, and the other end is connected to the epitaxial layer 200. When the MOSFET device is in operation, current flows through the first carrier channel 1.

[0105] From the above, it can be seen that for the trench MOSFET device prepared by the preparation method provided in the present application, its trench gate 420 is located in the well region layer 300, so that the trench corner of the trench gate 420 can be wrapped by the well region layer 300, thereby effectively realizing electric field shielding at the trench gate 420 through the well region layer 300, especially for the electric field shielding at the trench corner of the trench 421, which helps to suppress the problem of rapid breakdown of the gate dielectric layer 423 of the trench gate 420 under high drain voltage, thereby ensuring the reliability of the trench MOSFET device.

[0106] It should be noted that when the well region layer 300 is used to achieve electric field shielding for the trench gate 420, the doping concentration of the well region layer 300 has a significant impact on the effect of the electric field shielding. A low doping concentration cannot form a good shielding effect, while an excessively high doping concentration will affect the device's conduction characteristics, resulting in a significant degradation of the device's conduction characteristics. To this end, the doping concentration of the well region layer 300 decreases in the direction away from the epitaxial layer 200. The high doping concentration region in the well region layer 300 can form a good shielding effect, while the low doping concentration region can ensure the device's conduction characteristics. Subsequently, the well region layer 300 can form a good shielding effect while not affecting the device's conduction characteristics, effectively solving the problem of the trench gate 420's gate dielectric layer 423 being rapidly broken down under high drain voltages, thereby ensuring the reliability of the trench MOSFET device.

[0107] Based on the foregoing embodiment, in one embodiment of the present application, in step S3, forming a well region layer 300 on a side of the epitaxial layer 200 facing away from the substrate 100 includes:

[0108] A first well region 310 and a second well region 320 arranged along a first direction are formed on a side of the epitaxial layer 200 facing away from the substrate 100 . The first direction is from the epitaxial layer 200 to the well region layer 300 .

[0109] The doping concentration of the second well region 320 is lower than the doping concentration of the first well region 310, and the groove 421 is located in the second well region 320, so that the area with low doping concentration in the well region layer 300 ensures the conduction characteristics of the device, and the area with high doping concentration forms a good shielding effect, so that the well region layer 300 can form a good shielding effect while not affecting the conduction characteristics of the device.

[0110] Based on the above embodiments, in one embodiment of the present application, the preparation method further includes:

[0111] S5 : forming a first diode structure 500 . In at least one MOSFET structure 400 , there is a first diode structure 500 between two adjacent MOSFET structures 400 . The first diode structure 500 includes a carrier shielding layer 510 and a second carrier channel 2 .

[0112] Specifically, the second carrier channel 2 of the first diode structure 500 is located in the well region layer 300 and penetrates the first well region 310 and the second well region 320. That is, the second carrier channel 2 penetrates the well region layer 300, and its upper and lower ends are respectively exposed on the upper and lower surfaces of the well region layer 300. The source region 410 surrounds the second carrier channel 2, that is, the source region 410 surrounds the end of the second carrier channel 2 exposed on the upper surface of the well region layer 300, and the second carrier channel 2 surrounds the carrier shielding layer 510. Specifically, the carrier shielding layer 510 extends into the second well region 320 and is exposed on the side of the second well region 320 facing away from the epitaxial layer 200. That is, the carrier shielding layer 510 extends into the second well region 320, and the side of the carrier shielding layer 510 facing away from the epitaxial layer 200 is flush with the side of the second carrier channel 2 facing away from the epitaxial layer 200.

[0113] As can be seen from the above, there is a first diode structure 500 between two adjacent MOSFET structures 400 in the at least one MOSFET structure 400, and the first diode structure 500 can form a high-speed freewheeling diode controlled by a PN junction. Since the high-speed freewheeling diode is a unipolar device, there is no minority carrier storage effect, and the reverse recovery time is short, thereby reducing the switching loss of the trench MOSFET device. Specifically, when the high-speed freewheeling diode formed by the first diode structure 500 is in a reverse withstand voltage state, the second carrier channel 2 will be pinched off by the surrounding source region 410, the carrier shielding layer 510 and the depletion region of the well layer 300. At this time, the high-speed freewheeling diode is in a closed state, thereby effectively avoiding the degradation problem of the withstand voltage blocking characteristics of the MOSFET device, thereby reducing the switching loss of the trench MOSFET device.

[0114] Furthermore, the first diode structure 500 includes a carrier-shielding layer 510. In the well layer 300, the second carrier channel 2 surrounds the carrier-shielding layer 510. In other words, the carrier-shielding layer 510 is embedded in the second carrier channel 2. As the name implies, the carrier-shielding layer 510 is a film layer that blocks carriers. Therefore, the presence of the carrier-shielding layer 510 can narrow the second carrier channel 2, thereby pinching off the second carrier channel 2 during reverse withstand voltage.

[0115] Based on the above embodiments, in one embodiment of the present application, the preparation method further includes:

[0116] S6 : forming a second diode structure 600 , wherein a first diode structure 500 is provided between two adjacent MOSFET structures 400 in at least one MOSFET structure 400 , and the first diode structure 500 includes a carrier shielding layer 610 and a second carrier channel 2 .

[0117] Specifically, the carrier shielding layer 610 of the second diode structure 600 extends into the second well region 320 and is exposed on the side of the second well region 320 facing away from the epitaxial layer 200. That is, the carrier shielding layer 610 extends from the upper surface of the well region layer 300 into the second well region 320. The carrier shielding layer 610 includes a plurality of sub-shielding layers 611 arranged along a second direction, with first gaps between the plurality of sub-shielding layers 611. The second direction is parallel to the plane of the well region layer 300.

[0118] The second carrier channel 2 of the second diode structure 600 penetrates the well region layer 300, surrounds the portion of the carrier shielding layer 610 located within the second well region 320, and further fills the first gaps between the plurality of sub-shielding layers 611. The source region 410 surrounds the side of the second carrier channel 2 facing away from the epitaxial layer and the side of the carrier shielding layer 610 facing away from the epitaxial layer 200. That is, the source region 410 surrounds the second carrier channel 2 and the portion of the carrier shielding layer 610 located on the upper surface of the well region layer 300. In other words, the second carrier channel 2 located on the upper surface of the well region layer 300 is surrounded by and in contact with the source region 410, and the carrier shielding layer 610 located on the upper surface of the well region layer 300 is surrounded by and in contact with the source region 410.

[0119] Compared with the above embodiment, in this embodiment, the portion of the second carrier channel 2 of the second diode structure 600 located in the well region layer 300 surrounds the portion of the carrier shielding layer 610 located in the second well region 320, and the second carrier channel 2 located on the upper surface of the well region layer 300 corresponds to the first gap between the multiple sub-shielding layers 611, that is, the carrier shielding layer 610 is wider, so that the second carrier channel 2 of the second diode structure 600 can be narrower, so as to further ensure that the second carrier channel 2 can be pinched off during reverse withstand voltage.

[0120] In order to more clearly understand the preparation method of a trench MOSFET device provided in the present application, the preparation method is described in detail below through specific examples.

[0121] Example 1: Figure 15As shown, 1. Provide a substrate 100, and grow an N-type epitaxial layer 200 on the substrate 100. 2. Form a well region layer 300 by secondary epitaxial growth, wherein the well region layer 300 includes a first well region 310 and a second well region 320. 3. Form a source region 410 by ion implantation, wherein the source region 410 includes a first source region 411 and a second source region 412. 4. Then, form a third channel region 213 of the second carrier channel 2 by ion implantation. 5. Based on step 4, narrow the ion implantation window, and form a second channel region 212 of the second carrier channel 2 by ion implantation. 6. Based on step 5, the ion implantation window is further narrowed, and the first channel region 211 of the second carrier channel 2 is formed by ion implantation. 7. A trench 421 is formed by dry etching. 8. The first carrier channel 510 is formed by ion implantation. 9. A gate dielectric layer 423 and a gate 422 are sequentially grown in the trench 421. 10. A fin-shaped gate is formed by etching back. 11. A dielectric layer is formed on the surface of the structure formed in step 10, and a source electrode 430 and a drain electrode 440 are formed.

[0122] Example 2: Figure 16 As shown, 1. Provide a substrate 100, and grow an N-type epitaxial layer 200 on the substrate 100. 2. Form a well region layer 300 by secondary epitaxial growth, and the well region layer 300 includes a first well region 310 and a second well region 320. 3. Form a source region 410 by ion implantation, and the source region 410 includes a first source region 411 and a second source region 412. 4. Then form a third channel region 213 of the second carrier channel 2 by ion implantation, and form a third shielding region 6123 of the carrier shielding layer 610 by ion implantation. 5. Based on step 4, narrow the ion implantation window, and form a second carrier by ion implantation. 6. Based on step 5, the ion implantation window is further narrowed, and the first channel region 211 of the second carrier channel 2 and the first shielding region 6121 of the carrier shielding layer 610 are formed by ion implantation. 7. A trench 421 is formed by dry etching. 8. A first carrier channel 510 is formed by ion implantation. 9. A gate dielectric layer 423 and a gate 422 are sequentially grown in the trench 421. 10. A fin-shaped gate is formed by etching back. 11. A dielectric layer is formed on the surface of the structure formed in step 10, and a source 430 and a drain 440 are formed.

[0123] In summary, the present application provides a trench MOSFET device and a preparation method thereof, wherein the MOSFET device comprises: a substrate, an epitaxial layer, a well region layer and at least one MOSFET structure, wherein the doping concentration of the well region layer decreases in the direction away from the epitaxial layer, and the MOSFET structure comprises a source region, a trench gate, a source electrode, a drain electrode and a first carrier channel. The trench gate comprises a trench located on the side of the well region layer away from the epitaxial layer, and a gate electrode located in the trench, and a gate dielectric layer is filled between the gate electrode and the trench. It can be seen that for the MOSFET device, its trench gate is located in the well region layer, so that the groove corner of the trench gate can be wrapped by the well region layer, thereby effectively achieving electric field shielding at the trench gate through the well region layer, especially for the electric field shielding at the groove corner of the trench, which helps to suppress the problem of rapid breakdown of the gate dielectric layer of the trench gate under high drain voltage, thereby ensuring the reliability of the trench MOSFET device. In addition, the doping concentration of the well layer decreases in the direction away from the epitaxial layer. The area with high doping concentration in the well layer can form a good shielding effect, and the area with low doping concentration can ensure the conduction characteristics of the device. Then, the well layer can form a good shielding effect while not affecting the conduction characteristics of the device, effectively solving the problem of rapid breakdown of the gate dielectric layer of the trench gate under high drain voltage, thereby ensuring the reliability of the trench MOSFET device.

[0124] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and reference can be made to the descriptions of the embodiments for similar or identical areas. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple. For relevant details, refer to the descriptions of the methods.

[0125] It should be noted that in the description of this application, it should be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a centrally located component.

[0126] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0127] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A trench MOSFET device, characterized in that: include: substrate; an epitaxial layer, the epitaxial layer being located on the surface of the substrate; a well region layer, the well region layer being located on a side of the epitaxial layer away from the substrate, and the doping concentration of the well region layer decreasing in a direction away from the epitaxial layer; At least one MOSFET structure, the MOSFET structure comprising a source region, a trench gate, a source electrode, and a drain, the trench gate comprising a trench located on a side of the well region layer facing away from the epitaxial layer, a gate electrode located within the trench, and an interlayer dielectric layer filling the trench and covering the gate, with a gate dielectric layer further filling between the gate and the trench; the source region being located on a side of the well region layer facing away from the epitaxial layer and surrounding the trench, the source electrode being located on a side of the source region facing away from the epitaxial layer, and the drain being located on a side of the substrate facing away from the epitaxial layer; The MOSFET structure further includes a first carrier channel, the first carrier channel being located between the trench gate and the epitaxial layer, and one end of the first carrier channel being connected to the trench and the other end being connected to the epitaxial layer; The well region layer includes a first well region and a second well region arranged along a first direction, the first direction is from the epitaxial layer to the well region layer, the doping concentration of the second well region is less than the doping concentration of the first well region, and the trench is located in the second well region.

2. The trench MOSFET device according to claim 1, wherein: Also includes: A first diode structure, wherein a first diode structure is provided between two adjacent MOSFET structures in the at least one MOSFET structure, and the first diode structure includes a carrier shielding layer and a second carrier channel; The second carrier channel runs through the well region layer, the source region surrounds the second carrier channel, and the second carrier channel surrounds the carrier shielding layer; the carrier shielding layer extends into the second well region and is exposed on a side of the second well region facing away from the epitaxial layer, and the side of the carrier shielding layer facing away from the epitaxial layer is flush with a side of the second carrier channel facing away from the epitaxial layer.

3. The trench MOSFET device according to claim 2, wherein: The carrier shielding layer extends along a second direction, the second direction is parallel to the plane where the well region layer is located, and the second carrier channel surrounds the carrier shielding layer.

4. The trench MOSFET device according to claim 2, wherein the carrier shielding layer comprises a plurality of sub-shielding layers arranged along a second direction, and the second direction is parallel to a plane where the well region layer is located; There are first gaps between the plurality of sub-shielding layers, and the second carrier channel surrounds the carrier shielding layer and fills the first gaps between the plurality of sub-shielding layers.

5. The trench MOSFET device according to claim 1, wherein: Also includes: A second diode structure, wherein a second diode structure is provided between two adjacent MOSFET structures in the at least one MOSFET structure, and the second diode structure includes a carrier shielding layer and a second carrier channel; The carrier shielding layer extends into the second well region and is exposed on a side of the second well region facing away from the epitaxial layer; the carrier shielding layer includes a plurality of sub-shielding layers arranged along a second direction, with first gaps between the plurality of sub-shielding layers, and the second direction is parallel to the plane where the well region layer is located; The second carrier channel runs through the well region layer, and the second carrier channel surrounds the portion of the carrier shielding layer located in the second well region, and the second carrier channel also fills the first gap between the multiple sub-shielding layers, and the source region surrounds the side of the second carrier channel facing away from the epitaxial layer and the side of the carrier shielding layer facing away from the epitaxial layer.

6. The trench MOSFET device according to claim 2 or 5, characterized in that: The second carrier channel includes a plurality of channel regions arranged along the first direction, and the diameters of the plurality of channel regions gradually increase along the first direction; The carrier shielding layer includes a plurality of shielding regions arranged along the first direction, and diameters of the plurality of shielding regions gradually increase along the first direction.

7. The trench MOSFET device according to claim 6, wherein: The multiple channel regions include a first channel region, a second channel region, and a third channel region arranged along the first direction; the first channel region is located in the first well region, and the first channel region is exposed on a side of the first well region facing the epitaxial layer; the second channel region is located in the second well region, covering the first channel region; the third channel region extends in the second well region, covering the second channel region, and is exposed on a side of the second well region facing away from the epitaxial layer; The diameter of the first channel region is smaller than that of the second channel region, and the diameter of the second channel region is smaller than that of the third channel region.

8. The trench MOSFET device according to claim 1, wherein: The gate includes a first gate and a second gate; The first gate includes a first sub-gate and a second sub-gate, the first sub-gate covers the sidewall of the trench, the second sub-gate covers the sidewall of the trench, and a second gap is formed between the first sub-gate and the second sub-gate, the second gap exposes the bottom of the trench, and the interlayer dielectric layer covers the first gate and fills the second gap; The second gate covers the sidewall and bottom of the trench, is connected to the second gate of the adjacent MOSFET structure, and the interlayer dielectric layer covers the second gate. The trench MOSFET device according to claim 8 , wherein the gate is a fin-shaped gate.

10. A method for preparing a trench MOSFET device, characterized in that: include: providing a substrate; forming an epitaxial layer on the substrate; forming a well region layer on a side of the epitaxial layer away from the substrate, wherein the doping concentration of the well region layer decreases in a direction away from the epitaxial layer; forming at least one MOSFET structure, the MOSFET structure comprising a source region, a trench gate, a source electrode, and a drain, the trench gate comprising a trench located on a side of the well region layer facing away from the epitaxial layer, a gate electrode located within the trench, and an interlayer dielectric layer filling the trench and covering the gate, with a gate dielectric layer further filled between the gate and the trench; the source region being located on a side of the well region layer facing away from the epitaxial layer and surrounding the trench, the source electrode being located on a side of the source region facing away from the epitaxial layer, and the drain being located on a side of the substrate facing away from the epitaxial layer; The MOSFET structure further includes a first carrier channel, the first carrier channel being located between the trench gate and the epitaxial layer, and one end of the first carrier channel being connected to the trench and the other end being connected to the epitaxial layer; The forming of a well region layer on a side of the epitaxial layer facing away from the substrate comprises: forming a first well region and a second well region arranged along a first direction on a side of the epitaxial layer away from the substrate, wherein the first direction is from the epitaxial layer to the well region layer; The doping concentration of the second well region is lower than the doping concentration of the first well region, and the trench is located in the second well region.

11. The method for preparing a trench MOSFET device according to claim 10, wherein: The preparation method further comprises: forming a first diode structure, wherein a first diode structure is provided between two adjacent MOSFET structures in the at least one MOSFET structure, and the first diode structure includes a carrier shielding layer and a second carrier channel; The second carrier channel runs through the well region layer, the source region surrounds the second carrier channel, and the second carrier channel surrounds the carrier shielding layer; the carrier shielding layer extends into the second well region and is exposed on a side of the second well region facing away from the epitaxial layer, and the side of the carrier shielding layer facing away from the epitaxial layer is flush with a side of the second carrier channel facing away from the epitaxial layer.

12. The method for preparing a trench MOSFET device according to claim 10, wherein: The preparation method further comprises: forming a second diode structure, wherein a second diode structure is provided between two adjacent MOSFET structures in the at least one MOSFET structure, and the second diode structure includes a carrier shielding layer and a second carrier channel; The carrier shielding layer extends into the second well region and is exposed on a side of the second well region facing away from the epitaxial layer; the carrier shielding layer includes a plurality of sub-shielding layers arranged along a second direction, with first gaps between the plurality of sub-shielding layers, and the second direction is parallel to the plane where the well region layer is located; The second carrier channel runs through the well region layer, and the second carrier channel surrounds the portion of the carrier shielding layer located in the second well region, and the second carrier channel also fills the first gap between the multiple sub-shielding layers, and the source region surrounds the side of the second carrier channel facing away from the epitaxial layer and the side of the carrier shielding layer facing away from the epitaxial layer.

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