A power device and a manufacturing method thereof

Abstract

This application discloses a power device comprising: a gallium oxide substrate; an N-type gallium oxide epitaxial layer located on the surface of the gallium oxide substrate; a gallium nitride epitaxial layer located on the side of the gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer comprises a stacked first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer. The gallium nitride epitaxial layer comprises a trench extending into the first N-type gallium nitride layer. The gallium nitride epitaxial layer comprises a first region and a second region parallel to the plane of the gallium oxide substrate, the first region being located between adjacent trenches and the second region being located at the bottom of the trench. Furthermore, a second N-type gallium nitride layer is located in the first region of the gallium nitride epitaxial layer and within the surface of the second P-type gallium nitride layer; and a third N-type gallium nitride layer is located in the second region of the gallium nitride epitaxial layer and within the surface of the first P-type gallium nitride layer. This power device combines the advantages of GaN and Ga2O3 materials, achieving superior performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power device and a manufacturing method thereof. Background Art

[0002] In recent years, the application of power devices has become increasingly widespread. From fast charging of mobile phones and new energy vehicles to photovoltaic power generation and high-voltage power grid transmission, they have gradually penetrated into all aspects of life, bringing great convenience to our daily lives. Therefore, power devices will play a vital role in improving people's quality of life in the future. However, the performance of existing power devices needs to be improved. Summary of the Invention

[0003] In view of the above problems, this application provides a power device and a method for manufacturing the same to achieve the purpose of improving performance. The specific solution is as follows:

[0004] A power device, comprising:

[0005] Gallium oxide substrate;

[0006] an N-type gallium oxide epitaxial layer located on a first side surface of the gallium oxide substrate;

[0007] a gallium nitride epitaxial layer located on a surface of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate, the gallium nitride epitaxial layer comprising a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked together, the gallium nitride epitaxial layer comprising a trench, the trench penetrating the second P-type gallium nitride layer and extending into the first N-type gallium nitride layer, the gallium nitride epitaxial layer comprising a first region and a second region parallel to the plane of the gallium oxide substrate, the first region being located between adjacent trenches, and the second region being located at the bottom of the trench;

[0008] a second N-type gallium nitride layer located in the first region of the gallium nitride epitaxial layer and within a surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer located in the second region of the gallium nitride epitaxial layer and within a surface of the first P-type gallium nitride layer, wherein, in a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer;

[0009] a gate dielectric layer and a gate electrode layer located in the trench and covering at least a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer;

[0010] a source electrode layer electrically connected to the second N-type gallium nitride layer, the source electrode layer being electrically insulated from the gate electrode layer;

[0011] A drain electrode layer is electrically connected to a side of the gallium oxide substrate away from the N-type gallium oxide epitaxial layer.

[0012] Optionally, the second N-type gallium nitride layer is not formed in a third region of the second P-type gallium nitride layer away from the N-type gallium oxide epitaxial layer, and the second P-type gallium nitride layer is also electrically connected to the source electrode layer.

[0013] Optionally, the first region includes a first sub-region and a second sub-region, and in a plane parallel to the plane where the gallium nitride epitaxial layer is located, the third region is located between the first sub-region and the second sub-region.

[0014] Optionally, the power device includes at least one column of trenches arranged along a first direction, where one column of trenches includes at least one trench, and the first direction is parallel to the plane where the gallium oxide substrate is located.

[0015] Optionally, a column of grooves includes one groove, the projection of the groove on the gallium oxide substrate is rectangular, and the extending direction is a second direction, the second direction is parallel to the plane of the gallium oxide substrate, and the first direction and the second direction are different.

[0016] Optionally, a third N-type gallium nitride layer is provided at a position of one of the trenches corresponding to the first P-type gallium nitride layer, an extension direction of the third N-type gallium nitride layer is the same as an extension direction of the trench, and a size of the third N-type gallium nitride layer along the extension direction is the same as a size of the trench along the extension direction;

[0017] Alternatively, a plurality of third N-type gallium nitride layers are provided at positions of a trench corresponding to the first P-type gallium nitride layer, an extension direction of the third N-type gallium nitride layer is the same as an extension direction of the trench, and a dimension of the third N-type gallium nitride layer along the extension direction is smaller than a dimension of the trench along the extension direction.

[0018] Optionally, when a plurality of third N-type gallium nitride layers are provided at positions of a trench corresponding to the first P-type gallium nitride layer, sizes of different third N-type gallium nitride layers along their extension directions are the same or different.

[0019] Optionally, a row of trenches includes a plurality of trenches arranged along a second direction, the second direction is parallel to a plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

[0020] Optionally, a projection shape of the groove on the gallium oxide substrate is a circle, a polygon or a rounded square.

[0021] A method for manufacturing a power device, comprising:

[0022] forming an N-type gallium oxide epitaxial layer on a gallium oxide substrate;

[0023] forming a gallium nitride epitaxial layer on a side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate, wherein the gallium nitride epitaxial layer includes a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked together;

[0024] A second N-type gallium nitride layer is formed in a first region of the gallium nitride epitaxial layer within a surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer is formed in a second region of the gallium nitride epitaxial layer within a surface of the first P-type gallium nitride layer. The gallium nitride epitaxial layer comprises a trench, which penetrates the second P-type gallium nitride layer and extends into the first N-type gallium nitride layer. The gallium nitride epitaxial layer comprises a first region and a second region parallel to the plane of the gallium oxide substrate, the first region being located between adjacent trenches, and the second region being located at the bottom of the trench. In a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer.

[0025] forming a gate dielectric layer and a gate electrode layer located in the trench and covering at least a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer;

[0026] forming a source electrode layer electrically connected to the second N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer;

[0027] A drain electrode layer is formed which is located on a side of the gallium oxide substrate away from the N-type gallium oxide epitaxial layer and is electrically connected to the gallium oxide substrate.

[0028] Optionally, a second N-type gallium nitride layer is formed in the first region of the gallium nitride epitaxial layer within the surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer is formed in the second region of the gallium nitride epitaxial layer within the surface of the first P-type gallium nitride layer. The gallium nitride epitaxial layer has a trench, which penetrates the second P-type gallium nitride layer and extends into the first N-type gallium nitride layer. The gallium nitride epitaxial layer includes a first region and a second region parallel to the plane of the gallium oxide substrate, the first region is located between adjacent trenches, and the second region is located at the bottom of the trench and includes:

[0029] doping a fourth region of the gallium nitride epitaxial layer to form a second N-type gallium nitride layer in a fourth region of the second P-type gallium nitride layer on a side of the surface away from the gallium oxide substrate, wherein the fourth region includes the first region;

[0030] Etching the fifth region of the gallium nitride epitaxial layer to form a trench in the gallium nitride epitaxial layer, the trench penetrating the second P-type gallium nitride layer and extending into the first N-type gallium nitride layer, the fifth region being different from the first region;

[0031] Doping a portion of the first P-type gallium nitride layer corresponding to the trench to form a third N-type gallium nitride layer within the surface of the second region of the first P-type gallium nitride layer, wherein a thickness of the third N-type gallium nitride layer is equal to a thickness of the first P-type gallium nitride layer in a direction perpendicular to a plane of the gallium oxide substrate.

[0032] Optionally, a fourth region of the gallium nitride epitaxial layer is doped to form a second N-type gallium nitride layer in a fourth region on a surface of the second P-type gallium nitride layer away from the gallium oxide substrate, where the fourth region includes the first region.

[0033] doping the fourth region of the first P-type gallium nitride layer in the gallium nitride epitaxial layer, retaining the third region of the first P-type gallium nitride layer in the gallium nitride epitaxial layer, and forming a second N-type gallium nitride layer in a first region within a surface of the first P-type gallium nitride layer on a side away from the gallium oxide substrate;

[0034] The third region of the first P-type gallium nitride layer is electrically connected to the source electrode layer.

[0035] The power device provided in an embodiment of the present application includes an N-type gallium oxide epitaxial layer located on a gallium oxide substrate and a gallium nitride epitaxial layer located on a side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer comprises a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked together, forming a PNP sandwich structure. This allows the N-type gallium oxide epitaxial layer and the gallium nitride epitaxial layer to form an epitaxial structure with a heterojunction (PN) junction, resolving the device construction issues associated with the lack of P-type doping in existing gallium oxide materials. High-voltage devices can be fabricated using conventional processes. Furthermore, the power device provided in an embodiment of the present application integrates a GaN and Ga2O3 material system, leveraging the advantages of Ga2O3's high critical electric field and low substrate cost, while also leveraging GaN's P-type properties and high thermal conductivity, resulting in high performance. Furthermore, compared to P-type materials such as NiO and Cu2O, gallium nitride (GaN) does not decompose in high-temperature environments and has superior heat dissipation capabilities. In addition, the lattice mismatch rate between GaN and Ga2O3 can be as low as 2.6%. Therefore, the N-type gallium oxide layer and the gallium nitride epitaxial layer form a better heterogeneous interface and have higher performance.

[0036] In addition, in the power device provided in the embodiment of the present application, the power device forms an epitaxial structure with a heterogeneous PN junction by the N-type gallium oxide epitaxial layer and the gallium nitride epitaxial layer. There are fewer electrons in the gallium nitride epitaxial layer. Therefore, when the voltage applied to the gate of the power device is 0V, there is no need to generate a depletion region by depleting electrons, thereby lowering the requirement for the size between adjacent trenches, so that the size between adjacent trenches can be achieved to about 1μm, significantly reducing the process requirements of the power device.

[0037] In addition, in the power device provided in the embodiment of the present application, the second P-type gallium nitride layer is used to control the threshold voltage of the power device, and the first P-type gallium nitride layer is used to control the directional breakdown electric field of the power device. The first N-type gallium nitride layer is arranged between the first P-type gallium nitride layer and the second P-type gallium nitride layer. This can decouple the threshold voltage and reverse breakdown voltage of the power device, reduce the connection between the two, and make the design of the power device more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

[0039] Figure 1 A schematic diagram of the structure of a current power device;

[0040] Figure 2 A schematic diagram of the structure of a power device provided in one embodiment of the present application;

[0041] Figure 3 A top view of a trench and a third N-type gallium nitride layer in a power device provided by one embodiment of the present application;

[0042] Figure 4 A top view of a trench and a third N-type gallium nitride layer in a power device provided by another embodiment of the present application;

[0043] Figure 5 A top view of a trench and a third N-type gallium nitride layer in a power device provided in yet another embodiment of the present application;

[0044] Figure 6 A top view of a trench and a third N-type gallium nitride layer in a power device provided in yet another embodiment of the present application;

[0045] Figure 7 A top view of a trench and a third N-type gallium nitride layer in a power device provided in yet another embodiment of the present application;

[0046] Figure 8 A top view of a trench and a third N-type gallium nitride layer in a power device provided in yet another embodiment of the present application;

[0047] Figure 9 A schematic structural diagram of a power device provided in another embodiment of the present application;

[0048] Figure 10 A schematic structural diagram of a power device provided in yet another embodiment of the present application;

[0049] Figure 11 A schematic structural diagram of a power device provided in yet another embodiment of the present application;

[0050] Figure 12 A schematic diagram of the energy bands of separated P-type GaN and N-type β-Ga2O3 in a power device provided in one embodiment of the present application;

[0051] Figure 13 In the power device provided in one embodiment of the present application, the energy band diagram of P-type GaN and N-type β-Ga2O3 in the thermal equilibrium state is shown as follows:

[0052] Figure 14 A schematic diagram of the energy band contact between N-type GaN and N-type Ga2O3 in a power device provided in one embodiment of the present application;

[0053] Figures 15-31 A schematic diagram of some structures involved in a method for manufacturing a power device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0055] It will be apparent to those skilled in the art that various modifications and variations can be made to this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the embodiments provided in the examples of this application may be combined with each other unless there is any inconsistency.

[0056] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0057] As described in the background technology section, the performance of existing power devices needs to be improved.

[0058] It's important to note that in power device applications, the Baliga figure-of-merit (BFOM) is an indicator used to indicate the suitability of semiconductor materials for power electronics. It's expressed as: BFOM = εμE³, where ε is the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor. The BFOM value is roughly positively correlated with the sixth power of the bandgap width, Eg. Therefore, a larger bandgap width means that wide-bandgap semiconductors have lower power loss and higher conversion efficiency in power device applications, thus enabling more excellent and ideal power electronics applications.

[0059] Among wide-bandgap semiconductor materials, Ga2O3 boasts a bandgap of 4.8eV, an ideal breakdown electric field strength of 8MV / cm, and a high BFOM value of 30,700, approximately four times that of GaN and ten times that of SiC. Therefore, in today's power electronics applications, which demand higher power density and lower power consumption, Ga2O3 materials hold significant research significance and offer a broad market application prospect.

[0060] However, there are currently no reports of successful p-type doping in Ga2O3, which limits the variety of Ga2O3 devices available compared to silicon and SiC materials. Regarding the active region of gallium oxide power devices, enhancement-mode or high-voltage devices can only be fabricated by using a narrow fin structure to deplete carriers in the conductive channel.

[0061] In order to prepare enhancement-mode and high-voltage-resistant gallium oxide FET (Field Effect Transistor) devices, a multi-fin structure can be used. This structure can enable the mobile carriers in the channel between the two fins of the gallium oxide FET device to deplete each other, thereby generating a high-resistance region. When the voltage applied to the gate of the gallium oxide FET device is 0V, the gallium oxide FET device can be normally turned off. In addition, the field plate structure formed by the multi-fin in the gallium oxide FET device can withstand the reverse electric field and reduce the surface leakage current, thereby forming an enhancement-mode and high-voltage-resistant gallium oxide FET device.

[0062] However, the above solution has the following technical problems:

[0063] First, the spacing between two adjacent trenches needs to be around 0.35μm (i.e., the width of the fin needs to be around 0.35μm). This is because there is a work function difference between the metal deposited on the sidewalls of the two trenches and the gallium oxide. When the voltage applied to the gate is 0V, this power function difference depletes the conductive channel with a smaller spacing, creating a channel depletion region, thereby realizing the fabrication of an enhancement-mode device. However, the fabrication of such a small conductive channel requires a specific photoresist and lithography machine, which increases the cost of the entire device and the process difficulty.

[0064] Second, under the reverse bias state, the electric field is mainly concentrated on the side walls and bottom corners of the gate dielectric, causing the gate dielectric deposited at the bottom of the trench to be subjected to a larger electric field. Since the gate dielectric is usually thin, a large tunneling current may appear in the gate dielectric, increasing device leakage and affecting the long-term working stability of the device. In severe cases, the gate dielectric may be broken down and burned, resulting in a high failure rate of the device or even burning the device.

[0065] In view of this, an embodiment of the present application provides a power device and a manufacturing method thereof to reduce the process requirements and failure rate of the power device during application and improve performance. Optionally, the power device includes at least one field effect transistor.

[0066] like Figure 2 As shown, the power device provided in the embodiment of the present application includes:

[0067] Gallium oxide substrate 10;

[0068] an N-type gallium oxide epitaxial layer 20 located on a first side surface of the gallium oxide substrate 10;

[0069] a gallium nitride epitaxial layer 30 located on a surface of the N-type gallium oxide epitaxial layer 20 away from the gallium oxide substrate 10, the gallium nitride epitaxial layer 30 comprising a stacked first p-type gallium nitride layer 301, a first n-type gallium nitride layer 302, and a second p-type gallium nitride layer 303; a trench being defined in the gallium nitride epitaxial layer 300, the trench penetrating the second p-type gallium nitride layer 303 and extending into the first n-type gallium nitride layer 302; and a first region and a second region parallel to the plane of the gallium oxide substrate 10, the first region being located between adjacent trenches, and the second region being located at the bottom of the trenches;

[0070] a second N-type gallium nitride layer 304 located in the first region of the gallium nitride epitaxial layer 30 and on the surface of the second P-type gallium nitride layer 303, and a third N-type gallium nitride layer 305 located in the second region of the gallium nitride epitaxial layer 30 and on the surface of the first P-type gallium nitride layer 301; wherein, in a direction perpendicular to the plane of the gallium oxide substrate 10, the thickness of the second N-type gallium nitride layer 304 is less than the thickness of the second P-type gallium nitride layer 303, and the thickness of the third N-type gallium nitride layer 305 is equal to the thickness of the first P-type gallium nitride layer 301;

[0071] a gate dielectric layer 40 and a gate electrode layer 50 located in the trench and covering at least a portion of the second N-type gallium nitride layer 304 , wherein the gate dielectric layer 40 is located between the gate electrode layer 50 and the second N-type gallium nitride layer 304 ;

[0072] a source electrode layer 80 electrically connected to the second N-type gallium nitride layer 304 , wherein the source electrode layer 80 is electrically insulated from the gate electrode layer 50 ;

[0073] A drain electrode layer 90 is electrically connected to a side of the gallium oxide substrate 10 away from the N-type gallium oxide epitaxial layer 20 .

[0074] It should be noted that, in one embodiment of the present application, the power device includes at least one repeating unit A, and one repeating unit may correspond to one field effect transistor. The present application does not impose any limitation on this, and the specific situation may vary.

[0075] Specifically, in one embodiment of the present application, the gate dielectric layer covers at least the bottom and sidewalls of the trench. Optionally, the gate dielectric layer extends to cover a portion of the surface area of ​​the second N-type gallium nitride layer on a side away from the gallium oxide substrate. The gate electrode layer fills the trench. Optionally, the gate electrode layer also extends to cover a portion of the surface area of ​​the second N-type gallium nitride layer on a side away from the gallium oxide substrate. However, this application does not impose any limitation on this, and the specific situation depends on the circumstances.

[0076] The power device provided in an embodiment of the present application includes an N-type gallium oxide epitaxial layer located on a gallium oxide substrate and a gallium nitride epitaxial layer located on a side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer comprises a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked together, forming a PNP sandwich structure. This allows the N-type gallium oxide epitaxial layer and the gallium nitride epitaxial layer to form an epitaxial structure with a heterojunction (PN) junction, resolving the device construction issues associated with the lack of P-type doping in existing gallium oxide materials. High-voltage devices can be fabricated using conventional processes. Furthermore, the power device provided in an embodiment of the present application integrates a GaN and Ga2O3 material system, leveraging the advantages of Ga2O3's high critical electric field and low substrate cost, while also leveraging GaN's P-type properties and high thermal conductivity, resulting in high performance. Furthermore, compared to P-type materials such as NiO and Cu2O, gallium nitride (GaN) does not decompose in high-temperature environments and has superior heat dissipation capabilities. In addition, the lattice mismatch rate between GaN and Ga2O3 can be as low as 2.6%. Therefore, the N-type gallium oxide layer and the gallium nitride epitaxial layer form a better heterogeneous interface and have higher performance.

[0077] In addition, in the power device provided in the embodiment of the present application, the power device forms an epitaxial structure with a heterogeneous PN junction by the N-type gallium oxide epitaxial layer and the gallium nitride epitaxial layer. There are fewer electrons in the gallium nitride epitaxial layer. Therefore, when the voltage applied to the gate of the power device is 0V, there is no need to generate a depletion region by depleting electrons, thereby lowering the requirement for the size between adjacent trenches, so that the size between adjacent trenches can be achieved to about 1μm, significantly reducing the process requirements of the power device.

[0078] Furthermore, in the power device provided in the embodiment of the present application, the second P-type gallium nitride layer is used to control the threshold voltage of the power device, and the first P-type gallium nitride layer is used to control the directional breakdown electric field of the power device. Providing the first N-type gallium nitride layer between the first P-type gallium nitride layer and the second P-type gallium nitride layer can decouple the threshold voltage and reverse breakdown voltage of the power device, reducing the connection between the two and making the design of the power device more flexible. Furthermore, the power device provided in the embodiment of the present application can also achieve a deep masking effect of the power device by controlling the thickness of the first P-type gallium nitride layer, thereby reducing leakage current of the power device and achieving higher device reliability.

[0079] It should be noted that in this embodiment, the gallium oxide substrate is also N-type doped, but due to the growth process of the gallium oxide substrate, the doping concentration in the gallium oxide substrate is relatively high. If a subsequent gallium nitride epitaxial layer is formed directly on the gallium oxide substrate, the voltage resistance of the power device will be poor. Therefore, in the power device provided in the embodiment of the present application, a low-concentration N-type doped gallium oxide layer is formed on the gallium oxide substrate, and the gallium nitride epitaxial layer is formed on the surface of the N-type gallium oxide layer to improve the voltage resistance performance of the power device.

[0080] Optionally, in one embodiment of the present application, the doping concentration of the N-type gallium oxide epitaxial layer is 2E16cm -3 The thickness of the N-type gallium oxide epitaxial layer is in the range of 5 μm to 10 μm; the concentration of the first P-type gallium nitride layer is in the range of 1E18 cm -3 ~2E19 cm -3 , the thickness range is 0.3μm~1μm; the concentration of the first N-type gallium nitride layer is 1E18 cm -3 ~2E19 cm -3 , with a thickness of 0.3 μm to 1 μm; the concentration of the second P-type gallium nitride layer is in the range of 1E16 cm -3 ~2E17cm -3 The thickness range is 0.3um to 0.5μm. However, this application does not limit this, and the specific situation depends on the circumstances.

[0081] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 As shown, the second N-type gallium nitride layer 304 is not formed in the third region of the second P-type gallium nitride layer 303 on the side away from the N-type gallium oxide epitaxial layer 20. The second P-type gallium nitride layer 303 is also electrically connected to the source electrode layer 80, so that when a reverse voltage is applied to the power device, its electric field is concentrated on the contact surface of the gallium nitride epitaxial layer 30 and the N-type gallium oxide epitaxial layer 20, thereby reducing the electric field strength at the gate dielectric layer, reducing the risk of the gate dielectric layer being broken down or burned, thereby reducing the risk of failure of the power device and improving the stability of the power device.

[0082] Moreover, the second P-type gallium nitride layer 303 is also electrically connected to the source electrode layer 80 , which can further improve the stability of the threshold voltage of the power device and enhance the performance of the power device.

[0083] It should be noted that, in the above embodiment, the surface of the third region away from the gallium oxide substrate 10 may be flush with or not flush with the surface of the first region away from the gallium oxide substrate 10 . This application does not impose any limitation on this, and the specific situation may vary.

[0084] Optionally, in one embodiment of the present application, continue as Figure 2 As shown, the first region includes a first sub-region and a second sub-region, and the third region is located between the first sub-region and the second sub-region in a plane parallel to the plane of the gallium nitride epitaxial layer. However, this application is not limited to this. In other embodiments of this application, the first region and the third region may also be arranged side by side, such as the third region being located to one side of the first region, depending on the specific situation.

[0085] Based on any of the above embodiments, in one embodiment of the present application, the power device includes at least one column of trenches arranged along a first direction, and a column of trenches includes at least one trench, and the first direction is parallel to the plane of the gallium oxide substrate.

[0086] Based on the above embodiment, in one embodiment of the present application, a column of grooves includes a groove, the projection of the groove on the gallium oxide substrate is rectangular, and the extending direction is a second direction, the second direction is parallel to the plane of the gallium oxide substrate, and the first direction and the second direction are different.

[0087] Specifically, in one embodiment of the present application, Figure 2 and Figure 3 As shown, a third N-type GaN layer 305 is provided at a position corresponding to a trench 306 of the first P-type GaN layer 301. The extension direction of the third N-type GaN layer 305 is the same as that of the trench 306, and the dimension of the third N-type GaN layer 305 along the extension direction is the same as that of the trench 306 along the extension direction, so as to increase the on-current of the power device and enable the power device to have a lower on-resistance.

[0088] In another embodiment of the present application, Figure 2 and Figure 4 As shown, a plurality of third N-type GaN layers 305 are provided at positions corresponding to the first P-type GaN layer 301 in a trench 306. The extension direction of the third N-type GaN layer 305 is the same as that of the trench 306, and the dimension of the third N-type GaN layer 305 along the extension direction is smaller than the dimension of the trench 306 along the extension direction, thereby reducing the reverse leakage current of the power device. When a short circuit occurs in the power device, the power device has better regulation capability and greater robustness.

[0089] It should be noted that, in the above embodiment, Figure 2 and Figure 4As shown, when a plurality of third N-type GaN layers are disposed at positions of a trench 306 corresponding to the first P-type GaN layer 301 , the sizes of different third N-type GaN layers along their extension directions may be the same or different, depending on the specific circumstances.

[0090] It should also be noted that the larger the size of the third N-type gallium nitride layer along its extension direction, the smaller the on-resistance of the power device and the larger the on-current; the smaller the size of the third N-type gallium nitride layer along its extension direction, the smaller the reverse leakage current of the power device. This application does not impose any limitation on the size of the third N-type gallium nitride layer along its extension direction, and the specific size depends on the specific situation.

[0091] In other embodiments of the present application, Figure 2 and Figure 5 As shown, a third N-type gallium nitride layer may be provided at positions corresponding to the first P-type gallium nitride layer in some of the grooves, and multiple third N-type gallium nitride layers may be provided at positions corresponding to the first P-type gallium nitride layer in some of the grooves. This application does not limit this, and the specific situation depends on the circumstances.

[0092] In another embodiment of the present application, a column of trenches includes a plurality of trenches arranged along a second direction, the second direction is parallel to the plane of the gallium oxide substrate, and the first direction and the second direction are different; in this embodiment, a third N-type gallium nitride layer is disposed in one trench.

[0093] Optionally, in one embodiment of the present application, the projection shape of the groove 306 on the gallium oxide substrate may be circular, such as Figure 6 As shown, it can also be a polygon, such as a hexagon, as Figure 7 As shown, it can also be a rounded square, such as Figure 8 As shown, in other embodiments of the present application, the projection shape of the groove 306 on the gallium oxide substrate can also be other shapes, which is not limited in the present application and depends on the specific circumstances.

[0094] Based on any of the above embodiments, in one embodiment of the present application, a third N-type gallium nitride layer may be provided at a position of the trench corresponding to the first P-type gallium nitride layer, and the third N-type gallium nitride layer may be located in the middle region of the bottom of the trench in a plane parallel to the gallium oxide substrate. Figure 2 As shown, it can also be located in the non-middle area at the bottom of the groove, such as Figure 9 As shown; In another embodiment of the present application, at least two third N-type gallium nitride layers can be provided at a position of the trench corresponding to the first P-type gallium nitride layer, such as Figure 10As shown, optionally, in a plane parallel to the gallium oxide substrate, the at least two third N-type gallium nitride layers are evenly distributed at the bottom of the trench, but the present application does not limit this and it depends on the specific situation.

[0095] Based on any of the foregoing embodiments, in one embodiment of the present application, the power device further includes: a source ohmic contact layer 70 located between the source electrode layer 80 and the second N-type gallium nitride layer 304 , and a drain ohmic contact layer 91 located between the drain electrode layer 90 and the gallium oxide substrate 10 .

[0096] Based on any of the above embodiments, in one embodiment of the present application, the power device further includes a first insulating layer 60 located between the gate electrode layer 50 and the source electrode layer 80 to prevent the gate electrode layer 50 and the source electrode layer 80 from short-circuiting.

[0097] Based on any of the above embodiments, in one embodiment of the present application, continue as follows Figure 2 As shown, the power device further includes: a gate ohmic contact layer 110 electrically connected to the gate electrode layer 50, and a gate lead 120 electrically connected to the gate ohmic contact layer 110. Optionally, the source electrode layer 80 and the gate lead 120 are formed simultaneously; the source ohmic contact layer 70 and the gate ohmic contact layer 110 are formed simultaneously; however, this is not limited to this in the present application and may be determined based on specific circumstances.

[0098] Based on any of the above embodiments, in one embodiment of the present application, Figure 11 As shown, the power device also includes: a second insulating layer 100 covering the source electrode layer 80 to serve as a protective layer for the source electrode layer 80; at the same time, the second insulating layer 100 has an opening, and the opening of the second insulating layer 100 exposes a partial area of ​​the source electrode layer 80 to facilitate electrical connection of the source electrode layer 80 with the outside world, such as being electrically connected to the test terminal as a test lead-out terminal.

[0099] like Figure 12 and Figure 13 As shown, Figure 12 Shows the energy band diagram of separated GaN and N-type β-Ga2O3, Figure 13 The energy band diagram of P-type GaN and N-type β-Ga2O3 in thermal equilibrium is shown. The dotted line T represents the Fermi level, T1 is the Fermi level of P-type GaN, and T2 is the Fermi level of N-type β-Ga2O3; χ represents the electron affinity (the difference between the bottom of the conduction band and the vacuum energy level), such as the electron affinity (the difference between the bottom of the conduction band and the vacuum energy level) of P-type GaN is χ = 4.1eV; E gIndicates the bandgap width, that is, the width between the bottom of the conduction band and the top of the valence band, such as the bandgap width E of P-type GaN g =3.4 eV; E F -E V It represents the difference between the Fermi level and the valence band top of P-type GaN. The smaller the difference, the greater the P-type doping concentration. For example, the difference between the Fermi level and the valence band top of P-type GaN is E F -E V =0.12eV; △E F It represents the difference in Fermi levels between two semiconductors (P-type GaN and N-type β-Ga2O3). The larger the difference, the more severe the bending of the conduction band and valence band when the two are in contact, and the wider the depletion layer. V Indicates the valence band difference between P-type GaN and N-type β-Ga2O3; E C -E F It represents the difference between the Fermi level and the bottom of the conduction band of N-type Ga2O3. The smaller the difference, the greater the N-type doping concentration. d is the depletion width, where the depletion width d of P-type GaN is GaN =1.34μm, the depletion width d of N-type β-Ga2O3 Ga2O3 =0.60μm.

[0100] from Figure 13 It can be seen from FIG. 1 that, in the thermal equilibrium state, when the heterojunction is in the reverse bias state, the current of the heterojunction is generated by the conduction of minority carriers, so the leakage current is very small, and the reverse characteristic of the power device is good.

[0101] like Figure 14 As shown, Figure 14 Schematic diagram of the energy band contact between N-type GaN and N-type Ga2O3. Figure 14 It can be seen that the conduction band bottom △E of N-type GaN and N-type Ga2O3 C It is very close, with a barrier height of only 0.1eV. When forward biased, electrons can easily move from the N-type GaN side to the N-type Ga2O3 side, thereby achieving current conduction.

[0102] It can be seen that in the power device provided in the embodiment of the present application, the N-type GaN can provide an electron channel when the power device is forward biased, thereby achieving normal conduction of the device; at the same time, when reverse biased, the P-type GaN on both sides of the N-type GaN can play the role of shielding the electric field of the gate dielectric layer at the bottom of the trench, so that the power device can withstand a higher voltage.

[0103] In addition, the present invention also provides a method for manufacturing the power device provided in any of the above embodiments. Specifically, the method for manufacturing the power device provided in the present invention includes:

[0104] S1: If Figure 15 As shown, an N-type gallium oxide epitaxial layer 20 is formed on a gallium oxide substrate 10 .

[0105] Optionally, in one embodiment of the present application, forming an N-type gallium oxide epitaxial layer on the gallium oxide substrate includes: epitaxially growing the N-type gallium oxide epitaxial layer on the gallium oxide substrate using a HVPE (Hydride Vapor Phase Epitaxy) method.

[0106] It should be noted that in this embodiment, the gallium oxide substrate is also N-type doped, but due to the growth process of the gallium oxide substrate, the doping concentration in the gallium oxide substrate is relatively high. If a subsequent P-type gallium nitride layer is formed directly on the gallium oxide substrate, the voltage resistance of the power device will be poor. Therefore, the method for manufacturing a power device provided in the embodiment of the present application adopts an epitaxial process to epitaxially grow a low-concentration N-type doped gallium oxide layer on the gallium oxide substrate, and then performs subsequent process steps to improve the voltage resistance performance of the power device.

[0107] Specifically, in one embodiment of the present application, the doping concentration of the N-type gallium oxide epitaxial layer may be in the range of 1E16 cm -3 ~9E16cm -3 , optional 2E16cm -3 The thickness of the N-type gallium oxide epitaxial layer ranges from 3 μm to 15 μm, and can be optionally 5 μm to 10 μm, but this application does not limit this, and it depends on the specific situation.

[0108] S2: forming a gallium nitride epitaxial layer on a side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate, wherein the gallium nitride epitaxial layer includes a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked.

[0109] Optionally, in one embodiment of the present application, forming a gallium nitride epitaxial layer on a side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate includes:

[0110] like Figure 16As shown, a first P-type gallium nitride layer 301, a first N-type gallium nitride layer 302, and a second P-type gallium nitride layer 303 are sequentially formed on the side of the N-type gallium oxide epitaxial layer 20 away from the gallium oxide substrate 10 using an HVPE (Hydride Vapor Phase Epitaxy) process or an MOCVD (Metal-organic Chemical Vapor Deposition) process. It should be noted that in this embodiment, the second P-type gallium nitride layer is used to control the threshold voltage of the power device, and the first P-type gallium nitride layer is used to control the directional breakdown electric field of the power device. The provision of the first N-type gallium nitride layer between the first P-type gallium nitride layer and the second P-type gallium nitride layer can decouple the threshold voltage and reverse breakdown voltage of the power device, thereby reducing the correlation between the two.

[0111] Specifically, in one embodiment of the present application, the concentration of the first P-type gallium nitride layer is in the range of 1E18 cm -3 ~2E19 cm -3 , the thickness range is 0.3μm~1μm; the concentration of the first N-type gallium nitride layer is 1E18 cm -3 ~2E19 cm -3 , with a thickness of 0.3 μm to 1 μm; the concentration of the second P-type gallium nitride layer is in the range of 1E16 cm -3 ~2E17cm -3 The thickness range is 0.3 μm to 0.5 μm to ensure the normal operation of the power device and decouple the threshold voltage and reverse breakdown voltage of the power device, reducing the connection between the two. However, this application does not limit this and the specific situation depends on the specific situation.

[0112] S3: In the first region of the gallium nitride epitaxial layer, a second N-type gallium nitride layer is formed in the surface of the second P-type gallium nitride layer, and in the second region of the gallium nitride epitaxial layer, a third N-type gallium nitride layer is formed in the surface of the first P-type gallium nitride layer, the gallium nitride epitaxial layer has a groove, the groove penetrates the second P-type gallium nitride layer and extends into the first N-type gallium nitride layer, the gallium nitride epitaxial layer includes a first region and a second region parallel to the plane of the gallium oxide substrate, the first region is located between adjacent trenches, and the second region is located at the bottom of the trench, in a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer.

[0113] Optionally, in one embodiment of the present application, a second N-type gallium nitride layer is formed in the first region of the gallium nitride epitaxial layer within the surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer is formed in the second region of the gallium nitride epitaxial layer within the surface of the first P-type gallium nitride layer. The gallium nitride epitaxial layer has a trench, which penetrates the second P-type gallium nitride layer and extends into the first N-type gallium nitride layer. The gallium nitride epitaxial layer includes a first region and a second region parallel to the plane of the gallium oxide substrate, the first region is located between adjacent trenches, and the second region is located at the bottom of the trench. In a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer. The method includes:

[0114] S31: If Figure 17 As shown, the fourth region of the gallium nitride epitaxial layer 30 is doped to form a second N-type gallium nitride layer 304 in a surface of a fourth region of the gallium nitride epitaxial layer 30 on a side of the second P-type gallium nitride layer 303 away from the gallium oxide substrate 10, wherein the fourth region includes the first region.

[0115] Optionally, in one embodiment of the present application, doping the fourth region of the gallium nitride epitaxial layer to form a second N-type gallium nitride layer in a surface of the fourth region on a side of the second P-type gallium nitride layer away from the gallium oxide substrate includes:

[0116] Ion implantation is performed on a fourth region of the gallium nitride epitaxial layer away from the gallium oxide substrate to form a second N-type gallium nitride layer on a surface of the fourth region of the second P-type gallium nitride layer away from the gallium oxide substrate.

[0117] Specifically, in one embodiment of the present application, ion implantation is performed on a fourth region of the gallium nitride epitaxial layer away from the gallium oxide substrate to form a second N-type gallium nitride layer. The implanted element may be silicon, germanium, iron, carbon, vanadium, or the like. This application does not impose any limitation on this, and the specific implantation depends on the circumstances.

[0118] Optionally, in one embodiment of the present application, doping the fourth region of the gallium nitride epitaxial layer to form a second N-type gallium nitride layer in the fourth region on a surface of the second P-type gallium nitride layer away from the gallium oxide substrate includes:

[0119] forming a first dielectric layer on a surface of the gallium nitride epitaxial layer away from the gallium oxide substrate, wherein the first dielectric layer is optionally a silicon oxide layer;

[0120] forming a first photoresist layer on a surface of the first dielectric layer away from the gallium nitride epitaxial layer;

[0121] exposing and developing the first photoresist layer to form a first opening in the first photoresist layer;

[0122] Using the first photoresist layer as a mask, etching the first dielectric layer to expose a fourth region of the gallium nitride epitaxial layer, where the fourth region includes the first region;

[0123] removing the first photoresist layer;

[0124] Using the first dielectric layer as a mask, implanting silicon into the fourth region of the gallium nitride epitaxial layer, thereby forming a second N-type gallium nitride layer in the fourth region of the second P-type gallium nitride layer on a side away from the gallium oxide substrate;

[0125] The first dielectric layer is removed.

[0126] It should be noted that in this embodiment, the depth of the second N-type gallium nitride layer is less than the depth of the second P-type gallium nitride layer in a direction perpendicular to the plane of the gallium oxide substrate. The depth of the second N-type gallium nitride layer is its thickness in a direction perpendicular to the surface of the gallium oxide substrate; similarly, the depth of the second P-type gallium nitride layer is its thickness in a direction perpendicular to the surface of the gallium oxide substrate.

[0127] Optionally, in one embodiment of the present application, the fourth region of the gallium nitride epitaxial layer is doped, and a second N-type gallium nitride layer is formed in a fourth region of the surface of the second P-type gallium nitride layer on a side away from the gallium oxide substrate, and the fourth region includes the first region. The method includes: doping the first region of the second P-type gallium nitride layer, retaining the third region of the second P-type gallium nitride layer, and forming a second N-type gallium nitride layer in the first region of the surface of the second P-type gallium nitride layer on a side away from the gallium oxide substrate, so that the third region of the second P-type gallium nitride layer is subsequently electrically connected to the source electrode layer.

[0128] It should be noted that the third region of the second P-type gallium nitride layer is subsequently electrically connected to the source electrode layer. When a reverse voltage is applied to the power device, the electric field is concentrated at the interface between the gallium nitride epitaxial layer 30 and the N-type gallium oxide epitaxial layer 20, reducing the electric field strength at the gate dielectric layer and the risk of breakdown or burnout of the gate dielectric layer, thereby reducing the risk of power device failure and improving the stability of the power device. Furthermore, the second P-type gallium nitride layer is also electrically connected to the subsequently formed source electrode layer, which can also improve the stability of the threshold voltage of the power device and enhance its performance.

[0129] S32: Figure 18 As shown, the fifth region of the GaN epitaxial layer 30 is etched to form a trench 306 in the GaN epitaxial layer 30. The trench 306 penetrates the second P-type GaN layer 303 and extends into the first N-type GaN layer 302. The fifth region and the first region are distinct regions. It should be noted that the trench does not penetrate the first N-type GaN layer. That is, in a direction perpendicular to the plane of the gallium oxide substrate, the depth of the trench is greater than the depth of the second P-type GaN layer, but less than the sum of the depths of the second P-type GaN layer and the first N-type GaN layer.

[0130] Optionally, in one embodiment of the present application, the fourth region includes the first region and the fifth region, and etching the fifth region of the gallium nitride epitaxial layer to form a trench in the gallium nitride epitaxial layer includes:

[0131] The fourth region of the gallium nitride epitaxial layer is etched except for the first region, so as to form a trench in the gallium nitride epitaxial layer.

[0132] S33: Doping a portion of the first P-type gallium nitride layer corresponding to the groove to form a third N-type gallium nitride layer in the second region of the surface of the first P-type gallium nitride layer, wherein a thickness of the third N-type gallium nitride layer is equal to a thickness of the first P-type gallium nitride layer in a direction perpendicular to a plane of the gallium oxide substrate.

[0133] Optionally, in one embodiment of the present application, doping a portion of the first P-type gallium nitride layer corresponding to the trench to form a third N-type gallium nitride layer in the second region of the surface of the first P-type gallium nitride layer includes:

[0134] like Figure 19 As shown, a second photoresist layer 307 is formed on the surface of the second P-type gallium nitride layer 303 and the second N-type gallium nitride layer 304 away from the gallium oxide substrate 10 and the surface of the groove;

[0135] Etching the second photoresist layer 307 to form a second opening, wherein the second opening exposes the bottom of the trench;

[0136] like Figure 20As shown, ion implantation is performed into the first P-type gallium nitride layer 301 using the second photoresist layer 307 as a mask to form a third N-type gallium nitride layer 305 in the second region of the first P-type gallium nitride layer 301. It should be noted that in this embodiment, the ion implantation depth must penetrate the first P-type gallium nitride layer so that the thickness of the third N-type gallium nitride layer 305 is the same as that of the first P-type gallium nitride layer 301, that is, the third N-type gallium nitride layer 305 is in contact with the N-type gallium oxide epitaxial layer 20.

[0137] like Figure 21 As shown, a protective layer 308 is formed to cover the second photoresist layer 307 and the surface of the groove. Optionally, the protective layer 308 is a silicon nitride (Si3N4) layer. The thickness of the protective layer is about 300 nm. This application does not limit this, and the specific thickness depends on the circumstances.

[0138] Annealing the third N-type gallium nitride layer 305 to activate dopant ions in the third N-type gallium nitride layer 305. Optionally, annealing the third N-type gallium nitride layer 305 in an annealing furnace at an annealing temperature of 1200° C. for 5 minutes to activate dopant ions in the third N-type gallium nitride layer 305.

[0139] like Figure 22 As shown, the protective layer and the second photoresist layer are removed. Optionally, the protective layer is removed using a hot phosphoric acid solution, and the second photoresist layer is removed using a BOE solution, but this application does not limit this and it depends on the specific situation.

[0140] It should be noted that under high temperature conditions, atoms may migrate or detach from the crystal, leaving an uneven surface. In the embodiment of the present application, the purpose of forming a protective layer before annealing the third N-type gallium nitride layer is to use the protective layer to prevent atoms from detaching from the surface of the first N-type gallium nitride layer during the high-temperature activation process of the third N-type gallium nitride layer, thereby making the surface of the first N-type gallium nitride layer rough.

[0141] Optionally, in one embodiment of the present application, the second photoresist layer is a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, a carbon film layer, or other film layer that is easy to remove and not easily decomposed at high temperatures; the thickness of the second photoresist layer ranges from 1 μm to 5 μm, but the present application does not limit this, and it depends on the specific situation.

[0142] Optionally, in one embodiment of the present application, the power device includes at least one column of trenches arranged along a first direction, wherein a column of trenches includes at least one trench, and the first direction is parallel to the plane where the gallium oxide substrate is located.

[0143] Based on the above embodiment, in one embodiment of the present application, a column of grooves includes a groove, the projection of the groove on the gallium oxide substrate is rectangular, and the extending direction is a second direction, the second direction is parallel to the plane of the gallium oxide substrate, and the first direction and the second direction are different.

[0144] Specifically, in one embodiment of the present application, a third N-type gallium nitride layer is provided at a position corresponding to the first P-type gallium nitride layer in a trench, an extension direction of the third N-type gallium nitride layer is the same as an extension direction of the trench, and a dimension of the third N-type gallium nitride layer along its extension direction is the same as a dimension of the trench along its extension direction, so as to increase the on-current of the power device and enable the power device to have a smaller on-resistance.

[0145] In another embodiment of the present application, a plurality of third N-type gallium nitride layers are provided at positions of a trench corresponding to the first P-type gallium nitride layer. The extension direction of the third N-type gallium nitride layer is the same as the extension direction of the trench, and the dimension of the third N-type gallium nitride layer along the extension direction is smaller than the dimension of the trench along the extension direction, so as to reduce the reverse leakage current of the power device. When a short circuit occurs in the power device, the power device has better regulation capability and greater robustness.

[0146] It should be noted that, in the above embodiment, when a plurality of third N-type GaN layers are provided at positions corresponding to the first P-type GaN layer in a trench, the sizes of different third N-type GaN layers along their extension directions may be the same or different, depending on the specific circumstances.

[0147] It should also be noted that the larger the size of the third N-type gallium nitride layer along its extension direction, the smaller the on-resistance of the power device and the larger the on-current; the smaller the size of the third N-type gallium nitride layer along its extension direction, the smaller the reverse leakage current of the power device. This application does not impose any limitation on the size of the third N-type gallium nitride layer along its extension direction, and the specific size depends on the specific situation.

[0148] In other embodiments of the present application, a third N-type gallium nitride layer may be provided at positions of some grooves corresponding to the first P-type gallium nitride layer, and multiple third N-type gallium nitride layers may be provided at positions of some grooves corresponding to the first P-type gallium nitride layer. This application does not limit this and the specific situation depends on the situation.

[0149] In another embodiment of the present application, a column of grooves includes a plurality of grooves arranged along a second direction, the second direction is parallel to the plane of the gallium oxide substrate, and the first direction and the second direction are different; in this embodiment, a third N-type gallium nitride layer is provided at a position of a trench corresponding to the first P-type gallium nitride layer.

[0150] Optionally, in one embodiment of the present application, the projected shape of the groove on the gallium oxide substrate may be a circle, a polygon, such as a hexagon, or a rounded square. In other embodiments of the present application, the projected shape of the groove on the gallium oxide substrate may be other shapes, which is not limited in the present application and depends on the specific circumstances.

[0151] S4: forming a gate dielectric layer and a gate electrode layer located in the trench and covering at least a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer

[0152] Optionally, in one embodiment of the present application, forming a gate dielectric layer and a gate electrode layer located in the trench and covering at least a portion of the second N-type gallium nitride layer includes:

[0153] As shown in FIG23 , a gate dielectric layer 40 is formed to cover the second P-type gallium nitride layer 303 , the second N-type gallium nitride layer 304 and the surface of the trench. Optionally, the gate dielectric layer 40 is formed by an epitaxial process.

[0154] like Figure 24 As shown, a gate electrode layer 50 is formed on the surface of the gate dielectric layer 40 away from the third N-type gallium nitride layer 305, and the gate electrode layer 50 is etched using a self-aligned etching process, leaving the portion of the gate electrode layer 50 located in the trench 306. Optionally, the gate electrode layer 50 further extends to cover a portion of the second N-type gallium nitride layer 304 away from the gallium oxide substrate 10. In a direction perpendicular to the plane of the gallium oxide substrate 10, the thickness of the gate electrode layer 50 is much greater than that of the gate dielectric layer 40, and the gate electrode layer 50 completely fills the trench 306.

[0155] like Figure 25 As shown, a first insulating layer 60 is formed covering the gate dielectric layer 40 and the gate electrode layer 50. Optionally, the first insulating layer 60 is a silicon dioxide layer. Optionally, the first insulating layer is formed by a deposition process and has a thickness of about 1 μm. This application does not limit this and the specific process depends on the circumstances.

[0156] like Figure 26 As shown, the first insulating layer 60 and the gate dielectric layer 40 are etched to form an opening in the gate dielectric layer 40. The opening in the gate dielectric layer 40 exposes at least a portion of the surface of the second N-type gallium nitride layer 304 on a side away from the gallium oxide substrate 10, so as to facilitate electrical connection between the second N-type gallium nitride layer 304 and a subsequently formed source electrode layer.

[0157] Optionally, in one embodiment of the present application, the gate dielectric layer is a silicon nitride layer, and the thickness of the gate dielectric layer ranges from 30nm to 100nm, optionally 50nm; the gate electrode layer is a polysilicon layer, and the thickness of the gate electrode layer ranges from 200nm to 1500nm; the present application does not impose any restrictions on this, and the specific circumstances may vary.

[0158] It should be noted that when the power device is in operation, a source voltage is applied to the second N-type gallium nitride layer, and a gate voltage is applied to the gate electrode layer. Under the control of the source voltage and the gate voltage, electrons in the second N-type gallium nitride layer sequentially travel along the contact surface between the gate dielectric layer and the second N-type gallium nitride layer, and along the contact surface between the gate dielectric layer and the second P-type gallium nitride layer, enter the first N-type gallium nitride layer, and then enter the third N-type gallium nitride layer through the first N-type gallium nitride layer.

[0159] S5: forming a source electrode layer electrically connected to the second N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer, and forming a drain electrode layer electrically connected to a side of the gallium oxide substrate away from the N-type gallium oxide epitaxial layer.

[0160] Optionally, in one embodiment of the present application, forming a source electrode layer electrically connected to the second N-type gallium nitride layer and a drain electrode layer electrically connected to a side of the gallium oxide substrate away from the N-type gallium oxide epitaxial layer includes:

[0161] like Figure 27 As shown, a source ohmic contact layer 70 is formed on an exposed portion of the second N-type gallium nitride layer 304 away from the gallium oxide layer substrate 10, and a gate ohmic contact layer 110 is formed on an exposed portion of the gate electrode layer 50 away from the gallium oxide layer substrate 10. Optionally, the source ohmic contact layer 70 and the gate ohmic contact layer 110 are formed simultaneously.

[0162] like Figure 28 As shown, a drain ohmic contact layer 91 is formed on the side of the gallium oxide substrate 10 away from the N-type gallium oxide epitaxial layer 20;

[0163] like Figure 29 As shown, a source electrode layer 80 is formed on the side of the source ohmic contact layer 70 away from the second N-type gallium nitride layer 304, and a gate lead 120 is formed on the side of the gate ohmic contact layer 110 away from the gate electrode layer 50. Optionally, the source electrode layer 80 and the gate lead 120 are formed at the same time;

[0164] like Figure 30 As shown, a drain electrode layer 90 is formed on the side of the drain ohmic contact layer 91 away from the gallium oxide substrate 10 .

[0165] Specifically, in one embodiment of the present application, the source ohmic contact layer includes a stacked Ti metal layer and an Au metal layer, the thickness of the Ti metal layer in the source ohmic contact layer is 20 nm, and the thickness of the Au metal layer is 20 nm; the drain ohmic contact layer includes a stacked Ti metal layer and an Au metal layer, the thickness of the Ti metal layer in the drain ohmic contact layer is 20 nm, and the thickness of the Au metal layer is 20 nm. This application does not limit this, and it depends on the specific situation.

[0166] It should be noted that the source ohmic contact layer, the gate ohmic contact layer and the drain ohmic contact layer need to be annealed after formation to form ohmic contacts. In an embodiment of the present application, the method for manufacturing the power device may be to anneal once after the source ohmic contact layer and the gate ohmic contact layer are formed, and anneal again after the drain ohmic contact layer is formed. Alternatively, the source ohmic contact layer, the gate ohmic contact and the drain ohmic contact layer may be annealed once uniformly. The present application does not limit this, and the specific situation may depend on the circumstances.

[0167] Specifically, in one embodiment of the present application, forming a source ohmic contact layer on an exposed portion of the second N-type gallium nitride layer away from the gallium oxide layer substrate, forming a gate ohmic contact layer on an exposed portion of the gate electrode layer away from the gallium oxide layer substrate, and forming a drain ohmic contact layer on a side of the gallium oxide substrate away from the N-type gallium oxide epitaxial layer includes:

[0168] forming a first electrode layer on an exposed portion of the second N-type gallium nitride layer away from the gallium oxide layer substrate and an exposed portion of the gate electrode layer away from the gallium oxide layer substrate; optionally, the first electrode layer is formed by an evaporation process;

[0169] Using a lift-off process, remove the exposed portion of the first electrode layer that is not located on the side of the second N-type gallium nitride layer away from the gallium oxide layer substrate and the exposed portion of the gate electrode layer that is away from the gallium oxide layer substrate;

[0170] forming a second electrode layer on a side of the gallium oxide substrate away from the N-type gallium oxide epitaxial layer, and optionally, forming the second electrode layer by an evaporation process;

[0171] The first electrode layer and the second electrode layer are annealed in an N2 atmosphere at a temperature range of 450°C to 500°C for 1 minute to form a source ohmic base layer, a gate ohmic contact layer and a drain ohmic contact layer.

[0172] On the basis of any of the above embodiments, in one embodiment of the present application, the manufacturing method further includes:

[0173] like Figure 31 As shown, a second insulating layer 100 is formed to cover the source electrode layer 80. The second insulating layer 100 has an opening. The opening of the second insulating layer 100 exposes a partial area of ​​the source electrode layer 80 to facilitate electrical connection of the source electrode layer 80 with the outside world, such as being electrically connected to the test terminal as a test lead.

[0174] The power device fabrication method provided in the embodiments of the present application includes an N-type gallium oxide epitaxial layer located on a gallium oxide substrate and a gallium nitride epitaxial layer located on the side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate. The gallium nitride epitaxial layer comprises a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked together to form a PNP sandwich structure. This allows the N-type gallium oxide epitaxial layer and the gallium nitride epitaxial layer to form an epitaxial structure with a heterojunction (PN) junction, resolving the device construction issues associated with the lack of P-type doping in existing gallium oxide materials. High-voltage devices can be fabricated using conventional processes. Furthermore, the power device provided in the embodiments of the present application integrates a GaN and Ga2O3 material system, leveraging the advantages of Ga2O3's high critical electric field and low substrate cost, while also leveraging GaN's P-type properties and high thermal conductivity, resulting in high performance. Furthermore, compared to P-type materials such as NiO and Cu2O, gallium nitride (GaN) does not decompose in high-temperature environments and has superior heat dissipation capabilities. In addition, the lattice mismatch rate between GaN and Ga2O3 can be as low as 2.6%. Therefore, the N-type gallium oxide layer and the gallium nitride epitaxial layer form a better heterogeneous interface and have higher performance.

[0175] In addition, in the manufacturing method of the power device provided in the embodiment of the present application, the power device forms an epitaxial structure with a heterogeneous PN junction by the N-type gallium oxide epitaxial layer and the gallium nitride epitaxial layer. There are fewer electrons in the gallium nitride epitaxial layer. Therefore, when the voltage applied to the gate of the power device is 0V, there is no need to generate a depletion region by depleting electrons, thereby lowering the requirements for the size between adjacent trenches, so that the size between adjacent trenches can be achieved. About 1μm, significantly reducing the process requirements of the power device.

[0176] In addition, in the manufacturing method of the power device provided in the embodiment of the present application, the second P-type gallium nitride layer is used to control the threshold voltage of the power device, and the first P-type gallium nitride layer is used to control the directional breakdown electric field of the power device. The first N-type gallium nitride layer is arranged between the first P-type gallium nitride layer and the second P-type gallium nitride layer. The threshold voltage and reverse breakdown voltage of the power device can be decoupled, the connection between the two is reduced, and the design of the power device is more flexible.

[0177] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For relevant parts, refer to the description of the methods.

[0178] It should be noted that, in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure marks throughout the embodiments of the specification identify the same structure. It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the article or device comprising a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also include elements that are inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a..." do not exclude the presence of other identical elements in the article or device comprising the above elements.

[0179] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power device, characterized in that: include: Gallium oxide substrate; an N-type gallium oxide epitaxial layer located on a first side surface of the gallium oxide substrate; a gallium nitride epitaxial layer located on a surface of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate, the gallium nitride epitaxial layer comprising a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked together, the gallium nitride epitaxial layer comprising a trench, the trench penetrating the second P-type gallium nitride layer and extending into the first N-type gallium nitride layer, the gallium nitride epitaxial layer comprising a first region and a second region parallel to the plane of the gallium oxide substrate, the first region being located between adjacent trenches, and the second region being located at the bottom of the trench; a second N-type gallium nitride layer located in the first region of the gallium nitride epitaxial layer and within a surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer located in the second region of the gallium nitride epitaxial layer and within a surface of the first P-type gallium nitride layer, wherein, in a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer; a gate dielectric layer and a gate electrode layer located in the trench and covering at least a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer; a source electrode layer electrically connected to the second N-type gallium nitride layer, the source electrode layer being electrically insulated from the gate electrode layer; A drain electrode layer is electrically connected to a side of the gallium oxide substrate away from the N-type gallium oxide epitaxial layer.

2. The power device according to claim 1, wherein: The second N-type gallium nitride layer is not formed in a third region of the second P-type gallium nitride layer on a side away from the N-type gallium oxide epitaxial layer. The second P-type gallium nitride layer is also electrically connected to the source electrode layer.

3. The power device according to claim 2, characterized in that The first region includes a first sub-region and a second sub-region. In a plane parallel to the plane where the gallium nitride epitaxial layer is located, the third region is located between the first sub-region and the second sub-region.

4. The power device according to claim 1, wherein: The power device includes at least one row of trenches arranged along a first direction, where each row of trenches includes at least one trench, and the first direction is parallel to the plane where the gallium oxide substrate is located.

5. The power device according to claim 4, characterized in that: A row of grooves includes a groove, the projection of the groove on the gallium oxide substrate is rectangular, and the extending direction is a second direction, the second direction is parallel to the plane of the gallium oxide substrate, and the first direction and the second direction are different.

6. The power device according to claim 5, characterized in that A third N-type gallium nitride layer is provided at a position of the trench corresponding to the first P-type gallium nitride layer, an extension direction of the third N-type gallium nitride layer is the same as an extension direction of the trench, and a size of the third N-type gallium nitride layer along the extension direction is the same as a size of the trench along the extension direction; Alternatively, a plurality of third N-type gallium nitride layers are provided at positions of a trench corresponding to the first P-type gallium nitride layer, an extension direction of the third N-type gallium nitride layer is the same as an extension direction of the trench, and a dimension of the third N-type gallium nitride layer along the extension direction is smaller than a dimension of the trench along the extension direction.

7. The power device according to claim 6, characterized in that: When a plurality of third N-type GaN layers are disposed at positions of a trench corresponding to the first P-type GaN layer, sizes of different third N-type GaN layers along their extension directions may be the same or different.

8. The power device according to claim 4, characterized in that A row of trenches includes a plurality of trenches arranged along a second direction, the second direction is parallel to the plane where the gallium oxide substrate is located, and the first direction and the second direction are different.

9. The power device according to claim 8, characterized in that The projection shape of the groove on the gallium oxide substrate is circular, polygonal or rounded square.

10. A method for manufacturing a power device, characterized in that: include: forming an N-type gallium oxide epitaxial layer on a gallium oxide substrate; forming a gallium nitride epitaxial layer on a side of the N-type gallium oxide epitaxial layer away from the gallium oxide substrate, wherein the gallium nitride epitaxial layer includes a first P-type gallium nitride layer, a first N-type gallium nitride layer, and a second P-type gallium nitride layer stacked together; A second N-type gallium nitride layer is formed in a first region of the gallium nitride epitaxial layer within a surface of the second P-type gallium nitride layer, and a third N-type gallium nitride layer is formed in a second region of the gallium nitride epitaxial layer within a surface of the first P-type gallium nitride layer. The gallium nitride epitaxial layer comprises a trench, which penetrates the second P-type gallium nitride layer and extends into the first N-type gallium nitride layer. The gallium nitride epitaxial layer comprises a first region and a second region parallel to the plane of the gallium oxide substrate, the first region being located between adjacent trenches, and the second region being located at the bottom of the trench. In a direction perpendicular to the plane of the gallium oxide substrate, the thickness of the second N-type gallium nitride layer is less than the thickness of the second P-type gallium nitride layer, and the thickness of the third N-type gallium nitride layer is equal to the thickness of the first P-type gallium nitride layer. forming a gate dielectric layer and a gate electrode layer located in the trench and covering at least a portion of the second N-type gallium nitride layer, wherein the gate dielectric layer is located between the gate electrode layer and the second N-type gallium nitride layer; forming a source electrode layer electrically connected to the second N-type gallium nitride layer, wherein the source electrode layer is electrically insulated from the gate electrode layer; A drain electrode layer is formed which is located on a side of the gallium oxide substrate away from the N-type gallium oxide epitaxial layer and is electrically connected to the gallium oxide substrate.

11. The manufacturing method according to claim 10, characterized in that: In the first region of the gallium nitride epitaxial layer, a second N-type gallium nitride layer is formed on the surface of the second P-type gallium nitride layer, and in the second region of the gallium nitride epitaxial layer, a third N-type gallium nitride layer is formed on the surface of the first P-type gallium nitride layer, wherein the gallium nitride epitaxial layer has a trench, the trench penetrating the second P-type gallium nitride layer and extending into the first N-type gallium nitride layer, the gallium nitride epitaxial layer including a first region and a second region parallel to the plane of the gallium oxide substrate, the first region being located between adjacent trenches, and the second region being located at the bottom of the trench and including: doping a fourth region of the gallium nitride epitaxial layer to form a second N-type gallium nitride layer in a fourth region of the second P-type gallium nitride layer on a side of the surface away from the gallium oxide substrate, wherein the fourth region includes the first region; Etching the fifth region of the gallium nitride epitaxial layer to form a trench in the gallium nitride epitaxial layer, the trench penetrating the second P-type gallium nitride layer and extending into the first N-type gallium nitride layer, the fifth region being different from the first region; Doping a portion of the first P-type gallium nitride layer corresponding to the trench to form a third N-type gallium nitride layer within the surface of the second region of the first P-type gallium nitride layer, wherein a thickness of the third N-type gallium nitride layer is equal to a thickness of the first P-type gallium nitride layer in a direction perpendicular to a plane of the gallium oxide substrate.

12. The manufacturing method according to claim 11, characterized in that: Doping a fourth region of the gallium nitride epitaxial layer to form a second N-type gallium nitride layer in a fourth region on a surface of the second P-type gallium nitride layer away from the gallium oxide substrate, wherein the fourth region includes the first region. doping the fourth region of the first P-type gallium nitride layer in the gallium nitride epitaxial layer, retaining the third region of the first P-type gallium nitride layer in the gallium nitride epitaxial layer, and forming a second N-type gallium nitride layer in a first region within a surface of the first P-type gallium nitride layer on a side away from the gallium oxide substrate; The third region of the first P-type gallium nitride layer is electrically connected to the source electrode layer.

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