Package and method of manufacturing semiconductor device

Abstract

In one embodiment, a package includes a first die over and bonded to a first side of a package component, where a first bond between the first die and the package component includes a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and a second bond between the first die and the package component includes a metal-to-metal bond between a first bond pad of the first die and a second bond pad on the package component; a first portion of a redistribution structure adjacent to the first die and over the second bonding layer; and a second die over the first portion of the redistribution structure and coupled to the first portion of the redistribution structure using a first conductive connection electrically connected to the first conductive pad in the second bonding layer. The embodiment of the invention also relates to a method for manufacturing the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to packages and methods of manufacturing semiconductor devices. Background Art

[0002] Since the development of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) In most cases, these improvements in integration density have come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

[0003] These integration improvements are essentially two-dimensional (2D) in nature, as the area occupied by the integrated components is substantially on the surface of the semiconductor wafer. The increased density of integrated circuits and the corresponding reduction in area have generally outstripped the ability to bond integrated circuit chips directly to substrates. Interposers have been used to redistribute ball contact areas from the area of ​​the chip to a larger area of ​​the interposer. In addition, interposers have allowed three-dimensional (3D) packages that include multiple chips. Other packages have also been developed to incorporate 3D aspects. Summary of the invention

[0004] Some embodiments of the present application provide a package, comprising: a first die located above a first side of a package component and bonded to the first side of the package component, wherein a first bond between the first die and the package component comprises a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and a second bond between the first die and the package component comprises a metal-to-metal bond between a first bonding pad of the first die and a second bonding pad on the package component; a first portion of a redistribution structure adjacent to the first die and located above the second bonding layer; and a second die located above the first portion of the redistribution structure and coupled to the first portion of the redistribution structure using a first conductive connector, wherein the first conductive connector is electrically connected to a first conductive pad in the second bonding layer.

[0005] Other embodiments of the present application provide a package, comprising: a first multi-chip stack, located above a first side of an interposer and bonded to the first side of the interposer, wherein the first bond between the first multi-chip stack and the interposer includes a dielectric-to-dielectric bond between a first bonding layer of the first multi-chip stack and a second bonding layer on the interposer, wherein the first multi-chip stack includes: a first die; and a second die, located above a first side of the first die and bonded to the first side of the first die, wherein the second bond between the first die and the second die includes a dielectric-to-dielectric bond between a third bonding layer of the second die and a fourth bonding layer on the first die; and a third die, located above the first side of the interposer and coupled to the first side of the interposer using a first conductive connector, wherein the first conductive connector includes a solder microbump.

[0006] Still other embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: bonding a first die to a packaging component, wherein bonding the first die to the packaging component comprises directly bonding a first dielectric layer of the first die to a second dielectric layer on the packaging component, and directly bonding a first conductive connector of the first die to a second conductive connector on the packaging component; forming a first portion of a redistribution structure adjacent to the first die above the second dielectric layer; and coupling a second die to the first portion of the redistribution structure using a third conductive connector, wherein a first spacing between the first conductive connector and the second conductive connector is less than a second spacing of the third conductive connector. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figures 1 to 4A Cross-sectional views of intermediate steps during a process for forming a device package are shown in accordance with some embodiments.

[0009] Figure 4B Cross-sectional views of intermediate steps during a process for forming a device package are shown in accordance with alternative embodiments.

[0010] Figure 5A Cross-sectional views of intermediate steps during a process for forming a device package are shown in accordance with some embodiments.

[0011] Figure 5BCross-sectional views of intermediate steps during a process for forming a device package are shown in accordance with alternative embodiments.

[0012] Figure 6 Cross-sectional views of intermediate steps during a process for forming a device package are shown in accordance with some embodiments.

[0013] FIG. 7A to FIG. 7B Cross-sectional views of intermediate steps during a process for forming a device package are shown in accordance with alternative embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] Various embodiments include methods suitable for forming a device package. The method includes bonding at least one first semiconductor die (e.g., a first top die) to an interposer using a hybrid bonding configuration, wherein a first bonding pad of the first semiconductor die is bonded to a second bonding pad on the interposer by direct metal-to-metal bonding and electrically connected to the second bonding pad on the interposer. The hybrid bonding configuration also includes directly bonding the first bonding layer of the first semiconductor die to the second bonding layer on the interposer using dielectric-to-dielectric bonding. The method also includes coupling and electrically connecting at least one second semiconductor die (e.g., a second top die) to the interposer using a first conductive connector (such as a microbump, etc.). The first bonding pad and the second bonding pad may have a first pitch less than 9 μm, wherein the first pitch is the distance from the center of the first bonding pad or the second bonding pad to the center of the adjacent first bonding pad or the second bonding pad, respectively. The first conductive connector may have a second pitch greater than the first pitch (e.g., greater than 30 μm), wherein the second pitch is the distance from the center of the first conductive connector to the center of the adjacent first conductive connector. One or more embodiments disclosed herein may allow semiconductor dies with different interconnection bandwidth requirements to be bonded to an interposer. For example, the first semiconductor die may be a graphics processing unit (GPU), a central processing unit (CPU), or the like that requires high input / output signal transmission capabilities. Because the first pitch is less than 9 μm, the first semiconductor die and the interposer may utilize a larger number of first bonding pads and second bonding pads per unit area to bond the first semiconductor die to the interposer, which allows for greater interconnection bandwidth and faster signal transmission between the first semiconductor die and the interposer. Since the first semiconductor die and the interposer utilize a larger number of first bonding pads and second bonding pads per unit area, the size of the device package may be reduced compared to if other types of conductive connectors (e.g., solder bumps) having a pitch larger than the first pitch are used to bond the first semiconductor die to the interposer. The second semiconductor die may be a memory die, etc. that may not require such high signal transmission capabilities. Then, it is sufficient to couple the second semiconductor die to the interposer using a first conductive connector having a second pitch while still meeting the interconnection bandwidth requirements. Furthermore, using the first conductive connector to couple the second semiconductor die to the interposer results in lower manufacturing costs and also results in better electrical connections between the second semiconductor die and the interposer, which improves device yield and reliability.Therefore, forming a device package by combining the use of first and second bonding pads and first and second bonding layers to bond a first semiconductor die (e.g., having a high interconnection bandwidth requirement) to an interposer, and using a first conductive connector to couple a second semiconductor die (e.g., having a lower interconnection bandwidth requirement than the first semiconductor die) to the interposer can allow for an overall reduction in device package size, a reduction in manufacturing costs, and improved device yield and reliability of the device package.

[0017] The embodiments discussed herein are intended to provide examples of the subject matter of the disclosed embodiments that can be manufactured or used, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the contemplation of the different embodiments. The same reference numerals and characters in the following figures refer to the same components. Although the method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0018] Figures 1 to 6 Cross-sectional views of intermediate steps during a process for forming an integrated chip package 10 are shown, in accordance with some embodiments. Figure 1 A package assembly 50 is shown. The package assembly 50 may be an interposer including a substrate 70. The substrate 70 may be a wafer. The substrate 70 may include a bulk semiconductor substrate, an SOI substrate, a multilayer semiconductor substrate, etc. The semiconductor material of the substrate 70 may be: silicon, germanium; a compound semiconductor including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate 70 may be doped or undoped. In an embodiment where the package assembly 50 is an interposer, no active devices will be included in the package assembly 50, but the substrate 70 may include passive devices formed in and / or on the first surface 72 of the substrate 70. In an embodiment, the package component 50 may be an active die (e.g., a bottom die) that may include devices (such as transistors, capacitors, resistors, diodes, etc.) that may be formed in and / or on the first surface 72 (which may also be referred to as an active surface) of the substrate 70. In an embodiment, the package component 50 may be a microelectromechanical system (MEMS) die. In other embodiments, the package component 50 may be an organic interposer including a polymer-based layer, wherein metal traces and vias are embedded in the polymer-based layer. The polymer-based layer may include a polymer material, such as polyimide (PI), etc. The metal traces and vias may include conductive materials, such as copper, aluminum, etc.

[0019] Still reference Figure 1, the package component 50 may include a redistribution structure 76 formed over the first surface 72 of the substrate 70. The redistribution structure 76 may include an insulating layer and a metallization pattern 78 within each of the insulating layers. In some embodiments, the redistribution structure 76 may have any number of insulating layers or metallization patterns 78. The side of the package component 50 having the exposed top surface of the redistribution structure 76 may be subsequently referred to as the front side of the package component 50. The side of the package component 50 having the exposed surface of the substrate 70 may be subsequently referred to as the back side of the package component 50.

[0020] Each of the insulating layers may include, for example, a dielectric material such as silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0), etc. In other embodiments, each of the insulating layers may include a low-K dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO x C y , spin-on glass, spin-on polymer, silicon carbon material, their compounds, their composite materials, their combinations, etc. The insulating layer can be formed by any suitable method known in the art, such as spin coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), high density plasma chemical vapor deposition (HDP-CVD), etc. The metallization pattern 78 can then be formed in the insulating layer, for example, by using photolithography to deposit and pattern a photoresist material on the insulating layer to expose the portion of the insulating layer that will become the metallization pattern 78. An etching process such as an anisotropic dry etching process can be used to produce grooves and / or openings in the insulating layer corresponding to the exposed portion of the insulating layer. The grooves and / or openings can be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer can include one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, etc., or combinations thereof, deposited by atomic layer deposition (ALD), etc. The conductive material of the metallization pattern 78 can include copper, aluminum, tungsten, silver, and combinations thereof, etc., deposited by CVD, physical vapor deposition (PVD), etc. Any excess diffusion barrier and / or conductive material on the insulating layer may be removed, such as by using chemical mechanical polishing (CMP).

[0021] The package component 50 may include a through hole (TV) 74 formed to extend through the redistribution structure 76 and partially through the substrate 70 (e.g., extending from the first surface 72 of the substrate 70 into the substrate 70). When the substrate 70 is a silicon substrate, the TV 74 is sometimes also referred to as a through-substrate via or a through-silicon via. The TV 74 may be formed after the redistribution structure 76 is formed. In some embodiments, the TV 74 may be formed by forming a groove in the redistribution structure 76 and the substrate 70 by, for example, etching, milling, laser technology, a combination thereof, or the like. A thin dielectric material may be formed in the groove, such as by using an oxidation technique (e.g., to oxidize the silicon surface of the substrate 70 in the groove). A thin barrier layer may be conformally deposited over the front side of the package component 50 and in the opening, such as by CVD, ALD, PVD, thermal oxidation, a combination thereof, or the like. The barrier layer may include a nitride or oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tungsten nitride, a combination thereof, or the like. A conductive material may be deposited over the thin barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, etc. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material and barrier layers are removed from the front side of package component 50 by, for example, CMP. Thus, TV 74 may include conductive material and thin barrier layers between the conductive material and substrate 70 and between the conductive material and redistribution structure 76.

[0022] Figure 2 Semiconductor die 86 is shown bonded to package assembly 50. Although Figure 2 Two semiconductor dies 86 are shown, but any number of semiconductor dies 86 may be bonded to the package assembly 50. Each of the semiconductor dies 86 may be a logic die (e.g., an application processor (AP), a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wide IO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die), a biomedical die, etc. Each semiconductor die 86 may also be a system-on-chip (SoC) die, etc.

[0023] Each semiconductor die 86 may include a substrate 88 (e.g., a semiconductor substrate), an interconnect structure 90 disposed on the substrate 88, a bonding layer 94 disposed on the interconnect structure 90, and a bonding pad 96 disposed in the bonding layer 94 and exposed at a front side of the semiconductor die 86. The side of the semiconductor die including the bonding pad 96 and the bonding layer 94 may also be subsequently referred to as a front side of the semiconductor die 86.

[0024] The substrate 88 of the semiconductor die 86 may include crystalline silicon. The substrate 88 may include various doped regions (e.g., a p-type substrate or an n-type substrate) depending on the design requirements. In some embodiments, the doped regions may be doped with p-type or n-type dopants. The doped regions may be doped with: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured for n-type fin field effect transistors (FinFETs) and / or p-type FinFETs. In some optional embodiments, the substrate 88 may include an active layer of a semiconductor on insulator (SOI) substrate. The substrate 88 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0025] Active and / or passive devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and / or on substrate 88. The devices may be interconnected by interconnect structure 90. Interconnect structure 90 electrically connects the devices on substrate 88 to form one or more integrated circuits. Interconnect structure 90 may include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, etc.) and interconnect wiring or metallization patterns embedded in the one or more dielectric layers. The material of the one or more dielectric layers may include silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0) or other suitable dielectric materials. The interconnect wiring may include metal wiring. For example, the interconnect wiring includes copper wiring, copper pads, aluminum pads, or combinations thereof formed by one or more single damascene processes, dual damascene processes, etc. The side of semiconductor die 86 including the exposed backside surface of substrate 88 may also be subsequently referred to as the backside of semiconductor die 86.

[0026] The bonding layer 94 may include a dielectric layer. The bonding pad 96 is embedded in the bonding layer 94, and the bonding pad 96 allows connections to be made to the interconnect structure 90 and the devices on the substrate 88. The material of the bonding layer 94 may be silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0), tetraethyl orthosilicate (TEOS) or other suitable dielectric materials, and the bonding pad 96 may include a conductive pad (e.g., a copper pad), a conductive via (e.g., a copper via), or a combination thereof. The bonding layer 94 may be formed by: depositing a dielectric material over the interconnect structure 90 using a chemical vapor deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable process); patterning the dielectric material to form a bonding layer 94 including an opening or a hole; and filling the opening or hole defined in the bonding layer 94 with a conductive material to form a bonding pad 96 embedded in the bonding layer 94.

[0027] Further references Figure 2 , a bonding layer 80 and a bonding pad 84 are formed over the front side of the package component 50, such as over the redistribution structure 76. The bonding layer 80 and the bonding pad 84 can be formed using similar materials and similar processes as those described above for forming the bonding layer 94 and the bonding pad 96, respectively. The bonding pad 84 allows an electrical connection to be made to the metallization pattern 78 of the redistribution structure 76. The bonding pad 96 and the bonding pad 84 can have a first pitch P1 of less than 9 μm, wherein the first pitch P1 is the distance from the center of the bonding pad 96 or the bonding pad 84 to the center of the adjacent bonding pad 96 or the bonding pad 84, respectively. During the formation of the bonding pad 84, a conductive pad 82 is also formed in the bonding layer 80 using similar materials and similar processes as those previously described for forming the bonding pad 84 and the bonding pad 96. The conductive pad 82 can overlap with the corresponding TV 74. In an embodiment, the conductive pad 82 can also overlap with a portion of the redistribution structure 76. In an embodiment, the width of each conductive pad 82 is less than the width of each TV 74. In an embodiment, the width of each conductive pad 82 is greater than the width of each TV 74. Conductive pads 82 may be formed to physically contact TVs 74 and allow electrical connections to be made thereto.

[0028] After forming the bonding layer 80, the bonding pads 84, and the conductive pads 82, the semiconductor die 86 is bonded to the package component 50, for example, in a hybrid bonding configuration. The semiconductor die 86 can be disposed face-down so that the front side of the semiconductor die 86 faces the redistribution structure 76 of the package component 50, and the back side of the semiconductor die 86 faces away from the package component 50 (for example, in a face-to-face (F2F) configuration). The semiconductor die 86 is bonded to the bonding layer 80 on the front side of the package component 50 and the bonding pads 84 in the bonding layer 80. For example, the bonding layer 94 of the semiconductor die 86 can be directly bonded to the bonding layer 80 on the package component 50, and the bonding pads 96 of the semiconductor die 86 can be directly bonded to the bonding pads 84 on the package component 50. In an embodiment, the bonding between the bonding layer 94 and the bonding layer 80 can be an oxide-to-oxide bonding, etc. The hybrid bonding process also directly bonds the bonding pads 96 of the semiconductor die 86 to the bonding pads 84 on the package component 50 through direct metal-to-metal bonding. Thus, electrical connection between semiconductor die 86 and package assembly 50 is provided by the physical connection of bond pad 96 to bond pad 84 .

[0029] As an example, the hybrid bonding process begins by aligning the semiconductor die 86 with the package component 50, for example, by applying a surface treatment to one or more of the bonding layer 94 or the bonding layer 80. The surface treatment may include a plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more of the bonding layer 94 or the bonding layer 80. Then, the hybrid bonding process may continue to align the bonding pad 96 with the bonding pad 84. Next, the hybrid bonding includes a pre-bonding step during which the semiconductor die 86 is placed in contact with the package component 50. The pre-bonding may be implemented at room temperature (e.g., between about 21° C. and about 25° C.). The hybrid bonding process continues with annealing, for example, at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, so that the metal (e.g., copper) in the bonding pad 96 and the metal (e.g., copper) of the bonding pad 84 diffuse into each other, and thus form a direct metal-to-metal bond.

[0030] In other embodiments, bonding layer 94 and bonding pads 96 may be formed on the back side of semiconductor die 86 (e.g., on an exposed surface of substrate 88) rather than on the front side of semiconductor die 86 (e.g., on interconnect structure 90). Semiconductor die 86 may then be bonded to package assembly 50, for example, in a hybrid bonding configuration using a similar process as described above to bond bonding layer 94 of semiconductor die 86 directly to bonding layer 80 of package assembly 50 and to bond bonding pads 96 of semiconductor die 86 directly to bonding pads 84 of package assembly 50. After such bonding, semiconductor die 86 may be disposed face-up so that the front side of semiconductor die 86 faces away from package assembly 50 and the back side of semiconductor die 86 faces redistribution structure 76 of package assembly 50 (e.g., in a face-to-back (F2B) configuration).

[0031] Further references Figure 2 , a thinning process is performed on the exposed surface of the substrate 70 on the back side of the package component 50 to expose the TV 74. The thinning process may include an etching process, a grinding process, etc. or a combination thereof. The thinning process may be performed before or after the semiconductor die 86 is bonded to the package component 50.

[0032] Figure 3 Redistribution structure 98 is shown formed over package component 50, redistribution structure 76, bonding layer 80, and conductive pad 82. Specifically, redistribution structure 98 includes a first portion of redistribution structure 98A and a second portion of redistribution structure 98B disposed adjacent to semiconductor die 86. In an embodiment, semiconductor die 86 may be disposed between the first portion of redistribution structure 98A and the second portion of redistribution structure 98B.

[0033] Each of the first portion of the redistribution structure 98A and the second portion of the redistribution structure 98B may include an insulating layer (e.g., insulating layer 100 and insulating layer 102) and a metallization pattern within each of the insulating layers. In some embodiments, each of the first portion of the redistribution structure 98A and the second portion of the redistribution structure 98B may have any number of insulating layers or metallization patterns.

[0034] In an embodiment where the height H1 of each semiconductor die 86 is less than 30 μm, each of the insulating layers (e.g., insulating layers 100 and 102) may include, for example, a dielectric material such as silicon oxide, silicon nitride, etc., conformally formed over the semiconductor die 86, the bonding layer 80, and the conductive pad 82 using any suitable method known in the art (such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.). In other embodiments, each insulating layer may include ultra-low viscosity polyimide (PI) formed over the bonding layer 80 and the conductive pad 82 using a spin coating process, a spray coating process (e.g., by using a nozzle), etc., wherein, due to the low wetting properties of the ultra-low viscosity polyimide (PI), the insulating layer does not form a uniform film (i.e., is not formed) on the top surface and the top portion of the sidewall of the semiconductor die 86, but is formed only on the bonding layer 80 and the conductive pad 82 and the bottom portion of the sidewall of the semiconductor die 86. Then, a metallization pattern can be formed in the insulating layer, for example, by using photolithography to deposit and pattern a photoresist material over the semiconductor die 86 and the insulating layer to expose the portion of the insulating layer that will become the metallization pattern. An etching process such as an anisotropic dry etching process can be used to produce grooves and / or openings in the insulating layer corresponding to the exposed portion of the insulating layer. The grooves and / or openings can be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer can include one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, etc., or combinations thereof, deposited by atomic layer deposition (ALD) or the like. The conductive material of the metallization pattern can include copper, aluminum, tungsten, silver, and combinations thereof, etc., deposited by CVD, physical vapor deposition (PVD), etc. After forming the insulating layer and the metallization pattern in the insulating layer, the diffusion barrier layer, the conductive material, the photoresist material, and the portion of the insulating layer located above the top surface and sidewalls of the semiconductor die 86 (if present) can be removed, such as by using any suitable combination of processes such as chemical mechanical polishing (CMP), etching, ashing, chemical stripping, etc., to leave the insulating layer and the portion of the metallization pattern in the insulating layer disposed adjacent to the semiconductor die 86. In addition, any excess diffusion barrier layer, conductive material, and photoresist material above the portion of the insulating layer and the metallization pattern in the insulating layer (e.g., disposed adjacent to the semiconductor die 86) can be removed by any suitable combination of processes such as chemical mechanical polishing (CMP), etching, ashing, chemical stripping, etc. Any number of insulating layers and corresponding metallization patterns can be formed using similar processes and materials as described above to form a first portion of the redistribution structure 98A and a second portion of the redistribution structure 98B disposed adjacent to the semiconductor die 86.

[0035] Further references Figure 3, the first portion of the redistribution structure 98A and the second portion of the redistribution structure 98B may also include an under bump metal (UBM) 104 formed above the topmost insulating layer (e.g., insulating layer 102) for external connection to each of the first portion of the redistribution structure 98A and the second portion of the redistribution structure 98B. The UBM 104 may include a conductive pad, a conductive bump, etc. extending along a major surface of the topmost insulating layer (e.g., insulating layer 102) and in physical and electrical contact with a metallization pattern in the topmost insulating layer (e.g., insulating layer 102). The TV 74 is also electrically connected to the UBM 104 through the redistribution structure 98. The UBM 104 may be formed of the same material as the metallization pattern of the redistribution structure 98. In some embodiments, the UBM 104 may have a different size than the metallization pattern of the redistribution structure 98.

[0036] Figure 4A Semiconductor die 106 is shown coupled to package assembly 50. Although Figure 4A Two semiconductor dies 106 are shown, but any number of semiconductor dies 106 may be coupled to the package assembly 50. The semiconductor die 106 may be formed by a similar process as described above with reference to the semiconductor die 86. In some embodiments, the semiconductor die 106 may be a memory die, such as a stack of memory dies (e.g., a DRAM die, an SRAM die, a high bandwidth memory (HBM) die, a hybrid memory cube (HMC) die, etc.). In a stack of memory dies embodiment, the semiconductor die 106 may include a memory die and a memory controller, such as, for example, a stack of four or eight memory dies with a memory controller. In addition, in some embodiments, the semiconductor die 106 may be different sizes (e.g., different heights and / or surface areas), and in other embodiments, the semiconductor die 106 may be the same size (e.g., the same height and / or surface area). In some embodiments, each semiconductor die 106 may include multiple DRAM dies stacked vertically on top of each other. The stacking of these dies allows for increased memory density without significantly increasing the physical footprint of the memory module. Each individual DRAM die in the stack may be interconnected using through silicon vias (TSVs), micro bumps, and the like.

[0037] In some embodiments, semiconductor die 106 may be of similar heights to those of semiconductor die 86 , or in some embodiments, semiconductor die 86 and 106 may have different heights.

[0038] The semiconductor die 106 includes a body 108, an interconnect structure 112, and a die connector 114. The body 108 of the semiconductor die 106 may include any number of dies, substrates, transistors, active devices, passive devices, etc. In an embodiment, the body 108 may include a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, a multilayer semiconductor substrate, etc. The semiconductor material of the body 108 may be: silicon, germanium; compound semiconductors including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The body 108 may be doped or undoped. Devices such as transistors, capacitors, resistors, diodes, etc. may be formed in and / or on the active surface.

[0039] An interconnect structure 112 including one or more dielectric layers and corresponding metallization patterns is formed on the active surface. The metallization patterns in the dielectric layers can route electrical signals between devices, such as by using vias and / or traces, and can also include various electronic devices, such as capacitors, resistors, inductors, etc. The various devices and metallization patterns can be interconnected to implement one or more functions. Functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input / output circuits, etc. In addition, a die connector 114 including a metal such as copper, such as a conductive pad, a conductive column, etc., is formed in and / or on the interconnect structure 112 to provide external electrical connections to circuits and devices. In some embodiments, the die connector 114 can protrude from the interconnect structure 112 and can be used when the semiconductor die 106 is bonded to other structures. It will be understood by those skilled in the art that the above examples are provided for illustrative purposes. For a given application, other circuits may be used appropriately.

[0040] More specifically, an IMD layer may be formed in the interconnect structure 112. The IMD layer may be formed of, for example, a low-K dielectric material such as PSG, BPSG, FSG, SiO x C y, spin-on glass, spin-on polymer, silicon carbon material, their compounds, their composite materials, their combinations, etc., by any suitable method known in the art, such as spin coating, CVD, PECVD, HDP-CVD, etc. A metallization pattern can be formed in the IMD layer, for example, by using photolithography to deposit and pattern a photoresist material on the IMD layer to expose the portion of the IMD layer that will become the metallization pattern. An etching process such as an anisotropic dry etching process can be used to produce grooves and / or openings in the IMD layer corresponding to the exposed portion of the IMD layer. The grooves and / or openings can be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may include one or more layers of tantalum nitride, tantalum, titanium nitride, titanium, cobalt tungsten, etc., or combinations thereof, deposited by ALD, etc. The conductive material of the metallization pattern may include copper, aluminum, tungsten, silver, and combinations thereof, etc., deposited by CVD, PVD, etc. Any excess diffusion barrier layer and / or conductive material on the IMD layer can be removed, such as by using CMP.

[0041] To couple the semiconductor die 106 to the package assembly 50, a conductive connector 116 is formed on the corresponding exposed UBM 104. The conductive connector 116 is electrically coupled to the first portion of the redistribution structure 98A and the second portion of the redistribution structure 98B through the UBM 104. The conductive connector 116 may include a microbump, a solder ball, or the like. The conductive connector 116 may include a conductive material such as lead-free solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connector 116 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer has been formed on the structure, a reflow may be performed to shape the material into a desired bump shape.

[0042] After forming the conductive connectors 116, the semiconductor die 106 is placed on the conductive connectors 116, and an electrical connection is made between each semiconductor die 106 and any one of the first portion of the redistribution structure 98A or the second portion of the redistribution structure 98B through the UBM 104. The semiconductor die 106 can be placed on the conductive connectors 116 using a placement process such as a pick and place process. Each semiconductor die 106 can be placed so that the die connectors 114 are aligned with corresponding ones of the conductive connectors 116 on the UBM 104. Once in physical contact, a reflow process can be used to bond the conductive connectors 116 on the redistribution structure 98A and the second portion of the redistribution structure 98B to the semiconductor die 106. In some embodiments, the conductive connectors 116 are formed on the die connectors 114 of the semiconductor die 106 instead of or in addition to the conductive connectors 116 formed on the UBM 104. The conductive connectors 116 may have a second pitch P2 greater than the first pitch P1, wherein the second pitch P2 is a distance from a center of a conductive connector 116 to a center of an adjacent conductive connector 116. In an embodiment, the second pitch P2 may be greater than 30 μm.

[0043] Advantages can be achieved by forming an integrated chip package 10, wherein forming the integrated chip package 10 includes bonding each semiconductor die 86 to the package component 50 using a hybrid bonding configuration, wherein the bonding pads 96 of the semiconductor die 86 are bonded to and electrically connected to the bonding pads 84 on the package component 50 by direct metal-to-metal bonding. The hybrid bonding configuration also includes directly bonding the bonding layer 94 of each semiconductor die 86 to the bonding layer 80 on the package component 50 using dielectric-to-dielectric bonding. Forming the integrated chip package 10 also includes coupling and electrically connecting the semiconductor die 106 to the package component 50 using conductive connectors 116 (such as microbumps, etc.). The bonding pads 96 and the bonding pads 84 can have a first pitch P1 less than 9 μm. The conductive connectors 116 can have a second pitch P2 greater than the first pitch P1 (e.g., greater than 30 μm). These advantages include allowing semiconductor dies with different interconnect bandwidth requirements to be bonded to the package component 50. For example, semiconductor die 86 may be a graphics processing unit (GPU), a central processing unit (CPU), or the like that requires high input / output signal transmission capability. Because first pitch P1 is less than 9 μm, semiconductor die 86 and package assembly 50 may utilize a greater number of bonding pads 96 and bonding pads 84 for bonding each semiconductor die 86 to package assembly 50 per unit area (due to the hybrid bonding configuration), which allows for greater interconnection bandwidth and faster signal transmission between semiconductor die 86 and package assembly 50. Because a greater number of bonding pads 96 and bonding pads 84 are utilized per unit area of ​​semiconductor die 86 and package assembly 50, the size of integrated chip package 10 may be reduced compared to if other types of conductive connectors (e.g., solder bumps) having a pitch greater than first pitch P1 are used to bond semiconductor die 86 to package assembly 50. Semiconductor die 106 may be a memory die or the like that may not require such high signal transmission capability. Then, it is sufficient to use a conductive connector 116 having a second pitch P2 (e.g., greater than 30 μm) to couple the semiconductor die 106 to the package assembly 50, while still meeting the interconnection bandwidth requirements. In addition, due to the larger second pitch P2, using the conductive connector 116 to couple the semiconductor die 106 to the package assembly 50 results in lower manufacturing costs and also produces better electrical connections between the semiconductor die 106 and the package assembly 50, which improves device yield and reliability.Therefore, forming an integrated chip package 10 by simultaneously using bonding pads 96 / 84 and bonding layers 94 / 80 to bond semiconductor die 86 (e.g., having high interconnection bandwidth requirements) to packaging component 50, and using conductive connectors 116 to couple semiconductor die 106 (e.g., having lower interconnection bandwidth requirements than semiconductor die 86) to packaging component 50 can allow for an overall reduction in size of the integrated chip package 10, a reduction in manufacturing costs, and improved device yield and reliability of the integrated chip package 10.

[0044] Figure 4B An integrated chip package 10 according to an alternative embodiment is shown. Unless otherwise specified, the same reference numerals in this embodiment (and the embodiments discussed subsequently) represent Figures 1 to 4A The same components in the embodiments shown in the drawings are formed by the same process. Therefore, the process steps and applicable materials may not be repeated here. Figure 4B Examples and Figure 4A The embodiment of the present invention differs in that, in Figure 4B In the embodiment of FIG. 1 , after the semiconductor die 86 (eg, also referred to as the first semiconductor die 86 ) is bonded to the package assembly 50 , as previously described in Figure 2 As shown in , additional semiconductor dies 86 (e.g., also referred to as second semiconductor dies 86) are bonded to the top surface of each of the first semiconductor dies 86. In this manner, the semiconductor dies 86 are stacked directly on top of each other to form a multi-chip stack 87. After forming the multi-chip stack 87, a redistribution structure 98 is formed over the package assembly 50, as previously described in Figure 3 and semiconductor die 106 is coupled to package assembly 50 using conductive connectors 116, as previously described in Figure 4A Described in .

[0045] like Figure 4B As shown in , each of the first semiconductor dies 86 bonded to the package assembly 50 may include a bonding layer 95 disposed on the back side of each of the first semiconductor dies 86 and a bonding pad 97 disposed in the bonding layer 95. The bonding layer 95 and the bonding pad 97 may be used as previously described. Figure 2 The bonding layer 94 and the bonding pad 96 are formed by similar processes and materials as described in .

[0046] After the first semiconductor die 86 is bonded to the package assembly 50, as previously described in Figure 2As shown in , the second semiconductor die 86 is bonded to the top surface of the corresponding first semiconductor die 86, for example, in a hybrid bonding configuration. The second semiconductor die 86 can be arranged face-down so that the front side of the second semiconductor die 86 faces the back side of the first semiconductor die 86. The second semiconductor die 86 is bonded to the bonding layer 95 and the bonding pads 97 in the bonding layer 95 of the corresponding first semiconductor die 86. For example, the bonding layer 94 of each second semiconductor die 86 can be bonded to the bonding layer 95 as previously described. Figure 2 80 on the package assembly 50 in a similar manner and using a similar process as described in . In addition, the bonding pads 96 of each second semiconductor die 86 can be directly bonded to the bonding layer 95 of the corresponding first semiconductor die 86 as previously described in Figure 2 The semiconductor die 86 is bonded directly to the bond pads 97 of the corresponding first semiconductor die 86 in a similar manner as described in for bonding the bond pads 96 of the semiconductor die 86 to the bond pads 84 on the package assembly 50 and using a similar process.

[0047] After bonding the second semiconductor die 86 to the corresponding first semiconductor die 86 to form the multi-chip stack 87, a redistribution structure 98 is formed over the package assembly 50, as previously described. Figure 3 and semiconductor die 106 is coupled to package assembly 50 using conductive connectors 116, as previously described in Figure 4A As described in . In an embodiment, the second semiconductor die 86 can be electrically connected to the redistribution structure 76 through, for example, bonding pads 97 and circuits and / or through vias disposed within the first semiconductor die 86. In an embodiment, after the second semiconductor die 86 is bonded to the corresponding first semiconductor die 86, and after the semiconductor die 106 is coupled to the package assembly 50 using the conductive connector 116, the top surface of the second semiconductor die 86 can be lower than the top surface of the semiconductor die 106. In an embodiment, the bonding pads 97 of each first semiconductor die 86 can have a third pitch P3 less than 9 μm, where the third pitch P3 is the distance from the center of the bonding pad 97 to the center of an adjacent bonding pad 97.

[0048] exist Figure 5AIn the embodiment of the present invention, an underfill 118 may be formed between a first portion of the redistribution structure 98A and each semiconductor die 106 disposed on the first portion of the redistribution structure 98A, and between a second portion of the redistribution structure 98B and each semiconductor die 106 disposed on the second portion of the redistribution structure 98B. The underfill 118 surrounds the conductive connector 116. In addition, the underfill 118 may surround portions of the UBM 104 and the die connector 114. The underfill 118 may be formed by a capillary flow process after coupling the semiconductor die 106 to the first and second portions of the redistribution structure 98A / 98B, or may be formed by a suitable deposition method before coupling the semiconductor die 106 to the first and second portions of the redistribution structure 98A / 98B. The material of the underfill 118 may include a polymer, an epoxy resin, a molded underfill, etc.

[0049] Further references Figure 5A After forming the bottom filler 118, an encapsulant 120 is formed on the various components of the integrated chip package 10. The encapsulant 120 may be a molding compound, an epoxy resin, etc., and may be applied by compression molding, transfer molding, etc. A curing step is performed to cure the encapsulant 120, such as thermal curing, ultraviolet (UV) curing, etc. In some embodiments, each of the semiconductor die 86 and the semiconductor die 106 is buried in the encapsulant 120, and after curing the encapsulant 120, a planarization step, such as grinding, may be performed to remove an excess portion of the encapsulant 120 that is located above the top surface of the semiconductor die 106. Therefore, in some embodiments, after the planarization step, the top surface of the semiconductor die 106 is exposed and flush with the top surface of the encapsulant 120. In an embodiment, the top surface of the semiconductor die 86 is located below the top surface of the encapsulant 120. In some embodiments, after the planarization step, the top surfaces of the semiconductor die 86 and the semiconductor die 106 may still be covered by the encapsulant 120.

[0050] Figure 5B An integrated chip package 10 according to an alternative embodiment is shown. Unless otherwise specified, the same reference numerals in this embodiment (and the embodiments discussed subsequently) represent Figures 1 to 5A The same components in the embodiments shown in the drawings are formed by the same process. Therefore, the process steps and applicable materials may not be repeated here. Figure 5B Examples and Figure 5A The embodiment of the present invention differs in that, in Figure 5BIn an embodiment of the present invention, the formation of the bottom filler 118 is omitted. The encapsulant 120 is formed on the various components of the integrated chip package 10. In an embodiment, the encapsulant 120 can also be used as an underfill, and fills the space between the first portion of the redistribution structure 98A and each semiconductor die 106 disposed on the first portion of the redistribution structure 98A, and fills the space between the second portion of the redistribution structure 98B and each semiconductor die 106 disposed on the second portion of the redistribution structure 98B. The encapsulant 120 also surrounds the conductive connector 116. In addition, the encapsulant 120 can surround portions of the UBM 104 and the die connector 114.

[0051] exist Figure 6 In the embodiment, a dielectric layer 122 is formed on the back side of the package component 50, such as on the substrate 70 and the exposed TV 74. The dielectric layer 122 may include silicon oxide, silicon nitride, etc. formed using any suitable method known in the art, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. In an embodiment, the dielectric layer may include a polymer formed using a spin coating process, such as polybenzoxazole (PBO), polyimide (PI), a polyimide derivative, etc. Figure 6 Additionally shown is the patterning of dielectric layer 122 to form openings exposing TV 74. In an embodiment, dielectric layer 122 may be patterned to form an opening exposing TV 74 by initially applying a photoresist ( Figure 6 A photoresist (not separately shown) is applied to the dielectric layer 122, and the photoresist is then exposed to a patterned energy source (e.g., a patterned light source) to cause a chemical reaction, thereby causing a physical change in those portions of the photoresist exposed to the patterned light source to form an opening exposing TV 74. A developer is then applied to the exposed photoresist to take advantage of the physical change and selectively remove the exposed portions of the photoresist or the unexposed portions of the photoresist, depending on the desired pattern, and the underlying exposed portions of the dielectric layer 122 are removed using, for example, a dry etching process. However, any other suitable method for patterning the dielectric layer 122 to form the opening may be utilized.

[0052] After dielectric layer 122 is formed and patterned, UBM 126 is formed for external connection to TV 74. UBM 126 may have a bump portion located on and extending along a major surface of dielectric layer 122, and a through-hole portion extending through dielectric layer 122 to physically and electrically couple TV 74 of package component 50. Thus, UBM 126 is electrically coupled to redistribution structure 76 and redistribution structure 98. UBM 126 may be formed of a conductive material deposited by CVD, physical vapor deposition (PVD), or the like, such as copper, aluminum, tungsten, silver, combinations thereof, or the like.

[0053] Further references Figure 6 , a conductive connector 128 is formed on the UBM 126. The conductive connector 128 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. The conductive connector 128 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 128 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 128 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal cover layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process. The conductive connector 128 may be used to electrically and physically couple the integrated chip package 10 to other external devices (e.g., a package substrate, etc.).

[0054] Fig. 7A An integrated chip package 10 according to an alternative embodiment is shown. Unless otherwise specified, the same reference numerals in this embodiment (and the embodiments discussed subsequently) represent Figures 1 to 6 The same components in the embodiments shown in the drawings are formed by the same process. Therefore, the process steps and applicable materials may not be repeated here. Fig. 7A Examples and Figure 6 The embodiment of Fig. 7A In the embodiment of the present invention, the formation of the first portion of the redistribution structure 98A and the second portion of the redistribution structure 98B is omitted. In addition, the formation of the UBM 104 is also omitted. Instead, the conductive connectors 116 are formed on the corresponding conductive pads 82 in the bonding layer 80 disposed on the package component 50. The conductive connectors 116 are electrically coupled to the redistribution structure 76 and the TV 74 through the conductive pads 82. In other embodiments, the conductive connectors 116 are formed on the corresponding conductive vias 182 disposed in the bonding layer 80, such as Figure 7B After forming the conductive connector 116, the semiconductor die 106 is formed as previously described in Figure 4A Electrical connections are made between each semiconductor die 106 and redistribution structures 76 and TVs 74 through conductive pads 82 or conductive vias 182 in a similar manner as described in and using similar processes as described in FIG.

[0055] Embodiments of the present disclosure have some advantageous features. Embodiments include methods suitable for forming a device package, wherein the method includes bonding at least one first semiconductor die (e.g., a first top die) to an interposer using a hybrid bonding configuration, wherein a first bonding pad of the first semiconductor die is bonded to a second bonding pad on the interposer by direct metal-to-metal bonding and electrically connected to the second bonding pad on the interposer. The hybrid bonding configuration also includes directly bonding the first bonding layer of the first semiconductor die to the second bonding layer on the interposer using dielectric-to-dielectric bonding. The method also includes coupling and electrically connecting at least one second semiconductor die (e.g., a second top die) to the interposer using a first conductive connector (such as a microbump, etc.). The first bonding pad and the second bonding pad may have a first spacing of less than 9 μm, wherein the first spacing is the distance from the center of the first bonding pad or the second bonding pad to the center of the adjacent first bonding pad or the second bonding pad, respectively. The first conductive connector may have a second spacing greater than the first spacing (e.g., greater than 30 μm), wherein the second spacing is the distance from the center of the first conductive connector to the center of the adjacent first conductive connector. One or more embodiments disclosed herein may include allowing semiconductor dies with different interconnection bandwidth requirements to be bonded to an interposer. For example, the first semiconductor die may be a graphics processing unit (GPU), a central processing unit (CPU), or the like that requires high input / output signal transmission capabilities. Because the first pitch is less than 9 μm, the first semiconductor die and the interposer can utilize a larger number of first bonding pads and second bonding pads per unit area to bond the first semiconductor die to the interposer, which allows for greater interconnection bandwidth and faster signal transmission between the first semiconductor die and the interposer. Since the first semiconductor die and the interposer utilize a larger number of first bonding pads and second bonding pads per unit area, the size of the device package can be reduced compared to if other types of conductive connectors (e.g., solder bumps) with a pitch larger than the first pitch are used to bond the first semiconductor die to the interposer. The second semiconductor die may be a memory die, etc. that may not require such high signal transmission capabilities. Then, it is sufficient to couple the second semiconductor die to the interposer using a first conductive connector with a second pitch while still meeting the interconnection bandwidth requirements. Furthermore, using the first conductive connector to couple the second semiconductor die to the interposer results in lower manufacturing costs and also results in better electrical connections between the second semiconductor die and the interposer, which improves device yield and reliability.Therefore, forming a device package by combining the use of first and second bonding pads and first and second bonding layers to bond a first semiconductor die (e.g., having a high interconnection bandwidth requirement) to an interposer, and using a first conductive connector to couple a second semiconductor die (e.g., having a lower interconnection bandwidth requirement than the first semiconductor die) to the interposer can allow for an overall reduction in device package size, a reduction in manufacturing costs, and improved device yield and reliability of the device package.

[0056] According to an embodiment, a package includes: a first die located above and bonded to a first side of a package component, wherein a first bond between the first die and the package component includes a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and a second bond between the first die and the package component includes a metal-to-metal bond between a first bonding pad of the first die and a second bonding pad on the package component; a first portion of a redistribution structure adjacent to the first die and located above the second bonding layer; and a second die located above the first portion of the redistribution structure and coupled to the first portion of the redistribution structure using a first conductive connector, wherein the first conductive connector is electrically connected to a first conductive pad in the second bonding layer. In an embodiment, a first pitch of the first bonding pad is less than 9 μm. In an embodiment, a second pitch of the first conductive connector is greater than the first pitch of the first bonding pad. In an embodiment, the second pitch of the first conductive connector is greater than 30 μm. In an embodiment, the package component includes an interposer, and wherein the interposer includes a semiconductor substrate. In an embodiment, the package component includes an active die. In an embodiment, the first die includes a logic die, and the second die includes a memory die. In an embodiment, in an embodiment, the package further includes: an underfill disposed between the second die and the first portion of the redistribution structure.

[0057] According to an embodiment, a package includes: a first multi-chip stack located above a first side of an interposer and bonded to the first side of the interposer, wherein a first bond between the first multi-chip stack and the interposer includes a dielectric-to-dielectric bond between a first bond layer of the first multi-chip stack and a second bond layer on the interposer, wherein the first multi-chip stack includes: a first die; and a second die located above the first side of the first die and bonded to the first side of the first die, wherein a second bond between the first die and the second die includes a dielectric-to-dielectric bond between a third bond layer of the second die and a fourth bond layer on the first die; and a third die located above the first side of the interposer and coupled to the first side of the interposer using a first conductive connector, wherein the first conductive connector includes a solder microbump. In an embodiment, a third bond between the first multi-chip stack and the interposer includes a metal-to-metal bond between a first bond pad of the multi-chip stack and a second bond pad on the interposer, and wherein a fourth bond between the first die and the second die includes a metal-to-metal bond between a third bond pad of the second die and a fourth bond pad on the first die. In an embodiment, a first spacing between the first bonding pad and the second bonding pad is less than 9 μm, and a second spacing between the first conductive connector is greater than 30 μm. In an embodiment, the package further comprises: a first portion of a redistribution structure disposed between the interposer and the third die. In an embodiment, the package further comprises: a bottom filler disposed between the first portion of the redistribution structure and the third die, wherein the bottom filler surrounds the first conductive connector. In an embodiment, a top surface of the first multi-chip stack is below a top surface of the third die. In an embodiment, the first die and the second die comprise a logic die, and the third die comprises a memory die.

[0058] According to an embodiment, a method for manufacturing a semiconductor device includes: bonding a first die to a package assembly, wherein bonding the first die to the package assembly includes directly bonding a first dielectric layer of the first die to a second dielectric layer on the package assembly, and directly bonding a first conductive connector of the first die to a second conductive connector on the package assembly; forming a first portion of a redistribution structure adjacent to the first die over the second dielectric layer; and coupling the second die to the first portion of the redistribution structure using a third conductive connector, wherein a first pitch of the first conductive connector and the second conductive connector is less than a second pitch of the third conductive connector. In an embodiment, the method further includes: forming an underfill disposed between the first portion of the redistribution structure and the second die, and wherein the underfill surrounds the third conductive connector. In an embodiment, the method further includes: sealing the first die and the second die in an encapsulant, wherein the encapsulant is disposed between the first portion of the redistribution structure and the second die, and wherein the encapsulant surrounds the third conductive connector. In an embodiment, the method further includes: planarizing the encapsulant to expose a top surface of the second die, wherein after planarization, the top surface of the first die is below the top surface of the second die. In an embodiment, a package assembly includes an active die.

[0059] Some embodiments of the present application provide a package, comprising: a first die located above a first side of a package component and bonded to the first side of the package component, wherein a first bond between the first die and the package component comprises a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and a second bond between the first die and the package component comprises a metal-to-metal bond between a first bonding pad of the first die and a second bonding pad on the package component; a first portion of a redistribution structure adjacent to the first die and located above the second bonding layer; and a second die located above the first portion of the redistribution structure and coupled to the first portion of the redistribution structure using a first conductive connector, wherein the first conductive connector is electrically connected to a first conductive pad in the second bonding layer.

[0060] In some embodiments, the first pitch of the first bonding pads is less than 9 μm. In some embodiments, the second pitch of the first conductive connector is greater than the first pitch of the first bonding pads. In some embodiments, the second pitch of the first conductive connector is greater than 30 μm. In some embodiments, the package assembly includes an interposer, and wherein the interposer includes a semiconductor substrate. In some embodiments, the package assembly includes an active die. In some embodiments, the first die includes a logic die and the second die includes a memory die. In some embodiments, the package further includes: a bottom filler disposed between the second die and the first portion of the redistribution structure.

[0061] Other embodiments of the present application provide a package, comprising: a first multi-chip stack, located above a first side of an interposer and bonded to the first side of the interposer, wherein the first bond between the first multi-chip stack and the interposer includes a dielectric-to-dielectric bond between a first bonding layer of the first multi-chip stack and a second bonding layer on the interposer, wherein the first multi-chip stack includes: a first die; and a second die, located above a first side of the first die and bonded to the first side of the first die, wherein the second bond between the first die and the second die includes a dielectric-to-dielectric bond between a third bonding layer of the second die and a fourth bonding layer on the first die; and a third die, located above the first side of the interposer and coupled to the first side of the interposer using a first conductive connector, wherein the first conductive connector includes a solder microbump.

[0062] In some embodiments, the third bond between the first multi-chip stack and the interposer comprises a metal-to-metal bond between a first bond pad of the multi-chip stack and a second bond pad on the interposer, and wherein the fourth bond between the first die and the second die comprises a metal-to-metal bond between a third bond pad of the second die and a fourth bond pad on the first die. In some embodiments, the first spacing between the first bond pad and the second bond pad is less than 9 μm, and the second spacing of the first conductive connector is greater than 30 μm. In some embodiments, the package further comprises: a first portion of a redistribution structure disposed between the interposer and the third die. In some embodiments, the package further comprises: an underfill disposed between the first portion of the redistribution structure and the third die, wherein the underfill surrounds the first conductive connector. In some embodiments, a top surface of the first multi-chip stack is below a top surface of the third die. In some embodiments, the first die and the second die comprise logic die, and the third die comprises a memory die.

[0063] Still other embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: bonding a first die to a packaging component, wherein bonding the first die to the packaging component comprises directly bonding a first dielectric layer of the first die to a second dielectric layer on the packaging component, and directly bonding a first conductive connector of the first die to a second conductive connector on the packaging component; forming a first portion of a redistribution structure adjacent to the first die above the second dielectric layer; and coupling a second die to the first portion of the redistribution structure using a third conductive connector, wherein a first spacing between the first conductive connector and the second conductive connector is less than a second spacing of the third conductive connector.

[0064] In some embodiments, the method further comprises: forming an underfill disposed between the first portion of the redistribution structure and the second die, and wherein the underfill surrounds the third conductive connector. In some embodiments, the method further comprises: encapsulating the first die and the second die in an encapsulant, wherein the encapsulant is disposed between the first portion of the redistribution structure and the second die, and wherein the encapsulant surrounds the third conductive connector. In some embodiments, the method further comprises: planarizing the encapsulant to expose a top surface of the second die, wherein, after planarizing, the top surface of the first die is below the top surface of the second die. In some embodiments, the package assembly comprises an active die.

[0065] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A package comprising: a first die positioned over and bonded to a first side of the package assembly, wherein a first bond between the first die and the package assembly comprises a dielectric-to-dielectric bond between a first bond layer of the first die and a second bond layer on the package assembly, and a second bond between the first die and the package assembly comprises a metal-to-metal bond between a first bond pad of the first die and a second bond pad on the package assembly; a first portion of a redistribution structure adjacent to the first die and over the second bonding layer; and A second die is located over the first portion of the redistribution structure and coupled to the first portion of the redistribution structure using a first conductive connector, wherein the first conductive connector is electrically connected to a first conductive pad in the second bonding layer.

2. The package according to claim 1, wherein: The first pitch of the first bonding pads is less than 9 μm.

3. The package according to claim 2, wherein: The second pitch of the first conductive connectors is greater than the first pitch of the first bonding pads.

4. The package according to claim 3, wherein: The second interval of the first conductive connecting members is greater than 30 μm.

5. The package according to claim 1, wherein: The package assembly includes an interposer, and wherein the interposer includes a semiconductor substrate.

6. The package according to claim 1, wherein: The package assembly includes an active die.

7. The package according to claim 1, wherein: The first die comprises a logic die and the second die comprises a memory die.

8. The package according to claim 1, further comprising: An underfill is disposed between the second die and the first portion of the redistribution structure.

9. A package comprising: a first multi-chip stack positioned over and bonded to a first side of an interposer, wherein a first bond between the first multi-chip stack and the interposer comprises a dielectric-to-dielectric bond between a first bonding layer of the first multi-chip stack and a second bonding layer on the interposer, wherein the first multi-chip stack comprises: a first die; and a second die over and bonded to the first side of the first die, wherein a second bond between the first die and the second die comprises a dielectric-to-dielectric bond between a third bonding layer of the second die and a fourth bonding layer on the first die; and A third die is positioned over the first side of the interposer and coupled to the first side of the interposer using first conductive connections, wherein the first conductive connections include solder microbumps.

10. A method for manufacturing a semiconductor device, the method comprising: Bonding a first die to a package assembly, wherein bonding the first die to the package assembly includes directly bonding a first dielectric layer of the first die to a second dielectric layer on the package assembly, and directly bonding a first conductive connector of the first die to a second conductive connector on the package assembly; forming a first portion of a redistribution structure adjacent to the first die over the second dielectric layer; and A second die is coupled to the first portion of the redistribution structure using a third conductive connector, wherein a first pitch of the first conductive connector and the second conductive connector is less than a second pitch of the third conductive connector.

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