Memory controller performing wear balancing and memory system

Abstract

In some aspects, a storage system includes a non-volatile storage device and a memory controller coupled to the non-volatile storage device. The nonvolatile memory device includes a plurality of memory groups. Each of the plurality of memory groups includes a plurality of memory cells. The memory controller is configured to perform at least one of the following: at least one of: the memory controller; performing a first wear balance process by swapping a first storage group of the plurality of storage groups and a second storage group of the plurality of storage groups based on a first group write count for the first storage group and a second group write count for the second storage group; or performing a second wear balance process by swapping a first memory cell of the plurality of memory cells and a second memory cell based on a first cell write count for the first memory cell and a second cell write count for the second memory cell of the plurality of memory cells.

Description

Technical Field

[0001] The present disclosure relates to a storage device and a method of operating the same.

[0002] Storage class memory (SCM) is a type of nonvolatile memory that bridges the gap between traditional volatile memory, such as dynamic random access memory (DRAM), and nonvolatile memory, such as NAND flash or hard drives. SCM combines the advantages of both types, providing low latency, high-speed data access similar to DRAM, as well as the persistence and higher capacity typically found in nonvolatile storage. SCMs are increasingly being adopted in data centers and other high-performance computing environments, where they help reduce latency, improve overall system efficiency, and provide more effective data management solutions. Summary of the invention

[0003] In one aspect, a memory system includes a nonvolatile memory device and a memory controller coupled to the nonvolatile memory device. The nonvolatile memory device includes a plurality of memory groups. Each of the plurality of memory groups includes a plurality of memory cells. The memory controller is configured to perform at least one of the following: performing a first wear leveling process by swapping the first memory group and the second memory group based on a first group write count for a first memory group in the plurality of memory groups and a second group write count for a second memory group in the plurality of memory groups; or performing a second wear leveling process by swapping the first memory cell and the second memory cell based on a first cell write count for a first memory cell in the plurality of memory cells and a second cell write count for a second memory cell in the plurality of memory cells.

[0004] In some implementations, each storage unit in the plurality of storage units corresponds to a codeword.

[0005] In some embodiments, the memory controller is configured to exchange the first storage group and the second storage group by exchanging data of the first storage group and data of the second storage group, and to exchange a first physical group address of the first storage group and a second physical group address of the second storage group.

[0006] In some embodiments, to read the M data pages, the peripheral circuit includes a word line driver, which is coupled to the selection row through a selection word line among the word lines and is configured to apply an adjusted read voltage between the two threshold voltage ranges to the selection word line.

[0007] In some embodiments, the memory controller is configured to exchange the first storage unit and the second storage unit by exchanging data of the first storage unit and data of the second storage unit, and to exchange a first physical unit address of the first storage unit and a second physical unit address of the second storage unit.

[0008] In some embodiments, the storage system further comprises a volatile storage device. In some embodiments, the memory controller is configured to: monitor a group write count for each storage group of the non-volatile storage device; and store the group write count in the volatile storage device. In some embodiments, the first group write count for the first storage group in the group write count is a maximum group write count in the group write count, and the second group write count for the second storage group in the group write count is a minimum group write count in the group write count.

[0009] In some implementations, the group write count for each memory group of the nonvolatile memory device is an average cell write count of the plurality of memory cells in the memory group.

[0010] In some implementations, the memory controller is configured to perform the first wear leveling process in response to a difference between the first group write count and the second group write count being greater than a group count threshold.

[0011] In some implementations, the memory controller is configured to: after the first wear leveling process, reduce the first group write count for the first storage group by a preset value.

[0012] In some implementations, the memory controller is configured to: after the first wear leveling process, increase the second group write count for the second storage group by a preset value.

[0013] In some embodiments, the memory controller is configured to store a group mapping table between a logical group address and a physical group address of each storage group in the volatile storage device. In some embodiments, for each storage group, the logical group address and the physical group address are the same before the first wear leveling process.

[0014] In some implementations, the memory controller is configured to update the group mapping table by swapping the first physical group address of the first storage group and the second physical group address of the second storage group after the first wear leveling process.

[0015] In some embodiments, the memory controller is configured to: monitor a cell write count for each memory cell of the nonvolatile memory device; and store the cell write count in the nonvolatile memory device. In some embodiments, the first cell write count for the first memory cell in the cell write count is a maximum cell write count in the cell write count, and the second cell write count for the second memory cell in the cell write count is a minimum cell write count in the cell write count.

[0016] In some implementations, the memory controller is configured to perform the second wear leveling process in response to a difference between the first cell write count and the second cell write count being greater than a cell count threshold.

[0017] In some implementations, the memory controller is configured to reduce the first cell write count for the first storage cell by a preset value after the second wear leveling process.

[0018] In some implementations, the memory controller is configured to: after the second wear leveling process, increase the second cell write count for the second storage cell by a preset value.

[0019] In some embodiments, the memory controller is configured to: for each storage group, store a cell mapping table between a logical cell address and a physical cell address of each storage cell in the storage group in the non-volatile storage device. In some embodiments, for each storage cell, the logical cell address and the physical cell address are the same before the second wear leveling process.

[0020] In some implementations, the memory controller is configured to update the cell mapping table by swapping the first physical cell address of the first memory cell and the second physical cell address of the second memory cell after the second wear leveling process.

[0021] In some implementations, the memory controller is further configured to: store a swap bitmap in the volatile memory device, the swap bitmap indicating a swap index of each memory group of the non-volatile memory device.

[0022] In some embodiments, in response to not performing the second wear leveling process for the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a default value. In some embodiments, in response to performing the second wear leveling process for the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a swap value.

[0023] In some implementations, the memory controller is configured to: retrieve the cell mapping table of the storage group from the non-volatile storage device in response to the swap index of the storage group being the swap value; and store the cell mapping table in the volatile storage device.

[0024] In some embodiments, each storage unit of the plurality of storage units comprises a SCM unit.

[0025] In another aspect, a method for operating a nonvolatile memory device is provided. The nonvolatile memory device includes a plurality of memory groups. Each of the plurality of memory groups includes a plurality of memory cells. At least one of the following is performed: (i) performing a first wear leveling process by swapping the first memory group and the second memory group based on a first group write count for a first memory group in the plurality of memory groups and a second group write count for a second memory group in the plurality of memory groups; or (ii) performing a second wear leveling process by swapping the first memory cell and the second memory cell based on a first cell write count for a first memory cell in the plurality of memory cells and a second cell write count for a second memory cell in the plurality of memory cells.

[0026] In some implementations, each storage unit in the plurality of storage units corresponds to a codeword.

[0027] In some embodiments, in order to exchange the first storage group and the second storage group, data of the first storage group and data of the second storage group are exchanged, and a first physical group address of the first storage group and a second physical group address of the second storage group are exchanged.

[0028] In some embodiments, in order to exchange the first storage unit and the second storage unit, data of the first storage unit and data of the second storage unit are exchanged, and a first physical unit address of the first storage unit and a second physical unit address of the second storage unit are exchanged.

[0029] In some embodiments, a group write count for each storage group of the non-volatile storage device is monitored; and the group write count is stored in a volatile storage device. In some embodiments, the first group write count for the first storage group in the group write count is a maximum group write count in the group write count, and the second group write count for the second storage group in the group write count is a minimum group write count in the group write count.

[0030] In some implementations, the group write count for each memory group of the nonvolatile memory device is an average cell write count of the plurality of memory cells in the memory group.

[0031] In some implementations, the first wear leveling process is performed in response to a difference between the first group write count and the second group write count being greater than a group count threshold.

[0032] In some implementations, after the first wear leveling process, the first group write count for the first storage group is reduced by a preset value.

[0033] In some implementations, after the first wear leveling process, the second group write count for the second storage group is increased by a preset value.

[0034] In some embodiments, a group mapping table between a logical group address and a physical group address of each storage group is stored in the volatile storage device. In some embodiments, for each storage group, the logical group address and the physical group address are the same before the first wear leveling process.

[0035] In some implementations, the group mapping table is updated after the first wear leveling process by swapping the first physical group address of the first storage group and the second physical group address of the second storage group.

[0036] In some embodiments, a cell write count for each memory cell in the nonvolatile memory device is monitored; and the cell write count is stored in the nonvolatile memory device. In some embodiments, the first cell write count for the first memory cell in the cell write count is a maximum cell write count in the cell write count, and the second cell count for the second memory cell in the cell write count is a minimum cell write count in the cell write count.

[0037] In some implementations, the second wear leveling process is performed in response to a difference between the first cell write count and the second cell write count being greater than a cell count threshold.

[0038] In some implementations, after the second wear leveling process, the first cell write count for the first storage cell is reduced by a preset value.

[0039] In some implementations, after the second wear leveling process, the second cell write count for the second storage cell is increased by a preset value.

[0040] In some embodiments, for each storage group, a cell mapping table between a logical cell address and a physical cell address of each storage cell in the storage group is stored in the non-volatile storage device. In some embodiments, for each storage cell, the logical cell address and the physical cell address are the same before the second wear leveling process.

[0041] In some implementations, the cell mapping table is updated after the second wear leveling process by swapping the first physical cell address of the first memory cell with the second physical cell address of the second memory cell.

[0042] In some embodiments, a swap bitmap is stored in the volatile memory device. In some embodiments, the swap bitmap indicates a swap index for each storage group of the non-volatile memory device.

[0043] In some implementations, in response to not performing a second wear leveling process on the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a default value.

[0044] In some implementations, in response to performing the second wear leveling process on the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a swap value.

[0045] In some implementations, in response to the swap index of the storage group being the swap value, retrieving the unit mapping table of the storage group from the non-volatile storage device; and storing the unit mapping table in the volatile storage device.

[0046] In another aspect, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions that, when executed by a memory controller, cause the memory controller to perform at least one of the following: (i) performing a first wear leveling process by swapping a first storage group and a second storage group of a non-volatile storage device based on a first group write count for a first storage group and a second group write count for a second storage group of the non-volatile storage device, each of the first storage group and the second storage group including a plurality of storage cells; or (ii) performing a second wear leveling process by swapping the first storage cell and the second storage cell based on a first cell write count for a first storage cell of the plurality of storage cells and a second cell write count for a second storage cell of the plurality of storage cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate certain aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0048] Figure 1 A block diagram of a system including a storage system according to some aspects of the present disclosure is shown.

[0049] Figure 2 A schematic diagram of an SCM device according to some aspects of the present disclosure is shown.

[0050] Figure 3 A perspective view of a phase change memory (PCM) cell array is shown in accordance with some aspects of the present disclosure.

[0051] Figure 4 A detailed diagram of an SCM device according to some aspects of the present disclosure is shown.

[0052] Figure 5 A detailed diagram of a memory system including a memory controller that performs two-level wear leveling according to some aspects of the present disclosure is shown.

[0053] Figure 6 Codewords according to some aspects of the present disclosure are shown.

[0054] Figure 7 A block including multiple codewords is shown in accordance with some aspects of the present disclosure.

[0055] Figure 8 A detailed diagram of a memory controller is shown in accordance with some aspects of the present disclosure.

[0056] Fig.9A and Fig. 9B An L2P block table is shown before and after performing block-level wear leveling, respectively, according to some aspects of the present disclosure.

[0057] Fig. 10A and Fig. 10B An L2P codeword table is shown respectively before and after performing codeword level wear leveling according to some aspects of the present disclosure.

[0058] Fig.11 An exchange bitmap according to some aspects of the present disclosure is shown.

[0059] Fig.12 A flow chart of a method for operating a non-volatile storage device according to some aspects of the present disclosure is shown.

[0060] Fig.13A flow chart of a method for performing block-level wear leveling according to some aspects of the present disclosure is shown.

[0061] Fig.14 A flow chart of a method for performing codeword-level wear leveling according to some aspects of the present disclosure is shown.

[0062] Fig.15 A flow chart of a method for performing read / write operations according to some aspects of the present disclosure is shown.

[0063] Fig.16 A scheme for dynamic wear leveling is shown.

[0064] Fig.17 A scheme for static wear leveling is shown.

[0065] Fig.18 A scheme for updating a logical-to-physical (L2P) table for NAND flash memory is shown.

[0066] Fig.19 A scheme for updating the L2P table for an SCM according to some aspects of the present disclosure is shown.

[0067] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0068] Typically, a term can be understood, at least in part, from its use in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "one," "an," or "the" may be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. In addition, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but may instead depend, at least in part, on the context, allowing for the presence of other factors that are not necessarily explicitly described.

[0069] Data types such as hot data, warm data, and cold data affect the durability of storage products. Hot data will stress media with high program / erase (P / E) cycles, while cold data will protect media with low P / E cycles in storage products, such as NAND flash-based embedded multimedia cards (eMMC), universal flash storage (UFS), and solid-state drive (SSD) systems. How to uniformly stress all physical resources is handled by the wear leveling algorithm in storage products. Wear leveling is a technology used to ensure that P / E cycles are evenly distributed among all physical resources (e.g., storage blocks). This is important because the storage cells in storage products can withstand a limited number of P / E cycles before their reliability degrades or becomes unavailable. The wear leveling algorithm works by tracking the number of P / E cycles performed on each storage block and trying to evenly distribute write and erase operations across all blocks. When data needs to be written or updated, the wear leveling algorithm selects blocks with lower wear counts (i.e., fewer P / E cycles) to help balance the wear of the entire storage device.

[0070] In the current wear leveling algorithm, if the host does not notify the data type, the storage system will not know the data type (e.g., hot data, warm data, or cold data) of the data written by the host. For example, in a NAND flash memory system, the memory controller will record the P / E life cycle of each physical block. The memory controller will then perform dynamic wear leveling by using free blocks with smaller P / E life cycles, or perform static wear leveling by swapping data in younger physical blocks (with smaller P / E counts) to older physical blocks (with larger P / E counts) when the P / E life cycle gap is large enough and releasing the newer blocks for use. For example, Fig.16 As shown, under the dynamic wear leveling scheme, the free block list is sorted from the head (e.g., PE=6) to the tail (e.g., PE=66) according to the P / E count, so that the head with the smallest P / E cycle is always used as an open block for writing host data, regardless of the data type (e.g., hot data, warm data, or cold data). Fig.17 As shown, under the static wear leveling scheme, when the P / E life cycle gap (e.g., the maximum P / E cycle minus the minimum P / E cycle) becomes greater than a threshold, the youngest used block with data (e.g., PE=1) is released as the head of the free block list, and the data therein is copied to the tail of the free block list with the maximum P / E cycle (e.g., PE=66).

[0071] However, in the current wear leveling algorithm, the memory controller does not use different schemes to handle different types of data (such as heat), but only handles the consequences of large P / E life cycle gaps from different types of data because of the limitations of block erase and page programming and reading. For example, for NAND flash storage products, data cannot be rewritten to the same physical page without block erase. Fig.18 As shown in FIG. 1 , when the host writes data using the same logical block address (LBA, such as LBA 0), the data will be rewritten to a different physical page address (PPA, such as PPA=0, PPA=8, PPA=100, PPA=500). Since LBA and PPA have no fixed relationship, the program / write cycle count (also called write count) of the physical address is different from the program / write cycle count of the logical address known to the memory controller. Therefore, the write count cannot be used as an indicator of the heat of the host data.

[0072] To solve one or more of the above problems, the present disclosure proposes a two-level wear leveling scheme based on write counts of physical resources of different granularities to increase the durability of storage products. In some embodiments, since the write count can reflect the heat of the host data in the SCM product, the wear leveling scheme disclosed herein that takes into account the heat of the host data can be used to achieve better durability of the SCM product. In some embodiments, the write counts of physical resources of different granularities (e.g., physical codewords, blocks, etc.) can be used by the wear leveling schemes of the corresponding levels to achieve more accurate management of wear leveling, thereby making the SCM pressurization more uniform. In some embodiments, different levels of exchange bitmaps and L2P mapping tables are introduced to manage the data exchange relationship in wear leveling.

[0073] Figure 1 A block diagram of a system 100 including a storage system 102 according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1As shown, the system 100 may include a host 108 and a storage system 102 having one or more storage devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the storage system 102 or receive data (also referred to as user data or host data) from the storage system 102. The storage system 100 may be a storage product that integrates a memory controller 106 and one or more storage devices, such as an SCM system.

[0074] The storage device 104 may be any storage device disclosed in the present disclosure, including a non-volatile storage device, such as an SCM device. In some embodiments, the storage device 104 also includes one or more volatile storage devices, such as a DRAM device or a static random access memory (SRAM) device.

[0075] According to some embodiments, the memory controller 106 is coupled to the storage device 104 and the host 108, and is configured to control the storage device 104. The memory controller 106 can manage the data stored in the storage device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment SSD or eMMC as data storage for mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 106 can be configured to control the operation of the storage device 104, such as read, program / write and / or erase operations. The memory controller 106 can also be configured to manage various functions about the data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, L2P address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to: process error correction code (ECC) for data read from or written to the storage device 104. Any other suitable function can also be performed by the memory controller 106, for example, formatting the storage device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device through at least one of various interface protocols, such as a high-speed non-volatile memory express (NVMe) protocol, an NVMe over fiber (NVMe-oF) protocol, a PCI Express (PCI-E) protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.

[0076] Consistent with the scope of the present disclosure and disclosed in detail below, the memory controller 106 may be configured to perform block-level wear leveling based on block-level write counts, and / or to perform codeword-level wear leveling based on codeword-level write counts. According to some embodiments, to facilitate different levels of write-count-based wear leveling, the memory controller 106 is further configured to manage various data structures, such as different levels of L2P mapping tables and swap bitmaps.

[0077] Figure 2 A schematic diagram of an SCM device 200 according to some aspects of the present disclosure is shown. The SCM device 200 may be Figure 12 is an example of a memory device 104 in FIG. The SCM device 200 may include an SCM cell array 202 and a peripheral circuit 204 coupled to the SCM cell array 202. The SCM cell array 202 may include a word line (WL) 206, a bit line (BL) 208, and an SCM cell 210 at a cross point between the word line 206 and the bit line 208. In some embodiments, each SCM cell 210 includes an SCM element 212 connected in series with an access device 214 (also referred to as a selector). The SCM element 212 may be configured to store binary data (e.g., 0 and 1) persistently, for example, by maintaining a continuous, analog value, such as a voltage or charge, even when power is interrupted or turned off. According to some embodiments, the SCM element 212 includes, but is not limited to, a PCM element, a resistive memory element, a magnetoresistive memory element, a ferroelectric memory element, a spin transfer torque (STT) memory element, and the like. The access device 214 may be configured to control access of the peripheral circuit 204 to the corresponding SCM element 212. According to some embodiments, the access device 214 includes, but is not limited to, a transistor, a diode, an otto switch (OTS), a mixed ion-electron conductor (MIEC), a conductive oxide tunnel barrier, and the like.

[0078] like Figure 2 As shown, the SCM cell array 202 may include an array of SCM cells 210 in rows and columns. The rows of the SCM cells 210 may be respectively coupled to word lines 206, and the columns of the SCM cells 210 may be respectively coupled to bit lines 208. The peripheral circuit 204 may be coupled to the SCM cell array 202 via the bit lines 208 and the word lines 206.

[0079] Peripheral circuits 204 may include any suitable analog, digital, and mixed signal circuits for facilitating operation of SCM cell array 202 by applying and sensing voltage signals and / or current signals to SCM cells 210 through bit lines 208 and word lines 206. Peripheral circuits 204 may include various types of peripheral circuits formed using metal oxide semiconductor (MOS) technology.

[0080] It should be understood that, depending on the underlying memory technology forming the SCM element 212, the SCM device 200 may include any suitable type of SCM device, such as a PCM device, a resistive RAM (ReRAM) device, a magnetoresistive RAM (MRAM) device, a ferroelectric RAM (FeRAM) device, an STT-RAM device, etc. It should also be understood that the SCM device 200 is an example of a non-volatile memory device and can be extended to any other suitable non-volatile memory device, including a non-volatile memory (NVM) cell array having an NVM element and an access device.

[0081] Figure 3A perspective view of a PCM cell array 300 is shown according to some aspects of the present disclosure. The PCM cell array 300 may be Figure 2 The PCM cell array 300 may be formed in a three-dimensional (3D) vertical chain cell type architecture, wherein an access device 310 and a PCM element 308 forming a PCM cell 306 are connected in series and located at the intersection of a word line 302 and a bit line 304, as shown in FIG. Figure 3 It should be noted that Figure 3 The x-axis and y-axis are included in the figure to illustrate the two orthogonal directions in the wafer plane. The x-direction is the word line direction, while the y-direction is the bit line direction. It should be noted that the z-axis is also included in the figure. Figure 3 300 to further illustrate the spatial relationship of the components in the PCM cell array 300. The substrate (not shown) of the PCM cell array 300 includes two side surfaces extending laterally in the xy plane: a top surface on the front side of the wafer and a bottom surface on the back side opposite to the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when the substrate is located in the lowest plane of the semiconductor device in the z-direction, whether a component (e.g., a layer or a device) is "on", "above" or "below" another component (e.g., a layer or a device) of the semiconductor device (e.g., PCM cell array 300) is determined in the z-direction (vertical direction perpendicular to the xy plane) relative to the substrate of the semiconductor device. The same concept for describing spatial relationships is applied throughout this disclosure.

[0082] In some embodiments, PCM cell array 300 includes parallel word lines 302 and parallel bit lines 304 in different planes in a vertical direction. According to some embodiments, each bit line 304 extends laterally along the bit line direction in a plan view (parallel to the wafer plane), and each word line 302 extends laterally along the word line direction in a plan view. Therefore, each word line 302 can be perpendicular to each bit line 304.

[0083] like Figure 3 As shown, according to some embodiments, the PCM cell array 300 includes a plurality of PCM cells 306, each of which is disposed at the intersection of a bit line 304 and a corresponding word line 302. Each PCM cell 306 may have a vertical column shape. In some embodiments, each PCM cell 306 includes a vertically stacked PCM element 308 and an access device 310. Each PCM cell 306 may store data, which may be written or read by changing a voltage applied to a corresponding access device 310. Each PCM cell 306 may be individually accessed via a current applied through top and bottom conductors in contact with each PCM cell 306 (e.g., a corresponding word line 302 and a bit line 304).

[0084] In some embodiments, the PCM element 308 is a chain unit type PCM element, which includes a polysilicon transistor and a phase layer connected in parallel. The polysilicon transistor and the phase layer can be formed by a gate oxide layer, a channel polysilicon, and a phase change material formed on the hole side of the stacked gate 312. In some embodiments, the access device 310 is a polysilicon diode. In a write operation, a turn-off voltage can be applied to the selected gate 312, and a positive turn-on voltage can be applied to the unselected gate 312. When a set / reset pulse voltage is applied to the drain, a current can flow through the phase change layer at the selected gate 312, and the temperature can be increased by Joule heating, thereby causing a set / reset state. Similarly, by applying a voltage suitable for a read operation to the drain, the resistance of the phase change layer at the select gate 312 can be determined.

[0085] It should be understood that the PCM cell array 300 can be formed in any other suitable 2D or 3D architecture (e.g., a lateral chain cell type architecture or a 3D crosspoint (XPoint) architecture). It should also be understood that the PCM element 308 can include any other suitable PCM element, such as a phase layer vertically stacked between two carbon electrodes. It should also be understood that the access device 310 can include any other suitable access device, such as an OTS selector.

[0086] The SCM device can be divided into multiple physical modules, each of which includes an SCM cell array and peripheral circuits for the corresponding SCM cell array to achieve parallel processing of the SCM device. The physical module can be a die and / or a memory bank. For example, Figure 4 A detailed diagram of an SCM device 400 is shown according to some aspects of the present disclosure. The SCM device 400 may be Figure 2 An example of an SCM device 200 in FIG. Figure 4 As shown, the SCM device 400 may be divided into a plurality of memory banks 402 (e.g., 0, 1, 2, and 3), each memory bank including an SCM cell array 404. Although not shown, it is understood that in some examples, the plurality of memory banks 402 may be on the same die, and the SCM device 400 may include a plurality of dies, each die including a plurality of memory banks 402.

[0087] In some embodiments, each memory bank 402 further includes peripheral circuits for each SCM cell array 404, including a data buffer / sense amplifier 406, a column decoder / bit line driver 408, a row decoder / word line driver 410, a control logic 412, a register 414, an interface (I / F) 416, and a data bus 418. It should be understood that in some examples, the memory bank 402 may also include Figure 4 Additional peripheral circuits not shown may include voltage generators, charge pumps, and any suitable type of bus.

[0088] The data buffer / sense amplifier 406 may be configured to sense (read) data from and program (write) data to the SCM cell array 404 according to control signals from the control logic 412. For example, the sense amplifier may detect small voltage or current changes in the SCM cell array 404 during a read operation, while the data buffer may temporarily store data read from or written to the SCM cell array 404.

[0089] The column decoder / bit line driver 408 may be configured to be controlled by an address signal from the control logic 412 and to select / deselect one or more columns of SCM cells in the SCM cell array 404 by applying a bit line voltage to a corresponding bit line. The column decoder / bit line driver 408 may also be configured to drive a selected bit line. The row decoder / word line driver 410 may be configured to be controlled by an address signal from the control logic 412 and to select / deselect one or more rows of SCM cells in the SCM cell array 404 by applying a word line voltage to a corresponding word line. The row decoder / word line driver 410 may also be configured to drive a selected word line.

[0090] The control logic 412 may be coupled to each of the above-mentioned peripheral circuits and configured to control the operation of each peripheral circuit. The control logic 412 may include fixed logic units, such as logic gates, multiplexers, flip-flops, state machines, or discrete hardware circuits that perform given logic functions known at the time of device manufacture. In some embodiments, the control logic 412 is implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, a gated logic, a discrete hardware circuit, and other suitable hardware, firmware, and / or software configured to perform the various functions described herein.

[0091] Registers 414 may be coupled to control logic 412 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. Interface 416 may be coupled to control logic 412 and act as a control buffer to control the slave memory controller (not shown, for example, Figure 1 106) and / or a host (not shown, e.g., Figure 1The interface 416 may receive control commands from the control logic 412 from the host 108 in the SCM unit array 404 and receive status information from the memory controller and / or the host from the control logic 412 for buffering and relaying. The interface 416 may also be coupled to the data buffer / sense amplifier 406 via the data bus 418 and act as a data input / output (I / O) interface and data buffer to buffer and relay data to and from the SCM unit array 404.

[0092] and Fig.18 Unlike NAND flash storage products shown, where the same LBA is mapped to different PPAs, for SCM systems, such as PCM storage products, the same LBA is mapped to the same PPA by default, because data can be rewritten on the same physical page. Unlike NAND flash, PCM cells do not need to be erased before being rewritten; there is no erase operation for PCM memory. Fig.19 As shown, when the host writes data using the same LBA (e.g., LBA 0), the data is rewritten to the same physical page address (e.g., PPA=0) each time. Since the LBA and PPA have a fixed relationship, the program / write cycle count (also referred to as the write count) of the physical address is the same as the program / write cycle count of the logical address known to the memory controller. Therefore, the write count can be used as an indicator of the heat of the host data of the SCM system (e.g., PCM storage product). Consistent with the scope of the present disclosure, the write count is used as a factor in the improvement scheme of wear leveling, as disclosed in detail below.

[0093] Figure 5 A detailed diagram of a memory system 500 including a memory controller 502 that performs two-level wear leveling according to some aspects of the present disclosure is shown. The memory system 500 may be Figure 1 An example of a memory system 102 in FIG. 1 , and the memory controller 502 may be Figure 1 The memory system 500 may also include one or more non-volatile memory devices 504 and one or more volatile memory devices 506. The non-volatile memory devices 504 and the volatile memory devices 506 may be Figure 1 In some embodiments, non-volatile storage device 504 includes an SCM device, such as SCM devices 200 and 400, or any SCM device disclosed herein. In some embodiments, volatile storage device 506 includes DRAM or SRAM. It should be understood that although Figure 5 The volatile storage device 506 in FIG. 5 is shown as a standalone device separate from the memory controller 502 , but in some examples, part or all of the volatile storage device 506 may be part of the memory controller 502 .

[0094] like Figure 5 As shown, the memory controller 502 may include a wear balancing module 508, a write counting module 510, and an L2P module 512. Each of the wear balancing module 508, the write counting module 510, and the L2P module 512 may be implemented as a firmware module in the form of code or instructions, which may be executed by a processing unit (e.g., a microcontroller unit (MCU)). Additionally or alternatively, each of the wear balancing module 508, the write counting module 510, and the L2P module 512 may be implemented as an ASIC, including digital circuits, analog circuits, and / or mixed signal circuits. The wear balancing module 508 may also include two sub-modules, each of which is configured to control the wear balancing of the non-volatile storage device 504 at two different levels, such as a block wear balancing module 514 and a codeword wear balancing module 516. It should be understood that the number of sub-modules and / or the level of each sub-module may vary in different examples depending on the desired granularity for managing wear balancing.

[0095] Consistent with the scope of the present disclosure, in order to enable the non-volatile storage device 504 to perform wear leveling at different levels, the storage units of the non-volatile storage device 504 are organized at different levels, including storage groups and storage units. In some embodiments, the non-volatile storage device 504 includes a plurality of storage groups, and each storage group includes a plurality of storage units. In other words, according to some embodiments, the storage units of the non-volatile storage device 504 are divided into higher-level storage groups, and the plurality of storage units in each storage group are further divided into lower-level storage units. Figure 5 As shown, in some implementations, each storage group corresponds to a block 518 , and each storage unit corresponds to a codeword 520 including a plurality of pages 522 .

[0096] refer to Figure 6 , codeword 520 may be a single operation size in storage system 500. In other words, codeword 520 may be a basic unit for performing a write operation in storage system 500. For example, the size of codeword 520 may be 512 bytes, 4,096 bytes, 16,384 bytes, etc. Codeword 520 may be a single error correction code (ECC) codeword or a combination of multiple ECC codewords. In one example, codeword 520 may be a combination of 16 ECC codewords (each codeword having a size of 256 bytes) having a size of 4,096 bytes. Figure 6As shown, the codeword 520 may include multiple pages of user / host data 602 and multiple pages of spare data 604. In one example, the user / host data 602 of each codeword 520 may come from pages and / or dies with the same page number (e.g., page 0) of each memory bank (e.g., memory bank 0, memory bank 1, memory bank 2, and memory bank 3). Each page may correspond to a group of memory cells in the non-volatile memory device 504, referred to herein as a "physical page". Therefore, the codeword 520 may be referred to herein as a "logical codeword" known to the memory controller 502 or a "physical codeword" corresponding to multiple physical pages (a group of memory cells) in the non-volatile memory device 504. The spare data 604 may include parity data 608 for ECC and metadata 606, such as a write count of the codeword 520. For example, each time the memory controller 502 controls the non-volatile memory device 504 to perform a write operation on the codeword 520, the word count of the codeword 520 may be increased by 1. Therefore, the word count of each codeword 520 may indicate the temperature of the corresponding physical page (a group of memory cells) in the non-volatile storage device 504 .

[0097] refer to Figure 7 , block 518 can be a combination of multiple codewords 520 (e.g., n codewords). Similar to codewords 520, block 518 may be referred to herein as a "logical block" known to the memory controller 502 or a "physical block" corresponding to multiple physical codewords (a set of physical pages) in the non-volatile storage device 504. In one example, a physical block may include rows and / or columns of SCM cells in an SCM device. Since each codeword 520 in block 518 includes a corresponding word count, the heat of the codeword 520 can be indicated by the average word count of all codewords 520 in block 518. It should be understood that blocks 518, codewords 520, and pages 522 are used as examples of possible organizations and hierarchies of multiple storage cells in the non-volatile storage device 504 for different levels of wear leveling, and any other examples of organizations and hierarchies may also be applicable to the wear leveling schemes disclosed herein.

[0098] Return to reference Figure 5, the volatile storage device 506 can store various data structures for managing the wear leveling scheme disclosed herein, including a write count 528, an L2P table 530, and a swap bitmap 532. In some embodiments, the write count 528 includes a group write count of a storage group (e.g., a block 518) and a unit write count of a storage cell (e.g., a codeword 520) within the storage group. The write count module 510 of the memory controller 502 can be configured to manage the write count 528, for example, by monitoring the write count 528 and storing the write count 528 in the volatile storage device 506. As described above, the metadata 606 of the codeword 520 can store the corresponding write count. That is, the write count module 510 can also be configured to monitor the unit write count of each storage cell (e.g., a storage cell corresponding to the codeword 520) and store the unit write count in the non-volatile storage device 504 (e.g., in the metadata 606 of the codeword 520). Due to the large number of codewords 520 in the non-volatile storage device 504, the size of the unit write counts of all codewords 520 may be too large to be loaded into the volatile storage device 506 at the same time. Therefore, in some embodiments, only some of the unit write counts are loaded into the volatile storage device 506 by the write count module 510 as the write count 528.

[0099] As described above, the average cell write count of all storage cells in the storage group can be used as the group write count of the storage group to indicate the heat of the data in the storage group. In some embodiments, the write count module 510 is configured to monitor the group write count of each storage group (e.g., the storage cells corresponding to the block 518), and if the number of group write counts is acceptable to the volatile storage device 506, the group write count is directly stored in the volatile storage device 506. For example, for each block 518, the write count module 510 can monitor the cell write count of each codeword 520, and update the average cell write count (group write count) of the block 518 as the cell write count changes.

[0100] In some embodiments, the write count module 510 is further configured to determine the maximum write count and the minimum write count of the different levels of write counts 528. In one example, the write count module 510 can determine the hottest block 518 with the largest group write count and the coldest block 518 with the smallest group write count. Similarly, within each block 518, the write count module 510 can determine the hottest codeword 520 with the largest unit write count and the coldest codeword 520 with the smallest unit write count. The maximum write count and the minimum write count can be used as a trigger to start wear leveling and as a tag to identify the block 518 and / or codeword 520 on which wear leveling is performed.

[0101] In some embodiments, the block wear balancing module 514 of the memory controller 502 is configured to perform block wear balancing in response to the difference between the maximum group write count and the minimum group write count being greater than the group count threshold. That is, when the group write count gap exceeds the preset threshold, the block wear balancing module 514 can initiate block wear balancing between blocks 518. In some embodiments, the block wear balancing module 514 performs block wear balancing by swapping the hottest block 518 (with the maximum group write count) and the coldest block 518 (with the minimum group write count). Alternatively or additionally, in some embodiments, the codeword wear balancing module 516 of the memory controller 502 is configured to perform codeword wear balancing in response to the difference between the maximum unit write count and the minimum unit write count being greater than the unit count threshold. That is, when the unit write count gap exceeds the preset threshold, the codeword wear balancing module 516 can initiate codeword wear balancing between codewords 520 within the block 518. In some implementations, the codeword wear leveling module 516 performs codeword wear leveling by swapping the hottest codeword 520 (having the largest cell write count) and the coldest codeword 520 (having the smallest cell write count).

[0102] As described above, according to some embodiments, the block 518 is referred to as a logical block by the memory controller 502, while the block wear leveling is performed on the physical block. Therefore, the L2P table 530 stored in the volatile storage device 506 may include a group mapping table between the logical group address and the physical group address of each storage group (e.g., the block L2P table of the non-volatile storage device 504). Fig.9A As shown, for example, the block L2P table can map each logical block address to a corresponding physical block address (e.g., 0 to 0, 1 to 1, ..., N to N). The L2P module 512 of the memory controller 502 can be configured to maintain and manage the group mapping table and store the group mapping table as part of the L2P table 530 in the volatile storage device 506, because there is only one group mapping table for the non-volatile storage device 504.

[0103] Similarly, according to some embodiments, codeword 520 is referred to as a logical codeword by memory controller 502, while codeword wear leveling is performed on physical codewords. Therefore, a cell mapping table between the logical cell address and the physical cell address of each storage cell (e.g., codeword L2P table 524 for each block 518) can be stored in non-volatile storage device 504. Fig. 10AAs shown, for example, the codeword L2P table may map each logical codeword address to a corresponding physical codeword address (e.g., 0 to 0, 1 to 1, ..., N to N). Unlike a single block L2P table that the L2P module 512 can directly store and manage in the volatile storage device 506 due to its limited size, due to the large number of tables per block, the unit mapping table is maintained and managed by the L2P module 512 in the non-volatile storage device 504. For example, each codeword L2P table 524 may be stored in a corresponding block 518 or a designated area of ​​the non-volatile storage device 504. When performing codeword wear balancing for a particular codeword 520, the L2P module 512 may be configured to retrieve the corresponding codeword L2P table 524 from the non-volatile storage device 504 and store it in the volatile storage device 506 as part of the L2P table 530 in order to perform codeword wear balancing.

[0104] In some embodiments, to swap the hottest block 518 (with the largest group write count) and the coldest block 518 (with the smallest group write count), the block wear leveling module 514 is configured to swap the data in the hottest block 518 with the data in the coldest block 518, and also update the group mapping table by swapping the physical group address of the hottest block 518 with the physical group address of the coldest block 518. For example, Fig. 9B As shown, physical block addresses N and M may be swapped after data in logical blocks M and N are swapped, indicating that blocks M and N have been swapped through block wear balancing.

[0105] Similarly, in some embodiments, to swap the hottest codeword 520 (with the largest unit write count) and the coldest codeword 520 (with the smallest unit write count), the block wear leveling module 516 is configured to swap the data in the hottest codeword 520 with the data in the coldest codeword 520, and also update the corresponding unit mapping table by swapping the physical unit address of the hottest codeword 520 with the physical unit address of the coldest codeword 520. For example, Fig. 10B As shown, physical codeword addresses N and M may be swapped after data in logical codewords M and N are swapped, indicating that codewords M and N have been swapped through codeword wear balancing.

[0106] Return to reference Figure 5 , the swap bitmap 532 may indicate a swap index for each storage group (e.g., block 518). The swap index may be a default value in response to no codeword wear leveling process being performed in the corresponding storage group, or a swap value in response to a codeword wear leveling process being performed in the corresponding storage group. Fig.11As shown, the swap indexes of blocks 0, 1, 2, 4, and 1023 may be a default value of "0", indicating that the codeword wear leveling process has not been performed on blocks 0, 1, 2, 4, and 1023. Therefore, the codeword L2P tables of blocks 0, 1, 2, 4, and 1023 may remain unchanged in their default form (e.g., as Fig. 10A As shown in FIG. 1 ). In comparison, the swap indexes of blocks 3, 5, and 6 may be swap values ​​of “1”, indicating that at least one codeword wear leveling process is performed in blocks 3, 5, and 6. Therefore, the codeword L2P table for blocks 3, 5, and 6 may be changed (e.g., as shown in FIG. 1 ). Fig. 10B shown).

[0107] Return to reference Figure 5 In some embodiments, the codeword wear leveling module 516 is configured to maintain and manage a swap bitmap 532 and store the swap bitmap 532 in the non-volatile storage device 504. The codeword wear leveling module 516 can also be configured to retrieve the swap bitmap 532 from the non-volatile storage device 504 and store the swap bitmap 532 in the volatile storage device 506, for example, during initialization of the storage system 500. In some embodiments, the wear leveling module 508 is configured to check the swap bitmap 532 stored in the volatile storage device 506 to determine whether the codeword L2P table 524 needs to be loaded from the non-volatile storage device 504 to the volatile storage device 506 based on the swap index of the corresponding block 518 in the swap bitmap 532.

[0108] Figure 8 Detailed diagram of memory controller 802 is shown in accordance with some aspects of the present disclosure. Memory controller 802 may be Figure 5 An example of a memory controller 502 in FIG. Figure 8 As shown, the memory controller 802 may include a processing unit 840, an SRAM 850, and a read-only memory (ROM) 860. In some embodiments, the processing unit 840 includes one or more MCUs. Figure 5 The various firmware modules in the memory controller 502 described above may be implemented as firmware codes or instructions stored in the ROM 860 and executed by the processing unit 840. In some embodiments, the various data structures in the volatile storage device 506 may be stored in the SRAM 850. In some embodiments, the memory controller 830 also includes a memory device coupled to the SCM device 806 (e.g., Figure 1 The memory controller 830 may include an SCM interface 830 (eg, a memory device 104 in the example), which is configured to transmit data, commands, clocks, or any suitable signals between the SCM device 806 and the processing unit 840. In some embodiments, the memory controller 830 may also include various I / O layers to facilitate the host 804 (eg, Figure 1 Various communication protocols for data transmission, communication and management between the host 108 (an instance of the host 108 in FIG. 1 ) and the memory controller 802, including, for example, a PCIe layer 810 and an NVMe layer 820.

[0109] Fig.12 A flow chart of a method 1200 for operating a non-volatile storage device according to some aspects of the present disclosure is shown. The non-volatile storage device may be any suitable storage device disclosed herein, such as the non-volatile storage device 504. The method 1200 may be implemented by a memory controller, such as the memory controller 502, or any other suitable memory controller disclosed herein. It should be understood that the operations shown in the method 1200 may not be exhaustive, and other operations may be performed before, after, or between any of the illustrated operations. In addition, some of these operations may be performed simultaneously, or in parallel. Fig.12 In addition, you can not execute Fig.12 Some of the operations shown in .

[0110] The nonvolatile memory device may include a plurality of memory groups, and each memory group may include a plurality of memory cells. In some embodiments, each memory cell in the plurality of memory cells corresponds to a code word, and each memory group in the plurality of memory groups corresponds to a block including a plurality of code words. For example, Figure 5 As shown, each storage unit may correspond to a codeword 520 , and each storage group may correspond to a block 518 .

[0111] refer to Fig.12 , method 1200 begins at operation 1202, where a group write count for each storage group of a nonvolatile storage device is monitored. In some embodiments, the group write count for each storage group of the nonvolatile storage device is an average cell write count of a plurality of storage cells in the storage group. For example, Figure 5 As shown, the write count module 510 of the memory controller 502 can monitor a block write count for each block 518. The block write count can be an average of all codeword write counts for each codeword 520 in the corresponding block 518.

[0112] Method 1200 proceeds to operation 1204, such as Fig.12 As shown, the group write count is stored in a volatile storage device. Figure 5 As shown, the write count module 510 can store the block write count for the block 518 in the volatile storage device 506 as part of the write count 528 .

[0113] Method 1200 proceeds to operation 1206, such as Fig.12As shown, a group mapping table between the logical group address and the physical group address of each storage group is stored in a volatile storage device. In some embodiments, for each storage group, the logical group address and the physical group address are the same before the first wear leveling process. For example, Figure 5 As shown, the L2P module 512 of the memory controller 502 may store the block L2P table in the volatile storage device 506 as part of the L2P table 530. For example, Fig.9A As shown, the block L2P table may map the logical block address and the physical block address for each block 518. Before block wear leveling, the logical block address and the physical block address may be the same for each block 518 (eg, 0 to 0, 1 to 1, ..., N to N).

[0114] Method 1200 proceeds to operation 1208, such as Fig.12 As shown, a first wear leveling process is performed by swapping a first storage group in a storage group and a second storage group in a storage group based on a first group write count for a first storage group and a second group write count for a second storage group. Figure 5 As shown, the block wear leveling module 514 can perform block wear leveling by swapping the hottest block 518 and the coldest block 518 based on the block write count for each block 518 in the non-volatile storage device 504 .

[0115] In some embodiments, a first group write count for a first storage group in the group write counts is a maximum group write count in the group write counts, and a second group write count for a second storage group in the group write counts is a minimum group write count in the group write counts. In some embodiments, the first wear leveling process is performed in response to a difference between the first group write count and the second group write count being greater than a group count threshold. For example, Fig.13 As shown, at operation 1302, the block write count difference is compared with a preset block write count threshold (block_wc_th) to determine whether the block write count difference is greater than the block write count threshold. The block write count difference can be the difference between the maximum block write count and the minimum block write count of all blocks 518 in the non-volatile storage device 504.

[0116] In some embodiments, in order to exchange the first storage group and the second storage group, the data of the first storage group and the data of the second storage group are exchanged, and the first physical group address of the first storage group and the second physical group address of the second storage group are exchanged. Fig.13As shown, when the answer to operation 1302 is yes, block wear balancing is performed between the hottest block 518 with the largest block write count and the coldest block 518 with the smallest block write count. At operation 1304, data between the block with the largest block write count and the block with the smallest block write count is swapped. At operation 1306, the logical block to physical block mapping table is updated. For example, Fig. 9B As shown, the physical block addresses M and N may be swapped after data between the physical blocks M and N are swapped.

[0117] In some embodiments, the group mapping table is updated by exchanging the first physical group address of the first storage group and the second physical group address of the second storage group after the first wear leveling process. In some embodiments, after the first wear leveling process, the first group write count for the first storage group is reduced by a preset value, and after the first wear leveling process, the second group write count for the second storage group is increased by a preset value. That is, for example, by reducing the first group write count for the first storage group by a preset value, a forced cooling operation can be performed after the wear leveling process to avoid selecting the first storage group with the largest group write count again immediately after the wear leveling process. Similarly, for example, by increasing the second group write count for the second storage group by a preset value, a heating operation can be performed after the wear leveling process to increase the chance of selecting the second storage group with the smallest group write count after the wear leveling process. For example, as Fig.13 As shown, at operation 1308, the block write count of the block with the largest block write count is increased by a preset value N after the swap. In some examples, N may be 1 or 2. At operation 1310, the block write count of the block with the smallest block write count is increased by a preset value M after the swap. In some examples, M may be 1.

[0118] Return to reference Fig.12 , method 1200 proceeds to operation 1210, where a cell write count for each memory cell in the memory group is monitored. Figure 5 As shown, the write count module 510 of the memory controller 502 can monitor the cell write count for each codeword 520 in the block 518 .

[0119] Method 1200 proceeds to operation 1212, such as Fig.12 As shown, the cell write count is stored in a non-volatile storage device. Figure 5 As shown, the write count module 510 can store the unit write count of the code word 520 in the non-volatile storage device 504. For example, Figure 6 As shown, each cell write count may be stored as part of the metadata 606 in the corresponding codeword 520 .

[0120] Method 1200 proceeds to operation 1214, such as Fig.12 As shown, for each storage group, a cell mapping table between the logical cell address and the physical cell address of each storage cell in the storage group is stored in a non-volatile storage device. In some embodiments, for each storage cell, the logical cell address and the physical cell address are the same before the second wear leveling process. For example, Figure 5 As shown, the L2P module 512 of the memory controller 502 may store each codeword L2P table 524 in the non-volatile storage device 504, for example, in the corresponding block 518. For example, Fig. 10A As shown, the codeword L2P table can map the logical codeword address and the physical codeword address of each codeword 520 in the block 518. Before codeword wear leveling, the logical codeword address and the physical codeword address can be the same for each codeword 520 (e.g., 0 to 0, 1 to 1, ..., N to N).

[0121] Method 1200 proceeds to operation 1216, such as Fig.12 As shown, a second wear leveling process is performed by swapping the first storage cell and the second storage cell based on a first cell write count for a first storage cell in the storage cells and a second cell write count for a second storage cell in the storage cells. Figure 5 As shown, the codeword wear leveling module 516 may perform codeword wear leveling by swapping the hottest codeword 520 and the coldest codeword 520 in the block 518 based on the write count for each codeword 520 in the block 518 .

[0122] In some embodiments, a first cell write count for a first storage cell in the cell write counts is a maximum cell write count in the cell write counts, and a second cell write count for a second storage cell in the cell write counts is a minimum cell write count in the cell write counts. In some embodiments, the second wear leveling process is performed in response to a difference between the first cell write count and the second cell write count being greater than a cell count threshold. For example, Fig.14 As shown, at operation 1402, the codeword write count difference is compared with a preset codeword write count threshold (cw_wc_th) to determine whether the codeword write count difference is greater than the codeword write count threshold. The codeword write count difference can be the difference between the maximum codeword write count and the minimum codeword write count of all codewords 520 in block 518.

[0123] In some embodiments, in order to exchange the first storage unit and the second storage unit, the data of the first storage unit and the data of the second storage unit are exchanged, and the first physical unit address of the first storage unit and the second physical unit address of the second storage unit are exchanged. Fig.14As shown, when the answer to operation 1402 is yes, codeword wear leveling is performed between the hottest codeword 520 with the largest codeword write count and the coldest codeword 520 with the smallest codeword write count. At operation 1404, data between the codeword with the largest codeword write count and the codeword with the smallest codeword write count is swapped. At operation 1406, the logical codeword to physical codeword mapping table is updated. For example, Fig. 10B As shown, the physical codeword addresses M and N may be swapped after the data between the physical codewords M and N are swapped.

[0124] In some embodiments, the cell mapping table is updated by exchanging the first cell group address of the first storage cell and the second physical cell address of the second storage cell after the second wear leveling process. In some embodiments, after the second wear leveling process, the first cell write count for the first storage cell is reduced by a preset value, and after the second wear leveling process, the second cell write count for the second storage cell is increased by a preset value. That is, for example, by reducing the first cell write count for the first storage cell by a preset value, a forced cooling operation may be performed after the wear leveling process to avoid selecting the first storage cell with the maximum cell write count again immediately after the wear leveling process. Similarly, for example, by increasing the second cell write count for the second storage cell by a preset value, a heating operation may be performed after the wear leveling process to increase the chance of selecting the second storage cell with the minimum cell write count after the wear leveling process. For example, as Fig.14 As shown, at operation 1408, the codeword write count of the codeword with the largest codeword write count is increased by a preset value N after the swap. In some examples, N may be 1 or 2. At operation 1410, the codeword write count of the codeword with the smallest codeword write count is increased by a preset value M after the swap. In some examples, M may be 1.

[0125] It should be understood that operations 1202-1208 and operations 1210-1216 can be performed independently. In other words, the first wear leveling process and the second wear leveling process are two independent processes that are independent of each other. In one example, the codeword wear leveling process may not need to be performed in the hottest block or the coldest block on which the block wear leveling process is performed, and can be performed in any block as long as the trigger condition is met (for example, the codeword write count difference is greater than the codeword write count threshold). In another example, only the codeword wear leveling process or only the block wear leveling process may be performed. In yet another example, the codeword wear leveling process and the block wear leveling process may be performed in any order or in parallel.

[0126] In some embodiments, the swap bitmap is stored in a volatile storage device. The swap bitmap indicates a swap index for each storage group of the non-volatile storage device. In some embodiments, in response to not performing the second wear leveling process for the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a default value; and in response to performing the second wear leveling process for the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a swap value. For example, Figure 5 As shown, the codeword wear leveling module 516 can store the swap bitmap 532 in the volatile storage device 506 during initialization of the storage system 500. For example, Fig.12 As shown, the bitmap 532 may indicate that the value of the swap index of each block is a default value "0" or a swap value "1" depending on whether codeword wear leveling is performed in the corresponding block.

[0127] In some embodiments, in response to the swap index of the storage group being the swap value, retrieving the unit mapping table of the storage group from the non-volatile storage device; and storing the unit mapping table in the volatile storage device. Figure 5 As shown, only when the swap index of the corresponding block 518 in the swap bitmap 532 is the swap value "1", the L2P module 512 can load the codeword L2P table 524 for the block 518 from the non-volatile storage device 504 to the volatile storage device 506. Otherwise, since the codeword wear leveling process is not performed on the block 518, the logical codeword address and the physical codeword address remain the same for each codeword 520 in the block 518; there is no need to perform write operations and read operations on the codeword L2P table 524.

[0128] Fig.15 1500 is a flowchart of a method for performing read / write operations according to some aspects of the present disclosure. The method 1500 may be implemented by a memory controller, such as the memory controller 502, or any other suitable memory controller disclosed herein. It should be understood that the operations shown in the method 1500 may not be exhaustive, and other operations may be performed before, after, or between any of the illustrated operations. In addition, some of these operations may be performed simultaneously, or in parallel. Fig.15 In addition, you can not execute Fig.15 Some of the operations shown in .

[0129] refer to Fig.15, method 1500 begins at operation 1502, where a read / write command is received from a host. The read / write command may be associated with a logical codeword and a block address indicating the logical codeword on which the read / write operation is to be performed. At operation 1504, a physical block address is determined from the logical block address based on a logical block to physical block mapping table. At operation 1506, a swap bitmap is searched to determine the value of the swap index of the determined physical block address (the block). At operation 1508, it is determined whether the swap index (bit) is equal to the swap value "1". If the answer to operation 1508 is yes, then at operation 1510, the logical codeword to physical codeword mapping table of the block is loaded from a non-volatile storage device to a volatile storage device. At operation 1512, a physical codeword address is determined from the logical codeword address based on the logical codeword to physical codeword mapping table. At operation 1514, a read / write operation is performed on the physical codeword identified by the physical codeword address. If the answer to operation 1508 is no, operations 1510 and 1512 may be skipped because the physical codeword address is the same as the logical codeword address and there is no need to load a logical codeword to physical codeword mapping table to determine the physical codeword address.

[0130] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as instructions on a non-transitory computer-readable medium. Computer-readable media include computer storage media. The storage medium may be a computer program that can be accessed by a memory controller (e.g., Figure 5 Any available medium accessible by the memory controller 502 in the computer. By way of example and not limitation, such computer readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD), such as disk storage or other magnetic storage device, flash memory, SSD, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a processing system (such as a mobile device or computer). As used herein, disks and discs include CDs, laser discs, optical discs, digital video discs (DVDs), and floppy disks, where disks typically reproduce data magnetically, while optical discs use lasers to reproduce data optically. Combinations of the above should also be included within the scope of computer readable media.

[0131] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0132] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

[0133] Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. In addition, the inventive subject matter described in the present disclosure may also be used for various other applications. The functions and structural features described in the present disclosure may be combined, adjusted, modified, and rearranged in a manner consistent with the scope of the present disclosure.

Claims

1. A storage system, comprising: A nonvolatile storage device, the nonvolatile storage device comprising a plurality of storage groups, each of the plurality of storage groups comprising a plurality of storage cells; as well as a memory controller coupled to the non-volatile memory device and configured to perform at least one of the following: performing a first wear leveling process by swapping the first storage group and the second storage group based on a first set of write counts for a first storage group in the plurality of storage groups and a second set of write counts for a second storage group in the plurality of storage groups; or A second wear leveling process is performed by swapping the first memory cell and the second memory cell based on a first cell write count for a first memory cell among the plurality of memory cells and a second cell write count for a second memory cell among the plurality of memory cells.

2. The storage system according to claim 1, wherein: Each storage unit of the plurality of storage units corresponds to a codeword.

3. The storage system according to claim 1, wherein: The memory controller is configured to swap the first memory group and the second memory group by: exchanging data of the first storage group and data of the second storage group; and A first physical group address of the first memory group and a second physical group address of the second memory group are exchanged.

4. The storage system according to claim 1, wherein: The memory controller is configured to swap the first memory unit and the second memory unit by: exchanging data in the first storage unit and data in the second storage unit; and A first physical unit address of the first storage unit and a second physical unit address of the second storage unit are exchanged.

5. The storage system according to claim 3, further comprising a volatile storage device, wherein: The memory controller is configured to: monitoring a group write count for each memory group of the non-volatile memory device; and storing the group write count in the volatile storage device, The first group write count for the first storage group in the group write counts is a maximum group write count in the group write counts, and the second group write count for the second storage group in the group write counts is a minimum group write count in the group write counts.

6. The storage system according to claim 5, wherein: The group write count for each memory group of the nonvolatile memory device is an average cell write count of the plurality of memory cells in the memory group.

7. The storage system according to claim 5, wherein: The memory controller is configured to perform the first wear leveling process in response to a difference between the first group write count and the second group write count being greater than a group count threshold.

8. The storage system according to claim 5, wherein: The memory controller is configured to, after the first wear leveling process, reduce the first group write count for the first storage group by a preset value.

9. The storage system according to claim 5, wherein: The memory controller is configured to increase the second group write count for the second storage group by a preset value after the first wear leveling process.

10. The storage system according to claim 5, wherein The memory controller is configured to: store a group mapping table between a logical group address and a physical group address of each storage group in the volatile storage device; and For each storage group, the logical group address and the physical group address are the same before the first wear leveling process.

11. The storage system according to claim 10, wherein: The memory controller is configured to update the group mapping table by swapping the first physical group address of the first memory group and the second physical group address of the second memory group after the first wear leveling process.

12. The storage system according to claim 4, wherein: The memory controller is configured to: monitoring a cell write count for each memory cell of the non-volatile memory device; as well as storing the cell write count in the non-volatile storage device, The first cell write count for the first storage cell in the cell write counts is a maximum cell write count in the cell write counts, and the second cell write count for the second storage cell in the cell write counts is a minimum cell write count in the cell write counts.

13. The storage system according to claim 12, wherein: The memory controller is configured to perform the second wear leveling process in response to a difference between the first cell write count and the second cell write count being greater than a cell count threshold.

14. The storage system according to claim 12, wherein: The memory controller is configured to reduce the first cell write count for the first memory cell by a preset value after the second wear leveling process.

15. The storage system according to claim 12, wherein: The memory controller is configured to increase the second cell write count for the second storage cell by a preset value after the second wear leveling process.

16. The storage system according to claim 12, wherein The memory controller is configured to: for each storage group, store a cell mapping table between a logical cell address and a physical cell address of each storage cell in the storage group in the nonvolatile storage device; and For each memory cell, the logical cell address and the physical cell address are the same before the second wear leveling process.

17. The storage system according to claim 16, wherein: The memory controller is configured to update the cell mapping table by swapping the first physical cell address of the first memory cell and the second physical cell address of the second memory cell after the second wear leveling process.

18. The storage system according to claim 16, wherein: The memory controller is further configured to store a swap bitmap in the volatile memory device, the swap bitmap indicating a swap index of each memory group of the non-volatile memory device.

19. The storage system of claim 18, wherein In response to not performing a second wear leveling process for the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a default value; and In response to the second wear leveling process being performed on the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a swap value.

20. The storage system according to claim 19, wherein: The memory controller is configured to: In response to the swap index of the storage group being the swap value, retrieving the cell mapping table of the storage group from the non-volatile storage device; as well as The cell mapping table is stored in the volatile storage device.

21. The storage system according to claim 1, wherein: Each of the plurality of memory cells includes a storage class memory (SCM) cell.

22. A method for operating a non-volatile memory device, the non-volatile memory device comprising a plurality of memory groups, each of the plurality of memory groups comprising a plurality of memory cells, the method comprising: performing at least one of the following: (i) performing a first wear leveling process by swapping the first storage group and the second storage group based on a first set of write counts for a first storage group in the plurality of storage groups and a second set of write counts for a second storage group in the plurality of storage groups; or (ii) performing a second wear leveling process by swapping the first storage cell and the second storage cell based on a first cell write count for a first storage cell among the plurality of storage cells and a second cell write count for a second storage cell among the plurality of storage cells.

23. The method according to claim 22, wherein: Each storage unit of the plurality of storage units corresponds to a codeword.

24. The method according to claim 22, wherein: Swapping the first storage group and the second storage group includes: exchanging data of the first storage group and data of the second storage group; and A first physical group address of the first memory group and a second physical group address of the second memory group are exchanged.

25. The method according to claim 22, wherein: Exchanging the first storage unit and the second storage unit includes: exchanging data in the first storage unit and data in the second storage unit; and A first physical unit address of the first storage unit and a second physical unit address of the second storage unit are exchanged.

26. The method of claim 24, further comprising: monitoring a group write count for each storage group of the non-volatile storage device; as well as storing the group write count in a volatile storage device, The first group write count for the first storage group in the group write counts is a maximum group write count in the group write counts, and the second group write count for the second storage group in the group write counts is a minimum group write count in the group write counts.

27. The method according to claim 26, wherein: The group write count for each memory group of the nonvolatile memory device is an average cell write count of the plurality of memory cells in the memory group.

28. The method according to claim 26, wherein: The first wear leveling process is performed in response to a difference between the first group write count and the second group write count being greater than a group count threshold.

29. The method of claim 26, further comprising: After the first wear leveling process, the first group write count for the first storage group is reduced by a preset value.

30. The method of claim 26, further comprising: After the first wear leveling process, the second group write count for the second storage group is increased by a preset value.

31. The method of claim 26, further comprising: A group mapping table between a logical group address and a physical group address of each storage group is stored in the volatile storage device, wherein for each storage group, the logical group address and the physical group address are the same before the first wear leveling process.

32. The method of claim 31 further comprising: The group mapping table is updated by swapping the first physical group address of the first storage group and the second physical group address of the second storage group after the first wear leveling process.

33. The method of claim 25, wherein: Also includes: monitoring a cell write count for each memory cell of the nonvolatile memory device; and storing the cell write count in the non-volatile storage device, The first cell write count for the first storage cell in the cell write counts is a maximum cell write count in the cell write counts, and the second cell write count for the second storage cell in the cell write counts is a minimum cell write count in the cell write counts.

34. The method of claim 33, wherein: The second wear leveling process is performed in response to a difference between the first cell write count and the second cell write count being greater than a cell count threshold.

35. The method of claim 33, further comprising: After the second wear leveling process, the first cell write count for the first storage cell is reduced by a preset value.

36. The method of claim 33, further comprising: After the second wear leveling process, the second cell write count for the second storage cell is increased by a preset value.

37. The method of claim 33, further comprising: For each storage group, a cell mapping table between a logical cell address and a physical cell address of each storage cell in the storage group is stored in the nonvolatile storage device, wherein, for each storage cell, the logical cell address and the physical cell address are the same before the second wear leveling.

38. The method of claim 37, further comprising: The cell mapping table is updated by swapping the first physical cell address of the first memory cell and the second physical cell address of the second memory cell after the second wear leveling process.

39. The method of claim 38, further comprising: A swap bitmap is stored in the volatile memory device, the swap bitmap indicating a swap index of each memory group of the non-volatile memory device.

40. The method of claim 39, wherein: In response to not performing a second wear leveling process for the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a default value; as well as In response to performing the second wear leveling process on the first storage unit and the second storage unit in the storage group, the swap index of the storage group is a swap value.

41. The method of claim 40, further comprising: In response to the swap index of the storage group being the swap value, retrieving the cell mapping table of the storage group from the non-volatile storage device; as well as The cell mapping table is stored in the volatile storage device.

42. A non-transitory computer-readable storage medium comprising instructions that, when executed by a memory controller, cause the memory controller to: Perform at least one of the following: (i) perform a first wear leveling process by swapping the first storage group and the second storage group of a nonvolatile storage device based on a first group write count for the first storage group and a second group write count for the second storage group of the nonvolatile storage device, each of the first storage group and the second storage group including a plurality of storage cells; or (ii) perform a second wear leveling process by swapping the first storage cell and the second storage cell based on a first cell write count for a first storage cell among the plurality of storage cells and a second cell write count for a second storage cell among the plurality of storage cells.

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