Laminated ceramic electronic component and mounting structure for laminated ceramic electronic component

Abstract

The invention provides a laminated ceramic electronic component capable of suppressing degradation of insulation resistance caused by hydrogen. In a laminated ceramic electronic component, a first external electrode (30a) has: a first base electrode layer (32a); a first lower plating layer (34a1) disposed on the first base electrode layer (32a); and a first upper plating layer (34a2) disposed on the first lower plating layer (34a1) except the first plating layer exposed region (35a) such that the first lower plating layer (34a1) has the first plating layer exposed region (35a) exposed on the surface of the first external electrode (30a). The second external electrode (30b) has: a second base electrode layer (32b); a second lower plating layer (34b1) disposed on the second base electrode layer (32b); and a second upper plating layer (34b2) disposed on the second lower plating layer (34b1) except the second plating layer exposed region (35b) such that the second lower plating layer (34b1) has the second plating layer exposed region (35b) exposed on the surface of the second external electrode (30b).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic electronic component and a mounting structure of the laminated ceramic electronic component. Background Art

[0002] The stacked ceramic capacitor includes a stacked body and an external electrode. The stacked body includes an inner layer portion and an outer layer portion. The inner layer portion is formed by alternately stacking a plurality of ceramic layers and a plurality of internal electrode layers in a given stacking direction. The outer layer portion is formed by arranging ceramic layers on the surface of the inner layer portion so as to sandwich the inner layer portion in the stacking direction. The plurality of internal electrode layers are exposed at both end faces in a length direction orthogonal to the stacking direction. The external electrode is arranged on the surface of the end face so as to be electrically connected to the internal electrode layer exposed from the end face. The external electrode includes: a Ni plating layer for preventing solder erosion when the stacked ceramic capacitor is mounted on a substrate using solder; and a Sn plating layer, arranged on the Ni plating layer, for improving the coating performance of the solder. The Ni plating layer and the Sn plating layer are usually formed using an electrolytic plating method.

[0003] Patent document 1 discloses that hydrogen generated by chemical reaction in the plating process of forming the plating layer degrades the performance of the laminated ceramic capacitor. Specifically, the hydrogen generated in the plating process is absorbed by the internal electrode layer, and the hydrogen causes dielectric loss and deterioration of insulation resistance. Patent document 1 records that, in order to solve this problem, for example, the internal electrode layer mainly composed of Ag-Pd alloy contains metal such as Ni, thereby inhibiting the absorption of hydrogen by the internal electrode layer, thereby inhibiting the degradation of the ceramic layer.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 64-80011 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] However, although it is described in Patent Document 1 that Ni inactivates the hydrogen absorption effect, according to the research of the inventors of the present application, it is known that even when Ni or the like is included in the materials constituting the internal electrode layers and the external electrodes, hydrogen is absorbed by the internal electrode layers and the external electrodes, and the absorbed hydrogen is released from the metal according to the temperature conditions, and the hydrogen causes the deterioration of the insulation resistance. In particular, when a high-temperature and high-humidity load test such as PCBT (Pressure Cooker Bias Test) is performed, the deterioration of the insulation resistance becomes significant due to the hydrogen released from the metal that has absorbed hydrogen, which sometimes causes the deterioration of the multilayer ceramic capacitor.

[0009] Therefore, a main object of the present invention is to provide a multilayer ceramic electronic component and a mounting structure of the multilayer ceramic electronic component that can suppress degradation of insulation resistance due to hydrogen.

[0010] Technical solutions to solve problems

[0011] The laminated ceramic electronic component of the present invention is a laminated ceramic electronic component comprising: a laminate having a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a plurality of first internal electrode layers arranged on the plurality of ceramic layers and extending to the first end surface; a plurality of second internal electrode layers arranged on the plurality of ceramic layers and extending to the second end surface; a first external electrode arranged on the first end surface, extending from the first end surface and arranged on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer; and a second external electrode arranged on the second end surface On the laminate, extending from the second end face and arranged on a portion of the first main face, a portion of the second main face, a portion of the first side face and a portion of the second side face, and connected to the second internal electrode layer, the first external electrode comprising: a first base electrode layer, arranged on the laminate; a first lower plating layer, arranged on the first base electrode layer; and a first upper plating layer, arranged on the first lower plating layer except for the first plating exposed area, so that the first lower plating layer has a first plating exposed area exposed on the surface of the first external electrode, the second external electrode comprising: a second base electrode layer, arranged on the laminate; a second lower plating layer, arranged on the second base electrode layer; and a second upper plating layer, arranged on the second lower plating layer except for the second plating exposed area, so that the second lower plating layer has a second plating exposed area exposed on the surface of the second external electrode.

[0012] In the multilayer ceramic electronic component according to the present invention, the first lower plating layer is exposed on the surface of the first external electrode in the first plating layer exposed region, so that hydrogen in the multilayer ceramic electronic component can be released from the first plating layer exposed region to the outside of the multilayer ceramic electronic component. In addition, the second lower plating layer is exposed on the surface of the second external electrode in the second plating layer exposed region, so that hydrogen in the multilayer ceramic electronic component can be released from the second plating layer exposed region to the outside of the multilayer ceramic electronic component.

[0013] In the plating process for forming the first lower plating layer and the second lower plating layer, the first upper plating layer and the second upper plating layer, hydrogen ions are generated due to chemical reactions. The hydrogen ions are sometimes absorbed as hydrogen by at least one of, for example, the first lower plating layer and the second lower plating layer, the first internal electrode layer and the second internal electrode layer, the first base electrode layer and the second base electrode layer. According to the above structure, hydrogen absorbed by at least one layer (absorption layer) of the first lower plating layer and the second lower plating layer, the first internal electrode layer and the second internal electrode layer, the first base electrode layer and the second base electrode layer can be released from the first plating layer exposed area and the second plating layer exposed area to the outside of the laminated ceramic electronic component. Therefore, it is possible to suppress the state in which hydrogen is absorbed by the absorption layer, and it is possible to suppress the degradation of the insulation resistance caused by hydrogen. In particular, even when the gettering layer includes a metal such as Ni that does not easily absorb hydrogen, degradation of the insulation resistance of the ceramic layer can be suppressed by releasing hydrogen from the first and second plated layer exposed regions to the outside of the multilayer ceramic electronic component.

[0014] In addition, a first plating exposed area and a second plating exposed area are formed on the first main surface side, and the second main surface side becomes the mounting surface of the multilayer ceramic capacitor on the mounting substrate. When the solder is mainly applied to the first end surface side and the second end surface side, the hydrogen in the absorption layer can be efficiently released from the first main surface to which the solder is not applied and which does not face the mounting substrate through the first plating exposed area and the second plating exposed area.

[0015] Effects of the Invention

[0016] According to the present invention, it is possible to provide a multilayer ceramic electronic component and a mounting structure of the multilayer ceramic electronic component that can suppress degradation of insulation resistance due to hydrogen.

[0017] The above-mentioned object, other objects, features and advantages of the present invention will become more apparent from the following description of specific embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a perspective view showing the appearance of an example of a two-terminal type multilayer ceramic capacitor as a multilayer ceramic electronic component according to the first embodiment of the present invention.

[0019] Figure 2 yes Figure 1 Cross-sectional view at line II-II.

[0020] Figure 3 yes Figure 1 Cross-sectional view at line III-III.

[0021] Figure 4 yes Figure 2Cross-sectional view at line IV-IV.

[0022] Figure 5 yes Figure 2 Cross-sectional view at line V-V.

[0023] Figure 6 This is a side view showing an example of a two-terminal multilayer ceramic capacitor mounted on a mounting substrate using solder.

[0024] Figure 7 It is an explanatory diagram for explaining the calculation method of the exposed area according to the first example.

[0025] Figure 8 It is an explanatory diagram for explaining the calculation method of the exposed area according to the second example.

[0026] Fig. 9 It is a partial cross-sectional view showing a state in which the base electrode layer is exposed.

[0027] Fig.10 It is a partial cross-sectional view showing another embodiment in which the base electrode layer is exposed.

[0028] Fig.11 It is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention.

[0029] Fig.12 It is a plan view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention.

[0030] Fig.13 It is a front view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention.

[0031] Fig.14 yes Fig.11 Cross-sectional view at line XIV-XIV.

[0032] Fig.15 yes Fig.11 Cross-sectional view at line XV-XV.

[0033] Fig.16 yes Fig.14 Cross-sectional view at line XVI-XVI of .

[0034] Fig.17 yes Fig.14 Cross-sectional view taken along line XVII-XVII. DETAILED DESCRIPTION

[0035] A. First embodiment

[0036] 1. Two-terminal multilayer ceramic capacitors

[0037] As an example of the multilayer ceramic electronic component according to the first embodiment of the present invention, a two-terminal multilayer ceramic capacitor will be described.

[0038] Figure 1 This is a perspective view showing the appearance of an example of a two-terminal type multilayer ceramic capacitor as a multilayer ceramic electronic component according to the first embodiment of the present invention. Figure 2 yes Figure 1 Cross-sectional view at line II-II. Figure 3 yes Figure 1 Cross-sectional view at line III-III. Figure 4 yes Figure 2 Cross-sectional view at line IV-IV. Figure 5 yes Figure 2 Cross-sectional view at line V-V.

[0039] like Figures 1 to 3 As shown, the two-terminal multilayer ceramic capacitor 10 includes a rectangular parallelepiped multilayer body 12 and external electrodes 30 disposed at both ends of the multilayer body 12 .

[0040] (1) Laminated body

[0041] The stacked body 12 has a first main surface 12a and a second main surface 12b opposite to each other in the height direction x (stacking direction), a first side surface 12c and a second side surface 12d opposite to each other in the width direction y orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f opposite to each other in the length direction z orthogonal to the height direction x and the width direction y. In the stacked body 12 of the present embodiment, the corners and the ridges are rounded. In addition, the so-called corners are the parts where three adjacent faces of the stacked body 12 intersect, and the so-called ridges are the parts where two adjacent faces of the stacked body 12 intersect. In addition, it is also possible to form concave-convex portions on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0042] The laminate 12 includes an outer layer portion 14a composed of a plurality of ceramic layers 14 and an inner layer portion 14b composed of a single or multiple ceramic layers 14 and a plurality of internal electrode layers 16 arranged thereon. The outer layer portion 14a is located on the first main surface 12a side and the second main surface 12b side of the laminate 12. The outer layer portion 14a is an aggregate of a plurality of ceramic layers 14 (first outer layer portion) located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a, and a plurality of ceramic layers 14 (second outer layer portion) located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. Moreover, the area sandwiched by the two outer layer portions 14a is the inner layer portion 14b. In the inner layer portion 14b, the ceramic layers 14 and the internal electrode layers 16 are alternately stacked in the height direction x.

[0043] In addition, the portion of the laminate 12 where the first internal electrode layer 16a described later and the second internal electrode layer 16b described later are opposed to each other is referred to as an opposing portion (effective layer portion). In addition, the portion between the opposing portion and the first side surface 12c and the portion between the opposing portion and the second side surface 12d are also referred to as W gaps or side gaps. In addition, the portion between the opposing portion and the first end surface 12e and the portion between the opposing portion and the second end surface 12f, and including the lead electrode portion of either the first internal electrode layer 16a or the second internal electrode layer 16b, is also referred to as an L gap or an end gap.

[0044] The size of the laminate 12 is not particularly limited.

[0045] As the dielectric material forming the ceramic layer 14, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. In the case of containing the above-mentioned dielectric material as a main component, a material to which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound whose content is less than that of the main component may be added, depending on the desired characteristics of the laminate 12.

[0046] Furthermore, when a piezoelectric ceramic material is used for the ceramic layer 14, the laminated ceramic electronic component functions as a piezoelectric component. Specific examples of the piezoelectric ceramic material include, for example, PZT (lead zirconate titanate)-based ceramic materials.

[0047] Furthermore, the laminated ceramic electronic component functions as a thermistor element when a semiconductor ceramic material is used for the ceramic layer 14. Specific examples of the semiconductor ceramic material include spinel ceramic materials and the like.

[0048] In addition, when a magnetic ceramic material is used for the ceramic layer 14, the laminated ceramic electronic component functions as an inductor element. In addition, when it functions as an inductor element, the internal electrode layer 16 becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include ferrite ceramic materials.

[0049] The thickness of the ceramic layer 14 after firing is preferably 0.35 μm or more and 0.60 μm or less. The number of stacked ceramic layers 14 is preferably 10 or more and 2000 or less. In addition, the number of ceramic layers 14 is the total number of ceramic layers 14 of the inner layer portion 14b and the outer layer portion 14a on the first main surface 12a side and the outer layer portion 14a on the second main surface 12b side.

[0050] The laminate 12 has a plurality of first internal electrode layers 16a led to the first end face 12e and a plurality of second internal electrode layers 16b led to the second end face 12f as a plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are embedded in the inner layer portion 14b and are alternately arranged at equal intervals with the ceramic layer 14 sandwiched therebetween along the height direction x of the laminate 12. The surfaces of the plurality of first internal electrode layers 16a and the surfaces of the plurality of second internal electrode layers 16b are substantially parallel to the first main face 12a and the second main face 12b, and are, for example, substantially rectangular in a plan view.

[0051] like Figure 4 As shown in FIG. 1 , the first internal electrode layer 16a is arranged on the plurality of ceramic layers 14 and is located inside the laminate 12. The first internal electrode layer 16a includes a first opposing electrode portion 26a opposed to the second internal electrode layer 16b and a first lead electrode portion 28a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 26a to the first end surface 12e of the laminate 12. The end of the first lead electrode portion 28a is led out to the surface of the first end surface 12e and exposed from the laminate 12. That is, the first lead electrode portion 28a is not exposed on the first main surface 12a, the second main surface 12b, the first side surface 12c, the second side surface 12d, and the second end surface 12f. The end of the first opposing electrode portion 26a is located at a position retreated from the surface of the second end surface 12f in the width direction.

[0052] The shape of the first counter electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably a rectangular shape in a plan view. However, the corners may be rounded in a plan view, or the corners may be formed to be inclined (conical) in a plan view. In addition, the shape may be a cone that is inclined toward a certain direction in a plan view.

[0053] The shape of the first lead electrode portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably a rectangular shape in a plan view. However, the corners may be rounded in a plan view, or the corners may be formed to be inclined (conical) in a plan view. In addition, the shape may be a cone that is inclined toward a certain direction in a plan view.

[0054] The width of the first counter electrode portion 26a of the first internal electrode layer 16a and the width of the first lead electrode portion 28a of the first internal electrode layer 16a may be formed to be the same width, or the width of either one may be formed to be narrow.

[0055] like Figure 5 As shown in FIG. 1 , the second internal electrode layer 16b is arranged on the plurality of ceramic layers 14 and is located inside the stack 12. The second internal electrode layer 16b includes a second opposing electrode portion 26b opposed to the first internal electrode layer 16a and a second lead electrode portion 28b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end surface 12f of the stack 12. The end of the second lead electrode portion 28b is led out to the surface of the second end surface 12f and exposed from the stack 12. That is, the second lead electrode portion 28b is not exposed on the first main surface 12a, the second main surface 12b, the first side surface 12c, the second side surface 12d, and the first end surface 12e. The end of the second opposing electrode portion 26b is located at a position retreated from the surface of the first end surface 12e in the width direction.

[0056] The shape of the second counter electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably a rectangular shape in a plan view. However, the corners may be rounded in a plan view, or the corners may be formed to be inclined (conical) in a plan view. In addition, the shape may be a cone that is inclined toward a certain direction in a plan view.

[0057] The shape of the second lead electrode portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably a rectangular shape in a plan view. However, the corners may be rounded in a plan view, or the corners may be formed to be inclined (conical) in a plan view. In addition, the shape may be a cone that is inclined toward a certain direction in a plan view.

[0058] The width of the second counter electrode portion 26b of the second internal electrode layer 16b and the width of the second lead electrode portion 28b of the second internal electrode layer 16b may be formed to be the same width, or the width of either one may be formed to be narrow.

[0059] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag-Pd alloy. In addition, when the laminate 12 including the internal electrode layer 16 and the integral body including the external electrode 30 on the surface of the laminate 12 are fired simultaneously, the metal constituting the internal electrode layer 16 and the metal contained in the external electrode 30 form a compound.

[0060] The thickness of each of the internal electrode layers 16 , that is, the first internal electrode layer 16 a and the second internal electrode layer 16 b is preferably 0.40 μm or more and 0.50 μm or less.

[0061] Furthermore, the total number of the first internal electrode layers 16 a and the second internal electrode layers 16 b is preferably 10 or more and 2000 or less.

[0062] (2) External electrodes

[0063] like Figures 1 to 3 As shown in FIG. 1 , the external electrodes 30 are arranged on the first end surface 12 e side and the second end surface 12 f side of the stacked body 12 .

[0064] The external electrode 30 includes a first external electrode 30 a and a second external electrode 30 b .

[0065] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed at least on the surface of the first end surface 12e. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 28a of the first internal electrode layer 16a. In the present embodiment, the first external electrode 30a extends from the first end surface 12e of the stacked body 12 and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0066] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed at least on the surface of the second end face 12f. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 28b of the second internal electrode layer 16b. In the present embodiment, the second external electrode 30b extends from the second end face 12f and is also disposed on a portion of the first main face 12a, a portion of the second main face 12b, a portion of the first side face 12c, and a portion of the second side face 12d.

[0067] In the laminate 12, the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b are opposed to each other via the ceramic layer 14, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, showing the characteristics of a capacitor.

[0068] The external electrode 30 is preferably composed of a base electrode layer 32 and a plating layer 34. In the present embodiment, the external electrode 30 includes a base electrode layer 32 including a metal component and a plating layer 34 disposed on the base electrode layer 32. The plating layer 34 includes a first plating layer 34a and a second plating layer 34b.

[0069] The first external electrode 30a includes a first base electrode layer 32a including a metal component, a first lower plating layer 34a1 disposed on the first base electrode layer 32a, and a first upper plating layer 34a2 disposed on the first lower plating layer 34a1. In addition, the first external electrode 30a includes a first plating exposed region 35a exposed on the surface of the first external electrode 30a.

[0070] The second external electrode 30b includes a second base electrode layer 32b including a metal component, a second lower plating layer 34b1 disposed on the second base electrode layer 32b, and a second upper plating layer 34b2 disposed on the second lower plating layer 34b1. In addition, the second external electrode 30b includes a second plating exposed region 35b exposed on the surface of the second external electrode 30b.

[0071] (2-1) Base electrode layer

[0072] The first foundation electrode layer 32a is connected to the first internal electrode layer 16a and is arranged on the surface of the first end surface 12e. In this case, the first foundation electrode layer 32a is electrically connected to the first lead electrode portion 28a of the first internal electrode layer 16a. In the present embodiment, the first foundation electrode layer 32a extends from the first end surface 12e and is also arranged on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0073] The second foundation electrode layer 32b is connected to the second internal electrode layer 16b and is arranged on the surface of the second end surface 12f. In this case, the second foundation electrode layer 32b is electrically connected to the second lead electrode portion 28b of the second internal electrode layer 16b. In the present embodiment, the second foundation electrode layer 32b extends from the second end surface 12f and is also arranged on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0074] The base electrode layer 32 includes at least one selected from a sintered layer, a conductive resin layer, a thin film layer, and the like.

[0075] Hereinafter, each structure in the case where the base electrode layer 32 is set as the above-mentioned sintered layer, conductive resin layer, and thin film layer will be described.

[0076] (When the base electrode layer includes a sintered layer)

[0077] The sintered layer contains a glass component and a metal component. The glass component of the sintered layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. As the metal component of the sintered layer, for example, it contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The sintered layer can also be a plurality of layers. The sintered layer is a sintered layer in which a conductive paste containing a glass component and a metal component is applied to the stack 12 and sintered. It can be sintered at the same time as the internal electrode layer 16 and the ceramic layer 14, or it can be sintered after the internal electrode layer 16 and the ceramic layer 14 are sintered. In addition, when the sintered layer is sintered at the same time as the internal electrode layer 16 and the ceramic layer 14, it is preferred to add a ceramic component instead of the glass component to form the sintered layer. The ceramic component can use the same type of ceramic material as the ceramic layer 14, or it can use a ceramic material of a different type from the ceramic layer 14. The ceramic component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc. By making the sintered layer include a glass component or a ceramic component, the adhesion between the laminate 12 and the base electrode layer 32 as the sintered layer can be improved. In addition, the sintered layer may also include both a glass component and a ceramic component.

[0078] The thickness of the first sintered layer and the second sintered layer at the center of the first foundation electrode layer 32a and the second foundation electrode layer 32b in the height direction x located at the first end face 12e and the second end face 12f is preferably about 3 μm or more and 20 μm or less, for example.

[0079] In addition, when a base electrode layer 32 is provided on the first principal surface 12a and the second principal surface 12b, the first side surface 12c and the second side surface 12d, the thickness of the first sintered layer and the second sintered layer serving as the first base electrode layer 32a and the second base electrode layer 32b located on the first principal surface 12a and the second principal surface 12b, the first side surface 12c and the second side surface 12d at the central portion in the longitudinal direction z is preferably, for example, greater than 1 μm and less than 20 μm.

[0080] (Case where the base electrode layer includes a conductive resin layer)

[0081] The conductive resin layer may be a plurality of layers.

[0082] The conductive resin layer may be disposed on the sintered layer so as to cover the sintered layer, or the conductive resin layer may be disposed directly on the laminate 12 .

[0083] The situation that the conductive resin layer is configured on the sintered layer is further described as follows: the conductive resin layer is configured to cover the base electrode layer 32 as the sintered layer. The conductive resin layer has the first conductive resin layer and the second conductive resin layer. The first conductive resin layer is configured to cover the first base electrode layer 32a, and the second conductive resin layer is configured to cover the second base electrode layer 32b. Specifically, the first conductive resin layer and the second conductive resin layer are configured on the first base electrode layer 32a and the second base electrode layer 32b located on the first end face 12e and the second end face 12f. Furthermore, the first conductive resin layer and the second conductive resin layer are preferably configured to also reach the first main surface 12a and the second main surface 12b and the first side surface 12c and the second side surface 12d. However, the first conductive resin layer and the second conductive resin layer may be disposed only on the first base electrode layer 32a and the second base electrode layer 32b located on the first end face 12e and the second end face 12f. In addition, when the external electrode 30 has the plating layer 34, the conductive resin layer may be disposed between the base electrode layer 32 and the plating layer 34.

[0084] The conductive resin layer contains a thermosetting resin and a metal.

[0085] The conductive resin layer contains a thermosetting resin and is therefore more flexible than a conductive layer composed of, for example, a plated film or a sintered product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the two-terminal multilayer ceramic capacitor 10, the conductive resin layer functions as a buffer layer and can prevent cracks from being generated in the two-terminal multilayer ceramic capacitor 10.

[0086] As the metal contained in the conductive resin layer, Ag, Cu, Ni, Sn, Bi, or an alloy containing these can be used.

[0087] In addition, metal powder coated with Ag on the surface of the metal powder can also be used. When using a metal coated with Ag on the surface of the metal powder, as the metal powder, it is preferred to use Cu, Ni, Sn, Bi or their alloy powders. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, so it is suitable for electrode materials, and Ag is a noble metal, so it is not oxidized and has high weather resistance. In addition, the reason for using Ag-coated metal powder is that the metal of the base material can be made cheap while maintaining the aforementioned properties of Ag.

[0088] Furthermore, as the metal contained in the conductive resin layer, metal obtained by subjecting Cu and Ni to an oxidation-proof treatment can be used.

[0089] In addition, as the metal contained in the conductive resin layer, a metal powder obtained by coating the surface of Sn, Ni, or Cu can also be used. When a metal obtained by coating the surface of Sn, Ni, or Cu is used, as the metal powder, Ag, Cu, Ni, Sn, Bi, or alloy powders thereof are preferably used.

[0090] The metal contained in the conductive resin layer preferably accounts for 35 vol % or more and 75 vol % or less relative to the volume of the entire conductive resin.

[0091] The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0092] The metal contained in the conductive resin layer mainly bears the electrical conductivity of the conductive resin layer. Specifically, the conductive fillers are in contact with each other, thereby forming an electrical path inside the conductive resin layer.

[0093] The shape of the metal contained in the conductive resin layer is not particularly limited, and a spherical shape, a flat shape, etc. can be used. As the metal contained in the conductive resin layer, it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0094] As the resin of the conductive resin layer, various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, polyurethane resin, silicone resin, polyimide resin, etc. can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0095] The conductive resin layer preferably contains the resin in an amount of 25 vol % or more and 65 vol % or less based on the volume of the entire conductive resin.

[0096] In addition, it is preferred that a curing agent is included in the conductive resin layer together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenols, amines, acid anhydrides, imidazoles, active esters, and amide-imides can be used as the curing agent for the epoxy resin.

[0097] The thickness of the conductive resin layer located at the first end surface 12 e and the second end surface 12 f and located at the center of the stacked body 12 in the height direction x is preferably about 3 μm or more and 30 μm or less, for example.

[0098] In addition, when a conductive resin layer is also provided on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, the thickness of the conductive resin layer at the central portion of the conductive resin layer on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d in the longitudinal direction z is preferably, for example, greater than 3 μm and less than 30 μm.

[0099] (Case where the base electrode layer includes a thin film layer)

[0100] The thin film layer is a layer having a thickness of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition and in which metal particles are deposited.

[0101] (2-2) Plating layer

[0102] Next, refer to Figure 2 to Figure 5 The first plating layer 34a and the second plating layer 34b as the plating layer 34 disposed on the base electrode layer 32 will be described. The plating layer 34 has a plating-layer exposed region 35 .

[0103] The first plating layer 34a is arranged to cover the first base electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be arranged to cover the first base electrode layer 32a on the first main face 12a, the second main face 12b, the first side face 12c, and the second side face 12d side. However, the first plating layer 34a may be arranged only on the first base electrode layer 32a on the first end face 12e side. The first plating layer 34a includes a first lower plating layer 34a1 arranged on the first base electrode layer 32a and a first upper plating layer 34a2 arranged on the first lower plating layer 34a1. The first upper plating layer 34a2 is arranged on the first lower plating layer 34a1 so that a portion of the first lower plating layer 34a1 is exposed. That is, the first upper plating layer 34a2 is arranged on the first lower plating layer 34a1 except the first plating exposed region 35a so that the first lower plating layer 34a1 has the first plating exposed region 35a exposed on the surface of the first external electrode 30a.

[0104] In this embodiment, the first plating layer exposed area 35a is arranged on the first main surface 12a. Figure 6 As shown, the second main surface 12 b of the two-terminal multilayer ceramic capacitor 10 serves as a mounting surface for the mounting substrate 40 . Figure 6 FIG. 1 is a side view showing an example of a two-terminal multilayer ceramic capacitor mounted using solder. Figure 6A pair of planar lands 41 for mounting the two-terminal multilayer ceramic capacitor 10 is formed on the mounting substrate 40. The two-terminal multilayer ceramic capacitor 10 is arranged such that the first external electrode 30a and the second external electrode 30b are respectively located on the pair of lands 41 in a state where the second main surface 12b faces the mounting surface of the mounting substrate 40 and the first main surface 12a is farthest from the mounting surface. In this state, solder 42 is applied to the first end surface 12e and the second end surface 12f, thereby mounting the two-terminal multilayer ceramic capacitor 10 on the mounting substrate 40.

[0105] Although not limited to this, it is preferred that the first upper plating layer 34a2 covers the end of the first lower plating layer 34a1. Specifically, the front end of the second end face 12f side of the first lower plating layer 34a1 is preferably covered by the front end of the second end face 12f side of the first upper plating layer 34a2. Thus, peeling of the first lower plating layer 34a1 can be suppressed.

[0106] The first ratio of the area of ​​the first plating layer exposed region 35a on the first main surface 12a to the area of ​​the exposed region of the first external electrode 30a when viewed from the height direction x of the laminate 12 is preferably 0.4% or more and 83.4% or less. Since the first ratio is 0.4% or more, for example, hydrogen released from the first internal electrode layer 16a, the second internal electrode layer 16b, the first base electrode layer 32a, the second base electrode layer 32b, the first lower plating layer 34a1, and the second lower plating layer 34b1 can be fully released from the first plating layer exposed region 35a to the outside of the two-terminal multilayer ceramic capacitor 10, and degradation of the insulation resistance caused by hydrogen can be suppressed. In addition, since the first ratio is 83.4% or less, the ratio of the first lower plating layer 34a1 not covered by the first upper plating layer 34a2 can be suppressed. This can suppress a decrease in moisture resistance due to the intrusion of water vapor from the first plated layer exposed region 35 a into the two-terminal multilayer ceramic capacitor 10 .

[0107] More preferably, the first ratio is 1.17% or more and 83.4% or less. Further preferably, the first ratio is 1.40% or more and 83.4% or less. Further preferably, the first ratio is 1.40% or more and 25.0% or less.

[0108] As a first example, the first ratio can be obtained as follows. First, the area of ​​the exposed region of the first external electrode 30a can be obtained based on the area of ​​the region where the first external electrode 30a faces the outside of the two-terminal multilayer ceramic capacitor 10. For example, the area of ​​the exposed region of the first external electrode 30a can be obtained based on the area of ​​the region where the first external electrode 30a faces the outside of the two-terminal multilayer ceramic capacitor 10 among the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c, and the second side surface 12d. In addition, the area of ​​the first plated layer exposed region 35a can be obtained based on the area of ​​the region where the first lower plated layer 34a1 faces the outside of the two-terminal multilayer ceramic capacitor 10. For example, the area of ​​the first plated layer exposed region 35a can be obtained based on the area of ​​the first main surface 12a, the second main surface 12b, the second end surface 12f, the first side surface 12c, and the second side surface 12d where the first lower plated layer 34a1 faces the outside of the two-terminal multilayer ceramic capacitor 10. Then, the first ratio can be obtained based on the ratio of the area of ​​the first plated layer exposed region 35a to the area of ​​the exposed region of the first external electrode 30a.

[0109] In the case of the first example, in this embodiment, if Figure 7 As shown, the area S30a of the exposed region of the first external electrode 30a can be obtained based on the area of ​​the first external electrode 30a (first base electrode layer 32a, first lower plating layer 34a1, first upper plating layer 34a2) facing the outside of the two-terminal multilayer ceramic capacitor 10 in the first main surface 12a when viewed from the first main surface 12a side (when viewed in the direction of the first main surface). In addition, in the present embodiment, the area S35a of the first plating exposed region 35a can be obtained based on the area of ​​the first lower plating layer 34a1 facing the outside of the two-terminal multilayer ceramic capacitor 10 in all of the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c, and the second side surface 12d. In addition, in Figure 7 , as an example, the first plating layer exposed area 35a is shown on the first main surface 12a side. In addition, the first ratio can be obtained from the ratio of the area S35a of the first plating layer exposed area 35a to the area S30a of the exposed area of ​​the first external electrode 30a. The aforementioned area S30a and area S35a can be observed, for example, using a microscope (for example, VHX series manufactured by KEYENCE Co., Ltd. (hereinafter referred to as VHX)) at a magnification of 200 times and in a bright field.

[0110] In addition, as a second example, the first ratio can be obtained as follows. The area of ​​the exposed region of the first external electrode 30a is obtained in the same manner as in the first example. In addition, in addition to the first upper plating layer 34a2, the first lower plating layer 34a1 is also removed, and when the first plating exposed region 35a intersects with the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c or the second side surface 12d, the area of ​​the first plating exposed region 35a can be obtained by multiplying the thickness of the exposed first lower plating layer 34a1 and the length around the first plating exposed region 35a. Then, the first ratio can be obtained based on the ratio of the area of ​​the first plating exposed region 35a to the area of ​​the exposed region of the first external electrode 30a.

[0111] In the case of the second example, in this embodiment, Figure 7 Similarly, the area S30a of the exposed region of the first external electrode 30a can be obtained based on the area of ​​the first main surface 12a where the first external electrode 30a faces the outside of the two-terminal multilayer ceramic capacitor 10 when viewed from the first main surface 12a side (when viewed in the first main surface direction). In addition, when the first plated layer exposed region 35a intersects with the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c or the second side surface 12d, the area SS35a of the first plated layer exposed region 35a can be obtained by multiplying the thickness t35a of the exposed first lower plating layer 34a1 by the length of the periphery of the first plated layer exposed region 35a (the sum of l35a1, l35a2, l35a3, and l35a4). In addition, Figure 8 , the shape of the first plating exposed area 35a intersecting with respect to the first main surface 12a is shown as an example. Then, the first ratio can be obtained based on the ratio of the area SS35a of the first plating exposed area 35a to the area S30a of the exposed area of ​​the first external electrode 30a. The aforementioned lengths l35a1 to l35a4 can be observed, for example, using a microscope (VHX) at a magnification of 200 times and a bright field. In addition, the aforementioned thickness t35a can be observed, for example, using a microscope (VHX) at a magnification of 2000 times and a bright field after the cross section is polished to, for example, 1 / 2 of the W dimension in the width direction y of the two-terminal multilayer ceramic capacitor 10.

[0112] The second plating layer 34b is arranged to cover the second base electrode layer 32b on the second end face 12f side. Furthermore, the second plating layer 34b may be arranged to cover the second base electrode layer 32b on the first main face 12a, the second main face 12b, the first side face 12c, and the second side face 12d side. However, the second plating layer 34b may be arranged only on the second base electrode layer 32b on the second end face 12f side. The second plating layer 34b includes a second lower plating layer 34b1 arranged on the second base electrode layer 32b and a second upper plating layer 34b2 arranged on the second lower plating layer 34b1. The second upper plating layer 34b2 is arranged on the second lower plating layer 34b1 so that a portion of the second lower plating layer 34b1 is exposed. That is, the second upper plating layer 34b2 is arranged on the second lower plating layer 34b1 except for the second plating exposed area 35b, so that the second lower plating layer 34b1 has the second plating exposed area 35b exposed on the surface of the second external electrode 30b. In this embodiment, the second plating exposed area 35b is arranged on the first main surface 12a. In this case, the second main surface 12b of the two-terminal multilayer ceramic capacitor 10 becomes the mounting surface to the mounting substrate.

[0113] Although not limited to this, it is preferred that the second upper plating layer 34b2 covers the end of the second lower plating layer 34b1. Specifically, the front end of the second lower plating layer 34b1 on the first end face 12e side is preferably covered by the front end of the second upper plating layer 34b2 on the first end face 12e side. Thus, peeling of the second lower plating layer 34b1 can be suppressed.

[0114] For the same reason as the first ratio, the second ratio of the area of ​​the second plating layer exposed region 35b on the first main surface 12a when viewed from the height direction x of the laminate 12 is preferably 0.4% or more and 83.4% or less. Since the second ratio is 0.4% or more, for example, hydrogen released from the first internal electrode layer 16a, the second internal electrode layer 16b, the first base electrode layer 32a, the second base electrode layer 32b, the first lower plating layer 34a1, and the second lower plating layer 34b1 can be fully released from the second plating layer exposed region 35b to the outside of the two-terminal multilayer ceramic capacitor 10, and the degradation of the insulation resistance caused by hydrogen can be suppressed. In addition, since the second ratio is 83.4% or less, the decrease in moisture resistance caused by the intrusion of water vapor from the second plating layer exposed region 35b into the two-terminal multilayer ceramic capacitor 10 can be suppressed.

[0115] More preferably, the second ratio is 1.17% or more and 83.4% or less. Further preferably, the second ratio is 1.40% or more and 83.4% or less. Further preferably, the second ratio is 1.40% or more and 25.0% or less.

[0116] The second ratio can be obtained in the same manner as the first ratio. In the case of the first example described above, in the present embodiment, the area of ​​the exposed region of the second external electrode 30b can be obtained based on the area of ​​the region where the second external electrode 30b (the second base electrode layer 32b, the second lower plating layer 34b1, and the second upper plating layer 34b2) faces the outside of the two-terminal multilayer ceramic capacitor 10 on the first main surface 12a when viewed from the first main surface 12a. In addition, in the present embodiment, the area of ​​the second plating exposed region 35b can be obtained based on the area of ​​the region where the second lower plating layer 34b1 faces the outside of the two-terminal multilayer ceramic capacitor 10 when viewed from all of the first main surface 12a, the second main surface 12b, the second end surface 12f, the first side surface 12c, and the second side surface 12d.

[0117] Furthermore, in the case of the second example described above, in the present embodiment, the area of ​​the exposed region of the second external electrode 30b can be obtained in the same manner as in the first example. In addition, in the present embodiment, when the second plating layer exposed region 35b intersects with the first main surface 12a, the second main surface 12b, the second end surface 12f, the first side surface 12c, or the second side surface 12d, the area of ​​the second plating layer exposed region 35b can be obtained based on the area obtained by multiplying the thickness of the exposed second lower plating layer 34b1 by the length around the second plating layer exposed region 35b.

[0118] Then, the second ratio can be obtained from the ratio of the area of ​​the second plating layer exposed region 35 b to the area of ​​the exposed region of the second external electrode 30 b .

[0119] In the above, the first ratio and the second ratio are respectively obtained as the exposure ratio, but the exposure ratio may also be the ratio of the total area of ​​the first plating layer exposed region 35a and the second plating layer exposed region 35b to the total area of ​​the exposed region of the first external electrode 30a and the second external electrode 30b. Moreover, the total exposure ratio is preferably not less than 0.4% and not more than 83.4%.

[0120] The first plating layer 34 a and the second plating layer 34 b include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0121] Preferably, the first lower plating layer 34a1 and the second lower plating layer 34b1 are Ni plating layers, and the first upper plating layer 34a2 and the second upper plating layer 34b2 are Sn plating layers.

[0122] The first lower plating layer 34a1 and the second lower plating layer 34b1 formed of Ni plating layers are used to prevent the base electrode layer 32 from being corroded by the solder when mounting the two-terminal multilayer ceramic capacitor 10. In addition, the first upper plating layer 34a2 and the second upper plating layer 34b2 formed of Sn plating layers are used to improve the wettability of the solder when mounting the two-terminal multilayer ceramic capacitor 10, so that the mounting can be easily performed.

[0123] The thickness of the first lower plating layer 34a1 and the first upper plating layer 34a2 on the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c, and the second side surface 12d is preferably 2 μm or more and 7 μm or less. The thickness of the second lower plating layer 34b1 and the second upper plating layer 34b2 on the first main surface 12a, the second main surface 12b, the second end surface 12f, the first side surface 12c, and the second side surface 12d is preferably 2 μm or more and 7 μm or less.

[0124] In addition, when the conductive resin layer is formed on the base electrode layer 32, the plating layer 34 is arranged to cover the conductive resin layer. In this case, the Ni plating layer as the lower plating layer in the plating layer 34 also prevents the conductive resin layer from being corroded by the solder, and the Sn plating layer as the upper plating layer also improves the wettability of the solder.

[0125] (3) Dimensions of two-terminal multilayer ceramic capacitors

[0126] The dimension in the length direction z of the two-terminal multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a and the second external electrode 30b is set to L dimension, the dimension in the height direction x of the two-terminal multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a and the second external electrode 30b is set to T dimension, and the dimension in the width direction y of the two-terminal multilayer ceramic capacitor 10 including the stack 12, the first external electrode 30a and the second external electrode 30b is set to W dimension.

[0127] Regarding the dimensions of the two-terminal multilayer ceramic capacitor 10, the L dimension in the length direction z is greater than or equal to 0.2 mm and less than or equal to 6.5 mm, the W dimension in the width direction y is greater than or equal to 0.1 mm and less than or equal to 5.5 mm, and the T dimension in the height direction x is greater than or equal to 0.1 mm and less than or equal to 6.5 mm. In addition, the dimensions of the two-terminal multilayer ceramic capacitor 10 can be measured using a microscope.

[0128] 2. Method for manufacturing two-terminal multilayer ceramic capacitor

[0129] Next, a method for manufacturing the two-terminal multilayer ceramic capacitor 10 will be described.

[0130] (Process 1)

[0131] First, a dielectric sheet for the ceramic layer 14 and a conductive paste for the internal electrode layer 16 are prepared. The dielectric sheet and the conductive paste for the internal electrode layer 16 contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0132] (Process 2)

[0133] Then, a conductive paste for the internal electrode layer 16 is printed on the dielectric sheet in a given pattern by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first internal electrode layer 16a and a dielectric sheet having a pattern of the second internal electrode layer 16b are prepared.

[0134] In addition, regarding the dielectric sheet, a dielectric sheet for an outer layer on which the pattern of the internal electrode layer is not printed is also prepared.

[0135] (Process 3)

[0136] A predetermined number of outer layer dielectric sheets on which the pattern of the internal electrode layer is not printed are stacked to form the outer layer portion 14 a on the second main surface 12 b side (outer layer portion forming step).

[0137] The dielectric sheet on which the pattern of the first internal electrode layer 16a is printed and the dielectric sheet on which the pattern of the second internal electrode layer 16b is printed are sequentially stacked on the outer layer portion 14a on the second main surface 12b side to form the structure of the present invention, thereby forming the inner layer portion 14b (inner layer portion forming step).

[0138] Next, a predetermined number of outer layer dielectric sheets without the inner electrode layer pattern printed thereon are stacked on the inner layer, thereby forming the outer layer portion 14 a on the first main surface 12 a side on the inner layer portion 14 b (outer layer portion forming step).

[0139] (Process 4)

[0140] Next, the laminated sheets are pressed in the laminating direction by isostatic pressing or the like, thereby producing a laminated block.

[0141] (Process 5)

[0142] Then, the stacked block is cut into a given size to cut out stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0143] (Process 6)

[0144] Next, the stacked small pieces are fired to produce the stacked body 12. The firing temperature depends on the materials of the ceramic layers and internal electrode layers as dielectrics, but is preferably 900°C or higher and 1400°C or lower.

[0145] (Process 7)

[0146] Next, conductive paste for external electrodes is applied to both end surfaces 12e, 12f of the laminate 12 to form the base electrode layer 32. The manufacturing process will be described below for the base electrode layer 32 being a sintered layer, a conductive resin layer, and a thin film layer.

[0147] (When the base electrode layer is a sintered layer)

[0148] When the base electrode layer 32 is a sintered layer, a conductive paste containing a glass component and a metal is applied by dipping or screen printing, and then sintered to form the base electrode layer 32. The sintering temperature is preferably 700°C or more and 900°C or less.

[0149] The sintered layer may contain a ceramic component instead of a glass component, or may contain both. The ceramic component is preferably a ceramic material of the same type as the laminate. In addition, when the sintered layer contains a ceramic component, it is preferred that a conductive paste is applied to the laminated small pieces before firing, and the laminated small pieces before firing and the conductive paste applied to the laminated small pieces before firing are simultaneously sintered (fired), thereby forming a laminated body formed with a sintered layer. The temperature (firing temperature) of the sintering treatment at this time is preferably 900° C. or more and 1400° C. or less.

[0150] (When the base electrode layer is a conductive resin layer)

[0151] In the case where the base electrode layer 32 is a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the sintered layer or the laminate 12, and heat-treated at a temperature of 250° C. to 550° C. to thermally cure the resin to form a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0152] (When the base electrode layer is a thin film layer)

[0153] When the foundation electrode layer 32 is a thin film layer, the foundation electrode layer 32 can be formed by a thin film forming method such as sputtering or vapor deposition. The foundation electrode layer 32 formed of a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0154] (Process 8)

[0155] After forming the base electrode layer 32, a plating layer 34 is formed on the surface of the base electrode layer 32. When performing the plating process, either electrolytic plating or electroless plating can be used, but electroless plating requires pretreatment with a catalyst or the like in order to increase the deposition rate of the plating layer, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferably used. As a plating method, drum plating is preferably used. In the present embodiment, a first lower plating layer 34a1 and a second lower plating layer 34b1 (Ni plating layer) and a first upper plating layer 34a2 and a second upper plating layer 34b2 (Sn plating layer) are sequentially formed as the plating layer 34 on the base electrode layer 32.

[0156] When forming the conductive resin layer on the base electrode layer 32, a conductive resin paste containing a resin component and a metal component is prepared and applied to the base electrode layer 32 by a dipping method. Then, the plated layer 34 is formed on the conductive resin layer.

[0157] (Process 9)

[0158] Next, the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) are processed so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a predetermined exposure ratio. As a processing method, for example, a scraping method, a melting method, a method using laser processing, a method using a resist, etc. can be adopted.

[0159] In the scraping method, a metal terminal with a diameter of about 30 to 100 μm is brought into contact with the first upper plating layer 34 a 2 and the second upper plating layer 34 b 2 (Sn plating layer), thereby scraping away the soft Sn plating layer so that the first lower plating layer 34 a 1 and the second lower plating layer 34 b 1 (Ni plating layer) have a given exposure ratio.

[0160] In the dissolving method, the molded body after the plating layer 34 is formed is immersed in an ENSTRIP agent (stripping agent). For example, the heights of the plurality of molded bodies after the plating layer 34 is formed are aligned by an aligning jig, and one surface of the molded body is immersed in an ENSTRIP agent, thereby dissolving the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a given exposure ratio. At this time, it is preferred to immerse the first main surface 12a (and / or the second main surface 12b) side. As a result, the internal electrode layer 16 on the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d can be prevented from being immersed.

[0161] In the method utilizing laser processing, a plurality of molded bodies after forming the plating layer 34 are arranged, and a given area of ​​the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) of each molded body is removed by laser, so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a given exposure ratio.

[0162] By using a resist, the first lower plating layer 34 a 1 and the second lower plating layer 34 b 1 (Ni plating layer) can be formed with a predetermined exposure ratio.

[0163] As described above, the two-terminal multilayer ceramic capacitor 10 according to the present embodiment can be manufactured.

[0164] The first lower plating layer 34a1 is exposed on the surface of the first external electrode 30a in the first plating layer exposed region 35a, so that hydrogen in the two-terminal multilayer ceramic capacitor 10 can be released from the first plating layer exposed region 35a to the outside of the two-terminal multilayer ceramic capacitor 10. Similarly, the second lower plating layer 34b1 is exposed on the surface of the second external electrode 30b in the second plating layer exposed region 35b, so that hydrogen in the two-terminal multilayer ceramic capacitor 10 can be released from the second plating layer exposed region 35b to the outside of the two-terminal multilayer ceramic capacitor 10. Further explanation is as follows.

[0165] In the plating process for forming the first lower plating layer 34a1 and the second lower plating layer 34b1, and the first upper plating layer 34a2 and the second upper plating layer 34b2, hydrogen ions are generated due to chemical reactions. The hydrogen ions may be absorbed as hydrogen by at least one of, for example, the first lower plating layer 34a1 and the second lower plating layer 34b1, the first internal electrode layer 16a and the second internal electrode layer 16b, and the first foundation electrode layer 32a and the second foundation electrode layer 32b. According to the above structure, hydrogen absorbed by at least one of the first lower plating layer 34a1 and the second lower plating layer 34b1, the first internal electrode layer 16a and the second internal electrode layer 16b, and the first base electrode layer 32a and the second base electrode layer 32b (absorption layer) can be released from the first plating layer exposed area 35a and the second plating layer exposed area 35b to the outside of the two-terminal multilayer ceramic capacitor 10. Therefore, it is possible to suppress the state where hydrogen is absorbed by the absorption layer, and it is possible to suppress the degradation of the insulation resistance caused by hydrogen. In particular, even when the absorption layer includes a metal such as Ni that is not easy to absorb hydrogen, it is possible to suppress the degradation of the insulation resistance of the ceramic layer 14 by releasing hydrogen from the first plating layer exposed area 35a and the second plating layer exposed area 35b to the outside of the two-terminal multilayer ceramic capacitor 10.

[0166] In addition, a first plating exposed area 35a and a second plating exposed area 35b are formed on the first main surface 12a side, and the second main surface 12b side becomes the mounting surface of the two-terminal multilayer ceramic capacitor 10 on the mounting substrate. When the solder is mainly applied to the first end surface 12e and the second end surface 12f side, the hydrogen in the absorption layer can be efficiently released from the first main surface 12a that is not coated with solder and does not face the mounting substrate 40 through the first plating exposed area 35a and the second plating exposed area 35b.

[0167] 3. Modifications of Two-Terminal Multilayer Ceramic Capacitors

[0168] Next, a modification of the two-terminal multilayer ceramic capacitor 10 will be described. (1)

[0170] The external electrode 30 of the first embodiment described above includes the base electrode layer 32 and the plating layer 34 . Alternatively, the external electrode 30 may include the plating layer 34 instead of the base electrode layer 32 .

[0171] Although not shown in the drawings, a structure in which the plating layer 34 is provided instead of the base electrode layer 32 will be described below with respect to the first external electrode 30 a and the second external electrode 30 b.

[0172] The first external electrode 30a and the second external electrode 30b may each be formed directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the two-terminal laminated ceramic capacitor 10 may also be a structure in which the first end face 12e and the second end face 12f are plated to form a plating layer 34 electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, the plating layer 34 may be formed by plating after a catalyst is provided on the surface of the laminate 12 as a pretreatment. When the plating treatment is performed, either electrolytic plating or electroless plating may be used. However, electroless plating requires pretreatment with a catalyst or the like in order to increase the deposition rate of the plating layer, and has the disadvantage of complicating the process. Therefore, electrolytic plating is generally preferred. As a plating method, drum plating is preferably used.

[0173] In addition, when the plating layer 34 is formed directly on the stack 12 without providing the base electrode layer 32, the height can be reduced, i.e., the thickness can be thinned, or it can be converted into the thickness of the stack, i.e., the thickness of the effective layer portion, thereby increasing the design freedom of the thickness of the stack 12.

[0174] The plating layer 34 includes a first lower plating layer 34a1 and a second lower plating layer 34b1 (lower plating layer) formed on the surface of the laminate 12, and a first upper plating layer 34a2 and a second upper plating layer 34b2 (upper plating layer) formed on the surface of the first lower plating layer 34a1 and the second lower plating layer 34b1. As in the above-mentioned embodiment, the lower plating layer has a plating exposed area not covered by the upper plating layer. The lower plating layer and the upper plating layer each preferably include at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing the metal.

[0175] Furthermore, the lower plating layer is preferably formed using Ni having solder resist properties, and the upper plating layer is preferably formed using Sn or Au having good solder wettability.

[0176] In addition, for example, when Ni is used to form the first internal electrode layer 16a and the second internal electrode layer 16b, the lower plating layer is preferably formed using Cu having good bonding properties with Ni. The plating layer 34 may have the upper plating layer as the outermost layer, or may further form other plating electrodes on the surface of the upper plating layer.

[0177] Here, when the external electrode 30 is formed only by the plating layer 34 without providing the base electrode layer 32 , the thickness of each plating layer 34 arranged without providing the base electrode layer 32 is preferably 1.0 μm to 20.0 μm.

[0178] Furthermore, it is preferred that the plating layer 34 does not contain glass. It is preferred that the metal ratio per unit volume of the plating layer 34 is 99 volume % or more. (2)

[0180] In the first embodiment described above, the first lower plating layer 34a1 has the first plating exposed region 35a not covered by the first upper plating layer 34a2, and the second lower plating layer 34b1 has the second plating exposed region 35b not covered by the second upper plating layer 34b2. However, the form of the exposed region is not limited thereto, and the external electrode 30 may also have a base exposed region 36 where the base electrode layer 32 is not covered by the plating layer 34.

[0181] Specifically, the first base electrode layer 32a has a first base exposed region 36a which is not covered by the first plating layer 34a. Such a first base exposed region 36a can be formed, for example, Fig. 9 as well as Fig.10 The morphology is formed. Fig. 9In the embodiment, a first plating exposed region 35a is formed so that the first main surface 12a side of the first lower plating layer 34a1 is exposed, and a first base exposed region 36a is formed in the first plating exposed region 35a. In the first base exposed region 36a, the first main surface 12a side of the first base electrode layer 32a is not covered by the first lower plating layer 34a1 and the first upper plating layer 34a2 and is exposed. Fig.10 In the embodiment, the first plating layer exposed region 35 a and the first base exposed region 36 a are arranged at different positions on the first main surface 12 a .

[0182] like Fig. 9 as well as Fig.10 As shown in FIG. 1 , the first base exposed area 36a is preferably arranged on the first main surface 12a. Furthermore, the second main surface 12b is preferably a mounting surface. Figure 6 When the solder is mainly applied to the first end surface 12e and the second end surface 12f as shown, hydrogen in the gettering layer can be efficiently released from the first main surface 12a not applied with solder and not facing the mounting substrate 40 through the first base exposed region 36a.

[0183] The first base exposed region 36a may be arranged on any of the second main surface 12b, the first end surface 12e, the first side surface 12c, and the second side surface 12d other than the first main surface 12a as long as the solder is not applied.

[0184] Furthermore, the first plated layer exposed region 35a and the first base exposed region 36a may be formed on different surfaces, for example, the first plated layer exposed region 35a may be disposed on the first end surface 12e, and the first base exposed region 36a may be disposed on the first main surface 12a.

[0185] In addition, the first base exposed area 36a is preferably formed on the first end face 12e side relative to the front end portion on the second end face 12f side of the first lower plating layer 34a1. In other words, the front end portion on the second end face 12f side of the first base electrode layer 32a is preferably covered by the front end portion on the second end face 12f side of the first lower plating layer 34a1. Thus, peeling of the first base electrode layer 32a can be suppressed.

[0186] The first base exposed area 36a can be formed by removing the first lower plating layer 34a1 and the first upper plating layer 34a2 by scraping, melting, laser processing, or using an anti-etching agent, as in the first plating exposed area 35a.

[0187] Although not shown in the drawings, the second base electrode layer 32 b can also have a second base exposed region that is not covered by the second plating layer 34 b . (3)

[0189] In the first embodiment described above, the first plating exposed region 35a where the first lower plating layer 34a1 is not covered by the first upper plating layer 34a2 is provided on the first main surface 12a. Similarly, the second plating exposed region 35b where the second lower plating layer 34b1 is not covered by the second upper plating layer 34b2 is provided on the first main surface 12a. This is not limiting, and the plating exposed region 35 only needs to be provided on at least any one of the first main surface 12a, the second main surface 12b, the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d. (4)

[0191] In the first embodiment described above, the first plating exposed region 35a of the first external electrode 30a and the second plating exposed region 35b of the second external electrode 30b are provided. However, at least one of the first plating exposed region 35a and the second plating exposed region 35b may be provided. (5)

[0193] In the first embodiment described above, the first lower plating layer 34a1 is arranged to cover the entire first foundation electrode layer 32a, and the second lower plating layer 34b1 is arranged to cover the entire second foundation electrode layer 32b. However, this is not limiting, and the first lower plating layer 34a1 may be arranged to cover a portion of the first foundation electrode layer 32a, and the second lower plating layer 34b1 may be arranged to cover a portion of the second foundation electrode layer 32b.

[0194] B. Second Embodiment

[0195] 1. Three-terminal multilayer ceramic capacitors

[0196] As an example of the multilayer ceramic electronic component according to the second embodiment of the present invention, a three-terminal multilayer ceramic capacitor will be described.

[0197] Fig.11 It is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Fig.12 It is a plan view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Fig.13 It is a front view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Fig.14 yes Fig.11 Cross-sectional view at line XIV-XIV. Fig.15 yes Fig.11 Cross-sectional view at line XV-XV. Fig.16 yes Fig.14 Cross-sectional view at line XVI-XVI of . Fig.17 yes Fig.14 Cross-sectional view taken along line XVII-XVII.

[0198] like Fig.11 As shown, the three-terminal multilayer ceramic capacitor 100 includes, for example, a substantially rectangular parallelepiped multilayer body 12 and external electrodes 30 .

[0199] (1) Laminated body

[0200] The laminated body 12 includes a plurality of laminated ceramic layers 14 and a plurality of internal electrode layers 16 laminated on the ceramic layers 14. The ceramic layers 14 and the internal electrode layers 16 are laminated in the height direction x.

[0201] The stack 12 has the first principal surface 12a and the second principal surface 12b opposite in the height direction x, the first side surface 12c and the second side surface 12d opposite in the width direction y orthogonal to the height direction x, and the first end surface 12e and the second end surface 12f opposite in the length direction z orthogonal to the height direction x and the width direction y. In this stack 12, the corners and the ridges are rounded. In addition, the so-called corners are the parts where three adjacent faces of the stack intersect, and the so-called ridges are the parts where two adjacent faces of the stack intersect. In addition, it is also possible to form concave-convex etc. on part or all of the first principal surface 12a and the second principal surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0202] In addition, the dimension L of the laminate 12 in the longitudinal direction z is not necessarily longer than the dimension W in the width direction y.

[0203] The laminated body 12 includes an inner layer portion 18 , and a first main surface side outer layer portion 20 a and a second main surface side outer layer portion 20 b which are arranged to sandwich the inner layer portion 18 in the lamination direction.

[0204] The inner layer portion 18 includes a plurality of ceramic layers 14 and a plurality of internal electrode layers 16. The inner layer portion 18 includes the internal electrode layer 16 located closest to the first main surface 12a to the internal electrode layer 16 located closest to the second main surface 12b in the stacking direction. The internal electrode layer 16 includes a first internal electrode layer 16a extending to the first end surface 12e and the second end surface 12f and a second internal electrode layer 16b extending to the first side surface 12c and the second side surface 12d. In the inner layer portion 18, a plurality of first internal electrode layers 16a and second internal electrode layers 16b are opposed to each other via the ceramic layer 14. The inner layer portion 18 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0205] The laminate 12 has a first main surface side outer layer portion 20a, which is located on the first main surface 12a side and is formed by a plurality of ceramic layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a straight line on the outermost surface. The first main surface side outer layer portion 20a is an aggregate of a plurality of ceramic layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. The ceramic layer 14 used in the first main surface side outer layer portion 20a may be the same as the ceramic layer 14 used in the inner layer portion 18.

[0206] Similarly, the laminate 12 has a second main surface side outer layer portion 20b, which is located on the second main surface 12b side and is formed by a plurality of ceramic layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a straight line on the outermost surface. The second main surface side outer layer portion 20b is an aggregate of a plurality of ceramic layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The ceramic layer 14 used in the second main surface side outer layer portion 20b may be the same as the ceramic layer 14 used in the inner layer portion 18.

[0207] Furthermore, the laminate 12 has a first side surface outer layer portion 22a located on the first side surface 12c side and formed of a plurality of ceramic layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side.

[0208] Similarly, the laminate 12 has a second side outer layer portion 22b located on the second side 12d side and formed of a plurality of ceramic layers 14 located between the second side 12d and the outermost surface of the inner layer portion 18 on the second side 12d side.

[0209] In addition, the first side surface outer layer portion 22a and the second side surface outer layer portion 22b are also referred to as W gaps or side gaps.

[0210] Furthermore, the laminate 12 has a first end surface side outer layer portion 24a located on the first end surface 12e side and formed of a plurality of ceramic layers 14 located between the first end surface 12e and the outermost surface of the inner layer portion 18 on the first end surface 12e side.

[0211] Similarly, the laminate 12 has a second end surface side outer layer portion 24b located on the second end surface 12f side and formed of a plurality of ceramic layers 14 located between the second end surface 12f and the outermost surface of the inner layer portion 18 on the second end surface 12f side.

[0212] In addition, the first end surface side outer layer portion 24a and the second end surface side outer layer portion 24b are also referred to as L gaps or end gaps.

[0213] The size of the laminate 12 is not particularly limited.

[0214] The ceramic layer 14 can be formed of a dielectric material, for example, as a ceramic material. As such a dielectric material, for example, a dielectric ceramic containing a component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. In the case of containing the above-mentioned dielectric material as a main component, a material to which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound whose content is less than that of the main component can be added, for example, depending on the desired characteristics of the laminate 12.

[0215] The thickness of the ceramic layer 14 after firing is preferably 0.35 μm or more and 0.60 μm or less. The number of stacked ceramic layers 14 is preferably 10 or more and 2000 or less. In addition, the number of ceramic layers 14 is the total number of ceramic layers 14 of the inner layer portion 18 and the number of ceramic layers 14 of the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b.

[0216] The laminated body 12 includes a plurality of first internal electrode layers 16 a and a plurality of second internal electrode layers 16 b as the plurality of internal electrode layers 16 .

[0217] The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b may be alternately stacked with the ceramic layer 14 interposed therebetween, or the ceramic layer 14 having the second internal electrode layer 16b may be stacked after stacking a plurality of ceramic layers 14 having the first internal electrode layers 16a. In this way, the stacking pattern can be changed according to the capacitance value to be achieved.

[0218] like Fig.16 As shown in FIG. 1 , the first internal electrode layer 16a includes a first opposing electrode portion 26a opposed to the second internal electrode layer 16b, a first lead electrode portion 28a1 led from the first opposing electrode portion 26a to the surface of the first end face 12e of the multilayer body 12, and a second lead electrode portion 28a2 led from the first opposing electrode portion 26a to the surface of the second end face 12f of the multilayer body 12. Specifically, the first lead electrode portion 28a1 is exposed on the surface of the first end face 12e of the multilayer body 12, and the second lead electrode portion 28a2 is exposed on the surface of the second end face 12f of the multilayer body 12. Therefore, the first internal electrode layer 16a is not exposed on the surfaces of the first side face 12c and the second side face 12d of the multilayer body 12.

[0219] The shapes of the first counter electrode portion 26a and the first lead electrode portion 28a1 and the second lead electrode portion 28a2 are not particularly limited, but are preferably rectangular shapes. However, the corners may be rounded.

[0220] The lengths of the first lead electrode portion 28a1 and the second lead electrode portion 28a2 in the width direction y may be the same as or shorter than the length of the first counter electrode portion 26a in the width direction y.

[0221] Furthermore, the first extraction electrode portion 28a1 and the second extraction electrode portion 28a2 may have a tapered shape.

[0222] like Fig.17 As shown, the second internal electrode layer 16b is substantially cross-shaped and includes a second opposing electrode portion 26b opposed to the first internal electrode layer 16a, a third lead electrode portion 28b1 led from the second opposing electrode portion 26b to the surface of the first side surface 12c of the stacked body 12, and a fourth lead electrode portion 28b2 led from the second opposing electrode portion 26b to the surface of the second side surface 12d of the stacked body 12. Specifically, the third lead electrode portion 28b1 is exposed on the surface of the first side surface 12c of the stacked body 12, and the fourth lead electrode portion 28b2 is exposed on the surface of the second side surface 12d of the stacked body 12. Therefore, the second internal electrode layer 16b is not exposed on the surface of the first end surface 12e and the surface of the second end surface 12f of the stacked body 12.

[0223] The second counter electrode portion 26b and the third and fourth lead-out electrode portions 28b1 and 28b2 are preferably rectangular in shape, but the corners may be rounded.

[0224] The relationship between the dimension A of the second opposing electrode portion 26b in the length direction z connecting the side on the first end face 12e side and the side on the second end face 12f side and the dimension B of the third lead-out electrode portion 28b1 and the fourth lead-out electrode portion 28b2 in the length direction z connecting the side on the first end face 12e side and the side on the second end face 12f side is preferably A≥B.

[0225] The third lead electrode portion 28b1 may have a tapered shape whose width becomes narrower toward the first side surface 12c, and the fourth lead electrode portion 28b2 may have a tapered shape whose width becomes narrower toward the second side surface 12d.

[0226] In addition, the stacked body 12 has an opposing electrode portion 27. The opposing electrode portion 27 is a portion where the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b face each other. The opposing electrode portion 27 is configured as a part of the inner layer portion 18. In addition, the opposing electrode portion 27 is also called a capacitor effective portion.

[0227] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be formed of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0228] The number of the first internal electrode layers 16 a and the second internal electrode layers 16 b is not particularly limited, but is preferably about 10 or more and 2000 or less in total, for example.

[0229] The thickness of the first internal electrode layer 16 a is not particularly limited, but is preferably about 0.40 μm or more and 0.50 μm or less, for example.

[0230] The thickness of the second internal electrode layer 16 b is not particularly limited, but is preferably about 0.40 μm or more and 0.50 μm or less, for example.

[0231] (2) External electrodes

[0232] The external electrodes 30 are arranged on the first end face 12 e side and the second end face 12 f side, the first side face 12 c side and the second side face 12 d side of the laminate 12 , and the first main face 12 a and the second main face 12 b .

[0233] The external electrode 30 includes a first external electrode 30 a , a second external electrode 30 b , a third external electrode 30 c , and a fourth external electrode 30 d .

[0234] The first external electrode 30a is connected to the first internal electrode layer 16a and is arranged on the surface of the first end surface 12e. In addition, the first external electrode 30a extends from the first end surface 12e of the stacked body 12 and is also arranged on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 28a1 of the first internal electrode layer 16a.

[0235] The second external electrode 30b is connected to the first internal electrode layer 16a and is arranged on the surface of the second end surface 12f. In addition, the second external electrode 30b extends from the second end surface 12f of the stacked body 12 and is also arranged on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead electrode portion 28a2 of the first internal electrode layer 16a.

[0236] The third external electrode 30c is connected to the second internal electrode layer 16b and is arranged on the surface of the first side surface 12c. In addition, the third external electrode 30c extends from the first side surface 12c of the stacked body 12 and is also arranged on a part of the first main surface 12a and a part of the second main surface 12b. In this case, the third external electrode 30c is electrically connected to the third lead electrode portion 28b1 of the second internal electrode layer 16b. In addition, the third external electrode 30c may also be arranged only on the surface of the first side surface 12c.

[0237] The fourth external electrode 30d is connected to the second internal electrode layer 16b and is arranged on the surface of the second side surface 12d. In addition, the fourth external electrode 30d extends from the second side surface 12d of the stacked body 12 and is also arranged on a part of the first main surface 12a and a part of the second main surface 12b. In this case, the fourth external electrode 30d is electrically connected to the fourth lead electrode portion 28b2 of the second internal electrode layer 16b. In addition, the fourth external electrode 30d may be arranged only on the surface of the second side surface 12d.

[0238] In the laminate 12, the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b are opposed to each other via the ceramic layer 14, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a and the second external electrode 30b connected to the first internal electrode layer 16a and the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode layer 16b, showing the characteristics of a capacitor.

[0239] The external electrode 30 includes a base electrode layer 32 including a metal component and a glass component, and a plating layer 34 disposed on the surface of the base electrode layer 32. The plating layer 34 includes a lower plating layer and an upper plating layer.

[0240] The first external electrode 30a includes a first base electrode layer 32a including a metal component, a first lower plating layer 34a1 disposed on the first base electrode layer 32a, and a first upper plating layer 34a2 disposed on the first lower plating layer 34a1. In addition, the first external electrode 30a includes a first plating exposed region 35a exposed on the surface of the first external electrode 30a.

[0241] The second external electrode 30b includes a second base electrode layer 32b including a metal component, a second lower plating layer 34b1 disposed on the second base electrode layer 32b, and a second upper plating layer 34b2 disposed on the second lower plating layer 34b1. In addition, the second external electrode 30b includes a second plating exposed region 35b exposed on the surface of the second external electrode 30b.

[0242] The third external electrode 30c includes a third base electrode layer 32c including a metal component, a third lower plating layer 34c1 disposed on the third base electrode layer 32c, and a third upper plating layer 34c2 disposed on the third lower plating layer 34c1.

[0243] The fourth external electrode 30d includes a fourth base electrode layer 32d including a metal component, a fourth lower plating layer 34d1 disposed on the fourth base electrode layer 32d, and a fourth upper plating layer 34d2 disposed on the fourth lower plating layer 34d1.

[0244] (2-1) Base electrode layer

[0245] The foundation electrode layer 32 includes a first foundation electrode layer 32 a , a second foundation electrode layer 32 b , a third foundation electrode layer 32 c , and a fourth foundation electrode layer 32 d .

[0246] The first foundation electrode layer 32a is connected to the first internal electrode layer 16a and is arranged on the surface of the first end surface 12e. In addition, the first foundation electrode layer 32a extends from the first end surface 12e and is also arranged on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the first foundation electrode layer 32a is electrically connected to the first extraction electrode portion 28a1 of the first internal electrode layer 16a.

[0247] The second foundation electrode layer 32b is connected to the first internal electrode layer 16a and is arranged on the surface of the second end surface 12f. In addition, the second foundation electrode layer 32b extends from the second end surface 12f and is also arranged on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the second foundation electrode layer 32b is electrically connected to the second extraction electrode portion 28a2 of the first internal electrode layer 16a.

[0248] The third foundation electrode layer 32c is connected to the second internal electrode layer 16b and is arranged on the surface of the first side surface 12c. In addition, the third foundation electrode layer 32c extends from the first side surface 12c and is also arranged on a part of the first main surface 12a and a part of the second main surface 12b. In this case, the third foundation electrode layer 32c is electrically connected to the third extraction electrode portion 28b1 of the second internal electrode layer 16b.

[0249] The fourth foundation electrode layer 32d is connected to the second internal electrode layer 16b and is arranged on the surface of the second side surface 12d. In addition, the fourth foundation electrode layer 32d extends from the second side surface 12d and is also arranged on a part of the first main surface 12a and a part of the second main surface 12b. In this case, the fourth foundation electrode layer 32d is electrically connected to the fourth extraction electrode portion 28b2 of the second internal electrode layer 16b.

[0250] The base electrode layer 32 includes at least one selected from a sintered layer, a conductive resin layer, a thin film layer, and the like.

[0251] Hereinafter, each structure in the case where the base electrode layer 32 is set as the above-mentioned sintered layer, conductive resin layer, and thin film layer will be described.

[0252] (When the base electrode layer is a sintered layer)

[0253] The sintered layer contains a glass component and a metal component. The glass component of the sintered layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. As the metal component of the sintered layer, for example, it contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The sintered layer is a sintered layer obtained by applying a conductive paste containing a glass component and a metal component to the stacked body 12 and sintering it. The sintered layer can be a sintered layer obtained by simultaneously sintering the stacked small pieces having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the stacked small pieces, or it can be a sintered layer obtained by sintering the conductive paste to the stacked body 12 after the stacked small pieces having the internal electrode layer 16 and the ceramic layer 14 are sintered to obtain the stacked body 12. In addition, regarding the sintered layer, when the laminated small pieces having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the laminated small pieces are simultaneously sintered, the sintered layer is preferably formed by sintering a material to which a dielectric material is added instead of a glass component. The sintered layer may also be a plurality of layers.

[0254] When the base electrode layer 32 contains a dielectric material instead of a glass component, it is possible to improve the adhesion between the laminated body 12 and the base electrode layer 32. The base electrode layer 32 may contain both a glass component and a dielectric component.

[0255] The dielectric material included in the base electrode layer 32 may be the same as or different from the ceramic layer 14. The dielectric component includes, for example, at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, and the like.

[0256] When the first foundation electrode layer 32a is formed of a sintered layer, the thickness in the length direction z at the center of the first end surface 12e in the height direction x of the first foundation electrode layer 32a is preferably about 3 μm or more and 20 μm or less, for example.

[0257] When the second foundation electrode layer 32b is formed of a sintered layer, the thickness in the length direction z of the second foundation electrode layer 32b located in the center of the height direction x of the second end surface 12f is preferably about 3 μm to 20 μm, for example.

[0258] In addition, when the base electrode layer 32 is provided on the first principal surface 12a and the second principal surface 12b by a sintered layer, the thickness in the height direction x connecting the first principal surface 12a and the second principal surface 12b at the central portion in the length direction z of the first base electrode layer 32a located on the first principal surface 12a and the second principal surface 12b is, for example, preferably greater than 3 μm and less than 20 μm (the thickness of the base electrode layer in the central portion of the e dimension), and the thickness in the height direction x connecting the first principal surface 12a and the second principal surface 12b at the central portion in the length direction z of the second base electrode layer 32b located on the first principal surface 12a and the second principal surface 12b is, for example, preferably greater than 3 μm and less than 20 μm (the thickness of the base electrode layer in the central portion of the e dimension).

[0259] Furthermore, when the base electrode layer 32 is provided on the first side surface 12c and the second side surface 12d by means of a sintered layer, the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the central portion in the length direction z of the first base electrode layer 32a located on the first side surface 12c and the second side surface 12d is, for example, preferably greater than 3 μm and less than 20 μm (the thickness of the base electrode layer in the central portion of the end surface), and the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the central portion in the length direction z of the second base electrode layer 32b located on the first side surface 12c and the second side surface 12d is, for example, preferably greater than 3 μm and less than 20 μm (the thickness of the base electrode layer in the central portion of the side surface).

[0260] (When the base electrode layer is a conductive resin layer)

[0261] When a conductive resin layer is provided as the base electrode layer 32 , the conductive resin layer may be arranged on the sintered layer so as to cover the sintered layer, or may be arranged directly on the laminated body 12 .

[0262] The conductive resin layer contains metal and thermosetting resin.

[0263] The conductive resin layer may completely cover the base electrode layer or may cover a portion of the base electrode layer.

[0264] The conductive resin layer contains a thermosetting resin and is therefore more flexible than a conductive layer composed of, for example, a plated film or a sintered product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the three-terminal multilayer ceramic capacitor 100, the conductive resin layer functions as a buffer layer and can prevent cracks from being generated in the three-terminal multilayer ceramic capacitor 100.

[0265] As the metal contained in the conductive resin layer, Ag, Cu, Ni, Sn, Bi, or an alloy containing these can be used.

[0266] In addition, metal powder coated with Ag on the surface of the metal powder can also be used. When using a metal coated with Ag on the surface of the metal powder, as the metal powder, it is preferred to use Cu, Ni, Sn, Bi or their alloy powders. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, so it is suitable for electrode materials, and Ag is a noble metal, so it is not oxidized and has high weather resistance. In addition, the reason for using Ag-coated metal powder is that the metal of the base material can be made cheap while maintaining the above-mentioned characteristics of Ag.

[0267] Furthermore, as the metal contained in the conductive resin layer, metal obtained by subjecting Cu and Ni to an oxidation-proof treatment can be used.

[0268] In addition, as the metal contained in the conductive resin layer, a metal powder obtained by coating the surface of Sn, Ni, or Cu can also be used. When a metal obtained by coating the surface of Sn, Ni, or Cu is used, as the metal powder, Ag, Cu, Ni, Sn, Bi, or alloy powders thereof are preferably used.

[0269] The metal contained in the conductive resin layer preferably accounts for 35 vol % or more and 75 vol % or less relative to the volume of the entire conductive resin.

[0270] The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0271] The metal contained in the conductive resin layer mainly bears the electrical conductivity of the conductive resin layer. Specifically, the conductive fillers are in contact with each other, thereby forming an electrical path inside the conductive resin layer.

[0272] The metal contained in the conductive resin layer may be in a spherical shape, a flat shape, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0273] As the resin of the conductive resin layer, various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, polyurethane resin, silicone resin, polyimide resin, etc. can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0274] The conductive resin layer preferably contains the resin in an amount of 25 vol % or more and 65 vol % or less relative to the volume of the entire conductive resin.

[0275] In addition, it is preferred that a curing agent is included in the conductive resin layer together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenols, amines, acid anhydrides, imidazoles, active esters, and amide-imides can be used as the curing agent for the epoxy resin.

[0276] The conductive resin layer may be a plurality of layers.

[0277] The thickness of the conductive resin layer located at the first end surface 12 e and the second end surface 12 f and located at the center of the stacked body 12 in the height direction x is preferably about 3 μm or more and 30 μm or less, for example.

[0278] In addition, when a conductive resin layer is also provided on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, the thickness of the conductive resin layer at the central portion of the conductive resin layer located in the longitudinal direction z of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d is preferably, for example, greater than 3 μm and less than 30 μm.

[0279] (When the base electrode layer is a thin film layer)

[0280] When a thin film layer is provided as the base electrode layer 32 , the thin film layer is a layer having a thickness of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition and in which metal particles are deposited.

[0281] (2-2) Plating layer

[0282] Reference Figure 14 to Figure 17 The following describes the first plating layer 34 a , the second plating layer 34 b , the third plating layer 34 c , and the fourth plating layer 34 d as the plating layer 34 that can be disposed on the base electrode layer 32 . The plating layer 34 has a plating exposed region 35 .

[0283] The first plating layer 34a is arranged to cover the first base electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be arranged to cover the first base electrode layer 32a on the first main face 12a, the second main face 12b, the first side face 12c, and the second side face 12d side. However, the first plating layer 34a may be arranged only on the first base electrode layer 32a on the first end face 12e side. The first plating layer 34a includes a first lower plating layer 34a1 arranged on the first base electrode layer 32a and a first upper plating layer 34a2 arranged on the first lower plating layer 34a1. The first upper plating layer 34a2 is arranged on the first lower plating layer 34a1 so that a portion of the first lower plating layer 34a1 is exposed. That is, the first upper plating layer 34a2 is arranged on the first lower plating layer 34a1 except for the first plating exposed area 35a, so that the first lower plating layer 34a1 has the first plating exposed area 35a exposed on the surface of the first external electrode 30a. In this embodiment, the first plating exposed area 35a is arranged on the first main surface 12a. In this case, the second main surface 12b of the three-terminal multilayer ceramic capacitor 100 becomes the mounting surface to the mounting substrate.

[0284] The first upper plating layer 34a2 preferably covers the end of the first lower plating layer 34a1. This can suppress the first lower plating layer 34a1 from peeling off.

[0285] The first ratio of the area of ​​the first plating layer exposed region 35a on the first main surface 12a to the area of ​​the exposed region of the first external electrode 30a when viewed from the height direction x of the laminate 12 is preferably 0.4% or more and 83.4% or less. Since the first ratio is 0.4% or more, for example, hydrogen released from the first internal electrode layer 16a, the second internal electrode layer 16b, the first base electrode layer 32a, the second base electrode layer 32b, the first lower plating layer 34a1, and the second lower plating layer 34b1 can be fully released from the first plating layer exposed region 35a to the outside of the three-terminal multilayer ceramic capacitor 100, and the degradation of the insulation resistance caused by hydrogen can be suppressed. In addition, since the first ratio is 83.4% or less, the ratio of the first lower plating layer 34a1 not covered by the first upper plating layer 34a2 can be suppressed. This can suppress a decrease in moisture resistance due to the intrusion of water vapor from the first plated layer exposed region 35 a into the three-terminal multilayer ceramic capacitor 100 .

[0286] More preferably, the first ratio is 1.17% or more and 83.4% or less. Further preferably, the first ratio is 1.40% or more and 83.4% or less. Further preferably, the first ratio is 1.40% or more and 25.0% or less. In addition, the calculation method of the first ratio is the same as that of the first embodiment.

[0287] The second plating layer 34b is arranged to cover the second base electrode layer 32b on the second end face 12f side. Furthermore, the second plating layer 34b may be arranged to cover the second base electrode layer 32b on the first main face 12a, the second main face 12b, the first side face 12c, and the second side face 12d side. However, the second plating layer 34b may be arranged only on the second base electrode layer 32b on the second end face 12f side. The second plating layer 34b includes a second lower plating layer 34b1 arranged on the second base electrode layer 32b and a second upper plating layer 34b2 arranged on the second lower plating layer 34b1. The second upper plating layer 34b2 is arranged on the second lower plating layer 34b1 so that a portion of the second lower plating layer 34b1 is exposed. That is, the second upper plating layer 34b2 is arranged on the second lower plating layer 34b1 except for the second plating exposed area 35b, so that the second lower plating layer 34b1 has the second plating exposed area 35b exposed on the surface of the second external electrode 30b. In this embodiment, the second plating exposed area 35b is arranged on the first main surface 12a. In this case, the second main surface 12b of the three-terminal multilayer ceramic capacitor 100 becomes the mounting surface to the mounting substrate.

[0288] The second upper plating layer 34b2 preferably covers the end of the second lower plating layer 34b1. This can suppress the second lower plating layer 34b1 from peeling off.

[0289] For the same reason as the first ratio, the second ratio of the second plating layer exposed area 35b on the first main surface 12a relative to the exposed area of ​​the second external electrode 30b when viewed from the height direction x of the stack 12 is preferably 0.4% or more and 83.4% or less. More preferably, the second ratio is 1.17% or more and 83.4% or less. Further preferably, the second ratio is 1.40% or more and 83.4% or less. Further preferably, the second ratio is 1.40% or more and 25.0% or less. In addition, the calculation method of the second ratio is the same as that of the first embodiment.

[0290] In the above, the first ratio and the second ratio are respectively obtained as the exposure ratio, but the exposure ratio may also be the ratio of the total area of ​​the first plating layer exposed region 35a and the second plating layer exposed region 35b to the total area of ​​the exposed region of the first external electrode 30a and the second external electrode 30b. Moreover, the total exposure ratio is preferably not less than 0.4% and not more than 83.4%.

[0291] The third plating layer 34c is arranged to cover the third base electrode layer 32c on the first side surface 12c side. Furthermore, the third plating layer 34c may be arranged to cover the third base electrode layer 32c on the first main surface 12a and the second main surface 12b side. However, the third plating layer 34c may be arranged only on the third base electrode layer 32c on the first side surface 12c side. The third plating layer 34c includes a third lower plating layer 34c1 arranged on the third base electrode layer 32c and a third upper plating layer 34c2 arranged on the third lower plating layer 34c1. The third upper plating layer 34c2 covers the third lower plating layer 34c1, and the third lower plating layer 34c1 does not have an exposed area.

[0292] The fourth plating layer 34d is arranged to cover the fourth base electrode layer 32d on the second side surface 12d side. Furthermore, the fourth plating layer 34d may be arranged to cover the fourth base electrode layer 32d on the first main surface 12a and the second main surface 12b side. However, the fourth plating layer 34d may be arranged only on the fourth base electrode layer 32d on the second side surface 12d side. The fourth plating layer 34d includes a fourth lower plating layer 34d1 arranged on the fourth base electrode layer 32d and a fourth upper plating layer 34d2 arranged on the fourth lower plating layer 34d1. The fourth upper plating layer 34d2 covers the fourth lower plating layer 34d1, and the fourth lower plating layer 34d1 does not have an exposed area.

[0293] In the three-terminal multilayer ceramic capacitor 100 of the present embodiment, a positive potential is applied to the first external electrode 30a having the first plated exposed area 35a and the second external electrode 30b having the second plated exposed area 35b, and a negative potential is applied to the third external electrode 30c and the fourth external electrode 30d.

[0294] The first to fourth plating layers 34 a to 34 d include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0295] Preferably, the first to fourth lower plating layers 34a1 to 34d1 are Ni plating layers, and the first to fourth upper plating layers 34a2 to 34d2 are Sn plating layers.

[0296] The first lower plating layer 34a1 to the fourth lower plating layer 34d1 formed of the Ni plating layer are used to prevent the base electrode layer 32 from being corroded by the solder when mounting the three-terminal multilayer ceramic capacitor 100. In addition, the first upper plating layer 34a2 to the fourth upper plating layer 34d2 formed of the Sn plating layer are used to improve the wettability of the solder when mounting the three-terminal multilayer ceramic capacitor 100, so that it can be mounted easily.

[0297] The thickness of the first lower plating layer 34a1 and the first upper plating layer 34a2 on the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c, and the second side surface 12d is preferably 2 μm or more and 7 μm or less. The thickness of the second lower plating layer 34b1 and the second upper plating layer 34b2 on the first main surface 12a, the second main surface 12b, the second end surface 12f, the first side surface 12c, and the second side surface 12d is preferably 2 μm or more and 7 μm or less. In addition, the thickness of the third lower plating layer 34c1 and the third upper plating layer 34c2 on the first main surface 12a, the second main surface 12b, and the first side surface 12c is preferably 2 μm or more and 7 μm or less. The thickness of the fourth lower plating layer 34 d 1 and the fourth upper plating layer 34 d 2 on the first main surface 12 a , the second main surface 12 b , and the second side surface 12 d is preferably 2 μm or more and 7 μm or less.

[0298] In addition, when the conductive resin layer is formed on the base electrode layer 32, the plating layer 34 is arranged to cover the conductive resin layer. Even in this case, the Ni plating layer as the lower plating layer in the plating layer 34 prevents the conductive resin layer from being corroded by the solder, and the Sn plating layer as the upper plating layer improves the wettability of the solder.

[0299] (3) Dimensions of three-terminal multilayer ceramic capacitors

[0300] The dimension in the length direction z of the three-terminal multilayer ceramic capacitor 100 including the stack 12 and the first to fourth external electrodes 30a to 30d is set as the L dimension, the dimension in the height direction x of the three-terminal multilayer ceramic capacitor 100 including the stack 12 and the first to fourth external electrodes 30a to 30d is set as the T dimension, and the dimension in the width direction y of the three-terminal multilayer ceramic capacitor 100 including the stack 12 and the first to fourth external electrodes 30a to 30d is set as the W dimension.

[0301] The dimensions of the three-terminal multilayer ceramic capacitor 100 are not particularly limited, but the L dimension in the length direction z is 0.2 mm or more and 6.5 mm or less, the W dimension in the width direction y is 0.1 mm or more and 5.5 mm or less, and the T dimension in the height direction x is 0.1 mm or more and 6.5 mm or less. The dimensions of the three-terminal multilayer ceramic capacitor 100 can be measured using a microscope.

[0302] 2. Method for manufacturing three-terminal multilayer ceramic capacitor

[0303] Next, a method for manufacturing a three-terminal multilayer ceramic capacitor will be described.

[0304] (Process 1)

[0305] First, a dielectric sheet for a ceramic layer and a conductive paste for an internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0306] (Process 2)

[0307] Then, a conductive paste for the internal electrode layer is printed on the dielectric sheet in a given pattern by, for example, screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first internal electrode layer formed thereon and a dielectric sheet having a pattern of the second internal electrode layer formed thereon are prepared. More specifically, a screen plate for printing the first internal electrode layer and a screen plate for printing the second internal electrode layer can be prepared separately, and the patterns of the internal electrode layers can be printed using a printer capable of printing the two screen plates.

[0308] (Process 3)

[0309] Next, a predetermined number of dielectric sheets for the outer layer on which the pattern of the internal electrode layer is not printed are stacked, thereby forming a portion of the second main surface side that becomes the outer layer portion of the second main surface side. Then, a dielectric sheet on which the pattern of the first internal electrode layer is printed and a dielectric sheet on which the pattern of the second internal electrode layer is printed are sequentially stacked on the portion that becomes the outer layer portion of the second main surface side, so as to form the structure of the present invention, thereby forming a portion that becomes the inner layer portion. A predetermined number of dielectric sheets for the outer layer on which the pattern of the internal electrode layer is not printed are stacked on the portion that becomes the inner layer portion, thereby forming a portion of the first main surface side that becomes the outer layer portion of the first main surface side. Thus, a laminated sheet is produced.

[0310] (Process 4)

[0311] Next, the laminated sheets are pressed in the laminating direction by isostatic pressing or the like, thereby producing a laminated block.

[0312] (Process 5)

[0313] Then, the stacked block is cut into a given size to cut out stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0314] (Process 6)

[0315] Next, the cut-out laminated small pieces are fired to produce a laminated body. The firing temperature depends on the materials of the ceramic layer and the internal electrode layer, but is preferably 900° C. or higher and 1400° C. or lower.

[0316] (Process 7)

[0317] Next, the third foundation electrode layer 32c of the third external electrode 30c is formed on the first side surface 12c of the laminated body 12 obtained by firing, and the fourth foundation electrode layer 32d of the fourth external electrode 30d is formed on the second side surface 12d of the laminated body 12.

[0318] (When the base electrode layer is a sintered layer)

[0319] When forming the sintered layers as the third base electrode layer 32c and the fourth base electrode layer 32d, a conductive paste containing a glass component and a metal component is applied and then sintered to form the base electrode layers. The sintering temperature is preferably 700°C or more and 900°C or less.

[0320] Here, various methods can be used as a method for forming the sintered layer. For example, a method of extruding a conductive paste from a slit and applying the conductive paste can be used. In the case of this method, by increasing the amount of conductive paste extruded, the base electrode layer 32 can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0321] In addition, the base electrode layer 32 can also be formed using a roller transfer method. In the case of the roller transfer method, when the base electrode layer 32 is formed not only on the first side surface 12c and the second side surface 12d but also on a part of the first main surface 12a and a part of the second main surface 12b, the base electrode layer 32 can be formed on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during the roller transfer.

[0322] Next, in the laminate obtained by firing, the first foundation electrode layer 32a of the first external electrode 30a is formed on the first end surface 12e, and the second foundation electrode layer 32b of the second external electrode 30b is formed on the second end surface 12f.

[0323] When forming the sintered layers as the first and second base electrode layers 32a and 32b, similarly to the third and fourth base electrode layers 32c and 32d, a conductive paste containing a glass component and a metal component is applied and then sintered to form the base electrode layers. The sintering temperature is preferably 700° C. or higher and 900° C. or lower.

[0324] As a method of applying the conductive paste to both end surfaces of the laminate, for example, a dipping method, a screen printing method, or the like can be used.

[0325] In addition, during the sintering process, the third base electrode layer 32c, the fourth base electrode layer 32d, the first base electrode layer 32a and the second base electrode layer 32b can be sintered simultaneously, or they can be sintered separately on the two side faces 12c and 12d and the two end faces 12e and 12f.

[0326] When the base electrode layer is formed of a sintered layer, the sintered layer may contain a dielectric component. In this case, the dielectric component may be contained instead of the glass component, or both.

[0327] The dielectric component is preferably a dielectric material of the same type as the laminate. In addition, when the sintered layer contains the dielectric component, it is preferred that a conductive paste is applied to the laminated small pieces before firing, and the laminated small pieces before firing and the conductive paste applied to the laminated small pieces before firing are simultaneously sintered (fired) to form a laminated body having a sintered layer formed thereon. The temperature of the sintering treatment (firing temperature) at this time is preferably 900° C. or more and 1400° C. or less.

[0328] (When the base electrode layer is a conductive resin layer)

[0329] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the sintered layer, or the conductive resin layer may be formed directly on the laminate 12 as a single body without forming a sintered layer.

[0330] As a method for forming the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied on the sintered layer or the laminate 12, and heat-treated at a temperature of 250° C. to 550° C. to thermally cure the resin to form a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0331] As a method for applying the conductive resin paste, similar to the method of forming the base electrode layer 32 from a sintered layer, for example, a method of applying the conductive resin paste by squeezing it out from a slit or a roll transfer method can be used.

[0332] (When the base electrode layer is a thin film layer)

[0333] When the base electrode layer 32 is formed of a thin film layer, a mask setting or the like can be performed, and the base electrode layer can be formed by a thin film forming method such as sputtering or evaporation at a location where the external electrode 30 is to be formed. The base electrode layer formed of a thin film layer is a layer of 1 μm or less in which metal particles are deposited.

[0334] (Process 8)

[0335] Next, the plating layer 34 is formed. The plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, on the base electrode layer 32, a Ni plating layer is formed as a lower plating layer, and a Sn plating layer is formed as an upper plating layer. In the present embodiment, on the base electrode layer 32, as the plating layer 34, a first lower plating layer 34a1, a second lower plating layer 34b1, a third lower plating layer 34c1, and a fourth lower plating layer 34d1 as Ni plating layers and a first upper plating layer 34a2, a second upper plating layer 34b2, a third upper plating layer 34c2, and a fourth upper plating layer 34d2 as Sn plating layers are sequentially formed. The Ni plating layer and the Sn plating layer are sequentially formed, for example, by a barrel plating method. When performing the plating process, either electrolytic plating or electroless plating can be used. However, electroless plating requires pretreatment with a catalyst or the like in order to increase the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is generally preferred.

[0336] (Process 9)

[0337] Next, the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) are processed so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a predetermined exposure ratio. As a processing method, for example, a scraping method, a melting method, a method using laser processing, a method using a resist, etc. can be adopted.

[0338] In the scraping method, a metal terminal with a diameter of about 30 to 100 μm is brought into contact with the first upper plating layer 34 a 2 and the second upper plating layer 34 b 2 , thereby scraping away the soft Sn plating layer so that the first lower plating layer 34 a 1 and the second lower plating layer 34 b 1 (Ni plating layer) have a predetermined exposure ratio.

[0339] In the dissolving method, the molded body after the plating layer 34 is formed is immersed in an ENSTRIP agent (stripping agent). For example, the heights of the plurality of molded bodies after the plating layer 34 is formed are aligned using an aligning jig, and one surface of the molded body is immersed in an ENSTRIP agent, thereby dissolving the Sn plating layer so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a given exposure ratio. At this time, it is preferred to immerse the first main surface 12a (and / or the second main surface 12b) side. In this way, the internal electrode layer 16 on the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d can be prevented from being immersed.

[0340] In the method using laser processing, a plurality of molded bodies after forming the plating layer 34 are arranged, and a given area of ​​the Sn plating layer of each molded body is removed by laser so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a given exposure ratio.

[0341] Furthermore, by using a resist, it is also possible to form the first lower plating layer 34 a 1 and the second lower plating layer 34 b 1 (Ni plating layer) having a predetermined exposure ratio.

[0342] As described above, the three-terminal multilayer ceramic capacitor 100 according to the present embodiment can be manufactured.

[0343] The three-terminal multilayer ceramic capacitor 100 according to the present embodiment has the same operational effects as the two-terminal multilayer ceramic capacitor 10 according to the first embodiment.

[0344] 3. Modifications of three-terminal multilayer ceramic capacitors

[0345] Next, a modification of the three-terminal multilayer ceramic capacitor 100 will be described. (1)

[0347] The external electrode 30 of the second embodiment described above includes the base electrode layer 32 and the plating layer 34 . Alternatively, the external electrode 30 may include the plating layer 34 but may not include the base electrode layer 32 .

[0348] Although not shown in the drawings, a structure in which the plating layer 34 is provided instead of the base electrode layer 32 will be described below with respect to the first to fourth external electrodes 30 a to 30 d.

[0349] The first external electrode 30a to the fourth external electrode 30d may each be provided with a plated layer 34 directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the three-terminal laminated ceramic capacitor 100 may also be a structure in which the first end face 12e, the second end face 12f, the first side face 12c, and the second side face 12d are plated to form a plated layer 34 electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, the plated layer 34 may be formed by plating after a catalyst is provided on the surface of the laminate 12 as a pretreatment. When performing the plating treatment, either electrolytic plating or electroless plating may be used. However, electroless plating requires pretreatment with a catalyst or the like in order to increase the deposition speed of the plating layer, and has the disadvantage of complicating the process. Therefore, electrolytic plating is generally preferred. As a plating method, drum plating is preferably used.

[0350] In addition, when the plating layer 34 is formed directly on the stack 12 without providing a base electrode layer 32, the height can be reduced, i.e., the thickness can be thinned, or it can be converted into the thickness of the stack, i.e., the thickness of the effective layer portion, thereby increasing the design freedom of the thickness of the stack 12.

[0351] The plating layer 34 includes a first lower plating layer 34a1 to a fourth lower plating layer 34d1 (lower plating layer) formed on the surface of the laminate 12 and a first upper plating layer 34a2 to a fourth upper plating layer 34d2 (upper plating layer) formed on the surface of the first lower plating layer 34a1 to the fourth lower plating layer 34d1. As in the above-mentioned embodiment, the first lower plating layer 34a1 and the second lower plating layer 34b1 have a plating exposed region not covered by the upper plating layer. The lower plating layer and the upper plating layer each preferably include at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing the metal.

[0352] Furthermore, the lower plating layer is preferably formed using Ni having solder resist properties, and the upper plating layer is preferably formed using Sn or Au having good solder wettability.

[0353] In addition, for example, when Ni is used to form the first internal electrode layer 16a and the second internal electrode layer 16b, the lower plating layer is preferably formed using Cu having good bonding properties with Ni. The plating layer may be the upper plating layer as the outermost layer, or other plating electrodes may be further formed on the surface of the upper plating layer.

[0354] Here, when the external electrode 30 is formed only by the plating layer 34 without providing the base electrode layer 32 , the thickness of each plating layer 34 arranged without providing the base electrode layer 32 is preferably 1.0 μm to 20.0 μm.

[0355] Furthermore, it is preferred that the plating layer 34 does not contain glass. It is preferred that the metal ratio per unit volume of the plating layer 34 is 99 volume % or more. (2)

[0357] In the second embodiment described above, the first lower plating layer 34a1 has a first plating exposed region 35a not covered by the first upper plating layer 34a2, and the second lower plating layer 34b1 has a second plating exposed region 35b not covered by the second upper plating layer 34b2. However, the form of the exposed region is not limited thereto, and may be as described in the modification of the first embodiment (see Fig. 9 as well as Fig.10), the external electrode 30 has a base exposed area 36 where the base electrode layer 32 is not covered by the plating layer 34. For example, the first base electrode layer 32a may also have a first base exposed area that is not covered by the first plating layer 34a. In addition, the second base electrode layer 32b may also have a second base exposed area that is not covered by the second plating layer 34b. In this case, the first external electrode 30a has a first base exposed area 36a together with the first plating exposed area 35a, and the second external electrode 30b has a second base exposed area together with the second plating exposed area 35b, and a positive potential is applied to the first external electrode 30a and the second external electrode 30b.

[0358] The base exposed area 36 is preferably arranged on the first main surface 12a. Furthermore, the second main surface 12b is preferably a mounting surface. Figure 6 When the solder is mainly applied to the first end surface 12 e and the second end surface 12 f as shown, hydrogen in the gettering layer can be efficiently released from the first main surface 12 a not applied with solder and not facing the mounting substrate 40 through the base exposed region 36 .

[0359] The base exposed region 36 may be disposed on any of the second main surface 12b, the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d other than the first main surface 12a as long as the solder is not applied.

[0360] Furthermore, the first plated layer exposed region 35 a and the first base exposed region 36 a may be formed on different surfaces.

[0361] Furthermore, the first base exposed region 36a is preferably formed on the first end face 12e side relative to the front end portion of the first lower plating layer 34a1 on the second end face 12f side.

[0362] The first base exposed region 36 a can be formed by the same method as the first plated layer exposed region 35 a .

[0363] Although not shown, the third foundation electrode layer 32c may include a third foundation exposed region not covered by the third plating layer 34c, and the fourth foundation electrode layer 32d may include a fourth foundation exposed region not covered by the fourth plating layer 34d. (3)

[0365] In the second embodiment described above, the first exposed plating region 35a of the first lower plating layer 34a1 not covered by the first upper plating layer 34a2 is provided on the first main surface 12a. Similarly, the second exposed plating region 35b of the second lower plating layer 34b1 not covered by the second upper plating layer 34b2 is provided on the first main surface 12a. The present invention is not limited thereto, and the exposed plating region 35 may be provided on at least any one of the first main surface 12a, the second main surface 12b, the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d. (4)

[0367] In the second embodiment described above, the first plating exposed region 35a of the first external electrode 30a and the second plating exposed region 35b of the second external electrode 30b are provided. However, in addition to the first plating exposed region 35a of the first external electrode 30a and the second plating exposed region 35b of the second external electrode 30b, a third plating exposed region where the third lower plating layer 34c1 is not covered by the third upper plating layer 34c2 may be provided in the third external electrode 30c, and a fourth plating exposed region where the fourth lower plating layer 34d1 is not covered by the fourth upper plating layer 34d2 may be provided in the fourth external electrode 30d. In this case, a positive potential is applied to any one of the first external electrode 30a, the second external electrode 30b or the third external electrode 30c, the fourth external electrode 30d, and a negative potential is applied to the other.

[0368] The third ratio of the area of ​​the third plating exposed area in the first main surface 12a when observed in the direction of the first main surface to the area of ​​the exposed area of ​​the third external electrode 30c is preferably 0.4% or more and 83.4% or less. Similarly, the fourth ratio of the area of ​​the fourth plating exposed area in the first main surface 12a when observed in the direction of the first main surface to the area of ​​the exposed area of ​​the fourth external electrode 30d is preferably 0.4% or more and 83.4% or less. In addition, the total ratio of the first plating exposed area 35a to the fourth plating exposed area 35d to the total ratio of the exposed area of ​​the first external electrode 30a to the fourth external electrode 30d is preferably 0.4% or more and 83.4% or less.

[0369] Furthermore, the first external electrode 30a may not have the first plating exposed region 35a, the second external electrode 30b may not have the second plating exposed region 35b, the third external electrode 30c may have the third plating exposed region where the third lower plating layer 34c1 is not covered by the third upper plating layer 34c2, and the fourth external electrode 30d may have the fourth plating exposed region where the fourth lower plating layer 34d1 is not covered by the fourth upper plating layer 34d2. In this case, a positive potential is applied to the third external electrode 30c and the fourth external electrode 30d. (5)

[0371] In the second embodiment described above, the first to fourth lower plating layers 34a1 to 34d1 are arranged to cover the entire first to fourth base electrode layers 32a to 32d. However, the present invention is not limited thereto, and the first lower plating layer 34a1 may be arranged to cover a portion of the first base electrode layer 32a, the second lower plating layer 34b1 may be arranged to cover a portion of the second base electrode layer 32b, the third lower plating layer 34c1 may be arranged to cover a portion of the third base electrode layer 32c, and the fourth lower plating layer 34d1 may be arranged to cover a portion of the fourth base electrode layer 32d.

[0372] C. Experimental Examples

[0373] (1) Samples of the experimental example

[0374] First, a two-terminal type multilayer ceramic capacitor according to an example having the following specifications was produced according to the above-mentioned method for producing a multilayer ceramic capacitor.

[0375] ◎Structure of multilayer ceramic capacitors: Two terminals (refer to Figure 1 )

[0376] ◎Dimensions of multilayer ceramic capacitors L×W×T (including design values): 1.13mm×0.63mm×0.63mm

[0377] ◎Material of ceramic layer: BaTiO3

[0378] ◎Capacitance: 22μF

[0379] ◎Rated voltage: 4V

[0380] ◎Structure of external electrodes

[0381] Base electrode layer: an electrode containing conductive metal (Cu) and glass components

[0382] ·Thickness of the foundation electrode layer at the end surface: Thickness of the foundation electrode layer at the center of the height direction of the foundation electrode layer at the first end surface and the second end surface = 12 μm

[0383] ·Thickness of the underlying electrode layer on the main surface and side surface: The thickness of the underlying electrode layer located at the center of the first and second main surfaces, the first and second side surfaces in the longitudinal direction = 12 μm

[0384] ·Plating layer: Two-layer structure of Ni plating layer and Sn plating layer

[0385] ·Thickness of Ni plating layer on end surface: Thickness of Ni plating layer at the center of the height direction of Ni plating layer on the first end surface and the second end surface = 2 μm

[0386] ·Thickness of Ni plating layer on main surface and side surface: Thickness of Ni plating layer at the center of the length direction of Ni plating layer on the first and second main surfaces, first and second side surfaces = 2 μm

[0387] Thickness of the Sn plating layer on the end surface: Thickness of the Sn plating layer at the center of the height direction of the Sn plating layer on the first end surface and the second end surface = 3 μm

[0388] ·Thickness of Sn plating layer on main surface and side surface: Thickness of Sn plating layer at the center of the length direction of Sn plating layer on the first and second main surfaces, first and second side surfaces = 3 μm

[0389] ◎The exposure ratio of the first lower plating layer and the second lower plating layer (Ni plating layer) on the first main surface

[0390] Exposure ratio = (exposed area of ​​the first lower plating layer and the second lower plating layer) / area of ​​the first external electrode and the second external electrode on the first main surface × 100

[0391] The areas of the first external electrode and the second external electrode on the first main surface are respectively set to L (200 μm)×W (600 μm).

[0392] The exposure ratios of Examples 1 to 8 and Comparative Example 1 are as follows.

[0393] (Example 1) 0.2%

[0394] (Example 2) 0.4%

[0395] (Example 3) 1.17%

[0396] (Example 4) 1.4%

[0397] (Example 5) 1.67%

[0398] (Example 6) 25%

[0399] (Example 7) 83.4%

[0400] (Example 8) 89.2%

[0401] (Comparative Example 1) 0%

[0402] (2) Experimental results

[0403] For each of 100 samples of Examples 1 to 8 and Comparative Example 1, degradation of insulation resistance (IR) due to a PCBT test (125° C., 95% RH, 2 V, 72 hr) during solder mounting was confirmed, and the number of degraded samples was counted.

[0404] Table 1 shows the experimental results.

[0405] [Table 1]

[0406]

[0407] According to the results in Table 1, in Comparative Example 1, the number of pieces judged to have deteriorated insulation resistance was 11 out of 100. On the other hand, in Examples 1 to 8, the number of pieces judged to have deteriorated insulation resistance was 8 or less out of 100. In addition, in Examples 2 to 7, the number of pieces judged to have deteriorated insulation resistance was 4 or less out of 100, and in Examples 3 to 7, the number of pieces judged to have deteriorated insulation resistance was also 4 or less out of 100. Furthermore, in Examples 4 to 6, the number of pieces judged to have deteriorated insulation resistance was 0 out of 100.

[0408] Therefore, it is known that the degradation of the insulation resistance can be suppressed when the exposure ratio is greater than 0%. In addition, it is known that if the exposure ratio is 0.4% or more and 83.4% or less, the degradation of the insulation resistance can be further suppressed. In addition, it is known that even in the range of the exposure ratio of 1.17% or more and 83.4% or less, and further, even in the range of the exposure ratio of 1.40% or more and 83.4% or less, the degradation of the insulation resistance can be suppressed. Furthermore, it is known that in the case of the exposure ratio of 1.40% or more and 25.0% or less, the degradation of the insulation resistance can be further suppressed.

[0409] Furthermore, as described above, the embodiments of the present invention have been disclosed through the foregoing description, but the present invention is not limited thereto.

[0410] That is, various changes can be made to the above-described embodiments with respect to mechanism, shape, material, number, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these are included in the present invention.

[0411] <1>

[0412] A laminated ceramic electronic component comprising:

[0413] A laminate having a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the height direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the height direction and the length direction;

[0414] A plurality of first internal electrode layers, arranged on the plurality of ceramic layers and led out to the first end surface;

[0415] A plurality of second internal electrode layers, arranged on the plurality of ceramic layers and led out to the second end surface;

[0416] a first external electrode disposed on the first end surface, extending from the first end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer; and

[0417] a second external electrode disposed on the second end surface, extending from the second end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the second internal electrode layer;

[0418] The first external electrode comprises: a first base electrode layer arranged on the laminate; a first lower plating layer arranged on the first base electrode layer; and a first upper plating layer arranged on the first lower plating layer except for a first plating exposed region, so that the first lower plating layer has the first plating exposed region exposed on the surface of the first external electrode,

[0419] The second external electrode comprises: a second base electrode layer, arranged on the stack; a second lower plating layer, arranged on the second base electrode layer; and a second upper plating layer, arranged on the second lower plating layer except for the second plating exposed area, so that the second lower plating layer has the second plating exposed area exposed on the surface of the second external electrode.

[0420] <2>

[0421] A laminated ceramic electronic component comprising:

[0422] A laminate having a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the height direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the height direction and the length direction;

[0423] A plurality of first internal electrode layers, arranged on the plurality of ceramic layers and led out to the first end surface and the second end surface;

[0424] a plurality of second internal electrode layers, arranged on the plurality of ceramic layers and extending to the first side surface and the second side surface;

[0425] a first external electrode disposed on the first end surface, extending from the first end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer;

[0426] a second external electrode disposed on the second end surface, extending from the second end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer;

[0427] a third external electrode disposed on the first side surface, extending from the first side surface and disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; and

[0428] a fourth external electrode disposed on the second side surface, extending from the second side surface and disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer;

[0429] The first external electrode comprises: a first base electrode layer arranged on the laminate; a first lower plating layer arranged on the first base electrode layer; and a first upper plating layer arranged on the first lower plating layer except for a first plating exposed region, so that the first lower plating layer has the first plating exposed region exposed on the surface of the first external electrode,

[0430] The second external electrode comprises: a second base electrode layer arranged on the laminate; a second lower plating layer arranged on the second base electrode layer; and a second upper plating layer arranged on the second lower plating layer except for a second plating exposed region, so that the second lower plating layer has the second plating exposed region exposed on the surface of the second external electrode,

[0431] The third external electrode comprises: a third base electrode layer disposed on the laminate; a third lower plating layer disposed on the third base electrode layer; and a third upper plating layer disposed on the third lower plating layer.

[0432] The fourth external electrode includes: a fourth base electrode layer disposed on the laminate; a fourth lower plating layer disposed on the fourth base electrode layer; and a fourth upper plating layer disposed on the fourth lower plating layer.

[0433] <3>

[0434] The multilayer ceramic electronic component according to <2>,

[0435] The third upper plating layer is arranged on the third lower plating layer except for the third plating exposed region, so that the third lower plating layer has the third plating exposed region exposed on the surface of the third external electrode,

[0436] The fourth upper plating layer is arranged on the fourth lower plating layer except for a fourth plating layer exposed region, so that the fourth lower plating layer has the fourth plating layer exposed region exposed on the surface of the fourth external electrode.

[0437] <4>

[0438] A laminated ceramic electronic component comprising:

[0439] A laminate having a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the height direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the height direction and the length direction;

[0440] A plurality of first internal electrode layers, arranged on the plurality of ceramic layers and led out to the first end surface and the second end surface;

[0441] a plurality of second internal electrode layers, arranged on the plurality of ceramic layers and extending to the first side surface and the second side surface;

[0442] a first external electrode disposed on the first end surface, extending from the first end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer;

[0443] a second external electrode disposed on the second end surface, extending from the second end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer;

[0444] a third external electrode disposed on the first side surface, extending from the first side surface and disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; and

[0445] a fourth external electrode disposed on the second side surface, extending from the second side surface and disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer;

[0446] The first external electrode comprises: a first base electrode layer disposed on the laminate; a first lower plating layer disposed on the first base electrode layer; and a first upper plating layer disposed on the first lower plating layer.

[0447] The second external electrode comprises: a second base electrode layer disposed on the laminate; a second lower plating layer disposed on the second base electrode layer; and a second upper plating layer disposed on the second lower plating layer.

[0448] The third external electrode comprises: a third base electrode layer arranged on the laminate; a third lower plating layer arranged on the third base electrode layer; and a third upper plating layer arranged on the third lower plating layer except for a third plating exposed region, so that the third lower plating layer has the third plating exposed region exposed on the surface of the third external electrode,

[0449] The 4th external electrode comprises: a 4th base electrode layer, arranged on the stack; a 4th lower plating layer, arranged on the 4th base electrode layer; and a 4th upper plating layer, arranged on the 4th lower plating layer except for the 4th plating exposed area, so that the 4th lower plating layer has the 4th plating exposed area exposed on the surface of the 4th external electrode.

[0450] <5>

[0451] The multilayer ceramic electronic component according to any one of <1> to <3>,

[0452] A first ratio of an area of ​​the first plating layer exposed region on the first main surface to an area of ​​an exposed region of the first external electrode when viewed in the first main surface direction is 0.4% or more and 83.4% or less,

[0453] A second ratio of the area of ​​the second plating layer exposed region on the first main surface to the area of ​​the second external electrode exposed region when viewed in the first main surface direction is 0.4% or more and 83.4% or less.

[0454] <6>

[0455] The multilayer ceramic electronic component according to <5>,

[0456] The first ratio and the second ratio are greater than or equal to 1.17% and less than or equal to 83.4%.

[0457] <7>

[0458] The multilayer ceramic electronic component according to <6>,

[0459] The first ratio and the second ratio are greater than or equal to 1.40% and less than or equal to 83.4%.

[0460] <8>

[0461] The multilayer ceramic electronic component according to <7>,

[0462] The first ratio and the second ratio are greater than or equal to 1.40% and less than or equal to 25.0%.

[0463] <9>

[0464] The multilayer ceramic electronic component according to any one of <1> to <8>,

[0465] The first plating layer exposed region is arranged on the first main surface.

[0466] <10>

[0467] The multilayer ceramic electronic component according to any one of claims <1> to <9>,

[0468] The first lower plating layer has a thickness of 2 μm or more and 7 μm or less.

[0469] <11>

[0470] The multilayer ceramic electronic component according to any one of <1> to <10>,

[0471] A portion of the first foundation electrode layer is exposed on the first main surface.

[0472] <12>

[0473] The multilayer ceramic electronic component according to <3> or <4>,

[0474] The third ratio of the area of ​​the exposed area of ​​the third plating layer in the first principal surface when observed in the direction of the first principal surface to the area of ​​the exposed area of ​​the third external electrode and / or the fourth ratio of the area of ​​the exposed area of ​​the fourth plating layer in the first principal surface when observed in the direction of the first principal surface to the area of ​​the exposed area of ​​the fourth external electrode is greater than 0.4% and less than 83.4%.

[0475] <13>

[0476] A mounting structure for a laminated ceramic electronic component, comprising:

[0477] The multilayer ceramic electronic component according to any one of <1> to <12>; and

[0478] A mounting substrate on which the multilayer ceramic electronic component is mounted,

[0479] in,

[0480] The first plated layer exposed region is disposed on the first main surface, and the multilayer ceramic electronic component is mounted such that the second main surface faces the mounting substrate.

[0481] <14>

[0482] A mounting structure for a laminated ceramic electronic component, comprising:

[0483] The multilayer ceramic electronic component according to any one of <2>, <3>, and <12>; and

[0484] A mounting substrate on which the multilayer ceramic electronic component is mounted,

[0485] in,

[0486] The first external electrode and the second external electrode are electrodes to which a positive potential is applied.

[0487] <15>

[0488] A mounting structure for a laminated ceramic electronic component, comprising:

[0489] <4> The laminated ceramic electronic component described above; and

[0490] A mounting substrate on which the multilayer ceramic electronic component is mounted,

[0491] in,

[0492] The third external electrode and the fourth external electrode are electrodes to which a positive potential is applied.

[0493] Description of Reference Numerals

[0494] 10: Two-terminal multilayer ceramic capacitor;

[0495] 12: laminate;

[0496] 12a: 1st main side;

[0497] 12b: 2nd main side;

[0498] 12c: 1st side;

[0499] 12d: lateral side 2;

[0500] 12e: 1st end surface;

[0501] 12f: 2nd end surface;

[0502] 14: Ceramic layer;

[0503] 14a: outer part;

[0504] 14b: inner part;

[0505] 16: internal electrode layer;

[0506] 16a, 16b: first internal electrode layer, second internal electrode layer;

[0507] 18: inner layer;

[0508] 20a: first main surface side outer layer portion;

[0509] 20b: outer layer portion on the second main surface side;

[0510] 22a: first side outer layer portion;

[0511] 22b: 2nd side outer layer portion;

[0512] 24a: first end surface side outer layer portion;

[0513] 24b: second end surface side outer layer portion;

[0514] 26a: first opposing electrode portion;

[0515] 26b: second opposing electrode portion;

[0516] 27: opposing electrode portion;

[0517] 28a: first lead electrode portion;

[0518] 28b: second lead electrode portion;

[0519] 28a1: first lead electrode portion;

[0520] 28a2: second lead electrode portion;

[0521] 28b1: The third lead electrode portion;

[0522] 28b2: 4th lead electrode portion;

[0523] 30: external electrode;

[0524] 30a-30d: 1st external electrode to 4th external electrode;

[0525] 32: base electrode layer;

[0526] 32a to 32d: first to fourth base electrode layers;

[0527] 34: plating layer;

[0528] 34a to 34d: 1st to 4th plating layers;

[0529] 34a1 to 34d1: 1st lower plating layer to 4th lower plating layer;

[0530] 34a2 to 34d2: 1st upper plating layer to 4th upper plating layer;

[0531] 35: Exposed coating area;

[0532] 35a~35d: 1st plating layer exposed area~4th plating layer exposed area;

[0533] 36: basement exposure area;

[0534] 36a: first base exposed area;

[0535] 40: Install the substrate;

[0536] 41: connection plate;

[0537] 42: solder;

[0538] 100: Three-terminal multilayer ceramic capacitor.

Claims

1. A laminated ceramic electronic component comprising: A laminate having a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the height direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the height direction and the length direction; A plurality of first internal electrode layers, arranged on the plurality of ceramic layers and led out to the first end surface; A plurality of second internal electrode layers, arranged on the plurality of ceramic layers and led out to the second end surface; a first external electrode disposed on the first end surface, extending from the first end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer; as well as a second external electrode disposed on the second end surface, extending from the second end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the second internal electrode layer; The first external electrode comprises: a first base electrode layer disposed on the laminate; a first lower plating layer disposed on the first base electrode layer; and a first upper plating layer arranged on the first lower plating layer except for the first plating exposed region, so that the first lower plating layer has the first plating exposed region exposed on the surface of the first external electrode, The second external electrode comprises: a second base electrode layer disposed on the laminate; a second lower plating layer disposed on the second base electrode layer; and a second upper plating layer disposed on the second lower plating layer except for a second plating exposed region, so that the second lower plating layer has the second plating exposed region exposed on the surface of the second external electrode.

2. A laminated ceramic electronic component comprising: A laminate having a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the height direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the height direction and the length direction; A plurality of first internal electrode layers, arranged on the plurality of ceramic layers and led out to the first end surface and the second end surface; a plurality of second internal electrode layers, arranged on the plurality of ceramic layers and extending to the first side surface and the second side surface; a first external electrode disposed on the first end surface, extending from the first end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer; a second external electrode disposed on the second end surface, extending from the second end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer; a third external electrode disposed on the first side surface, extending from the first side surface and disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; as well as a fourth external electrode disposed on the second side surface, extending from the second side surface and disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; The first external electrode comprises: a first base electrode layer disposed on the laminate; a first lower plating layer disposed on the first base electrode layer; and a first upper plating layer arranged on the first lower plating layer except for the first plating exposed region, so that the first lower plating layer has the first plating exposed region exposed on the surface of the first external electrode, The second external electrode comprises: a second base electrode layer disposed on the laminate; a second lower plating layer disposed on the second base electrode layer; and a second upper plating layer arranged on the second lower plating layer except for the second plating exposed region, so that the second lower plating layer has the second plating exposed region exposed on the surface of the second external electrode, The third external electrode comprises: a third base electrode layer disposed on the laminate; a third lower plating layer disposed on the third base electrode layer; and a third upper plating layer disposed on the third lower plating layer. The fourth external electrode includes: a fourth base electrode layer disposed on the laminate; a fourth lower plating layer disposed on the fourth base electrode layer; and a fourth upper plating layer disposed on the fourth lower plating layer.

3. The multilayer ceramic electronic component according to claim 2, wherein: The third upper plating layer is arranged on the third lower plating layer except for the third plating exposed region, so that the third lower plating layer has the third plating exposed region exposed on the surface of the third external electrode, The fourth upper plating layer is arranged on the fourth lower plating layer except for a fourth plating layer exposed region, so that the fourth lower plating layer has the fourth plating layer exposed region exposed on the surface of the fourth external electrode.

4. A laminated ceramic electronic component comprising: A laminate having a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the height direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the height direction and the length direction; A plurality of first internal electrode layers, arranged on the plurality of ceramic layers and led out to the first end surface and the second end surface; a plurality of second internal electrode layers, arranged on the plurality of ceramic layers and extending to the first side surface and the second side surface; a first external electrode disposed on the first end surface, extending from the first end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer; a second external electrode disposed on the second end surface, extending from the second end surface and disposed on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and connected to the first internal electrode layer; a third external electrode disposed on the first side surface, extending from the first side surface and disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; as well as a fourth external electrode disposed on the second side surface, extending from the second side surface and disposed on a portion of the first main surface and a portion of the second main surface, and connected to the second internal electrode layer; The first external electrode comprises: a first base electrode layer disposed on the laminate; a first lower plating layer disposed on the first base electrode layer; and a first upper plating layer disposed on the first lower plating layer. The second external electrode comprises: a second base electrode layer disposed on the laminate; a second lower plating layer disposed on the second base electrode layer; and a second upper plating layer disposed on the second lower plating layer. The third external electrode comprises: a third base electrode layer arranged on the laminate; a third lower plating layer arranged on the third base electrode layer; and a third upper plating layer arranged on the third lower plating layer except for a third plating exposed region, so that the third lower plating layer has the third plating exposed region exposed on the surface of the third external electrode, The 4th external electrode comprises: a 4th base electrode layer, arranged on the stack; a 4th lower plating layer, arranged on the 4th base electrode layer; and a 4th upper plating layer, arranged on the 4th lower plating layer except for the 4th plating exposed area, so that the 4th lower plating layer has the 4th plating exposed area exposed on the surface of the 4th external electrode.

5. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein A first ratio of an area of ​​the first plating layer exposed region on the first main surface to an area of ​​an exposed region of the first external electrode when viewed in the first main surface direction is 0.4% or more and 83.4% or less, A second ratio of the area of ​​the second plating layer exposed region on the first main surface to the area of ​​the second external electrode exposed region when viewed in the first main surface direction is 0.4% or more and 83.4% or less.

6. The multilayer ceramic electronic component according to claim 5, wherein The first ratio and the second ratio are greater than or equal to 1.17% and less than or equal to 83.4%.

7. The multilayer ceramic electronic component according to claim 6, wherein The first ratio and the second ratio are greater than or equal to 1.40% and less than or equal to 83.4%.

8. The multilayer ceramic electronic component according to claim 7, wherein The first ratio and the second ratio are greater than or equal to 1.40% and less than or equal to 25.0%.

9. The multilayer ceramic electronic component according to any one of claims 1 to 8, wherein The first plating layer exposed region is arranged on the first main surface.

10. The multilayer ceramic electronic component according to any one of claims 1 to 9, wherein The first lower plating layer has a thickness of 2 μm or more and 7 μm or less.

11. The multilayer ceramic electronic component according to any one of claims 1 to 10, wherein A portion of the first foundation electrode layer is exposed on the first main surface.

12. The multilayer ceramic electronic component according to claim 3 or 4, wherein: The third ratio of the area of ​​the exposed area of ​​the third plating layer in the first principal surface when observed in the direction of the first principal surface to the area of ​​the exposed area of ​​the third external electrode and / or the fourth ratio of the area of ​​the exposed area of ​​the fourth plating layer in the first principal surface when observed in the direction of the first principal surface to the area of ​​the exposed area of ​​the fourth external electrode is greater than 0.4% and less than 83.4%.

13. A mounting structure of a laminated ceramic electronic component, comprising: The multilayer ceramic electronic component according to any one of claims 1 to 12; and A mounting substrate on which the multilayer ceramic electronic component is mounted, in, The first plated layer exposed region is disposed on the first main surface, and the multilayer ceramic electronic component is mounted such that the second main surface faces the mounting substrate.

14. A mounting structure for a laminated ceramic electronic component, comprising: The multilayer ceramic electronic component according to any one of claims 2, 3 and 12; and A mounting substrate on which the multilayer ceramic electronic component is mounted, in, The first external electrode and the second external electrode are electrodes to which a positive potential is applied.

15. A mounting structure of a laminated ceramic electronic component, comprising: The laminated ceramic electronic component according to claim 4; and A mounting substrate on which the multilayer ceramic electronic component is mounted, in, The third external electrode and the fourth external electrode are electrodes to which a positive potential is applied.

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