Laminated structure and thin film transistor

Abstract

The laminated structure has a base insulating layer, a metal oxide layer provided on the base insulating layer, and an oxide semiconductor layer provided in contact with the metal oxide layer, and the oxide semiconductor layer has a region in which the same metal element as the metal element contained in the metal oxide layer has a concentration gradient. The concentration gradient of the metal element increases as approaching the interface between the metal oxide layer and the oxide semiconductor layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a stacked structure including an oxide semiconductor layer having a polycrystalline structure. Another embodiment of the present invention relates to a thin film transistor including the stacked structure. Background Art

[0002] In recent years, the development of thin film transistors that use oxide semiconductor films as channels instead of silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon and single crystal silicon has been progressing (see, for example, Patent Documents 1 to 6). Such thin film transistors including oxide semiconductor layers can be formed with a simple structure and by a low-temperature process, just like thin film transistors including amorphous silicon films. In addition, it is known that thin film transistors including oxide semiconductor layers have higher mobility than thin film transistors including amorphous silicon films.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] However, the field effect mobility of a conventional thin film transistor including an oxide semiconductor layer is not that high even when a crystalline oxide semiconductor layer is used. Therefore, it is desirable to improve the crystal structure of the oxide semiconductor layer used in the thin film transistor to increase the field effect mobility of the thin film transistor.

[0013] In view of the above problems, an object of one embodiment of the present invention is to provide a novel stacked structure including an oxide semiconductor layer having a polycrystalline structure. Another object is to provide a thin film transistor including the stacked structure.

[0014] Means for solving problems

[0015] An embodiment of the present invention involves a stacked structure comprising: a base insulating layer; a metal oxide layer, which is arranged on the base insulating layer; and an oxide semiconductor layer having a polycrystalline structure, which is arranged in contact with the metal oxide layer, and the oxide semiconductor layer has a region having a concentration gradient of the same metal element as the metal element contained in the metal oxide layer, and the concentration gradient of the metal element increases as it approaches the interface between the metal oxide layer and the oxide semiconductor layer.

[0016] A thin film transistor according to one embodiment of the present invention includes: the stacked structure described above; a gate insulating film provided on an oxide semiconductor layer; and a gate electrode provided on the gate insulating film so as to overlap with at least a portion of the oxide semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] [ Figure 1 ] is a schematic diagram showing a stacked structure according to one embodiment of the present invention.

[0018] [ Figure 2 ] is a cross-sectional view showing an overview of a thin film transistor according to one embodiment of the present invention.

[0019] [ Figure 3 ] is a top view showing an overview of a thin film transistor according to one embodiment of the present invention.

[0020] [ Figure 4 ] is a flowchart showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0021] [ Figure 5 ] is a cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0022] [ Figure 6 ] is a cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0023] [ Figure 7 ] is a cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0024] [ Figure 8 ] is a cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0025] [ Fig. 9 ] is a cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0026] [ Fig.10 ] is a cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0027] [ Fig.11 ] is a cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0028] [ Fig.12 ] is a cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0029] [ Fig.13 ] is a schematic diagram of an electronic device involved in one embodiment of the present invention.

[0030] [ Fig.14 ] is a STEM image near the channel region of the thin film transistor in Example A.

[0031] [ Fig.15 ] is a STEM image near the source region of the thin film transistor in Example A.

[0032] [ Fig.16 ] is a STEM image near the channel region of the thin film transistor in comparison example A.

[0033] [ Fig.17 ] is a STEM image near the source region of the thin film transistor in comparison example A.

[0034] [ Fig.18 ] is the EDX analysis result of Al near the channel region of the thin film transistor in Example A.

[0035] [ Fig.19 ] is the EDX analysis result of Al near the source region of the thin film transistor in Example A.

[0036] [ Fig. 20 ] is a curve graph obtained by fitting the Al distribution obtained by EDX analysis in the channel region of Example A using a Gaussian function.

[0037] [ Fig.21 ] is a curve graph obtained by fitting the Al distribution obtained by EDX analysis in the source region of Example A using a Gaussian function.

[0038] [ Fig. 22 ] is a curve graph obtained by fitting the distribution of Al obtained by EDX analysis in the channel region of Example A using a complementary error function.

[0039] [ Fig.23 ] is a curve graph obtained by fitting the distribution of Al obtained by EDX analysis in the source region of Example A using a complementary error function.

[0040] [ Fig.24 ] is a curve graph obtained by fitting the Al distribution obtained by EDX analysis in the channel region of Example A using a Lorentz function.

[0041] [ Fig.25 ] is a curve graph obtained by fitting the Al distribution obtained by EDX analysis in the source region of Example A using the Lorentz function.

[0042] [ Fig.26 ] is the EDX analysis result of In in the channel region of the thin film transistor in Example A.

[0043] [ Fig. 27 ] is the EDX analysis result of In near the source region of the thin film transistor in Example A. DETAILED DESCRIPTION

[0044] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily conceived by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. In order to make the description clearer, the accompanying drawings sometimes schematically show the width, thickness, shape, etc. of each part compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same configuration as that described in the accompanying drawings that have appeared, and the detailed description is sometimes appropriately omitted.

[0045] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the phrases such as above or below are used for explanation, but, for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured in a different direction than that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Above or below refers to the stacking order in a structure having multiple layers stacked, and in the case of a pixel electrode described as above a transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode described as vertically above a transistor, it refers to a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0046] In the present specification, the term "film" and the term "layer" can be used interchangeably according to circumstances.

[0047] "Semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are a form of semiconductor devices. The semiconductor device of the embodiment shown below may also be a transistor used in an integrated circuit (IC) such as a display device, a microprocessor (MPU), or a memory circuit.

[0048] A "display device" refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel that includes an electro-optical layer, or sometimes refers to a structure in which a display unit is equipped with other optical components (such as a polarization component, a backlight, a touch panel, etc.). As long as there is no technical contradiction, the "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described later, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to display devices including the above-mentioned other electro-optical layers.

[0049] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes multiple combinations of A to C. In addition, the above expressions do not exclude the case where α includes other elements.

[0050] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0051] <First embodiment>

[0052] Reference Figure 1 A stacked structure 1 according to one embodiment of the present invention will be described.

[0053] A stacked structure 1 according to an embodiment of the present invention includes a base insulating layer 11 provided on a substrate 100 , a metal oxide layer 130 (MO) provided on the base insulating layer 11 , and an oxide semiconductor layer 140 (OS) provided in contact with the metal oxide layer 130 .

[0054] As the substrate 100, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. When the substrate 100 needs to be flexible, a substrate containing resin such as a polyimide substrate, an acrylic substrate, a siloxane substrate, a fluororesin substrate or the like can be used as the substrate 100. When a substrate containing resin is used as the substrate 100, impurities may be introduced into the above-mentioned resin in order to improve the heat resistance of the substrate 100.

[0055] As the base insulating layer 11, a common insulating material can be used. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), Silicon Nitride (SiN x ), silicon oxide nitride (SiN x O y ) or a laminated film thereof. The thickness of the base insulating layer 11 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0056] It should be noted that the above-mentioned SiO x N y It is a silicon compound or aluminum compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y It is a silicon compound containing oxygen at a ratio smaller than nitrogen (x>y).

[0057] The metal element contained in the metal oxide layer 130 is preferably a metal element having a function of widening the band gap of the oxide semiconductor layer 140. Specifically, a metal oxide having a band gap of 4.0 eV or more is preferred, and as examples of the metal element, one or more metal elements selected from aluminum (Al), magnesium (Mg), calcium (Ca), scandium (Sc), gallium (Ga), germanium (Ge), strontium (Sr), nickel (Ni), tantalum (Ta), yttrium (Y), zirconium (Zr), barium (Ba), hafnium (Hf), cobalt (Co) and lanthanide elements are used. For example, as the metal oxide layer 130, a metal oxide layer mainly composed of aluminum can also be used. As the metal oxide layer mainly composed of aluminum, for example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x) and other inorganic insulating layers. “Metal oxide layer with aluminum as the main component” means that the ratio of aluminum contained in the metal oxide layer 130 is greater than 1% of the entire metal oxide layer 130. The ratio of aluminum contained in the metal oxide layer 130 may also be greater than 5% and less than 70%, greater than 10% and less than 60%, or greater than 30% and less than 50% of the entire metal oxide layer 130. The above ratios may be mass ratios or weight ratios. The thickness of the metal oxide layer 130 is, for example, greater than 1 nm and less than 100 nm, greater than 1 nm and less than 50 nm, greater than 1 nm and less than 30 nm, or greater than 1 nm and less than 10 nm.

[0058] The oxide semiconductor layer 140 contains indium (In) and at least one metal element (M) other than indium. The composition ratio of the oxide semiconductor film is preferably such that the atomic ratio of indium to at least one metal element satisfies formula (1). In other words, the ratio of indium to all metal elements in the oxide semiconductor film is preferably 50% or more. By increasing the ratio of indium, a crystalline oxide semiconductor film can be formed. In addition, the crystal structure of the oxide semiconductor film preferably has a pyroxene-type structure. By increasing the ratio of indium, an oxide semiconductor film having a pyroxene-type structure can be formed.

[0059] [Mathematical formula 1]

[0060]

[0061] It should be noted that the metal elements other than indium are not limited to one type of metal elements, and the elements other than indium may include a plurality of types of metal elements.

[0062] The detailed manufacturing method of the oxide semiconductor layer 140 will be described later, and a sputtering target of an oxide semiconductor can be used and a film can be formed by sputtering. The composition of the oxide semiconductor layer formed by sputtering depends on the composition of the sputtering target. In the sputtering target having the above composition, an oxide semiconductor layer with no deviation in the composition of the metal elements can be formed by sputtering. Therefore, the composition of the metal elements (such as indium and other metal elements) of the oxide semiconductor layer can also be regarded as equivalent to the composition of the metal elements of the sputtering target. For example, the composition of the metal elements of the oxide semiconductor layer can be determined based on the composition of the metal elements of the sputtering target. It should be noted that the oxygen contained in the oxide semiconductor layer will change according to the process conditions of the sputtering, so this is not the case.

[0063] In addition, the composition of the metal elements of the oxide semiconductor layer 140 can also be determined using fluorescent X-ray analysis or electron probe microanalyzer (EPMA) analysis. In addition, since the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor layer 140 can also be determined using an X-ray diffraction (XRD) method. Specifically, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer 140 obtained by the XRD method.

[0064] The oxide semiconductor layer 140 involved in this embodiment has a polycrystalline structure including a plurality of crystal grains. The oxide semiconductor layer 140 having a novel polycrystalline structure different from the conventional one can be formed by using the Poly-OS (Poly-crystalline Oxide Semiconductor) technology, and the details will be described later. Therefore, in order to distinguish it from the oxide semiconductor layer 140 having the conventional polycrystalline structure, the oxide semiconductor layer 140 having the polycrystalline structure involved in this embodiment is sometimes referred to as a Poly-OS film.

[0065] The crystal structure of the Poly-OS film is not particularly limited, but preferably includes a pyroxenite structure. The crystal structure of the Poly-OS film can be determined using an XRD method or an electron beam diffraction method. As described above, by increasing the ratio of indium in the oxide semiconductor layer 140, a Poly-OS film having a pyroxenite structure can be formed.

[0066] In this embodiment, the oxide semiconductor layer 140 is in contact with the metal oxide layer 130. Therefore, the oxide semiconductor layer 140 may also include a metal element derived from the metal oxide layer 130. That is, the oxide semiconductor layer 140 may also include the same metal element as the metal element included in the metal oxide layer 130. In this case, it is preferred that the oxide semiconductor layer 140 has a region 140a where the metal element included in the metal oxide layer 130 has a concentration gradient, and the concentration gradient of the metal element increases as it approaches the interface between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0067] As described above, the metal element contained in the metal oxide layer 130 is a metal element having a function of widening the band gap. For example, it is preferred that the metal oxide layer 130 use a metal oxide having a band gap of 4.0 eV or more, and as an example of the metal element, one or more metal elements selected from aluminum (Al), magnesium (Mg), calcium (Ca), scandium (Sc), gallium (Ga), germanium (Ge), strontium (Sr), nickel (Ni), tantalum (Ta), yttrium (Y), zirconium (Zr), barium (Ba), hafnium (Hf), cobalt (Co) and lanthanide elements are used. By diffusing the metal element contained in the metal oxide layer 130 into the oxide semiconductor layer 140, the band gap is widened in the region 140a where the metal element is diffused. As a result, the region 140a in the oxide semiconductor layer 140 where the metal element is diffused becomes a region that functions like an insulator.

[0068] The oxide semiconductor layer 140 has a thickness of at least 15 nm, and the region 140 a is a region smaller than 14 nm from the interface with the metal oxide layer 130 in the thickness direction of the oxide semiconductor layer 140 .

[0069] The oxide semiconductor layer 140 has a thickness of at least 15 nm, and the oxide semiconductor layer 140 further has a region 140 b having no concentration gradient of the metal element on the side not in contact with the metal oxide layer 130, the region 140 b is in contact with the region 140 a, and has a thickness of 1 nm or more in the thickness direction of the oxide semiconductor layer 140. In other words, the region 140 b from the surface of the oxide semiconductor layer 140 to the region 140 a is a region having no concentration gradient of the metal element.

[0070] The concentration of the metal element contained in the metal oxide layer 130 and the oxide semiconductor layer 140 can be confirmed by, for example, energy dispersive X-ray spectroscopy (EDX), secondary ion mass spectrometry (SIMS), etc. Based on the concentration distribution of the metal element obtained by EDX analysis, the thickness of the oxide semiconductor layer 140 in the region 140a having the concentration gradient of the metal element can be confirmed.

[0071] The concentration gradient of the metal element contained in the metal oxide layer 130 and the oxide semiconductor layer 140 in the film thickness direction can be evaluated by TEM-EDX as follows.

[0072] First, the stacked structure or TFT is processed by focused ion beam: FIB (Focused Ion Beam) at an acceleration voltage of 20kV to 30kV using a composite beam processing and observation device (manufactured by JEOL Ltd., “JIB-4700F”), and then a thin film sample for cross-sectional TEM observation is picked up using a microsampling method at an acceleration voltage of 40kV using a focused ion beam processing and observation device (FIB) (manufactured by Hitachi High-Technologies Corporation, “FB-2100”).

[0073] The thin film sample for cross-sectional TEM observation is prepared as a thin film including the entire region in the thickness direction of the metal oxide layer 130 and the oxide semiconductor layer 140 .

[0074] Next, cross-sectional TEM observation is performed on the thin film sample for cross-sectional TEM observation, and EDX line analysis is performed on the gate insulating layer 120 , the metal oxide layer 130 , the oxide semiconductor layer 140 , and the gate insulating layer 150 in the film thickness direction.

[0075] EDX analysis was performed using an energy dispersive X-ray analyzer (manufactured by JEOL Ltd., “JED-2300T”) under the following conditions.

[0076] Accelerating voltage: 200 kV

[0077] Measurement mode: STEM mode

[0078] Spot diameter: 0.16nm

[0079] Measurement interval: 1nm

[0080] In the EDX analysis, in addition to In and Al, constituent elements of the gate insulating layer 120, the metal oxide layer 130, the oxide semiconductor layer 140 and the gate insulating layer 150 and all elements that can be detected by the device are selected as elements set as detection objects (detectable elements), and the concentration gradient of the metal elements in the film thickness direction is evaluated by performing EDX line analysis.

[0081] Here, the thickness of the region where Al has a concentration gradient in the oxide semiconductor layer 140 can also be calculated using a fitting function. As described above, the region 140a where the metal element has a concentration gradient is formed by diffusion of the metal element. Since it is believed that the diffusion of the metal element in the region where the metal element has a concentration gradient is Gaussian distributed, the distribution of the metal element can be fitted using a Gaussian function (Formula (2)) or a complementary error function (Formula (3)).

[0082] [Mathematical formula 2]

[0083]

[0084] [Mathematical formula 3]

[0085]

[0086] In equations (2) and (3), the value b is an offset value for adjusting the position of the interface between the metal oxide layer 130 and the oxide semiconductor layer 140, and the value c is a scale parameter. In addition, the value A is the concentration of the metal element at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140. The thickness Δd of the oxide semiconductor layer corresponding to the thickness Δd of the region where the metal element has a concentration gradient can be calculated based on the value c. For example, in the case of a Gaussian function, the distance over which the concentration of the metal element changes by approximately 99.7% can be expressed as 3c. That is, in the fitting using a Gaussian function, by using Δd=3c, most of the Δd in the region where the metal element has a concentration gradient can be covered. The same is true for the complementary error function. Therefore, when using a fitting function, the thickness Δd in the region where the metal element has a concentration gradient can be calculated as Δd=3c.

[0087] The fitting function of the concentration distribution of the metal element is not limited to the Gaussian function and the complementary error function. For example, the Lorentz function (Formula (4)) may be used as the fitting function.

[0088] [Formula 4]

[0089]

[0090] In the formula (4), the value A is the concentration of the metal element at the interface between the metal oxide layer 130 and the oxide semiconductor layer 140, b is the offset value, and c is the half-value width. In this case, the thickness Δd can also be calculated as Δd=3c.

[0091] It should be noted that not all of the thickness Δd of the region having the concentration gradient of the metal element calculated using the fitting function functions as an insulator. For example, the region with a thickness corresponding to c becomes a region that functions as an insulator. That is, the region with a thickness corresponding to c corresponds to the region 140a having the concentration gradient of the same metal element as the metal element contained in the metal oxide layer 130.

[0092] The oxide semiconductor layer 140 contains indium and at least one metal element other than indium, and the metal oxide layer 130 has a region containing indium.

[0093] Indium included in the metal oxide layer 130 has a concentration gradient, and the concentration gradient of indium increases as approaching the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 .

[0094] <Second embodiment>

[0095] Reference Figure 2-3 A thin film transistor according to one embodiment of the present invention will be described.

[0096] [1. Structure of thin film transistor]

[0097] Figure 2 1 is a cross-sectional view schematically showing a thin film transistor 10 according to an embodiment of the present invention. Figure 3 It is a plan view schematically showing a thin film transistor 10 according to an embodiment of the present invention.

[0098] like Figure 2 As shown, the thin film transistor 10 is provided on a substrate 100. The thin film transistor 10 includes a gate electrode 105, gate insulating layers 110 and 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they are sometimes collectively referred to as source / drain electrodes 200.

[0099] In this embodiment, the gate insulating layers 110 and 120 correspond to Figure 1 The base insulating layer 11 shown in the figure, the metal oxide layer 130 is equivalent to Figure 1 The metal oxide layer 130 and the oxide semiconductor layer 140 shown are equivalent to Figure 1 Thus, the stacked structure of the gate insulating layers 110, 120, the metal oxide layer 130, and the oxide semiconductor layer 140 is equivalent to Figure 1 The stacked structure 1 is shown. Therefore, the oxide semiconductor layer 140 has a region 140a having a concentration gradient of the same metal element as the metal element contained in the metal oxide layer 130, and the concentration gradient of the metal element increases as it approaches the interface between the metal oxide layer and the oxide semiconductor layer 140. In this embodiment, the thin film transistor 10 includes the stacked structure 1.

[0100] The gate electrode 105 is provided on the substrate 100. The gate insulating layer 110 and the gate insulating layer 120 are provided on the substrate 100 and the gate electrode 105. The metal oxide layer 130 is provided on the gate insulating layer 120. The metal oxide layer 130 is in contact with the gate insulating layer 120. The oxide semiconductor layer 140 is provided on the metal oxide layer 130. The oxide semiconductor layer 140 is in contact with the metal oxide layer 130. The surface of the main surface of the oxide semiconductor layer 140 that is in contact with the metal oxide layer 130 is referred to as a lower surface 142. The end of the metal oxide layer 130 is substantially consistent with the end of the oxide semiconductor layer 140.

[0101] In the thin film transistor 10 according to this embodiment, no semiconductor layer or oxide semiconductor layer is provided between the metal oxide layer 130 and the substrate 100 .

[0102] exist Figure 2 In the embodiment, the side wall of the metal oxide layer 130 and the side wall of the oxide semiconductor layer 140 are arranged in a straight line, but the present invention is not limited to this configuration. The angle of the side wall of the metal oxide layer 130 relative to the main surface of the substrate 100 may be different from the angle of the side wall of the oxide semiconductor layer 140 relative to the main surface of the substrate 100. The cross-sectional shape of the side wall of at least one of the metal oxide layer 130 and the oxide semiconductor layer 140 may be curved.

[0103] The gate electrode 160 is opposite to the oxide semiconductor layer 140. The gate insulating layer 150 is provided between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. The surface in contact with the gate insulating layer 150 among the main surfaces of the oxide semiconductor layer 140 is referred to as an upper surface 141. The surface between the upper surface 141 and the lower surface 142 is referred to as a side surface 143. The insulating layers 170 and 180 are provided on the gate insulating layer 150 and the gate electrode 160. The insulating layers 170 and 180 are provided with openings 171 and 173 for exposing the oxide semiconductor layer 140. The source electrode 201 is provided so as to fill the inside of the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided so as to fill the inside of the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0104] The gate electrode 105 has a function as a bottom gate of the thin film transistor 10 and a function as a light shielding film for the oxide semiconductor layer 140. The gate insulating layer 110 has a function as a barrier film for shielding impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The gate insulating layers 110 and 120 have a function as a gate insulating layer for the bottom gate. The metal oxide layer 130 is a layer containing a metal oxide mainly composed of aluminum, and not only improves the crystallinity of the oxide semiconductor layer 140, but also has a function as a gas barrier film for shielding gases such as oxygen and hydrogen.

[0105] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region of the oxide semiconductor layer 140 located vertically below the gate electrode 160. The source region S is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 140 that does not overlap with the gate electrode 160 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 140 in the channel region CH has physical properties as a semiconductor. The oxide semiconductor layer 140 in the source region S and the drain region D has physical properties as a conductor.

[0106] The gate electrode 160 has the function of serving as the top gate of the thin film transistor 10 and a light shielding film for the oxide semiconductor layer 140. The gate insulating layer 150 has the function of serving as a gate insulating layer for the top gate and has the function of releasing oxygen through heat treatment in the manufacturing process. The insulating layers 170 and 180 have the function of insulating the gate electrode 160 from the source / drain electrode 200 to reduce the parasitic capacitance between the two. The operation of the thin film transistor 10 is mainly controlled by the voltage supplied to the gate electrode 160. An auxiliary voltage is supplied to the gate electrode 105. However, in the case where the gate electrode 105 is used only as a light shielding film, it is also possible to float the gate electrode 105 instead of supplying a specific voltage. That is, the gate electrode 105 may also be simply referred to as a "light shielding film".

[0107] The oxide semiconductor layer 140 has a thickness of at least 15 nm. In the oxide semiconductor layer 140, a region 140a having a concentration gradient of the same metal element as the metal element contained in the metal oxide layer 130 is a region less than 14 nm from the interface with the metal oxide layer 130 in the thickness direction of the oxide semiconductor layer 140. This region 140a is a region that is affected by the metal oxide layer 130 and is difficult to crystallize immediately after the oxide semiconductor layer 140 is formed. In addition, the metal element contained in the metal oxide layer 130 has the effect of widening the band gap of the oxide semiconductor layer 140. In addition, in the thickness direction of the oxide semiconductor layer 140, a region 140b having a concentration gradient of more than 1 nm from the surface of the oxide semiconductor layer 140 is a region where the metal element does not have a concentration gradient. In this way, in the oxide semiconductor layer 140, the band gap can be made different between the region 140b (front channel side) close to the gate electrode 160 and the region 140a (back channel side) close to the metal oxide layer 130. It is known that in the Hall effect measurement of oxide semiconductors, the mobility increases due to the increase in the volume density of carriers. By limiting the generation area of ​​free carriers generated by applying a voltage to the gate electrode of the transistor to region 140b, the volume density of free carriers increases and the mobility increases. Therefore, in the stacked structure 1 involved in one embodiment of the present invention, it is inferred that the oxide semiconductor layer 140 also has a high mobility. It should be noted that the mobility in this specification, etc. refers to the field effect mobility in the saturation region of the thin film transistor 10, and refers to the maximum value of the field effect mobility in the region where the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the thin film transistor 10 from the voltage supplied to the gate electrode is smaller than the potential difference (Vd) between the source electrode and the drain electrode.

[0108] The oxide semiconductor layer 140 includes indium and at least one metal element other than indium, and the metal oxide layer 130 includes a region including indium.

[0109] Indium included in the metal oxide layer 130 has a concentration gradient, and the concentration gradient of indium increases as approaching the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 .

[0110] In this embodiment, a dual-gate transistor in which gate electrodes are provided both above and below the oxide semiconductor layer 140 is exemplified as the thin film transistor 10, but the present invention is not limited to this configuration. For example, a top-gate transistor in which a gate electrode is provided only above the oxide semiconductor layer 140 may be used as the thin film transistor 10. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0111] like Figure 3As shown, in a top view, the top view pattern of the metal oxide layer 130 is substantially the same as the top view pattern of the oxide semiconductor layer 140. Figure 2 and Figure 3 , the lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130. In particular, in the thin film transistor 10 involved in the present embodiment, the lower surface 142 of the oxide semiconductor layer 140 is entirely covered by the metal oxide layer 130. In the D1 direction, the width of the gate electrode 105 is greater than the width of the gate electrode 160. The D1 direction is a direction connecting the source electrode 201 and the drain electrode 203, and is a direction indicating the channel length L of the thin film transistor 10. Specifically, the length in the D1 direction of the region (channel region CH) where the oxide semiconductor layer 140 overlaps with the gate electrode 160 is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W.

[0112] In this embodiment, a configuration in which the entire lower surface 142 of the oxide semiconductor layer 140 is covered by the metal oxide layer 130 is exemplified, but the present invention is not limited to this configuration. For example, a portion of the lower surface 142 of the oxide semiconductor layer 140 may not be in contact with the metal oxide layer 130. For example, the entire lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may be covered by the metal oxide layer 130, and the entire or a portion of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be covered by the metal oxide layer 130. That is, the entire or a portion of the lower surface 142 of the oxide semiconductor layer 140 in the source region S and the drain region D may not be in contact with the metal oxide layer 130. However, in the above configuration, a portion of the lower surface 142 of the oxide semiconductor layer 140 in the channel region CH may not be covered by the metal oxide layer 130, and the other portion of the lower surface 142 may be in contact with the metal oxide layer 130.

[0113] In this embodiment, the gate insulating layer 150 is formed on the entire surface and the openings 171 and 173 are provided in the gate insulating layer 150, but the present invention is not limited to this configuration. The gate insulating layer 150 may also be patterned. For example, the gate insulating layer 150 may be patterned so that not only the upper surface of the oxide semiconductor layer 140 but also the side surface of the oxide semiconductor layer 140 is exposed.

[0114] exist Figure 3 , a structure in which the source / drain electrode 200 does not overlap with the gate electrodes 105 and 160 in a plan view is illustrated, but the present invention is not limited to this structure. For example, in a plan view, the source / drain electrode 200 may overlap with at least one of the gate electrodes 105 and 160. The above structure is only one embodiment, and the present invention is not limited to the above structure.

[0115] [2. Materials of the Members of the Multilayer Structure 1 and the Thin Film Transistor 10]

[0116] The materials of the respective members of the stacked structure 1 are as described in the first embodiment, and thus the description thereof will be appropriately omitted.

[0117] As the substrate 100, the materials for the substrate 100 described in the stacked structure 1 can be applied. When the thin film transistor 10 is a pixel transistor included in a display device such as a top emission type OLED, since the substrate 100 does not need to be transparent, impurities that reduce the transparency of the substrate 100 may be used. When the thin film transistor 10 is used in an integrated circuit that is not a display device, as the substrate 100, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate that does not have light transparency may be used.

[0118] As the gate electrode 105, the gate electrode 160, and the source / drain electrode 200, a common metal material can be used. As these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), or alloys thereof or compounds thereof can be used. As the gate electrode 105, the gate electrode 160, and the source / drain electrode 200, the above-mentioned materials can be used in a single layer form or in a stacked form.

[0119] The gate insulating layers 110 and 120 may be made of the same material as the base insulating layer 11 described in the multilayer structure 1. The insulating layers 170 and 180 may be made of a common insulating material. For example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), Silicon Nitride (SiN x ) or silicon oxide nitride (SiN x O y ) etc. The above materials may be used in a single layer or in a stacked form.

[0120] As the gate insulating layer 150, an insulating layer containing oxygen among the above insulating layers is used. For example, as the gate insulating layer 150, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ) and other inorganic insulating layers.

[0121] As the gate insulating layer 120, an insulating layer having a function of releasing oxygen by heat treatment is preferably used. The temperature of the heat treatment for causing the gate insulating layer 120 to release oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the gate insulating layer 120 releases oxygen at the heat treatment temperature performed in the manufacturing process of the thin film transistor 10 when a glass substrate is used as the substrate 100, for example.

[0122] As the gate insulating layer 150, it is preferable to use an insulating layer with few defects. For example, when the composition ratio of oxygen in the gate insulating layer 150 is compared with the composition ratio of oxygen in an insulating layer having the same composition as the gate insulating layer 150 (hereinafter referred to as "other insulating layer"), the composition ratio of oxygen in the gate insulating layer 150 is closer to the stoichiometric ratio for the insulating layer than the composition ratio of oxygen in the other insulating layer. Specifically, silicon oxide (SiO x ), the oxygen composition ratio of silicon oxide used as the gate insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio of silicon oxide used as the insulating layer 180. For example, as the gate insulating layer 150, a layer in which no defects are observed when evaluated by an electron spin resonance method (ESR) may be used.

[0123] As the metal oxide layer 130, the materials of the metal oxide layer 130 described in the stacked structure 1 can be used. As the metal oxide layer 130, for example, a metal oxide containing aluminum as a main component is used. As the metal oxide layer 130, for example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) or other inorganic insulating layers. “A metal oxide layer mainly composed of aluminum” means that the ratio of aluminum contained in the metal oxide layer 130 is greater than 1% of the entire metal oxide layer 130. The ratio of aluminum contained in the metal oxide layer 130 may also be greater than 5% and less than 70%, greater than 10% and less than 60%, or greater than 30% and less than 50% of the entire metal oxide layer 130. The above ratio may be a mass ratio or a weight ratio.

[0124] A crystalline oxide semiconductor layer can be used as the oxide semiconductor layer 140. A crystalline oxide semiconductor is less likely to have oxygen vacancies than an amorphous oxide semiconductor.

[0125] [3. Method for Manufacturing Multilayer Structure 1 and Thin Film Transistor 10]

[0126] Next, a method for manufacturing the stacked structure 1 and the thin film transistor 10 will be described. Figure 4 1 is a flowchart showing a method for manufacturing the stacked structure 1 and the thin film transistor 10 according to one embodiment of the present invention. Figure 5 to Figure 12 It is a cross-sectional view showing a method for manufacturing the stacked structure 1 and the thin film transistor 10 according to one embodiment of the present invention.

[0127] First, a method for manufacturing a stacked structure 1 according to an embodiment of the present invention will be described. Figure 4 and Figure 5 As shown, a gate electrode 105 serving as a bottom gate is formed on a substrate 100, and gate insulating layers 110 and 120 are formed on the gate electrode 105 ( Figure 4 The gate insulating layer 110 may be formed of silicon nitride, for example. The gate insulating layer 120 may be formed of silicon oxide, for example. The gate insulating layers 110 and 120 are formed by CVD (Chemical Vapor Deposition).

[0128] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block, for example, impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. Silicon oxide used as the gate insulating layer 120 has a physical property of releasing oxygen by heat treatment.

[0129] like Figure 4 and Figure 6 As shown, a metal oxide layer 130 and an oxide semiconductor layer 140 are formed on the gate insulating layer 120 ( Figure 4 The metal oxide layer 130 is formed by sputtering or atomic layer deposition (ALD: Atomic Layer Deposition).

[0130] The thickness of the metal oxide layer 130 is, for example, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 30 nm or 1 nm to 10 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 130. Aluminum oxide has a high barrier property against gas. In this embodiment, aluminum oxide used as the metal oxide layer 130 blocks hydrogen and oxygen released from the gate insulating layer 120, and inhibits the released hydrogen and oxygen from reaching the oxide semiconductor layer 140.

[0131] Next, an oxide semiconductor layer 140 is formed on the metal oxide layer 130. The thickness of the oxide semiconductor layer 140 is, for example, 15 nm to 100 nm, 15 nm to 70 nm, or 15 nm to 40 nm. If the thickness of the oxide semiconductor layer 140 is less than 15 nm, the oxide semiconductor layer 140 tends not to crystallize. Therefore, it is preferred that the thickness of the oxide semiconductor layer 140 is at least 15 nm. In the case of crystallizing the oxide semiconductor layer 140 by OS annealing described later, the oxide semiconductor layer 140 after film formation and before OS annealing is preferably a film with a small crystalline component, and is particularly preferably amorphous (a state in which the oxide semiconductor has a small crystalline component). That is, the film formation conditions of the oxide semiconductor layer 140 are preferably conditions in which the oxide semiconductor layer 140 does not crystallize as much as possible immediately after film formation.

[0132] In film formation based on sputtering, the atoms recoiled by the ions generated in the plasma and the sputtering target will collide with the substrate, so even if the substrate temperature is room temperature at the start of sputtering, the substrate temperature will rise during film formation. If the substrate temperature rises during film formation, it is easy to contain microcrystals in the oxide semiconductor layer just after film formation. Therefore, it is preferred to form the oxide semiconductor layer while controlling the substrate temperature. The substrate temperature is, for example, below 100°C, preferably below 70°C, and more preferably below 50°C. The substrate temperature can also be below 30°C. The substrate temperature can be controlled, for example, by cooling the substrate. In addition, the oxide semiconductor layer can be formed at a film formation rate at which the substrate temperature does not exceed a specified temperature. In addition, the distance between the target and the substrate can be increased so that the substrate is adjusted in a manner that is not affected by the sputtering target, thereby controlling the substrate temperature.

[0133] In addition, in the sputtering process, the oxide semiconductor layer is formed under the condition that the oxygen partial pressure is less than 10%. If the oxygen partial pressure is high, the oxide semiconductor layer will easily contain microcrystals in the oxide semiconductor layer just after the film is formed due to excess oxygen. Therefore, it is preferred to form the oxide semiconductor layer under the condition of low oxygen partial pressure. The oxygen partial pressure is, for example, greater than 2% and less than 20%, preferably greater than 3% and less than 15%, and more preferably greater than 3% and less than 10%. It should be noted that when the oxide semiconductor layer is formed under the condition that the oxygen partial pressure is less than 2%, the oxide semiconductor layer will not crystallize even if the annealing process is performed.

[0134] like Figure 4 and Figure 7 As shown, the pattern of the oxide semiconductor layer 140 is formed ( Figure 4Although not shown in the figure, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. The oxide semiconductor layer 140 can be etched by wet etching or dry etching. As wet etching, an acidic etchant can also be used for etching. As an etchant, for example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide or hydrofluoric acid can be used.

[0135] After the patterning of the oxide semiconductor layer 140, the oxide semiconductor layer 140 is subjected to a heat treatment (OS annealing) ( Figure 4 In this embodiment, the oxide semiconductor layer 140 is crystallized by the OS annealing.

[0136] In the OS annealing, the oxide semiconductor layer 140 is maintained at a predetermined reaching temperature for a predetermined time. The predetermined reaching temperature is 300° C. to 500° C., preferably 350° C. to 450° C. In addition, the holding time at the reaching temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes. By performing the OS annealing, the oxide semiconductor layer 140 is crystallized to form an oxide semiconductor layer 140 having a polycrystalline structure.

[0137] By performing OS annealing, the metal element contained in the metal oxide layer 130 diffuses into the oxide semiconductor layer 140 during the crystallization process of the oxide semiconductor layer 140. As a result, the oxide semiconductor layer 140 has a region 140a having a concentration gradient of the same metal element as the metal element contained in the metal oxide layer, and the concentration gradient of the metal element increases as it approaches the interface between the metal oxide layer and the oxide semiconductor layer 140.

[0138] As described above, the metal element contained in the metal oxide layer 130 is a metal element having a function of widening the band gap. The metal element contained in the metal oxide layer 130 diffuses into the oxide semiconductor layer 140, thereby widening the band gap in the region 140a where the metal element is diffused. As a result, the region 140a where the metal element is diffused in the oxide semiconductor layer 140 becomes a region that functions as an insulator.

[0139] In thin film transistors, there is a tendency that by reducing the thickness of the oxide semiconductor layer, the carriers near the interface with the gate insulating layer are increased, the influence of the back channel is reduced, and the field effect mobility is increased. That is, the thin film transistor has a tendency that the smaller the thickness of the region that functions as the channel of the oxide semiconductor layer, the higher the field effect mobility. Therefore, the smaller the thickness of the oxide semiconductor layer, the better. However, after forming the oxide semiconductor layer to a thickness of less than 15nm, there is a tendency that the oxide semiconductor layer will not crystallize well even if an annealing process is performed. In the case where the oxide semiconductor layer is not crystallized well, the oxide semiconductor layer and the metal oxide layer will disappear when an etching process is subsequently performed to pattern the oxide semiconductor layer. Therefore, it is difficult to take into account both the thin film and good crystallization of the oxide semiconductor layer.

[0140] According to the method for manufacturing the stacked structure 1 according to one embodiment of the present invention, the oxide semiconductor layer 140 has a region 140a having a concentration gradient of the same metal element as the metal element contained in the metal oxide layer 130. The concentration gradient of the metal element increases as it approaches the interface between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0141] The oxide semiconductor layer 140 has a thickness of at least 15 nm. In the oxide semiconductor layer 140, a region 140a having a concentration gradient of the same metal element as the metal element contained in the metal oxide layer 130 is a region less than 14 nm from the interface with the metal oxide layer 130 in the thickness direction of the oxide semiconductor layer 140. This region 140a is a region that is affected by the metal oxide layer 130 and is difficult to crystallize immediately after the oxide semiconductor layer 140 is formed. In addition, the metal element contained in the metal oxide layer 130 has the effect of widening the band gap of the oxide semiconductor layer 140. Therefore, in the oxide semiconductor layer, the region 140a having a concentration gradient of the metal element can be set as a region that acts as an insulator.

[0142] When the oxide semiconductor layer is formed, the film can be formed with a film thickness of 15 nm or more. Therefore, in the annealing process, the oxide semiconductor layer 140 can be well crystallized. That is, in the oxide semiconductor layer 140, after the film is formed with a film thickness that can be crystallized, the metal element contained in the metal oxide layer 130 is diffused into the oxide semiconductor layer 140 in the annealing process. As a result, a region 140a that functions as an insulator can be formed in the oxide semiconductor layer 140. Therefore, the film thickness of the region 140b that functions as a semiconductor can be substantially reduced in the oxide semiconductor layer 140.

[0143] In addition, in the thickness direction of the oxide semiconductor layer 140, the region 140b from the surface of the oxide semiconductor layer 140 to the region 140a is a region where the metal element does not have a concentration gradient. In this way, in the oxide semiconductor layer 140, the band gap can be different in the region 140b (front channel side) close to the gate electrode 160 and the region 140a (back channel side) close to the metal oxide layer 130. Thus, in the oxide semiconductor layer 140, free carriers can be concentrated in the region 140b close to the gate electrode 160. Therefore, the field effect mobility of the thin film transistor 10 can be improved. Therefore, in the stacked structure 1 involved in one embodiment of the present invention, it is presumed that the oxide semiconductor layer 140 also has high mobility.

[0144] In addition, due to the OS annealing, indium contained in the oxide semiconductor layer 140 may diffuse into the metal oxide layer 130. As a result, the metal oxide layer 130 has a region containing indium. The indium contained in the metal oxide layer 130 has a concentration gradient, and the concentration gradient of indium increases as it approaches the interface between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0145] like Figure 4 and Figure 8 As shown, the pattern of the metal oxide layer 130 is formed ( Figure 4 The metal oxide layer 130 is etched using the oxide semiconductor layer 140 patterned in the above process as a mask. The metal oxide layer 130 may be etched by wet etching or dry etching. For wet etching, for example, diluted hydrofluoric acid (DHF) is used. As described above, the metal oxide layer 130 is etched by using the oxide semiconductor layer 140 as a mask, thereby omitting the photolithography process.

[0146] Through the above process, it is possible to produce Figure 1 The laminated structure 1 shown. It should be noted that in the method for manufacturing the laminated structure 1, the step of forming a pattern of the metal oxide layer 130 may be omitted.

[0147] Next, a method for manufacturing the thin film transistor 10 according to an embodiment of the present invention will be described. In the method for manufacturing the thin film transistor 10, the thin film transistor 10 is manufactured using the stacked structure 1 described above.

[0148] like Figure 4 and Fig. 9 As shown, the gate insulating layer 150 ( Figure 4("GI formation" in step S3006). As the gate insulating layer 150, for example, silicon oxide is formed. The gate insulating layer 150 is formed by a CVD method. For example, as the gate insulating layer 150, in order to form an insulating layer with few defects as described above, the gate insulating layer 150 may be formed at a film forming temperature of 350°C or higher. The thickness of the gate insulating layer 150 is, for example, not less than 50nm and not more than 300nm, not less than 60nm and not more than 200nm, or not less than 70nm and not more than 150nm. After the gate insulating layer 150 is formed, a process of injecting oxygen into a portion of the gate insulating layer 150 may be performed.

[0149] In a state where the gate insulating layer 150 is formed on the oxide semiconductor layer 140, heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 140 is performed ( Figure 4 In the process from forming the oxide semiconductor layer 140 to forming the gate insulating layer 150 on the oxide semiconductor layer 140, a large number of oxygen vacancies are generated on the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140. The oxygen released from the gate insulating layers 120 and 150 by the above-mentioned oxidation annealing is supplied to the oxide semiconductor layer 140 to repair the oxygen vacancies.

[0150] like Figure 4 and Fig.10 As shown, the film-forming gate electrode 160 ( Figure 4 The gate electrode 160 is formed by sputtering or atomic layer deposition and patterned by a photolithography process.

[0151] In the state where the gate electrode 160 is patterned, the resistance of the source region S and the drain region D of the oxide semiconductor layer 140 is reduced ( Figure 4 Specifically, impurities are injected into the oxide semiconductor layer 140 from the gate electrode 160 side through the gate insulating layer 150 by ion implantation. For example, argon (Ar), phosphorus (P), and boron (B) are implanted into the oxide semiconductor layer 140 by ion implantation. Oxygen vacancies are formed in the oxide semiconductor layer 140 by ion implantation, thereby reducing the resistance of the oxide semiconductor layer 140. Since the gate electrode 160 is provided above the oxide semiconductor layer 140 that functions as the channel region CH of the thin film transistor 10, impurities are not injected into the oxide semiconductor layer 140 in the channel region CH.

[0152] like Figure 4 and Fig.11 As shown, insulating layers 170 and 180 are formed on the gate insulating layer 150 and the gate electrode 160 as interlayer films ( Figure 4The insulating layers 170 and 180 are formed by CVD. For example, silicon nitride is formed as the insulating layer 170, and silicon oxide is formed as the insulating layer 180. The materials used as the insulating layers 170 and 180 are not limited to the above materials. The thickness of the insulating layer 170 is not less than 50 nm and not more than 500 nm. The thickness of the insulating layer 180 is not less than 50 nm and not more than 500 nm.

[0153] like Figure 4 and Fig.12 As shown, openings 171 and 173 are formed in the gate insulating layer 150 and the insulating layers 170 and 180 ( Figure 4 The oxide semiconductor layer 140 in the source region S is exposed through the opening 171. The oxide semiconductor layer 140 in the drain region D is exposed through the opening 173. The source / drain electrodes 200 ( Figure 4 Step S3012 of "SD formation"), thereby completing Figure 2 The thin film transistor 10 is shown.

[0154] In the thin film transistor 10 manufactured by the above manufacturing method, the thickness of the oxide semiconductor layer that functions as a channel can be substantially reduced. As a result, a mobility of 30 cm-1 can be obtained when the channel length L of the channel region CH is within a range of 2 μm to 4 μm and the channel width of the channel region CH is within a range of 2 μm to 25 μm. 2 / Vs or above, 35cm 2 / Vs or above, 40cm 2 / Vs or above or 50cm 2 / Vs or above such electrical characteristics.

[0155] <Third Embodiment>

[0156] Reference Fig.13 An electronic device according to an embodiment of the present invention will be described.

[0157] Fig.13 1 is a schematic diagram showing an electronic device 1000 according to an embodiment of the present invention. Fig.13An example of an electronic device 1000, namely a smartphone, is shown in FIG. The electronic device 1000 includes a display device 1100 having a curved side. The display device 1100 includes a plurality of pixels for displaying an image, and the plurality of pixels are controlled by a pixel circuit and a driving circuit, etc. The pixel circuit and the driving circuit include the thin film transistor 10 described in the second embodiment. Since the thin film transistor 10 has a high field effect mobility, the responsiveness of the pixel circuit and the driving circuit can be improved, and as a result, the performance of the electronic device 1000 can be improved.

[0158] It should be noted that the electronic device 1000 involved in this embodiment is not limited to a smartphone. The electronic device 1000 also includes, for example, an electronic device with a display device such as a clock, a tablet computer, a laptop computer, a car navigation system, or a television. In addition, the oxide semiconductor layer described in the first embodiment or the thin film transistor 10 described in the second embodiment can be applied to all electronic devices regardless of whether there is a display device or not.

[0159] Example

[0160] In this example, the thin film transistor 10 according to one embodiment of the present invention is manufactured, and the results of verifying the concentrations of the metal elements in the oxide semiconductor layer 140 and the metal oxide layer 130 are described.

[0161] (Example A)

[0162] As Example A, a thin film transistor 10 according to an embodiment of the present invention was manufactured. The thin film transistor 10 was manufactured according to Figure 3 Here, a glass substrate was used as a substrate, a silicon nitride film was used as a gate insulating layer 110, and a silicon oxide film was used as a gate insulating layer 120. In addition, a 10 nm aluminum oxide layer was used as a metal oxide layer 130. As an oxide semiconductor layer 140, an oxide semiconductor having a polycrystalline structure of 30 nm and in which the atomic ratio of indium to all metal elements contained in the film was 70% was used. As a gate insulating layer 150, a silicon oxide film was used.

[0163] (Comparative Example A)

[0164] As a comparative example, a thin film transistor without the metal oxide layer 130 was manufactured. The thin film transistor of the comparative example A was manufactured according to the method described above except that the metal oxide layer 130 was not formed. Figure 3 That is, the MO film formation process of step S3003 and the MO pattern formation process of step S3005 are omitted. Other structures, film thicknesses, film formation conditions, etc. are the same as those of Example A.

[0165] The thin film transistor 10 according to Example A and the thin film transistor according to Comparative Example A were subjected to cross-sectional STEM (Scanning Transmission Electron Microscopy) observation. Fig.14 is a STEM image of the vicinity of the channel region of the thin film transistor in Example A. Fig.15 This is a STEM image of the vicinity of the source region of the thin film transistor in Example A. Fig.16 is a STEM image of the vicinity of the channel region of the thin film transistor in Comparative Example A. Fig.17 This is a STEM image of the vicinity of the source region of the thin film transistor in Comparative Example A.

[0166] Next, the use of energy dispersive X-ray spectroscopy (EDX) to analyze Figure 14 to Figure 17 The results of elemental analysis of the observation area in .

[0167] Figure 14 to Figure 17 The EDX analysis results of the constituent elements on the straight line shown in the STEM image are as follows Figure 18 to Figure 21 shown.

[0168] Fig.18 This is the EDX analysis result of Al near the channel region of the thin film transistor in Example A. Fig.19 This is the EDX analysis result of Al near the source region of the thin film transistor in Example A. Fig.18 and Fig.19 In FIG. 1 , the depth of the interface between the aluminum oxide layer and the oxide semiconductor layer is approximately 80 nm. The interface between the aluminum oxide layer and the oxide semiconductor layer is indicated by a dotted line. In addition, the film thickness of the aluminum oxide layer and the film thickness of the oxide semiconductor layer are indicated by dotted lines based on 80 nm.

[0169] like Fig.18 and Fig.19 As shown in FIG. 1 , it can be seen that Al has a concentration gradient in the channel region and the source region of the thin film transistor of Example A. Fig.18 and Fig.19 It can be seen that the region where Al has a concentration gradient is a region less than 15 nm from the interface with the metal oxide layer 130 in the thickness direction of the oxide semiconductor layer 140. In addition, it can be seen that in the thickness direction of the oxide semiconductor layer 140, a region of about 15 nm from the surface of the oxide semiconductor layer 140 is a region where Al does not have a concentration gradient.

[0170] Next, the results of fitting the Al distribution obtained by EDX analysis in Example A using the Gaussian function shown in equation (2), the complementary error function shown in equation (3), and the Lorentz function shown in equation (4) are described.

[0171] Fig. 20 This is a graph obtained by fitting the Al distribution obtained by EDX analysis in the channel region of Example A using a Gaussian function. Fig.21 This is a graph obtained by fitting the Al distribution in the source region of Example A obtained by EDX analysis using a Gaussian function. Fig. 22 This is a graph obtained by fitting the Al distribution obtained by EDX analysis in the channel region of Example A using a complementary error function.

[0172] Fig.23 This is a graph obtained by fitting the distribution of Al in the source region of Example A obtained by EDX analysis using a complementary error function. Fig.24 This is a graph obtained by fitting the Al distribution obtained by EDX analysis in the channel region of Example A using a Lorentzian function. Fig.25 This is a graph obtained by fitting the distribution of Al in the source region of Example A obtained by EDX analysis using a Lorentzian function.

[0173] exist Figure 20 to Figure 25 , a solid line represents the fitting function of Example A. The positive direction of the distance is from the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 toward the oxide semiconductor layer 140 , and the negative direction of the distance is from the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 toward the metal oxide layer 130 .

[0174] Table 1 shows the values ​​c (scaling parameter or half-peak width) calculated by fitting the Al concentrations of the channel region and the source region using the fitting functions. Table 2 shows the thickness Δd converted from the calculated values ​​c based on Δd=3c.

[0175] [Table 1]

[0176]

[0177] [Table 2]

[0178]

[0179] As shown in Table 2, regardless of which fitting function is used, the thickness Δd of the region where Al has a concentration gradient in the oxide semiconductor layer 140 of Example A is 12 nm. As described in the first embodiment, the thickness Δd of the region where Al has a concentration gradient does not all act like an insulator. Here, the region with a thickness corresponding to c=4 nm becomes a region that acts like an insulator. That is, it can be seen that the region with a thickness from the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 to 4 nm corresponds to region 140a. In other words, the region 5 nm or more from the interface between the metal oxide layer 130 and the oxide semiconductor layer 140 is a region that acts as a semiconductor.

[0180] Fig.26 This is the EDX analysis result of In in the channel region of the thin film transistor in Example A. Fig. 27 This is the EDX analysis result of In near the source region of the thin film transistor in Example A. Fig.26 and Fig. 27 In the embodiment A, the depth of the interface between the aluminum oxide layer and the oxide semiconductor layer is about 80 nm. The interface between the aluminum oxide layer and the oxide semiconductor layer is indicated by a dotted line. In addition, the film thickness of the aluminum oxide layer and the film thickness of the oxide semiconductor layer are indicated by dotted lines based on 80 nm.

[0181] like Fig.26 and Fig. 27 As shown, in the thin film transistor in Example A, In contained in the oxide semiconductor layer 140 is contained in the metal oxide layer 130. The In contained in the metal oxide layer 130 has a concentration gradient, and the concentration gradient of In increases as it approaches the interface between the metal oxide layer 130 and the oxide semiconductor layer 140.

[0182] As described above, in a thin film transistor of one embodiment of the present invention, there is the following feature: the oxide semiconductor layer has a region where the same metal element as the metal element contained in the metal oxide layer has a concentration gradient, and the concentration gradient of the metal element increases as it approaches the interface between the metal oxide layer and the oxide semiconductor layer. Thus, it is suggested that the oxide semiconductor layer can be well crystallized and the thickness that functions as a channel can be substantially reduced. Thus, the carrier concentration can be increased in the region that functions as a channel. Therefore, it is believed that the field effect mobility of the thin film transistor can be greatly increased.

[0183] As the embodiments of the present invention, the embodiments described above can be appropriately combined to implement as long as they do not contradict each other. In addition, the solutions obtained by adding, deleting or designing the components or adding, omitting or changing the conditions of the processes based on the embodiments by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0184] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

[0185] Description of Reference Numerals

[0186] 1: stacked structure, 10: thin film transistor, 11: base insulating layer, 100: substrate, 105, 160: gate electrode, 110, 120, 150: gate insulating layer, 130: metal oxide layer, 140: oxide semiconductor layer, 140a: region, 140b: region, 141: upper surface, 142: lower surface, 143: side surface, 170, 180: insulating layer, 171, 173: opening, 200: source / drain electrode, 201: source electrode, 203: drain electrode, 1000: electronic device, 1100: display device

Claims

1. A laminated structure comprising: Base insulation layer; a metal oxide layer disposed on the base insulating layer; and an oxide semiconductor layer having a polycrystalline structure, which is disposed in contact with the metal oxide layer, The oxide semiconductor layer has a first region having a concentration gradient of a metal element that is the same as a metal element included in the metal oxide layer, and the concentration gradient of the metal element increases as approaching an interface between the metal oxide layer and the oxide semiconductor layer.

2. The laminated structure according to claim 1, wherein The oxide semiconductor layer has a thickness of at least 15 nm. The first region is a region smaller than 14 nm from the interface with the metal oxide layer in the thickness direction of the oxide semiconductor layer.

3. The laminated structure according to claim 1, wherein The oxide semiconductor layer has a thickness of at least 15 nm. The oxide semiconductor layer further has a second region on a side not in contact with the metal oxide layer, and the second region does not have a concentration gradient of the metal element. The second region is in contact with the first region and has a thickness of 1 nm or more in a thickness direction of the oxide semiconductor layer.

4. The laminated structure according to claim 1, wherein The oxide semiconductor layer comprises: Indium; and At least one metal element other than the indium element, The metal oxide layer has a region including the indium.

5. The laminated structure according to claim 4, wherein: The oxide semiconductor layer includes a region in which a ratio of the indium to the indium and the at least one metal element is 50% or more.

6. The laminated structure according to claim 5, wherein: The indium element included in the metal oxide layer has a concentration gradient, and the concentration gradient of the indium element increases as approaching an interface between the metal oxide layer and the oxide semiconductor layer.

7. The laminated structure according to claim 1, wherein The metal oxide layer includes a metal oxide having a band gap of 4.0 eV or more.

8. The laminated structure according to claim 1, wherein The metal oxide layer contains one or more metal elements selected from aluminum (Al), magnesium (Mg), calcium (Ca), scandium (Sc), gallium (Ga), germanium (Ge), strontium (Sr), nickel (Ni), tantalum (Ta), yttrium (Y), zirconium (Zr), barium (Ba), hafnium (Hf), cobalt (Co) and lanthanide elements as the metal element.

9. The laminated structure according to claim 1, characterized in that: The oxide semiconductor layer has a bixbyite type crystal structure.

10. A thin film transistor having: The laminated structure according to claim 1; a gate insulating film provided on the oxide semiconductor layer; and A gate electrode is provided on the gate insulating film so as to overlap with at least a portion of the oxide semiconductor layer.

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