Semiconductor device and power conversion device

Abstract

An electric field acting on a body diode in an off state of a transistor is relaxed, and the maximum unipolar current density is improved. The semiconductor device includes a first partition region extending in a first direction and a second direction in plan view, and a second partition region extending in at least the first direction in plan view, the first partition region having at least one first folded-back region folded back in the second direction, and the second partition region having at least one second folded-back region folded back in the second direction in plan view. The width of the second partition region in the second direction is greater than or equal to the width of the first partition region in the first direction or the second direction.

Description

Technical Field

[0001] The technology disclosed in this application specification relates to a semiconductor device. Background Art

[0002] In a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) using silicon carbide, a unipolar diode is sometimes built in as a freewheeling diode.

[0003] For example, Patent Document 1 proposes a method of using a Schottky barrier diode (SBD) as a unipolar diode built into a unit cell of a MOSFET.

[0004] In such a unipolar transistor in which a unipolar diode, i.e., a diode that conducts electricity only when a large number of carriers is built into the active region, the diffusion potential of the unipolar diode, i.e., the voltage at which the power-on action starts, is designed to be lower than the voltage at which the power-on action starts of the PN junction (hereinafter sometimes referred to as the body diode) in the MOS structure, thereby suppressing the forward current in the body diode and the expansion of defects.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2018-049951 Summary of the invention

[0008] In a MOSFET having a built-in SBD, when a current of a specific current density flows through the SBD, the body diode starts to be energized. This specific current density is defined as the maximum unipolar current density.

[0009] When the width or length of the SBD, that is, the area, is designed to be large, the maximum unipolar current density increases, and the current flowing through the body diode can be suppressed. On the other hand, when the transistor is in the off state, the electric field tends to concentrate on the PN diode formed around the SBD, and sometimes leakage current flows and generates heat, thereby damaging the element or circuit.

[0010] Based on the above, there is a situation where, in order to increase the maximum unipolar current density, it is desirable to design the SBD area to be large; conversely, in order to prevent damage to the element when the transistor is in the off state, it is desirable to design the SBD area to be narrow.

[0011] The technology disclosed in the present application specification has been accomplished in view of the above-described problems, and is a technology for relaxing the electric field acting on the body diode in the off state of the transistor and increasing the maximum unipolar current density.

[0012] The semiconductor device as the first aspect of the technology disclosed in the specification of the present application comprises: a drift layer of the first conductivity type, which is arranged on the upper surface of a semiconductor substrate of the first conductivity type; a plurality of well regions of the second conductivity type, which are arranged in a surface layer of the drift layer in a manner separated from each other; a source region of the first conductivity type, which is arranged in a surface layer of the well region; a first separation region of the first conductivity type, which is a region between the plurality of well regions on the surface layer of the drift layer; a second separation region of the first conductivity type, which is a region different from the first separation region and between the plurality of well regions on the surface layer of the drift layer; a gate insulating film, which is arranged to be in contact with the well region sandwiched by the source region and the drift layer; and a gate electrode, which is arranged arranged to be in contact with the gate insulating film; a Schottky electrode, arranged on the upper surface of the first separation region, and Schottky-bonded with the first separation region; an ohmic electrode, arranged on the upper surface of the source region; and a source electrode, arranged to be in contact with the Schottky electrode and the ohmic electrode, the first separation region extending in a first direction and a second direction when viewed from above, the second direction being a direction different from the first direction, the first separation region having at least one first return region that turns back in the second direction, the second separation region extending in at least the first direction when viewed from above, and the width of the second separation region in the second direction being greater than or equal to the width of the first separation region in the first direction or the second direction.

[0013] According to at least one first aspect of the technology disclosed in the specification of the present application, by providing the first return region in the first separation region, the maximum unipolar current density can be increased. On the other hand, by making the width of the first separation region narrower than the width of the second separation region, the electric field acting on the PN junction formed by the first separation region and the well region can be reduced.

[0014] In addition, the objects, features, schemes, and advantages of the technology disclosed in this application specification will become more apparent from the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a top view of a MOSFET with built-in SBD as a semiconductor device according to an embodiment.

[0016] Figure 2 yes Figure 1 Schematic diagram of the cross section at section AA' in FIG.

[0017] Figure 3 It shows that the configuration is repeated and continuous in the direction X and the direction Y. Figure 1 The schematic diagram of the structure is shown in a top view.

[0018] Figure 4 It is a plan view of a terminal portion of an active region of a MOSFET with a built-in Schottky diode (SBD) as a semiconductor device according to an embodiment.

[0019] Figure 5 It is a plan view showing a modification of the SBD-embedded MOSFET as the semiconductor device according to the embodiment.

[0020] Figure 6 It is a plan view showing a modification of the SBD-embedded MOSFET as the semiconductor device according to the embodiment.

[0021] Figure 7 It is a top view of a MOSFET with a built-in Schottky diode (SBD) as a semiconductor device according to an embodiment.

[0022] Figure 8 It is a plan view of a modified example of a MOSFET with a built-in Schottky diode (SBD) as a semiconductor device according to the embodiment.

[0023] Fig. 9 It is a top view of a MOSFET with a built-in Schottky diode (SBD) as a semiconductor device according to the present embodiment.

[0024] Fig.10 It is a schematic diagram showing an example of arrangement of lattice-type cells.

[0025] Fig.11 It is a block diagram showing the configuration of a power conversion system to which the power conversion device according to the embodiment is applied.

[0026] Fig.12 It is a plan view showing an example of the structure of an active region of an SBD-embedded trench MOSFET as a semiconductor device according to an embodiment.

[0027] Fig.13 yes Fig.12 Schematic diagram of the cross section at section AA' in FIG.

[0028] (Explanation of Reference Numerals)

[0029] 10: semiconductor substrate; 20: drift layer; 21: separation region; 21A: separation region; 21B: separation region; 21C: separation region; 21D: separation region; 22: separation region; 22C: separation region; 22D: separation region; 30: well region; 30C: well region; 30D: well region; 32: protection region; 33: protection region; 34: separation region; 40: source region; 40C: source region; 40D: source region; 50: gate insulating film; 50A: gate insulating film; 60: Gate electrode; 60A: Gate electrode; 70: Ohmic electrode; 71: Schottky electrode; 71A: Schottky electrode; 80: Source electrode; 200: Power conversion device; 201: Main conversion circuit; 202: Drive circuit; 203: Control circuit; 221: Turn-back region; 221A: Turn-back region; 221B: Turn-back region; 221C: Turn-back region; 221D: Turn-back region; 222C: Turn-back region; 302: Gate trench; 303: Schottky trench; 304: Turn-back region. DETAILED DESCRIPTION

[0030] The following embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of describing the technology, but these features are examples and are not all essential features for implementing the embodiments.

[0031] In addition, the drawings are schematically shown, and for the convenience of explanation, the structure is appropriately omitted or simplified in the drawings. In addition, the mutual relationship between the size and position of the structures shown in different drawings is not necessarily accurately recorded and can be appropriately changed. In addition, in drawings such as top views that are not cross-sectional views, shadows are sometimes given to make the contents of the embodiments easier to understand.

[0032] In the following description, the same components are denoted by the same reference numerals and their names and functions are the same, and therefore, their detailed description may be omitted to avoid duplication.

[0033] In addition, in the description described in the specification of the present application, when a certain component is described as “having”, “including” or “having”, it is not an exclusive expression excluding the existence of other components unless otherwise specified.

[0034] In the descriptions recorded in the specification of the present application, even if ordinal numbers such as "1st" or "2nd" are sometimes used, these terms are used only to facilitate understanding of the contents of the implementation methods, and the contents of the implementation methods are not limited to the order that can be generated by these ordinal numbers.

[0035] In addition, in the descriptions recorded in the specification of this application, even if terms such as "up", "down", "left", "right", "side", "bottom", "front" or "back" are sometimes used to indicate specific positions or directions, these terms are used only to facilitate understanding of the contents of the implementation method and have nothing to do with the position or direction when the implementation method is actually implemented.

[0036] In addition, in the descriptions described in the specification of the present application, when it is described as "the upper surface of..." or "the lower surface of...", in addition to the upper surface itself or the lower surface itself of the target component, it also includes a state where other components are formed on the upper surface or the lower surface of the target component. That is, for example, when it is described as "B provided on the upper surface of A", it does not prevent other component "C" from being interposed between A and B.

[0037] <First embodiment>

[0038] Hereinafter, a semiconductor device according to this embodiment will be described.

[0039] In this specification, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - Indicates that the impurity concentration is lower than n, n + indicates that the impurity concentration is higher than n. Similarly, p - Indicates that the impurity concentration is lower than p, p + Indicates that the impurity concentration is higher than p.

[0040] <Structure of semiconductor devices>

[0041] Figure 1 1 is a plan view of a MOSFET with built-in SBD as a semiconductor device according to the present embodiment. This plan view is a view when a semiconductor substrate is viewed from above with source electrodes, gate wiring layers, insulating films, etc. omitted. Figure 2 yes Figure 1 Schematic diagram of the cross section at section AA' in FIG.

[0042] exist Figure 1 In the embodiment, a partition area 21 having a folding area 221 is provided, and the folding area 221 extends in the direction X and the direction Y and folds back in the direction Y. Figure 1 Although a plurality of return regions 221 are provided, one return region 221 may also be provided.

[0043] exist Figure 2 In the embodiment, an n-type drift layer 20 is formed on the upper surface of a low-resistance n-type semiconductor substrate 10. In addition, a plurality of p-type well regions 30 are provided on the surface layer of the drift layer 20.

[0044] In the surface layer portion of each well region 30 , an n-type source region 40 is formed at a position a predetermined distance from the outer periphery of the well region 30 into the inside.

[0045] A low-resistance p-type contact region 35 is formed on the side of the source region 40 in the surface portion of each well region 30 . In addition, an n-type separation region 21 is formed between the well regions 30 separated from each other in the surface portion of the drift layer 20 .

[0046] The n-type impurity concentration of the separation region 21 may be the same as the n-type impurity concentration of the drift layer 20 , or may be higher or lower than the n-type impurity concentration of the drift layer 20 .

[0047] A Schottky electrode 71 is formed on the upper surface of the separation region 21 and is Schottky-connected to the separation region 21. Here, the Schottky electrode 71 is preferably formed to cover at least the separation region 21 in a plan view, that is, the area of ​​the Schottky electrode 71 is larger than that of the separation region 21.

[0048] Different from the separation region 21, the region between the mutually separated well regions 30 in the surface layer portion of the drift layer 20 becomes the n-type separation region 22. The separation region 22 has the same width as the separation region 21 or a width wider than the separation region 21. In other words, the separation region 21 has the same width as the separation region 22 or a width narrower than the separation region 22.

[0049] The n-type impurity concentration of the separation region 22 may be the same as the n-type impurity concentration of the drift layer 20 , or may be higher or lower than the n-type impurity concentration of the drift layer 20 .

[0050] Gate insulating film 50 is formed on the upper surfaces of well regions 30, the upper surfaces of separation regions 22 between well regions 30, and the upper surfaces of source regions 40 in each well region 30. Gate insulating film 50 is provided in contact with well regions 30 sandwiched between source regions 40 and drift layer 20.

[0051] Gate electrode 60 is formed in the region of the upper surface of gate insulating film 50 that overlaps source region 40 and well region 30 in plan view. The surface portion of well region 30 below the portion where gate electrode 60 is formed and facing gate insulating film 50 is referred to as a channel region.

[0052] The ohmic electrode 70 is formed on a portion of the upper surface of the source region 40 and a portion of the upper surface of the contact region 35. Then, the source electrode 80 is formed so as to cover the ohmic electrode 70 and the Schottky electrode 71.

[0053] The source region 40 can easily transfer electrons via the ohmic electrode 70 . The well region 30 can easily transfer holes via the low-resistance contact region 35 and the ohmic electrode 70 .

[0054] However, the ohmic electrode 70 does not contact the separation region 21 . This is to prevent the Schottky junction formed between the separation region 21 and the source electrode 80 from being bypassed due to the ohmic contact. Specifically, the separation region 21 and the ohmic electrode 70 are electrically isolated by the contact region 35 and the well region 30 .

[0055] The interlayer insulating film 55 is formed to cover the gate electrode 60 . The source electrode 80 contacts the upper surfaces of the ohmic electrode 70 , the Schottky electrode 71 , and the contact region 35 through a contact hole 90 formed through the interlayer insulating film 55 and the gate insulating film 50 .

[0056] On the other hand, a drain electrode 84 is formed on the lower surface of the semiconductor substrate 10 .

[0057] like Figure 1 As shown, the well region 30, the contact region 35 and the separation region 22 extend along the direction X and are formed into a stripe shape. Figure 2 The gate electrode 60 in FIG. 1 is also formed to extend along the X direction.

[0058] The separation region 21 extends in the direction X and the direction Y which is different from the direction X, and is arranged to repeatedly turn back between the well regions 30 (this turning back occurs in the turning region 221 ). This is defined as being arranged in a meandering shape (zigzag shape).

[0059] When the partition region 21 is arranged in a meandering shape, the width of the partition region 21 is the same as the width of the partition region 22 or a width narrower than the width of the partition region 22 .

[0060] exist Figure 1 In FIG. 1 , the direction X is a direction parallel to the direction in which the well region 30 , the contact region 35 , and the separation region 22 extend, and the direction Y is a direction orthogonal to the direction X.

[0061] <About the Operation of Semiconductor Devices>

[0062] Next, the operation of the SBD built-in MOSFET as the semiconductor device according to the present embodiment will be described. Hereinafter, a silicon carbide semiconductor device whose semiconductor material is 4H-type silicon carbide will be described as an example. In this case, the diffusion potential of the pn junction is about 2V.

[0063] First, the freewheeling operation will be described.

[0064] In the freewheeling operation, current flows from the source electrode 80 to the drain electrode 84. In particular, when an off voltage is applied to the gate electrode 60, there is no current path through the channel.

[0065] At this time, an SBD is formed between the isolation region 21 and the Schottky electrode 71 , which is turned on at a voltage lower than the body diode including the well region 30 and the drift layer 20 . Therefore, when the current density is low, the freewheeling current flows entirely through the SBD and does not flow through the body diode.

[0066] However, when the current density increases, a voltage exceeding about 2 V is generated as a voltage drop generated at the Schottky interface and the separation region 21 , and this voltage is applied to the parallel PN junction, so that the body diode starts to be turned on.

[0067] In order to increase the current density at this time, that is, the maximum unipolar current density, it is effective to increase the n-type concentration of the separation region 21 or to increase the width of the separation region 21 to reduce the resistance of the separation region 21. However, in either method, the electric field strength applied to the Schottky interface or the PN junction portion increases in the off state of the transistor.

[0068] Here, when the separation region 21 is arranged in a meandering manner as in the present embodiment, the amount of electrons flowing through the SBD can be increased without increasing the n-type concentration of the separation region 21 or widening the width of the separation region 21, thereby increasing the maximum unipolar current density.

[0069] Furthermore, as the meandering period of the separation region 21 is reduced, the amount of electrons flowing through the SBD can be increased, and thus the maximum unipolar current density can be further increased.

[0070] Next, a case where the transistor is turned off will be described.

[0071] In a state where the transistor is off, the electric field is easily concentrated on the PN junction formed by the separation region 21 and the well region 30 and the PN junction formed by the separation region 22 and the well region 30 .

[0072] As a method of alleviating the electric field concentration at the PN junction formed by the separation region 21 and the well region 30 and the PN junction formed by the separation region 22 and the well region 30, it is considered to narrow the width of the separation region 21 and the width of the separation region 22, respectively. When the width of the separation region 21 and the width of the separation region 22 are narrowed, the potential changes at the separation region 21 and the separation region 22 in the off state of the transistor are respectively reduced. Therefore, the electric field concentration at the PN junction formed by the separation region 21 and the well region 30 and the PN junction formed by the separation region 22 and the well region 30 can be alleviated, respectively.

[0073] like Figure 2As shown, a gate insulating film 50 is formed on the upper surface of the separation region 22. When a reverse voltage is applied in the off state of the transistor, the gate insulating film 50 shares the voltage applied to the entire device. In this way, the electric field applied to the PN junction formed by the separation region 22 and the well region 30 is reduced. Therefore, a strong electric field is easily concentrated on the PN junction formed by the separation region 21 and the well region 30, where there is no layer for sharing the electric field on the upper surface.

[0074] Therefore, when the width of the separation region 21 is made narrower than the width of the separation region 22, the electric field acting on the PN junction formed by the separation region 21 and the well region 30 can be reduced. Therefore, it is possible to suppress the destruction of the element when the transistor is in the off state.

[0075] For the above reasons, when the separation region 21 is configured in a winding manner, by making the width of the separation region 21 the same as or narrower than the width of the separation region 22, the electric field concentration of the body diode formed by the separation region 21 and the well region 30 when the transistor is cut off can be suppressed, thereby preventing damage to the element.

[0076] As described above, according to the semiconductor device of this embodiment, the maximum unipolar current density can be increased by suppressing the operation of the body diode during the freewheeling operation, and the damage of the element in the off state of the transistor can be suppressed, thereby improving the trade-off relationship between the two.

[0077] <About method for manufacturing semiconductor device>

[0078] Next, a method for manufacturing a SBD built-in MOSFET as a semiconductor device according to the present embodiment will be described. Hereinafter, a silicon carbide semiconductor device whose semiconductor material is 4H-type silicon carbide will be described as an example.

[0079] First, a semiconductor substrate 10 having a first principal surface oriented to be a (0001) plane with an off angle and including n-type low-resistance silicon carbide having a 4H polytype is deposited by chemical vapor deposition (CVD) at a density of, for example, 1×10 15 cm -3 Above and 1×10 17 cm -3 At an impurity concentration of 10 μm or less, an n-type drift layer 20 made of silicon carbide having a thickness of, for example, 5 μm or more and 50 μm or less is epitaxially grown.

[0080] Next, an implantation mask is formed by photoresist or the like in a predetermined region on the upper surface of the drift layer 20, and then Al (aluminum) is ion-implanted as a p-type impurity. At this time, the depth of the Al ion implantation is set to be not less than the thickness of the drift layer 20, for example, 0.5 μm or more and 3 μm or less. In addition, the impurity concentration of the ion-implanted Al has a maximum value at a depth away from the upper surface of the drift layer 20, and its concentration is, for example, 1×10 17 cm -3 Above and 1×10 19 cm -3 Below, the impurity concentration is higher than that of the drift layer 20. On the other hand, the impurity concentration of the implanted Al becomes dilute on the upper surface of the drift layer 20, and its concentration is, for example, 1×10 15 cm -3 Above and 1×10 18 cm -3 Next, the implantation mask is removed. The region into which Al ions are implanted in this step becomes the well region 30 .

[0081] Next, an implantation mask is formed on the upper surface of the drift layer 20 by using a photoresist or the like, and Al is ion-implanted as a p-type impurity concentration. At this time, the depth of the Al ion implantation does not exceed the thickness of the drift layer 20, and is set to, for example, 0.5 μm or more and 3 μm or less. It is preferred that the implantation depth of the Al ion implantation is shallower than the well region 30 so that the high-concentration implantation defects remain inside the well region 30. In addition, the impurity concentration of the ion-implanted Al is, for example, 1×10 19 cm -3 Above and 1×10 21 cm -3 Hereinafter, the impurity concentration is set to be higher than that of the drift layer 20 and lower than that of the well region 30 . Thereafter, the implantation mask is removed. The region into which Al is ion-implanted in this step becomes the contact region 35 .

[0082] Next, an implantation mask is formed by a photoresist or the like so as to open a predetermined portion of the upper surface of the drift layer 20 inside the well region 30 when viewed from above. Then, N (nitrogen) is ion implanted as an n-type impurity. The ion implantation depth of N is shallower than the thickness of the well region 30. In addition, the impurity concentration of the ion implanted N is 1×10 18 cm -3 Above and 1×10 21 cm -3 In the following, the impurity concentration of N is set to be higher than that of the p-type well region 30. In order to reduce the sheet resistance or the contact resistance with the ohmic electrode 70, the impurity concentration of N is preferably higher than 1×10 19 cm -3In this step, the region exhibiting n-type conductivity in the region into which N is implanted becomes the source region 40 .

[0083] Next, an annealing process is performed in an inert gas atmosphere such as argon (Ar) gas, for example, at a temperature of 1300° C. to 1900° C. for a time of 30 seconds to 1 hour, for example, by a heat treatment device (not shown). The ion-implanted N and Al are electrically activated by the annealing process.

[0084] Next, using CVD method or photolithography technology, a field insulating film (not shown here) containing silicon oxide is formed on the upper surface of the drift layer 20 in an area outside the active area (i.e., an area roughly corresponding to the area where the well area 30 is formed) and has a thickness thicker than that of the gate oxide film, for example, greater than 0.5 μm and less than 2 μm.

[0085] Next, the upper surface of the drift layer 20 not covered by the field insulating film is thermally oxidized to form a silicon oxide film of a desired thickness as the gate insulating film 50. Next, a polysilicon film having conductivity is formed on the upper surface of the gate insulating film 50 and the upper surface of the field insulating film by a reduced pressure CVD method, and is further patterned to form a gate electrode 60.

[0086] Next, an interlayer insulating film 55 made of silicon oxide is formed by a reduced pressure CVD method. Next, a contact hole 90 is formed which penetrates the interlayer insulating film 55 and the gate insulating film 50 and reaches the contact region 35 and the source region 40 in the active region.

[0087] Next, a metal film with Ni as the main component is formed by sputtering or the like, and then heat treated at a temperature of, for example, above 600°C and below 1100°C, so that the metal film with Ni as the main component reacts with the silicon carbide layer in the contact hole 90, thereby forming silicide between the silicon carbide layer and the metal film.

[0088] Next, the remaining metal film other than the silicide formed in the above reaction is removed by wet etching, thereby forming the ohmic electrode 70 .

[0089] Next, a metal film mainly composed of Ni is formed on the lower surface (second main surface) of the semiconductor substrate 10 , and further heat treatment is performed to form a back ohmic electrode (not shown) on the lower surface side of the semiconductor substrate 10 .

[0090] Next, the interlayer insulating film 55 and the gate insulating film 50 on the upper surface of the separation region 21 are removed by patterning using a photoresist or the like. As a method of removal, wet etching is used so as not to damage the surface of the silicon carbide layer that becomes the Schottky interface. After the wet etching, if a photoresist is used, the photoresist is removed.

[0091] Next, a metal film to be a Schottky electrode is deposited by sputtering or the like, and patterned using a photoresist or the like to form the Schottky electrode 71 on the upper surface of the isolation region 21 in the contact hole 90. The material of the Schottky electrode 71 may be Ti, Mo, or the like.

[0092] Next, a wiring metal such as Al is formed by sputtering or evaporation on the upper surface of the drift layer 20 formed to the Schottky electrode 71. Then, the ohmic electrode 70 on the source side, the source electrode 80 in contact with the Schottky electrode 71, the gate pad (not shown here) in contact with the gate electrode 60, and the gate wiring (not shown here) are formed by photolithography into a predetermined shape.

[0093] Furthermore, if a drain electrode 84 as a metal film is formed on the lower surface of the back ohmic electrode (not shown here) formed on the lower surface of the semiconductor substrate 10, the Figure 1 as well as Figure 2 The semiconductor device shown.

[0094] In addition, in this embodiment, an example of performing each ion implantation in a predetermined order is shown, but the order of ion implantation may be appropriately changed. In addition, the order of forming the back ohmic electrode on the lower surface of the semiconductor substrate 10, the ohmic electrode 70 on the upper surface of the semiconductor substrate 10, and the Schottky electrode 71 may be appropriately changed.

[0095] In this embodiment, an example is shown in which the Schottky electrode 71 is formed only on the upper surface of the separation region 21 and the upper surface of the well region 30 . However, the Schottky electrode 71 may be formed on the upper surface of the ohmic electrode 70 or the upper surface of the interlayer insulating film 55 .

[0096] In addition, in the present embodiment, a planar type is assumed in which the channel or Schottky electrode 71 is formed parallel to the main surface of the semiconductor substrate 10, but it may also be a trench type in which the channel or Schottky electrode 71 is formed obliquely or perpendicularly to the main surface of the semiconductor substrate 10. In other words, it may also have a trench gate, in which a trench is provided that penetrates the well region 30 and reaches the drift layer 20, and a gate insulating film 50 and a gate electrode 60 are formed inside the trench.

[0097] Fig.12 1 is a plan view showing an example of the structure of an active region of a trench SBD-embedded SiC-MOSFET as a semiconductor device according to the present embodiment. Fig.13 yes Fig.12 Schematic diagram of the cross section at section AA' in FIG.

[0098] exist Fig.12 as well as Fig.13 In the embodiment, a drift layer 20 made of n-type silicon carbide is formed on the upper surface of a semiconductor substrate 10 made of n-type and low-resistance silicon carbide. A well region 30 made of p-type silicon carbide is formed in the surface layer of the drift layer 20 .

[0099] A source region 40 made of n-type silicon carbide is formed on a portion of the surface of the well region 30. A low-resistance p-type contact region 35 is formed in a region adjacent to the source region 40 on the surface of the well region 30.

[0100] In addition, a gate trench 302 is formed in the active region, and the gate trench 302 penetrates the source region 40 and the well region 30 to reach the drift layer 20 .

[0101] In addition, a Schottky trench 303 is formed at a location different from the location where the gate trench 302 is formed, and the Schottky trench 303 penetrates the source region 40 and the well region 30 to reach the drift layer 20 .

[0102] The gate trenches 302 and the Schottky trenches 303 are arranged to extend alternately and in parallel with each other. In addition, the gate trenches 302 and the Schottky trenches 303 may be formed to have the same width, or the widths thereof may be different.

[0103] A gate electrode 60A is formed in the gate trench 302 surrounded by a gate insulating film 50A made of silicon oxide. The gate electrode 60A is made of low-resistance polysilicon with a high impurity concentration. An interlayer insulating film 55 made of silicon oxide is formed on the upper surface of the gate electrode 60A.

[0104] In the Schottky trench 303, a source electrode 80 is formed surrounded by a Schottky electrode 71A. The Schottky electrode 71A is formed to contact the drift layer 20 and is Schottky-connected to the drift layer 20. In addition, a p-type protection region 32 is formed in the drift layer 20 in contact with the bottom surface of the gate trench 302. In addition, a p-type protection region 33 is formed in the drift layer 20 in contact with the bottom surface of the Schottky trench 303. The depths of the protection region 32 and the protection region 33 may be the same or different. In addition, the impurity concentrations of the protection region 32 and the protection region 33 may be the same or different.

[0105] The ohmic electrode 70 is formed on a portion of the upper surface of the source region 40 and a portion of the upper surface of the contact region 35. Then, the source electrode 80 is formed to cover the ohmic electrode 70 and the Schottky electrode 71A.

[0106] On the other hand, a drain electrode 84 is formed on the lower surface of the semiconductor substrate 10 .

[0107] Hereinafter, the operation of the trench SBD-embedded SiC-MOSFET as the semiconductor device according to the present embodiment will be described.

[0108] First, the freewheeling operation will be described.

[0109] The freewheeling action is similar to the case of a planar SBD with built-in SiC-MOSFET. When the current density is low, the freewheeling current flows entirely through the SBD without flowing through the body current. On the other hand, when the current density is high, a voltage exceeding about 2V is generated as a voltage drop generated at the Schottky interface and the separation region 34, which is a region sandwiched by the Schottky trench 303 and the gate trench 302, and is applied to the parallel PN junction, and the conduction of the body diode begins.

[0110] In order to increase the current density in this case, that is, the maximum unipolar current density, it is effective to increase the n-type concentration of the separation region 34 or deepen the depth of the separation region 34 (that is, deepen the depth of the gate trench 302 and the Schottky trench 303) to reduce the resistance of the separation region 34.

[0111] However, in either method, the intensity of the electric field applied to the Schottky interface or the PN junction portion increases when the transistor is in the off state.

[0112] Here, when the Schottky trench 303 is arranged in a meandering manner as in the present embodiment, the separation region 34 is also arranged in a meandering manner. Here, the region where the Schottky trench 303 meandering in a zigzag shape turns back in the direction Y is referred to as the turning region 304. Fig.12 In the embodiment, a plurality of return regions 304 are provided at constant intervals, but the intervals between the return regions 304 may not be constant.

[0113] In this case, the amount of electrons flowing through the SBD can be increased without increasing the n-type concentration of the separation region 34 and without increasing the depth of the separation region 34 (i.e., without increasing the depth of the gate trench 302 and the Schottky trench 303), thereby increasing the maximum unipolar current density.

[0114] Next, a case where the transistor is turned off will be described.

[0115] When the transistor is in the off state, the electric field is easily concentrated on the PN junction formed by the guard region 32 and the drift layer 20 and the PN junction formed by the guard region 33 and the drift layer 20 .

[0116] As a method of alleviating the electric field concentration at the PN junction formed by the protection region 32 and the drift layer 20 and the PN junction formed by the protection region 33 and the drift layer 20, it is considered to reduce the depth of the separation region 34 (that is, reduce the depth of the gate trench 302 and the Schottky trench 303, respectively). When the depth of the gate trench 302 and the Schottky trench 303 is reduced, the potential change at the separation region 34 in the off state of the transistor becomes smaller. Therefore, the electric field concentration at the PN junction formed by the protection region 32 and the drift layer 20 and the PN junction formed by the protection region 33 and the drift layer 20 can be alleviated, respectively.

[0117] like Fig.13 As shown in FIG. 1 , a gate insulating film 50A is formed on the upper portion of the protection region 32. When a reverse voltage is applied in the off state of the transistor, the gate insulating film 50A shares the voltage applied to the entire device. In this way, the electric field applied to the PN junction formed by the protection region 32 and the drift layer 20 is reduced. Therefore, a strong electric field is easily concentrated on the PN junction formed by the protection region 33 and the drift layer 20, where there is no layer for sharing the electric field on the upper portion.

[0118] Therefore, by making the depth of Schottky trench 303 equal to or shallower than the depth of gate trench 302, the electric field acting on the PN junction formed by guard region 33 and drift layer 20 can be reduced. Therefore, damage to the element when the transistor is in the off state can be suppressed.

[0119] In addition, when the depth of the Schottky trench 303 is made equal to or shallower than the depth of the gate trench 302, the electric field acting on the Schottky electrode 71 can be reduced. Therefore, the leakage current in the off state of the transistor can be reduced.

[0120] For the above reasons, when the Schottky trench 303 is arranged in a meandering manner, the depth of the Schottky trench 303 is formed in a manner that is the same as or shallower than the depth of the gate trench 302, thereby suppressing the electric field concentration on the body diode formed by the protection region 33 and the drift layer 20 in the off state of the transistor, thereby preventing damage to the element. In addition, the electric field acting on the Schottky electrode 71 can be reduced to suppress leakage current.

[0121] As described above, according to the semiconductor device involved in this embodiment, by suppressing the action of the body diode during freewheeling action, the maximum unipolar current density can be increased, and the damage of the element when the transistor is in the off state can be suppressed. Furthermore, the leakage current can be reduced, and the trade-off relationship between the two can be improved.

[0122] In addition, when Al ions are implanted to form the well region 30, the ion implantation is performed through the portion of the separation region 21 covered with a photoresist or the like, but at this time, the photoresist sometimes collapses. The narrower the width of the separation region 21, the smaller the size of the photoresist used, so the photoresist is prone to collapse.

[0123] On the other hand, in this embodiment, the separation region 21 is arranged in a meandering manner, so the photoresist used when implanting Al ions is also formed in a meandering manner. In this case, compared with the case where the photoresist is formed in a straight line, the photoresist is less likely to collapse, and the occurrence of pattern defects can be suppressed.

[0124] Figure 3 It shows that the configuration is repeated and continuous in the direction X and the direction Y. Figure 1 The schematic diagram of the structure is shown in the top view. Figure 3 For convenience, only the separation region 21, the well region 30, and the separation region 22 are shown. In addition, the following mainly assumes a planar SBD with a built-in SiC-MOSFET structure, but it can also be replaced by the above Fig.12 as well as Fig.13 The trench-type SBD shown is suitably applied by having a SiC-MOSFET built in. In this case, the meandering separation region 21 can be appropriately renamed as a Schottky trench 303 .

[0125] exist Figure 3 In the embodiment, the n-type separation region 21 which roughly corresponds to the SBD in a plan view is sandwiched in the direction Y, and the p-type well region 30 which roughly corresponds to the MOSFET in a plan view is formed. Furthermore, the bands extending in the direction X of the well region 30 sandwiching the separation region 21 are repeatedly arranged in a stripe shape in the direction Y. Such an arrangement is called a "striped type".

[0126] In the above-mentioned stripe type, when the surface orientation of the upper surface (first main surface) of the semiconductor substrate 10 is a (0001) plane having a deviation angle in the <11-20> direction, a stripe-shaped well region 30 extending in the direction X can be formed parallel to the <11-20> direction (i.e., the deviation direction), or can be formed parallel to a direction orthogonal to the deviation direction.

[0127] In addition, when the Figure 3 When the region of the SBD built-in MOSFET illustrated in the example is called the active region, when the period of extension of the separation region 21 in the direction X and the direction Y is constant, that is, when the period of the meander is constant, the maximum unipolar current density at the active region in the semiconductor chip becomes uniform, and the performance of the element can be improved. However, the period of the meander can be appropriately changed according to the formation position of the active region in the semiconductor chip.

[0128] Figure 4 FIG. 1 is a top view of the terminal portion of the active region of a MOSFET having a built-in Schottky diode (SBD) as a semiconductor device according to the present embodiment. Figure 4 : the active region C is a region where the meandering period of the partition region 21 is constant; the vicinity region D of the active region end is a region where the meandering period of the partition region 21 is not constant; and the terminal portion B of the active region (active region end) are shown. The vicinity region D of the active region end is arranged so as to surround the active region C. In addition, the terminal portion B of the active region is arranged so as to surround the vicinity region D of the active region end.

[0129] In the terminal portion B of the active region, the current density of the SBD tends to decrease. Figure 4 As shown in the example, in the active region C, the meandering period of the separation region 21 is constant, but in the region D near the end of the active region, by increasing the number of meandering times of the separation region 21 (i.e., shortening the meandering period), the current density of the SBD in the region D near the end of the active region can be increased. Therefore, the decrease in the maximum unipolar current that may be generated in the terminal portion B of the active region during the freewheeling action can be suppressed, and the performance of the element can be improved.

[0130] In addition, Figure 1 2 shows an example in which the partition region 21 meanders by including a return region 221 having a portion extending in the direction X and a portion extending in the direction Y orthogonal thereto. However, the partition region 21 only needs to have a component extending in the direction X and a component extending in the direction Y.

[0131] That is to say, Figure 5 As shown in the example, the partition area 21A can be configured to be repeatedly bent by having a return area 221A, and the return area 221A has portions extending in two directions inclined to the direction X. In addition, there is no limitation on the direction in which the partition area extends, and it can also extend in three or more directions. In addition, Figure 5 It is a plan view showing a modification of the SBD-embedded MOSFET as the semiconductor device according to the present embodiment.

[0132] <About Modifications>

[0133] Figure 6 21B is a top view showing a modified example of an SBD built-in MOSFET as a semiconductor device according to the present embodiment. Figure 6As shown in the example, the separation region 21B is curved in a curved shape in the turn-back region 221B. When the separation region 21B is curved in a plan view, the change in the width of the separation region 21B during the bending (i.e., the width in the direction Y, the width in the direction oblique to the direction X and the direction Y, and the change in the width in the direction X) becomes small. Therefore, it is easy to alleviate the electric field concentration on the PN junction portion formed by the separation region 21B and the well region 30 when the transistor is turned off.

[0134] In addition, when the separation region 21B is curved, there is no restriction on its curvature, and its width does not need to be constant if it is less than the width of the separation region 22. When the width of the separation region 21B is constant, it is difficult to generate local electric field concentration when the transistor is turned off, so the element is difficult to be damaged.

[0135] Furthermore, when the curved region of the separation region 21B is formed in a curved shape, the corner portion becomes a curved portion, and the electric field concentration in the region is alleviated.

[0136] <Second embodiment>

[0137] In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof is appropriately omitted.

[0138] <Structure of semiconductor devices>

[0139] Figure 7 It is a top view of a MOSFET with a built-in Schottky diode (SBD) as a semiconductor device according to the present embodiment.

[0140] The separation region 21C is configured to be repeatedly zigzag-bent between the well regions 30 by having a return region 221C having portions extending in two directions (directions inclined in the direction Y) inclined in relation to the direction X. In addition, in the separation region 21C, unlike the separation region 21A, there is no portion that is a component extending only in the direction Y (i.e., portions between the return regions 221A).

[0141] Since the pattern of the separation region 21C in the present embodiment is simple, pattern deformation is unlikely to occur when the pattern is formed using a resist.

[0142] In addition, as the period of the zigzag bending of the separation region 21C decreases, the area of ​​the SBD increases, so the current carrying capacity of the SBD increases, and the maximum unipolar current density increases.

[0143] The period of the zigzag bending of the partition regions 21C or the width of the partition regions 21 does not need to be constant, and can be applied to a stripe type or a grid type (an arrangement in which the partition regions 22 are arranged in a grid shape in a plan view).

[0144] Furthermore, when the partition region 21C is bent, it may be bent in a curved shape. In addition, there is no limitation on the number of times the partition region 21C is bent.

[0145] <About Modifications>

[0146] Figure 8 It is a plan view of a modified example of a MOSFET with a built-in Schottky diode (SBD) as the semiconductor device according to the present embodiment.

[0147] exist Figure 8 In the embodiment, the separation region 22C is repeatedly bent by including a turning region 222C having a portion extending in two directions inclined to the direction X at the same period as the period of the separation region 21C being bent in a zigzag manner (i.e., the period of providing the turning region 221C). Accordingly, the shapes of the well region 30C, the contact region 35C, and the source region 40C in a plan view are also changed.

[0148] By zigzag-bending the partition region 22C in such a manner that the bending period of the partition region 22C (i.e., the period of setting the return region 222C) is consistent with the bending period of the partition region 21C (i.e., the period of setting the return region 221C), the partition region 21C extends in parallel with the partition region 22C in the direction X, so that Figure 8 The pitch of the cells in the direction Y in the middle is narrowed. Thus, the semiconductor chip can be miniaturized.

[0149] In addition, the period or width of the zigzag bending of the partition region 22C does not need to be constant. In addition, when the partition region 21C and the partition region 22C are bent, they can also be bent in a curved line. In addition, there is no limit to the number of times the partition region 21C is bent.

[0150] <Third embodiment>

[0151] In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof is appropriately omitted.

[0152] <Structure of semiconductor devices>

[0153] The cell structure is not limited to the stripe type, and may be, for example, a lattice type. Fig. 9This is a top view of a Schottky diode (SBD) built-in MOSFET as a semiconductor device involved in this embodiment. In the first and second embodiments, the separation regions 21 arranged in a bent manner are repeatedly arranged in one direction (direction Y) when viewed from above, but in this embodiment, grid-like units including the separation regions 21 are repeatedly arranged in directions X and Y, separated from each other. This structure is called a "grid type".

[0154] exist Fig. 9 In the embodiment, the separation regions 21D are separated from each other and repeatedly arranged in the directions X and Y, and the separation regions 21D are bent by having a return region 221D, and the return region 221D has a portion extending in the direction X and a portion extending in the direction Y orthogonal thereto. Furthermore, the well region 30D clamps the separation region 21D, and is separated from each other and repeatedly arranged in the directions X and Y. Furthermore, the contact region 35D surrounds the well region 30D, and is separated from each other and repeatedly arranged in the directions X and Y. Furthermore, the source region 40D surrounds the contact region 35D, and is separated from each other and repeatedly arranged in the directions X and Y. Furthermore, the well region 30D surrounds the source region 40D, and is separated from each other and repeatedly arranged in the directions X and Y. Furthermore, the separation region 22D divides the well region 30D into a grid shape, and is arranged to extend in the directions X and Y.

[0155] Fig.10 is a schematic diagram showing an example of the arrangement of cells in a grid type. Fig.10 , only the separation region 21D, the well region 30D, and the separation region 22D are shown.

[0156] In the lattice type, the unit cell region is divided by the partition region 22D and is repeatedly arranged in the directions X and Y in a plan view. The unit cell region includes an n-type partition region 21D roughly corresponding to an SBD and a p-type well region 30D roughly corresponding to a MOSFET.

[0157] The separation region 21D is configured by repeatedly bending as in the first embodiment and the second embodiment. Furthermore, the well region 30D is configured so as to surround the separation region 21D. There is no limitation on the number of times the separation region 21D in the unit cell region is bent, and any number of times is acceptable. In addition, the period or number of times the separation region 21D in each unit cell region is bent can be appropriately changed according to the formation position in the semiconductor chip.

[0158] <Fourth embodiment>

[0159] In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof is appropriately omitted.

[0160] <About the structure of the power conversion device>

[0161] This embodiment is an embodiment in which the semiconductor devices according to the first, second and third embodiments are applied to a power conversion device. This technology is not limited to a specific power conversion device, and the following describes a case in which this technology is applied to a three-phase inverter as a fourth embodiment.

[0162] Fig.11 Detailed Description of the Invention This is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

[0163] Fig.11 The power conversion system illustrated in the example includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can include various power supplies, for example, it can include a DC system, a solar cell or a storage battery, and it can also include a rectifier circuit or an AC / DC converter connected to an AC system. In addition, the power supply 100 can also include a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0164] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. Fig.11 As illustrated in the figure, it comprises: a main conversion circuit 201, which converts DC power into AC power and outputs it; a drive circuit 202, which outputs a drive signal for driving each switching element of the main conversion circuit 201; and a control circuit 203, which outputs a control signal of the control drive circuit 202 to the drive circuit 202.

[0165] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. The load 300 is not limited to a specific use, and is a motor mounted on various electrical devices, for example, used as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0166] The power conversion device 200 is described in detail below. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown here), and the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300 by opening and closing the switching element. There are many specific circuit structures of the main conversion circuit 201, but the main conversion circuit 201 involved in this embodiment is a 2-level three-phase full-bridge circuit, which can include 6 switching elements and 6 freewheeling diodes connected in anti-parallel with each switching element. The semiconductor device of any one of the first embodiment, the second embodiment and the third embodiment is applied to each switching element of the main conversion circuit 201. The 6 switching elements are connected in series for every 2 switching elements to form an upper and lower branch, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. In addition, the output terminal of each upper and lower branch, that is, the three output terminals of the main conversion circuit 201, is connected to the load 300.

[0167] The drive circuit 202 generates a drive signal for driving the switch element of the main conversion circuit 201, and supplies it to the control electrode of the switch element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, the drive signal for turning the switch element into the on state and the drive signal for turning the switch element into the off state are output to the control electrode of each switch element. When the switch element is maintained in the on state, the drive signal is a voltage signal (on signal) above the threshold voltage of the switch element, and when the switch element is maintained in the off state, the drive signal is a voltage signal (off signal) below the threshold voltage of the switch element.

[0168] The control circuit 203 controls the switch elements of the main conversion circuit 201 to supply the desired power to the load 300. Specifically, based on the power to be supplied to the load 300, the time (on-time) for each switch element of the main conversion circuit 201 to be in the on state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on-time of the switch element according to the voltage to be output. In addition, a control instruction (control signal) is output to the drive circuit 202 in such a manner that an on signal is output to the switch element that should be in the on state and an off signal is output to the switch element that should be in the off state at each time point. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switch element in accordance with the control signal.

[0169] In the power conversion device 200 involved in this embodiment, by applying the semiconductor devices involved in the first embodiment, the second embodiment and the third embodiment as switching elements of the main conversion circuit 201, the power conversion device 200 with low loss and improved reliability of high-speed switching can be realized.

[0170] In this embodiment, an example of applying the present technology to a 2-level three-phase inverter is described, but the present technology is not limited thereto and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device 200 is used, but a 3-level or multi-level power conversion device can also be used. When power is supplied to a single-phase load, the present technology can also be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the present technology can also be applied to a DC / DC converter or an AC / DC converter.

[0171] In addition, the power conversion device applying the present technology is not limited to the case where the above-mentioned load is an electric motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0172] <Effects of the above-described embodiments>

[0173] Next, examples of the effects produced by the multiple embodiments described above are shown. In addition, in the following description, the effects are recorded based on the specific structures shown as examples in the multiple embodiments described above, but within the scope of producing the same effect, they can be replaced with other specific structures shown as examples in the specification of this application. That is, below, for convenience, sometimes only any one of the corresponding specific structures is representatively recorded, but the representatively recorded specific structure can also be replaced with other corresponding specific structures.

[0174] In addition, this substitution may be performed across a plurality of embodiments. That is, it is also possible to combine the respective structures shown as examples in different embodiments to produce the same effect.

[0175] According to the above-described embodiment, the semiconductor device includes: a drift layer 20 of the first conductivity type (n-type); a plurality of well regions 30 (or well regions 30C, well regions 30D) of the second conductivity type (p-type); an n-type source region 40 (or source region 40, source region 40D); an n-type first separation region; an n-type second separation region; a gate insulating film 50; a gate electrode 60; a Schottky electrode 71; an ohmic electrode 70 and a source electrode 80. Here, the first separation region corresponds to, for example, at least one of the separation region 21, the separation region 21A, the separation region 21B, the separation region 21C, the separation region 21D, etc. In addition, the second separation region corresponds to, for example, at least one of the separation region 22, the separation region 22C, the separation region 22D, etc. The drift layer 20 is provided on the upper surface of the n-type semiconductor substrate 10. The well regions 30 are provided on the surface layer of the drift layer 20 to be separated from each other. The source region 40 is provided on the surface layer of the well region 30. The separation region 21 is a region between a plurality of well regions on the surface layer of the drift layer 20. The separation region 22 is a region between a plurality of well regions on the surface layer of the drift layer 20 and different from the separation region 21. The gate insulating film 50 is provided to be in contact with the well region 30 sandwiched between the source region 40 and the drift layer 20. The gate electrode 60 is provided to be in contact with the gate insulating film 50. The Schottky electrode 71 is provided on the upper surface of the separation region 21 and is Schottky-bonded to the separation region 21. The ohmic electrode 70 is provided on the upper surface of the source region 40. The source electrode 80 is provided to be in contact with the Schottky electrode 71 and the ohmic electrode 70. Moreover, the separation region 21 extends in a first direction and a second direction when viewed from above, and the second direction is a direction different from the first direction. Here, the first direction corresponds to, for example, the direction X. In addition, the second direction corresponds to, for example, the direction Y. In addition, the partition area 21 has at least one first turning area that turns back in the direction Y. Here, the first turning area corresponds to, for example, at least one of the turning area 221, the turning area 221A, the turning area 221B, the turning area 221C, the turning area 221D, etc. In addition, the partition area 22 extends at least in the direction X when viewed from above. In addition, the width of the partition area 22 in the direction Y is greater than or equal to the width of the partition area 21 in the direction X or the direction Y.

[0176] According to such a structure, by providing the return region 221 in the separation region 21, the amount of electrons flowing through the SBD can be increased without increasing the n-type concentration of the separation region 21, and the maximum unipolar current density can be increased without increasing the width of the separation region 21. On the other hand, by making the width of the separation region 21 narrower than the width of the separation region 22, the electric field acting on the PN junction formed by the separation region 21 and the well region 30 can be reduced. As a result, the electric field acting on the body diode in the off state of the transistor can be alleviated, and the maximum unipolar current density can be increased.

[0177] In addition, when other structures shown as examples in the specification of the present application are appropriately added to the above structure, that is, even when other structures in the specification of the present application that are not mentioned as the above structure are appropriately added, the same effect can be produced.

[0178] In addition, according to the above-described embodiment, a plurality of return regions 221 are provided for the separation region 21. According to such a structure, the separation region 21 can be made into a meandering shape by repeatedly providing the return region 221. Thus, the amount of electrons flowing through the SBD can be increased without increasing the n-type concentration of the separation region 21 and without increasing the width of the separation region 21, and the maximum unipolar current density can be increased.

[0179] In addition, according to the above-described embodiment, the return region 221 of the separation region 21 is provided at a constant distance. According to such a structure, by making the period (distance interval) of the separation region 21 meandering constant, the maximum unipolar current density in the active region of the semiconductor chip becomes uniform, and the performance of the element can be improved. In addition, through various calculations, the effect of improving the maximum unipolar current density using this structure has been confirmed.

[0180] In addition, according to the embodiment described above, the separation region 21 is zigzag-shaped when viewed from above. According to such a structure, the separation region 21 can be made zigzag-shaped by repeatedly setting the return region 221. As a result, there is no need to increase the n-type concentration of the separation region 21, and in addition, there is no need to expand the width of the separation region 21, so the amount of electrons flowing through the SBD can be increased, and the maximum unipolar current density can be increased. In addition, the separation region 21 is configured in a zigzag shape, so the photoresist used when injecting Al ions is also formed in a zigzag shape. In this case, compared with the case where the photoresist is formed in a straight line, the photoresist is not easy to collapse, and the occurrence of pattern defects can be suppressed.

[0181] In addition, according to the embodiment described above, the partition area 22C extends in the direction Y when viewed from above. Moreover, the partition area 22C has at least one second return area that turns back in the direction Y. Here, the second return area corresponds to the return area 222C, etc. By correspondingly setting the return area 221C and the return area 222C, the partition area 21C extends in parallel with the partition area 22C in the direction X. According to such a structure, the partition area 21C extends in parallel with the partition area 22C in the direction X, which can make Figure 8 The pitch of the cells in the direction Y in the middle is narrowed. Thus, the semiconductor chip can be miniaturized.

[0182] In addition, according to the above-described embodiment, the direction X is orthogonal to the direction Y. Furthermore, the well region 30 (or the well region 30C) and the gate electrode 60 are stripe-shaped extending in the direction X when viewed from above. According to such a structure, the meandering separation region 21 can be continuously arranged in the direction X, so it is easy to make the SBD current density in the semiconductor chip uniform compared to the case where it is intermittently arranged in the direction X. In addition, according to such a structure, the meandering shape extends in directions orthogonal to each other, so it is easy to lay out.

[0183] In addition, according to the above-described embodiment, the return region 221B is curved in a plan view. According to such a structure, the change in the width of the separation region 21B when the separation region 21B is bent becomes smaller. Therefore, it is easy to alleviate the electric field concentration to the PN junction formed by the separation region 21B and the well region 30 when the transistor is turned off.

[0184] In addition, according to the above-described embodiment, the semiconductor device includes a trench that penetrates the well region 30 and reaches the drift layer 20. Furthermore, the gate insulating film 50 is formed to cover the side surface of the well region 30 sandwiched by the source region 40 and the drift layer 20 in the trench. In addition, the gate electrode 60 is formed to be surrounded by the gate insulating film 50 in the trench. According to such a structure, the technology described in the above-described embodiment can be applied not only to a planar gate type MOSFET but also to a trench gate type MOSFET.

[0185] In addition, according to the above-described embodiment, the power conversion device includes: a main conversion circuit 201 having the above-described semiconductor device and converting input power and outputting it; a drive circuit 202 outputting a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit 203 outputting a control signal for controlling the drive circuit 202 to the drive circuit 202. According to such a structure, since the above-described semiconductor device is used, the electric field acting on the body diode in the off state of the transistor can be relaxed, and the maximum unipolar current density can be increased.

[0186] <Regarding Modifications of the Multiple Embodiments Described Above>

[0187] In the above-described embodiments, the material, size, shape, relative arrangement relationship, implementation conditions, etc. of each component are sometimes described, but these are merely examples and are not restrictive in all aspects.

[0188] Therefore, numerous variations and equivalents not shown in the examples are conceivable within the scope of the technology disclosed in the present specification, including the case where at least one component is deformed, added, or omitted, and the case where at least one component in at least one embodiment is extracted and combined with components in other embodiments.

[0189] In at least one embodiment described above, when a material name or the like is described without being particularly specified, the material is assumed to include other additives, such as an alloy, unless there is any contradiction.

[0190] Furthermore, when the above-described embodiment is described as including “one” component, the embodiment may include “one or more” of the component, unless any contradiction occurs.

[0191] In addition, each component in the above-described embodiments is a conceptual unit, and the technical scope disclosed in the present application specification includes: a case where one component includes multiple structures; a case where one component corresponds to a part of a certain structure; and a case where multiple components are possessed by one structure.

[0192] In addition, each component in the above-described embodiment may include a structure having another structure or shape as long as it exhibits the same function.

[0193] In addition, the descriptions in the specification of this application are referenced for all purposes related to the present technology and are not to be regarded as prior art.

Claims

1. A semiconductor device comprising: A drift layer of the first conductivity type is disposed on the upper surface of the semiconductor substrate of the first conductivity type; A plurality of well regions of the second conductivity type are disposed separately from each other on the surface layer of the drift layer; A source region of the first conductivity type, disposed on a surface layer of the well region; A first separation region of the first conductivity type is a region between the plurality of well regions in the surface layer of the drift layer; A second separation region of the first conductivity type is a region different from the first separation region and located between the plurality of well regions in the surface layer of the drift layer; a gate insulating film provided to be in contact with the well region sandwiched by the source region and the drift layer; a gate electrode disposed in contact with the gate insulating film; A Schottky electrode is disposed on the upper surface of the first separation region and is Schottky-bonded to the first separation region; An ohmic electrode, disposed on the upper surface of the source region; as well as A source electrode, arranged to contact the Schottky electrode and the ohmic electrode; The first partition region extends in a first direction and a second direction when viewed from above, the second direction being a direction different from the first direction. The first partition region has at least one first turning region that turns back in the second direction. The second partition region extends at least in the first direction when viewed from above. The width of the second partition region in the second direction is greater than or equal to the width of the first partition region in the first direction or the second direction.

2. The semiconductor device according to claim 1, wherein The first partition region includes a plurality of first turning regions.

3. The semiconductor device according to claim 2, wherein: The first turning regions of the first partition region are provided at constant intervals.

4. The semiconductor device according to claim 2 or 3, wherein: The first partition region has a sawtooth shape in a plan view.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The second partition region extends in the second direction when viewed from above, The second partition region has at least one second turning region that turns back in the second direction. By providing the first turning region and the second turning region correspondingly, the first partition region and the second partition region extend in parallel in the first direction.

6. A semiconductor device comprising: A drift layer of the first conductivity type is disposed on the upper surface of the semiconductor substrate of the first conductivity type; A plurality of well regions of the second conductivity type are disposed separately from each other on the surface layer of the drift layer; A source region of the first conductivity type, disposed on a surface layer of the well region; a first trench, arranged to extend from the upper surface of the well region to the inside of the drift layer; a second trench extending from the upper surface of the well region into the drift layer and disposed at a position different from that of the first trench; A separation area, sandwiched by the first groove and the second groove; a gate insulating film covering a side surface of the well region sandwiched by the source region and the drift layer in the second trench; a gate electrode formed in the second trench so as to be surrounded by the gate insulating film; A Schottky electrode, Schottky-bonded to the separation region in the first trench; An ohmic electrode, disposed on the upper surface of the source region; as well as a source electrode, arranged to be in contact with the Schottky electrode and the ohmic electrode, The first groove extends in a first direction and a second direction when viewed from above, the second direction being a direction different from the first direction. The first groove has at least one first turning region that turns back in the second direction, The second groove extends at least in the first direction when viewed from above, A depth of the second trench from an upper surface of the well region is greater than or equal to a depth of the first trench from an upper surface of the well region.

7. The semiconductor device according to claim 6, wherein: The first groove has a plurality of first turning regions.

8. The semiconductor device according to claim 7, wherein: The first turning regions of the first grooves are provided at constant intervals.

9. The semiconductor device according to claim 7 or 8, wherein: The first groove has a sawtooth shape in a plan view.

10. The semiconductor device according to any one of claims 6 to 9, wherein: The second groove extends in the second direction when viewed from above, The second groove has at least one second turning region that turns back in the second direction, By providing the first turning region and the second turning region correspondingly, the first groove and the second groove extend in parallel in the first direction.

11. The semiconductor device according to any one of claims 1 to 10, wherein: The first direction is orthogonal to the second direction, The well region and the gate electrode have a stripe shape extending in the first direction in a plan view.

12. The semiconductor device according to any one of claims 1 to 10, wherein: The first turning region has a curved shape in a plan view.

13. A power conversion device comprising: A main conversion circuit, comprising a semiconductor device according to any one of claims 1 to 12, wherein the main conversion circuit converts input power and outputs the power; a driving circuit, outputting a driving signal for driving the semiconductor device to the semiconductor device; as well as The control circuit outputs a control signal for controlling the drive circuit to the drive circuit.

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