Stacked complementary field effect transistor (CFET) and method of manufacturing same

Abstract

A stacked gate-all-around (GAA) complementary field effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dimensional (3D) semiconductor plate having a channel region and a first surface. A first gate structure surrounds a channel region in the first GAA FET and a second gate structure surrounds a channel region in the second GAA FET. The first gate structure is stacked opposite the second gate structure in a direction orthogonal to the first surface. In some examples, the first crystal structure of the 3D semiconductor plate in the first GAA FET has a first orientation, and the second crystal structure of the 3D semiconductor plate in the second GAA FET has a different orientation to improve carrier mobility.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. patent application No. 17 / 812,300, entitled “Stacked Complementary Field Effect Transistor (CFET) and Method of Fabrication Thereof,” filed on July 13, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology of the present disclosure generally relates to complementary metal-oxide semiconductor (CMOS) field effect transistors (FETs) (CFETs), and more particularly to stacked field effect transistors. Background Art

[0004] Integrated circuits (ICs) are responsible for performing a variety of functions with high levels of performance in electronic devices. There is constant market pressure to minimize the size of electronic devices, which provides motivation to reduce the size of integrated circuits. Complementary metal-oxide semiconductor (CMOS) technology is often used for integrated circuits because of its power savings, improved performance, and better noise immunity compared to circuits that only use N-type (MOS) (NMOS) or P-type MOS (PMOS) technology. However, each CMOS transistor includes a PMOS transistor (such as a P-type field effect transistor (FET) (PFET)) and an NMOS transistor (such as an NFET). Regardless of whether the PFET and NFET of the CFET are vertically stacked, fin-type, or all-around gate (GAA) FETs, each CFET in the circuit includes the area occupied by at least one PFET and at least one NFET. Since there may be millions of circuit entities in an IC, the area of ​​the circuit can significantly affect the area of ​​the IC. In addition, the carrier mobility of the NFET is significantly higher than that of the PFET, so the PFET is usually enlarged to compensate for this difference to provide a more balanced performance, which further increases the circuit unit area of ​​the CMOS transistor. Therefore, it is desirable for CMOS devices to reduce the circuit unit area while maintaining balanced performance. Summary of the invention

[0005] Aspects disclosed in the detailed description include stacked complementary field effect transistors (FETs) (CFETs). Related methods for manufacturing stacked CFETs are also disclosed. A stacked all-around gate (GAA) CFET includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dimensional (3D) semiconductor plate having a channel region and a first surface. The first gate structure surrounds the channel region in the first GAA FET, and the second gate structure surrounds the channel region in the second GAA FET. The first gate structure is stacked relative to the second gate structure in a direction orthogonal to the first surface. In some examples, the stacked GAA CFET is a hybrid CFET, wherein the first crystal structure of the 3D semiconductor plate in the first GAA FET has a first orientation, and the second crystal structure of the 3D semiconductor plate in the second GAA FET has a second orientation different from the first orientation to improve carrier mobility.

[0006] In an exemplary aspect, a stacked CFET is disclosed. The stacked CFET includes a first GAA FET of a first type. The first GAA FET includes a first channel region, the first channel region includes a first crystal structure, the first crystal structure includes a first orientation. The first GAA FET includes a first gate structure surrounding the first channel region. The stacked CFET includes a second GAA FET of a second type, the second GAA FET includes a second channel region, the second channel region includes a second crystal structure, the second crystal structure includes a second orientation different from the first orientation. The second GAA FET includes a second gate structure surrounding the second channel region.

[0007] In another exemplary aspect, a method of manufacturing a stacked CFET is disclosed. The method includes forming a first GAA FET of a first type, the first GAA FET including a first channel region. The method includes forming a first gate structure surrounding the first channel region. The method includes forming a second GAA FET of a second type, the second GAA FET including a second channel region. The method includes forming a second gate structure surrounding the second channel region. The first channel region includes a first crystal structure, the first crystal structure including a first orientation, and the second channel region includes a second crystal structure, the second crystal structure including a second orientation different from the first orientation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is an illustration of a cross-sectional side view of a stacked gate-all-around (GAA) complementary field effect transistor (FET) (CFET) including a first GAA FET of a first type stacked opposite a second GAA FET of a second type;

[0009] Figure 2 is an illustration of a first GAA FET formed on a first insulator and a second GAA FET formed on a second insulator, whereby crystal structures of three-dimensional (3D) semiconductor plates of the first GAA FET and the second GAA FET may be formed in different orientations;

[0010] Figure 3 Is manufacturing Figure 1 Flowchart of the method for stacking GAA CFET;

[0011] Figures 4A-4F is Figure 1 an illustration of a cross-sectional side view of a manufacturing stage in a method of manufacturing a stacked GAA CFET;

[0012] Figures 5A-5F yes Figures 4A-4F A method flow chart of corresponding manufacturing stages of a stacked GAA CFET as shown;

[0013] Figure 6-8 is an illustration of a cross-sectional side view of another example of a stacked GAA CFET formed on an insulator;

[0014] Fig. 9 is an illustration of a first GAA FET formed on a first semiconductor substrate and a second GAA FET formed on a second semiconductor substrate such that orientations of crystal structures of channel regions of the first GAA FET and the second GAA FET may be different;

[0015] Figure 10-12 is an illustration of a cross-sectional side view of an example of a stacked GAA CFET formed on a semiconductor substrate;

[0016] Fig.13 is a block diagram of an exemplary wireless communication device, which may include Figure 1 Stacked GAA CFETs; and

[0017] Fig.14 is a block diagram of an exemplary processor-based system that may include Figure 1 Stacked GAA CFET. DETAILED DESCRIPTION

[0018] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0019] Aspects disclosed in the detailed description include stacked complementary field effect transistors (FETs) (CFETs). Related methods for manufacturing stacked CFETs are also disclosed. A stacked all-around gate (GAA) CFET includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dimensional (3D) semiconductor plate having a channel region and a first surface. A first gate structure surrounds the channel region of the 3D semiconductor plate in the first GAA FET, and a second gate structure surrounds the channel region of the 3D semiconductor plate in the second GAA CFET. The first gate structure is stacked relative to the second gate structure in a third direction orthogonal to the surface. In some examples, the stacked GAA CFET is a hybrid CFET in which a first crystal structure of the 3D semiconductor plate in the first GAA FET has a first orientation, and a second crystal structure of the 3D semiconductor plate in the second GAA FET has a second orientation different from the first orientation to improve carrier mobility.

[0020] Figure 1 is an illustration of a cross-sectional side view of a stacked GAA CFET circuit 100 ("CFET 100") including a first GAA FET 102 of a first type stacked relative to a second GAA FET 104 of a second type. In one aspect, CFET 100 is an example of a complementary metal-oxide semiconductor (CMOS) inverter that occupies the substrate area of ​​the first GAA FET 102, providing an area reduction compared to conventional CMOS inverters that are disposed adjacent to each other on a substrate. In another aspect, CFET 100 is a hybrid CFET in which a 3D semiconductor plate 106 of the first GAA FET 102 has a different surface orientation than a 3D semiconductor plate 108 of the second GAA FET 104 to improve performance, as further explained below. GAA CFET 100 can be a unit circuit having a layout according to a unit design that a designer can place in a die layout.

[0021] Compared to circuits with only one type of FET, CMOS circuits offer higher performance, lower power consumption, and better noise tolerance, but may include twice as many transistors. Stacking the first GAA FET 102 and the second GAA FET 104 relative to each other can significantly reduce (e.g., by up to 50%) the area of ​​the CMOS circuit compared to circuits with only one type of FET. In this example, the first GAA FET 102 is a good reference voltage source (e.g., ground or V SS ) of the first type, the second GAA FET 104 is a good supply voltage source (e.g., 1.8 volts or V DD) of the second type.

[0022] The terms "first type" and "second type" refer to one of N-type and P-type, which may also be referred to as N-channel and P-channel. In an N-type device, the semiconductor source and drain are doped with pentavalent dopants, and a voltage is applied to the gate in the channel region to produce an N-channel, in which electrons are the main carriers. In a P-type or P-channel device, the semiconductor source and drain are doped with trivalent dopants, and the applied gate voltage produces a P-channel in the channel region, in which holes are the main carriers. The 3D semiconductor plates 106, 108 in the P-type device may include silicon (Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), or compounds thereof. The 3D semiconductor plates 106, 108 in the N-type device may include Si, GaAs gallium, or compounds thereof.

[0023] The first GAA FET 102 includes three 3D semiconductor plates 106, but may have fewer or more 3D semiconductor plates. The first gate structure 110 surrounds the 3D semiconductor plate 106 in the channel region 112 (e.g., on all sides). The first GAAFET 102 also includes epitaxial source / drain 114A and 114B coupled to opposite ends of the 3D semiconductor plate 106. The second GAAFET 104 includes three 3D semiconductor plates 108, but may have fewer or more 3D semiconductor plates. The 3D semiconductor plate 106 includes a surface 116 extending along the X-axis direction and the Y-axis direction. The second gate structure 118 surrounds the 3D semiconductor plate 108 in the channel region 120. The first gate structure 110 is stacked relative to the second gate structure 118 along the z-axis direction. The second GAA FET 104 also includes epitaxial regions 122A and 122B, also referred to herein as epitaxial source / drain 122A and 122B, coupled to opposite ends of the 3D semiconductor slab 108. The first gate structure 110 is insulated from the 3D semiconductor slab 106 by an insulator layer 124, and the second gate structure 118 is insulated from the 3D semiconductor slab 108 by an insulator layer 126.

[0024] The first GAA FET 102 is disposed in a first layer 128, which includes a layer of fill material 130, which is an insulator or dielectric material. The first layer 128 is disposed adjacent to a first base layer 132, which is also an electrical insulator and / or dielectric material. The second GAA FET 104 is disposed in a second layer 134, which may also include a fill material 130. The second layer 134 is disposed adjacent to a second base layer 136. The first base layer 132 and the second base layer 136 may be insulating layers, which may include an oxide material. Between the first layer 128 and the second layer 134, the CFET 100 includes a third layer 138. In some examples, as described below, the third layer 138 is a bonding layer for bonding the second layer 134 to the first layer 128. In other examples, the third layer 138 may be a base layer formed on the first layer 128 before forming the second layer 134.

[0025] The CFET 100 also includes a first contact layer 140 and a second contact layer 142, which include contacts CON(1)-CON(7) electrically coupled to one or both of the first GAA FET 102 and the second GAA FET 104 through vias VIA(1)-VIA(9). The contacts CON(1)-CON(7) may couple the first GAA FET 102 to the second GAA FET 104 and provide a connection to an external circuit. The number of contacts CON(1)-CON(7) and vias VIA(1)-VIA(9) may vary depending on the configuration of the CFET 100.

[0026] The first gate structure 110 and the second gate structure 118 are electrically coupled to each other. This electrical coupling may be internal, through a via VIA(5) extending from the first gate structure 110 through the third layer 138 to the second gate structure 118. In other examples, the first gate structure 110 and the second gate structure 118 may be electrically coupled to each other internally or externally in another manner, rather than through the via VIA(5). Since the first gate structure 110 is electrically coupled to the second gate structure 118, the binary input IN 100 The source / drain 114A is coupled to the reference voltage V through via VIA(2). SS , and the contact CON(2) and the source / drain 122A are coupled to the power supply voltage V through vias VIA(7) and VIA(1) and contacts CON(5) and CON(1) DD . Binary output OUT with binary state 100In contrast to the binary input IN100, a voltage is provided through one of the source / drain 114B or 122B to the contacts CON(4) and CON(7), which are coupled through vias VIA(4), VIA(6) and VIA(8). The channel direction CD through the 3D semiconductor board 106 100 and the channel direction CD through the 3D semiconductor plate 108 100 is Figure 1 In this configuration, CFET 100 can be coupled to an external circuit through contacts CON(1)-CON(4) in first contact layer 140, but in an alternative contact arrangement, CFET 100 can be coupled to an external circuit through second contact layer 142.

[0027] As the following reference Figure 2-Figure 6 As further explained in FIG. 1 , the first GAA FET 102 and the second GAA FET 104 can be fabricated separately as silicon-on-insulator (SOI) devices or bulk semiconductor devices. After being fabricated separately, the first GAA FET 102 and the second GAA FET 104 can be bonded to each other by using layer transfer and stacking processes to form the CFET 100. Alternatively, the second GAA FET 104 can be fabricated separately on the first GAA FET 102.

[0028] Since the first GAA FET 102 and the second GAA FET 104 are manufactured separately, as disclosed in detail below, the 3D semiconductor plate 106 of the first GAA FET 102 is manufactured separately from the 3D semiconductor plate 108 of the second GAA FET 104. Therefore, a crystal structure 144 of the 3D semiconductor plate 106 may be formed, which has a different orientation than the crystal structure 146 of the 3D semiconductor plate 108. In particular, in an example where the first GAA FET 102 is an N-type FET, the crystal structure 144 may have a (100) surface orientation, and <110> The channel direction D 100 Provides high electron mobility. For example, the second GAA FET 104 is a P-type FET, in which the crystal structure 146 has a (110) surface orientation and <110> The channel direction D 100The hole mobility on the P-type FET is improved, and its performance is better than that of a P-type FET whose crystal structure has the same surface orientation as the N-type FET. In conventional structures, the P-type field effect transistor and the N-type field effect transistor formed on the same substrate have a common orientation (e.g., (100)), which hinders the performance of the P-type field effect transistor. Separately forming a crystal structure 146 with a surface orientation (110) improves the performance of the P-type second GAA FET 104 by up to 15%. In addition, after forming the N-type FET (e.g., the first GAA FET 102) or separately forming the P-type FET (e.g., the second GAA FET 104), the P-type FET does not need to undergo high temperature treatment (e.g., annealing) used in the manufacture of the N-type field effect transistor, which may cause the P-type field effect transistor to degrade.

[0029] Figure 2 2 is a diagram of a first GAA FET 202 formed on a first insulating layer 204 and a second GAA FET 206 formed on a second insulating layer 208. The first GAA FET 202 and the second GAA FET 206 may be Figure 1 The first GAAFET 102 and the second GAAFET 104 in the Figure 2 In the example of , the first GAA FET 202 is an N-type FET, including a 3D semiconductor plate 210 and a first gate structure 212. After forming a first insulating layer 204 on the substrate, a first GAA FET 202 (not shown) can be formed on the first insulating layer 204. The first insulating layer 204 can be formed of an oxide, such as silicon dioxide (SiO2) or another suitable insulator material, and the substrate can be a semiconductor substrate (such as silicon). The substrate can then be removed from the first insulating layer 204. In this example, the second GAA FET 206 is a P-type FET, including a 3D semiconductor plate 218 and a second gate structure 220.

[0030] Figure 2 The first GAA FET 202 and the second GAA FET 206 in FIG. 2 are shown in a perspective view before forming epitaxial regions (epitaxial source / drain) at both ends of the 3D semiconductor plates 210 and 218 to more clearly present the Figure 1 Here it can be seen that the first gate structure 212 is formed on the first insulating layer 204 and the second gate structure 220 is formed on the second insulating layer 208 .

[0031] As described above, the first GAA FET 102 is formed in the first layer 128 including the fill material 130, but for simplicity Figure 2 The diagram in Figure 2In the stacking process, the second GAA FET 206 can be reversed so as to be stacked face to face on the first GAA FET 202. Figure 1 A bonding layer (not shown) corresponding to the third layer 138 in the embodiment of the present invention is provided to bond the first GAA FET 202 to the second GAA FET 206. In an alternative example, the second GAA FET 206 can be stacked as shown to perform face-to-back bonding with the first GAA FET 202.

[0032] Figure 3 Is manufacturing Figure 1 Flowchart of a method 300 for stacking a GAA CFET 100 in a stacked GAA CFET 100. The method includes forming a first GAA FET 102 of a first type (box 302), which includes forming a first channel region 112, the first channel region 112 including a first crystal structure, the first crystal structure including a first orientation (box 304). The method of forming the first GAA FET 102 includes forming a first gate structure 110 surrounding the first channel region 112 (box 306). The method includes forming a second GAA FET 104 (308), which includes forming a second channel region 120, the second channel region 120 including a second crystal structure, the second crystal structure including a second orientation different from the first orientation (box 310). The method of forming the second GAA FET includes forming a second gate structure 118 surrounding the second channel region 120 (box 312).

[0033] Figures 4A-4F Is manufacturing Figure 1 Schematic diagram of a cross-sectional side view of stages 400A(1)-400F of CFET 100, and Figures 5A-5F is with Figures 4A-4F Flowchart of method 500 corresponding to the manufacturing stages of CFET 100 in FIG. Figure 4A include Figure 1400A(1) of manufacturing a first GAA FET 102 in the method. The method includes forming a first base layer 132 on a bottom substrate 402 (box 502), and forming a first type of first GAA FET 102 on the first base layer 132, the first GAA FET 102 including a 3D semiconductor plate 106, a source / drain 114A, 114B, and a first gate structure 110 (box 504). In this example, the first GAAFET 102 is a silicon-on-insulator (SOI) transistor formed on the bottom substrate 402. The bottom substrate 402 is an insulating layer, which can be an oxide layer (e.g., SiO2). Before forming the first GAA FET 102, the bottom substrate 402 can be formed on a supporting substrate (not shown) such as a semiconductor substrate, and the semiconductor substrate can be removed thereafter. Alternatively, in some examples, the first GAA FET 102 can be a bulk silicon transistor, wherein the bottom substrate 402 is a semiconductor (e.g., silicon) substrate, and the first GAA FET 102 is formed on an STI layer. Whether SOI or bulk, the first GAA FET 102 is formed in the first layer 128, including a fill material 130, such as an interlayer dielectric (ILD). After forming the first GAA FET 102 on the bottom substrate 402, the method includes polishing the first layer 128 and forming a third layer 138 on the first layer 128 (box 506). Polishing can be chemical polishing, mechanical polishing (CMP), or other known methods. The third layer 138 in this example is an adhesive layer for bonding the first layer 128 to the second layer 134. The third layer 138 can include a bonding oxide such as SiO2. The method also includes forming vias VIA(5), VIA(6) through the third layer (138) (box 508).

[0034] Figure 4A Also included is a manufacturing stage 400A(2) of a second GAA FET 104. The second GAA FET 104 in this example is also SOI, whose top substrate 406 is an insulator layer, or can alternatively be a bulk transistor, in which case the top substrate 406 is a semiconductor substrate. The method 500 also includes forming a second base layer 136 on the top substrate 406 (box 510). The method includes forming a second layer 134 including a second GAA FET 104 on the second base layer 136, the second GAA FET 104 also including a 3D semiconductor plate 108, a source / drain 122A, 122B, and a second gate structure 118 (box 512). The method includes polishing (e.g., by CMP) the second layer 134 (box 514) and forming a via VIA(6) in the second layer 134 (box 516).

[0035] Figure 4BThe manufacturing stage 400B of the CFET 100 in the method 500 includes bonding the second layer 134 to the third layer 138 with the second gate structure 118 opposite to the first gate structure 110 and annealing (block 518). In this regard, the term "opposite" indicates that the first gate structure 110 and the second gate structure 118 are directly opposite to each other on opposite sides of the third layer 138 and in a direction orthogonal to the third layer 138. An annealing process may be used during the bonding process to ensure bonding between the third layer 138 and the oxide of the second layer 134.

[0036] Figure 4C Included is stage 400C of manufacturing CFET 100 . Figure 5C The method in includes removing the top substrate 406 from the second GAA FET 104 (block 520 ). Removing the top substrate 406 may include chemically and / or mechanically removing the top substrate 406 from the second base layer 136 . Figure 4D The method 500 includes a stage 400D of manufacturing the CFET 100. According to the stage 400D, the method 500 includes forming vias (VIA(1), VIA(7)-VIA(9)) in the second layer 134 (box 522) and forming a second contact layer 142, including contacts CON(5)-CON(7) on the second base layer 136 (box 524). Forming the vias VIA(1), VIA(7)-VIA(9) includes forming vias (e.g., etching and filling with conductive metal) through the second base layer 136 of the second GAA FET 104. Forming the second contact layer 142 may include first forming contacts CON(5)-CON(7) on the second base layer 136 and disposing a dielectric on the second base layer 136 and on the contacts CON(5)-CON(7). Alternatively, the contacts CON(5)-CON(7) may be formed in the second base layer 136.

[0037] Figure 4E Included is stage 400E of manufacturing CFET 100 . Figure 5E The method in includes inverting the CFET 100 and removing the bottom substrate 402 from the first GAA FET 102 (block 526 ). Removing the bottom substrate 402 may include chemically and / or mechanically removing the bottom substrate 402 from the first base layer 132 . Figure 4F comprising stage 400F in the manufacture of CFET 100, Fig. 5F The method includes forming vias VIA(1)-VIA(4) in the first GAA FET 102 (block 528), and adding a first contact layer 140, including contacts CON(1)-CON(4) (block 530). Figure 4FThe CFET 100 can be coupled to an external circuit from the first contact layer 140 or the second contact layer 142, which can include thinning the dielectric on one of the first contact layer and the second contact layer (140, 142) to expose the contacts (CON(1)-CON(4)) or (CON(1) and CON(5)-CON(7)).

[0038] In the CFET 100 manufactured by the method described above, the first GAA FET 102 of the first type can be an N-type or P-type transistor, and can form an SOI or bulk transistor. In the above-mentioned manufacturing method, the first GAA FET 102 and the second GAA FET 104 are manufactured separately, and, therefore, 3D semiconductor plates 106 and 108 having crystal structures 144 and 146 with different surface orientations can be formed to improve carrier migration performance. In this regard, the improved performance can include improved performance of the P-type FET without negatively affecting the performance of the N-type FET, thereby obtaining more balanced performance. The relative improvement in the performance of the P-type FET can avoid the need to increase the size of the P-type FET to achieve more balanced performance. In this way, the size of the CFET 100 can be reduced.

[0039] Figure 6-8 is an illustration of a cross-sectional side view of another example of a stacked GAA CFET circuit with SOI transistors.

[0040] Figure 6 6 is an illustration of a cross-sectional side view of a CFET 600 having a first GAA FET 602, which is a first type SOI transistor, stacked face-to-face with respect to a second GAA FET 604, which is a second type second SOI transistor. The first GAA FET 602 includes a first channel direction D 606 The 3D semiconductor plate 606 has a channel direction D 606 The second GAA FET 604 includes a 3D semiconductor plate 614, whose channel direction D 606The CFET 600 includes a first GAA FET 602 formed in the first layer 622 and a second GAA FET 604 formed in the second layer 624. The third layer 626 between the first layer 622 and the second layer 624 may be in direct contact with the first layer 622 and the second layer 624. In this regard, the third layer 626 may be a bonding layer that bonds the first layer 622 to the second layer 624. The CFET 600 also includes a bottom base layer 628 on the first layer 622 and a top base layer 630 on the second layer 624. The CFET 600 also includes a contact layer 632 and a contact layer 634 formed on the bottom base layer 628 and the top base layer 630, respectively.

[0041] In the aspects described above, the first GAA FET 602 corresponds to Figure 1 102 in the first GAA FET 104, and the second GAA FET 604 corresponds to the second GAA FET 104. However, in terms of vias VIA(1)-VIA(8) and contacts CON(1)-CON(7), CFET 600 is similar to Figure 1 It should be noted that the electrical coupling between the first gate structure 612 and the second gate structure 620 is not Figure 6 600 , but may be provided in a different cross-section (not shown) of CFET 600 or outside of CFET 600 .

[0042] Figure 700 is a cross-sectional view of a CFET 700 having a first GAA FET 702 in a first layer 704 and a second GAA FET 706 in a second layer 708. The CFET 700 includes a third layer 710 located between the first layer 704 and the second layer 708. The first GAA FET 702 and the second GAA FET 706 are formed as SOI transistors. In general, the CFET 700 corresponds to Figure 1 100 in CFET 700. However, in CFET 700, the second GAA FET 706 is stacked back-to-back with respect to the first GAA FET 702. That is, the third layer 710 in CFET 700 is an insulating layer, on which the second GAA FET 706 is formed in an SOI process. The first layer 704 is formed on the insulating layer 712. The second layer 708 is formed on the third layer 710, and the third layer 710 is bonded to the first layer 704. A base layer 714 and a contact layer 716 are formed on the second layer 708, and a contact layer 718 is formed on the insulating layer 712. The vias VIA(1)-VIA(9) and the contacts CON(1)-CON(7) correspond to Figure 1The same marking features in .

[0043] Figure 8 8 is a cross-sectional view of a CFET 800, which includes a first GAA FET 802 formed on a first insulating layer 804 and a second GAA FET 806 formed on a second insulating layer 808. The CFET 800 corresponds to Figure 6 600 in FIG. 600 is the same as the case of CFET 700 except that the second GAA FET 806 is stacked back-to-back with the second insulating layer 808 bonded to the first layer 810 including the first GAA FET 802.

[0044] Fig. 9 is an illustration of a first GAA FET 902 located on a first semiconductor substrate 904, and an illustration of a second GAA FET 906 located on a second semiconductor substrate 908. Since the first GAA FET 902 and the second GAA FET 906 are formed on different semiconductor substrates, the orientation of the crystal structure 910 of one or more 3D semiconductor plates 912 in the first GAA FET 902 can be different from the orientation of the crystal structure 914 of one or more 3D semiconductor plates 916 of the second GAA FET 906. As an example, the first GAA FET 902 can be a P-type FET, wherein at least one 3D semiconductor plate 912 has a (110) surface orientation, and the second GAA FET 906 can be an N-type FET, wherein at least one 3D semiconductor plate 916 has a (100) surface orientation. It should be understood that other surface orientations of the crystal structures 910 and 914 are possible because they are formed on different semiconductor substrates 904 and 908, respectively. The 3D semiconductor plates 912 and 916 can both have <100> The channel direction D 900 , corresponding to Fig. 9 . The first GAA FET 902 and the second GAA FET 906 are formed as bulk transistors and are shown in a perspective view without epitaxial source / drain at both ends of the 3D semiconductor plates 912 and 916 to provide a clearer view of certain features. Here, it can be seen that a first gate structure 918 is formed on an STI layer 920 that is electrically isolated from the first semiconductor substrate 904. A second gate structure 922 is formed on an STI layer 924 on the second semiconductor substrate 908.

[0045] The first GAA FET 902 includes a well 926 located between the 3D semiconductor plate 912 and the first semiconductor substrate 904. When the first GAA FET 902 is inactive, the well 926 is provided to reduce or avoid a channel direction D through the first semiconductor substrate 904. 900Reducing the leakage current can improve the performance of the first GAA FET 902 and reduce its power consumption.

[0046] In the example where the first GAA FET 902 is a P-type FET, the well 926 may be an N+ well doped with a high concentration of N-type dopants. In the example where the first GAA FET 902 is an N-type FET, the well 926 may be a P+ well doped with a high concentration of P-type dopants. In this regard, the second GAA FET 906 also has a well 928 between the 3D semiconductor plate 916 and the second semiconductor substrate 908. The wells corresponding to the wells 926 and 928 are located at Figure 10-12 may not be visible in the illustration because vias are formed through the wells at the location of the illustrated cross section.

[0047] Figure 10-12 is an illustration of a cross-sectional side view of an example of a stacked GAA CFET circuit formed on a semiconductor substrate. To avoid redundancy, Figure 10-12 Features corresponding to previously presented features may not be labeled and described separately. Fig.10 1 is a cross-sectional side view of CFET 1000. CFET 1000 includes a first GAA FET 1002 and a second GAA FET 1004 stacked in a face-to-face configuration. CFET 1000 corresponds to Figure 1 The first GAA FET 102 and the second GAA FET 104 are shown in FIG. 1 , except that the first GAA FET 1002 and the second GAA FET 1004 are bulk transistors formed on the first and second semiconductor substrates 1006 and 1008 , respectively, rather than transistors formed on the first and second insulating layers 204 and 208 .

[0048] The first GAA FET 1002 includes a 3D semiconductor plate 1010 that may be formed from a first semiconductor substrate 1006. The second GAA FET 1004 includes a 3D semiconductor plate 1012 that may be formed from a second semiconductor substrate 1008. The first GAA FET 1002 is included in a first layer 1014 and the second GAA FET 1004 is included in a second layer 1016. The CFET 1000 includes a third layer 1018, which may be a bonding layer including an oxide or other bonding material 1020. The CFET 1000 includes a first semiconductor substrate 1006 and an STI layer adjacent to the first layer 1014. The CFET 1000 also includes a first contact layer 1024 including a contact 1026. Due to the conductivity of the first semiconductor substrate 1006, an insulating wall 1028 is provided between each via 1030 and the first semiconductor substrate 1006. The CFET 1000 also includes an STI layer 1032 between the second layer 1016 and the second semiconductor substrate 1008. A second contact layer 1034 including a contact 1036 is formed on the second semiconductor substrate 1008.

[0049] Fig.11 is a cross-sectional view of a CFET 1100 in which a first GAA FET 1102 and a second GAA FET 1104 are stacked on top of each other in a face-to-face configuration, corresponding to Figure 6 1100 is a bulk device rather than an SOI device. The differences between CFET 1100 and CFET 600 include having a first semiconductor substrate 1106 and an STI layer 1108, wherein CFET 600 includes a bottom base layer 628, and having a second semiconductor substrate 1110 and an STI layer 1112 instead of Figure 6 The top base layer 630 in.

[0050] Fig.12 is an illustration of a cross-sectional view of CFET 1200, wherein a first GAA FET 1202 and a second GAA FET 1204 are stacked face to back, corresponding to Figure 8 However, CFET 1200 is a bulk transistor, which results in differences between CFET 1200 and CFET 800, including that CFET 1200 has a first semiconductor substrate 1206 and an STI layer 1208, wherein CFET 800 includes a first insulating layer 804, and CFET 1200 includes a second semiconductor substrate 1210 and an STI layer 1212, instead of Figure 8 The second insulating layer 808 in.

[0051] It should be noted that due to Figure 10-12Each of the CFETs 1000-1200 is formed according to the method described above, wherein the 3D semiconductor plate of the first GAA FET and the 3D semiconductor plate of the second GAA FET can form different crystal structure orientations to improve the performance of the P-type device without reducing the performance of the N-type device. In this case, the term "3D semiconductor plate" refers to a thin layer of semiconductor material having a crystal structure.

[0052] According to aspects disclosed herein, stacked GAA CFETs may be provided in or integrated into any processor-based device, including, for example, but not limited to, set-top boxes, entertainment units, navigation devices, communications devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, drones, and multirotors.

[0053] Fig.13 An exemplary wireless communication device 1300 is illustrated, which includes a radio frequency (RF) component formed by one or more integrated circuits (ICs) 1302, which may include an exemplary stacked GAA CFET, wherein the gate structures of a first GAA FET and a second GAA FET are stacked relative to each other, such as Figure 1 , 6 -8 and 10-12, and according to any aspect disclosed herein. As an example, the wireless communication device 1300 may include or be provided in any of the above-referenced devices. Figure 8 As shown, the wireless communication device 1300 includes a transceiver 1304 and a data processor 1306. The data processor 1306 may include a memory for storing data and program codes. The transceiver 1304 includes a transmitter 1308 and a receiver 1310 that support two-way communication. In general, the wireless communication device 1300 may include any number of transmitters 1308 and / or receivers 1310 for any number of communication systems and frequency bands. All or part of the transceiver 1304 may be implemented on one or more analog ICs, RFICs, mixed signal ICs, etc.

[0054] The transmitter 1308 or the receiver 1310 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig.13 In the wireless communication device 1300 in FIG. 1 , the transmitter 1308 and the receiver 1310 are implemented using a direct conversion architecture.

[0055] In the transmit path, the data processor 1306 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1308. In the exemplary wireless communication device 1300, the data processor 1306 includes digital-to-analog converters (DACs) 1312(1), 1312(2) for converting the digital signals generated by the data processor 1306 into I and Q analog output signals, such as I and Q output currents, for further processing.

[0056] Within the transmitter 1308, low pass filters 1314(1), 1314(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1316(1), 1316(2) amplify the signals from the low pass filters 1314(1), 1314(2), respectively, and provide I and Q baseband signals. An up-converter 1318 up-converts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from a TX LO signal generator 1322 through mixers 1320(1), 1320(2) to provide up-converted signals 1324. A filter 1326 filters the up-converted signals 1324 to remove unwanted signals caused by the frequency up-conversion and noise in the receive frequency band. A power amplifier (PA) 1328 amplifies the up-converted signals 1324 from the filter 1326 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1330 and transmitted via an antenna 1332 .

[0057] In the receive path, antenna 1332 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 1330 and provided to a low noise amplifier (LNA) 1334. The duplexer or switch 830 is designed to operate using a specific receive (RX) to TX duplexer frequency separation to isolate the RX signal from the TX signal. The received RF signal is amplified by LNA 1334 and filtered by filter 1336 to obtain the desired RF input signal. Down-conversion mixers 1338 (1), 1338 (2) mix the output of filter 1336 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1340 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1342 (1), 1342 (2) and filtered by low pass filters 1344 (1), 1344 (2) to obtain I and Q analog input signals, which are provided to the data processor 1306. In this example, the data processor 1306 includes analog-to-digital converters (ADCs) 1346 (1), 1346 (2) for converting the analog input signals into digital signals for further processing by the data processor 1306.

[0058] exist Fig.13 In the wireless communication device 1300 of the embodiment of the present invention, the TX LO signal generator 1322 generates I and Q TX LO signals for frequency up-conversion, and the RX LO signal generator 1340 generates I and Q RX LO signals for frequency down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1348 receives timing information from the data processor 1306 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 1322. Similarly, the RX PLL circuit 1350 receives timing information from the data processor 1306 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 1340.

[0059] The wireless communication device 1300 may include an exemplary stacked GAA CFET circuit, in which the gate structures of the first GAA FET and the second GAA FET are stacked relative to each other, such as Figure 1 , 6-8 and 10-12, and according to any aspect disclosed herein, can be provided in or integrated into any processor-based device. Examples, but not limited to, include set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablets, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (such as smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, drones, and multirotors.

[0060] Fig.14 An example of a processor-based system 1400 is illustrated, which includes a circuit including an exemplary stacked GAA FET circuit, wherein the gate structures of a first GAA FET and a second GAA FET are stacked relative to each other, such as Figure 1 , 6 -8 and 10-12, and according to any aspect disclosed herein. In this example, the processor-based system 1400 includes one or more central processing units (CPUs) 1402, which may also be referred to as CPUs or processor cores, each core including one or more processors 1404. The CPU 1402 may have a cache memory 1406 coupled to the processor 1404 for quick access to temporarily stored data. The CPU 1402 is coupled to a system bus 1408 and may couple master devices and slave devices included in the processor-based system 1400 to each other. As is well known, the CPU 1402 communicates with these other devices by exchanging address, control, and data information on the system bus 1408. For example, the CPU 1402 may communicate a bus transaction request to a memory controller 1410, as an example of a slave device. Although in Fig.14 It is not illustrated, but multiple system buses 1408 may be provided; each system bus 1408 forming a different structure.

[0061] Other master devices and slave devices may be connected to the system bus 1408. Fig.14As illustrated, as an example, these devices may include a memory system 1412, the memory system 1412 including a memory controller 1410 and one or more memory arrays 1414, one or more input devices 1416, one or more output devices 1418, one or more network interface devices 1420, and one or more display controllers 1422. The input device 1416 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device 1418 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device 1420 may be any device configured to allow data to be exchanged with a network 1424. The network 1424 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH TM Networks and the Internet. The network interface device 1420 may be configured to support any type of communication protocol desired.

[0062] The CPU 1402 may also be configured to access a display controller 1422 via the system bus 1408 to control information sent to one or more displays 1426. The display controller 1422 sends information to the display 1426 to be displayed via one or more video processors 1428, which process the information to be displayed into a format suitable for the display 1426. The display 1426 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, or a light emitting diode (LED) display, etc.

[0063] Those skilled in the art will further understand that the various illustrative logic boxes, modules, circuits and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master device and slave device described herein can be used in any circuit, hardware component, IC or IC chip. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information required. In order to clearly illustrate this interchangeability, various illustrative components, frames, modules, circuits and steps are generally described above according to their functions. How to implement these functions depends on specific applications, design choices and / or design constraints imposed on the entire system. The technician can implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing deviations from the scope of the present disclosure.

[0064] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative embodiment, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0065] The aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an optional solution, the storage medium may be an integral part of the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote site. Alternatively, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0066] It should also be noted that the operational steps described in any exemplary aspects are described herein to provide examples and discussions. The described operations can be performed in many different orders other than the illustrated order. In addition, the operations described in a single operational step can actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps illustrated in the flow chart can be subject to many different modifications, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using various technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be cited throughout the description above can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0067] The above description of the present disclosure is provided to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but is to be given the broadest scope consistent with the principles and novel features disclosed herein.

[0068] Implementation examples are described in the following numbered clauses:

[0069] 1. A stacked complementary field effect transistor (CFET), comprising:

[0070] A first gate-all-around (GAA) FET of a first type, the first GAA FET comprising:

[0071] a first channel region comprising a first crystal structure, the first crystal structure comprising a first orientation; and

[0072] a first gate structure surrounding the first channel region; and

[0073] A second GAA FET of a second type, the second GAA FET comprising:

[0074] a second channel region including a second crystal structure including a second orientation different from the first orientation; and

[0075] A second gate structure surrounds the second channel region.

[0076] 2. The stacked CFET of clause 1, wherein:

[0077] The first orientation of the first crystal structure is (100); and

[0078] The second orientation of the second crystal structure is (110).

[0079] 3. The stacked CFET of clause 1 or clause 2, wherein:

[0080] The first GAA FET of the first type is an N-type FET; and

[0081] The second GAA FET of the second type is a P-type FET.

[0082] 4. The stacked CFET of any one of clauses 1 to 3, further comprising:

[0083] A first layer including the first GAA FET;

[0084] a second layer including the second GAA FET; and

[0085] The third layer is between the second layer and the first layer.

[0086] 5. The stacked CFET of clause 4, wherein the third layer comprises a bonding layer bonding the first layer to the second layer.

[0087] 6. The stacked CFET of clause 5, wherein the bonding layer comprises an oxide layer.

[0088] 7. The stacked CFET of any of clauses 4 to 6, wherein the third layer comprises a semiconductor substrate.

[0089] 8. The stacked CFET of any of clauses 4 to 7, further comprising a via extending from the first gate structure through the third layer to the second gate structure.

[0090] 9. The stacked CFET of any of clauses 4 to 8, further comprising:

[0091] a first dielectric layer on the first layer, the first dielectric layer comprising a first contact coupled to the first GAA FET; and

[0092] A second dielectric layer is provided on the second layer, the second dielectric layer including a second contact coupled to the second GAA FET.

[0093] 10. The stacked CFET of clause 9, further comprising:

[0094] A via extends from the first contact through the first layer, the third layer, and the second layer to the second contact.

[0095] 11. The stacked CFET of clause 9 or 10, further comprising a first semiconductor substrate between the first layer and the first dielectric layer.

[0096] 12. The stacked CFET of clause 11, further comprising a second semiconductor substrate between the second layer and the second dielectric layer.

[0097] 13. The stacked CFET of any of clauses 1 to 12, wherein a first epitaxial region coupled to the first channel region of the first GAA FET is coupled to a second epitaxial region coupled to the second channel region of the second GAA FET.

[0098] 14. The stacked CFET of any of clauses 1 to 13, integrated in an integrated circuit (IC).

[0099] 15. Integrate the stacked CFET described in any of clauses 1 to 14 into a device selected from the following components: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cell phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer display; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; a motor vehicle; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor helicopter.

[0100] 16. A method of manufacturing a stacked complementary field effect transistor (CFET), the method comprising:

[0101] forming a first gate-all-around (GAA) FET of a first type, the first GAA FET comprising:

[0102] a first channel region comprising a first crystal structure, the first crystal structure comprising a first orientation; and

[0103] a first gate structure surrounding the first channel region;

[0104] A second GAA FET of a second type is formed, the second GAA FET comprising:

[0105] a second channel region comprising a second crystal structure, the second crystal structure comprising a second orientation different from the first orientation; and

[0106] A second gate structure surrounds the second channel region.

[0107] 17. The method of clause 16, wherein:

[0108] Forming the first GAA FET further includes: forming the first GAA FET in a first layer on a first oxide layer on a first substrate; and

[0109] Forming the second GAA FET further includes forming the second GAA FET in a second layer on a second oxide layer on a second substrate.

[0110] 18. The method of clause 16 or 17, wherein:

[0111] The first orientation is a (100) orientation; and

[0112] The second orientation is a (110) orientation.

[0113] 19. The method of clause 17 or 18, further comprising:

[0114] forming a bonding layer on one of the first layer and the second layer; and

[0115] The second layer is stacked on the first layer.

[0116] 20. The method of clause 19, further comprising:

[0117] A via is formed extending through the bonding layer to couple the first gate structure to the second gate structure.

Claims

1. A stacked complementary field effect transistor (CFET), comprising: A first gate-all-around (GAA) FET of a first type, the first GAA FET comprising: a first channel region comprising a first crystal structure, the first crystal structure comprising a first orientation; and a first gate structure surrounding the first channel region; and A second GAA FET of a second type, the second GAA FET comprising: a second channel region including a second crystal structure including a second orientation different from the first orientation; and A second gate structure surrounds the second channel region.

2. The stacked CFET of claim 1, wherein: The first orientation of the first crystal structure is (100); and The second orientation of the second crystal structure is (110).

3. The stacked CFET of claim 1 , wherein: The first GAA FET of the first type is an N-type FET; and The second GAA FET of the second type is a P-type FET.

4. The stacked CFET of claim 1 , further comprising: A first layer including the first GAA FET; A second layer including the second GAA FET; as well as The third layer is between the second layer and the first layer. 5 . The stacked CFET of claim 4 , wherein the third layer comprises a bonding layer bonding the first layer to the second layer. The stacked CFET of claim 5 , wherein the bonding layer comprises an oxide layer. The stacked CFET of claim 4 , wherein the third layer comprises a semiconductor substrate.

8. The stacked CFET of claim 4 further comprising a via extending from the first gate structure through the third layer to the second gate structure.

9. The stacked CFET of claim 4, further comprising: a first dielectric layer on the first layer, the first dielectric layer comprising a first contact coupled to the first GAA FET; as well as A second dielectric layer is provided on the second layer, the second dielectric layer including a second contact coupled to the second GAA FET.

10. The stacked CFET of claim 9, further comprising: A via extends from the first contact through the first layer, the third layer, and the second layer to the second contact.

11. The stacked CFET of claim 9, further comprising a first semiconductor substrate between the first layer and the first dielectric layer. 12 . The stacked CFET of claim 11 , further comprising a second semiconductor substrate between the second layer and the second dielectric layer.

13. The stacked CFET of claim 1, wherein a first epitaxial region coupled to the first channel region of the first GAA FET is coupled to a second epitaxial region coupled to the second channel region of the second GAA FET.

14. The stacked CFET of claim 1 integrated into an integrated circuit (IC).

15. The stacked CFET of claim 1, integrated into a device selected from the following components: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cell phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer display; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; a motor vehicle; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor helicopter.

16. A method of manufacturing a stacked complementary field effect transistor (CFET), the method comprising: forming a first gate-all-around (GAA) FET of a first type, the first GAA FET comprising: a first channel region comprising a first crystal structure, the first crystal structure comprising a first orientation; and a first gate structure surrounding the first channel region; A second GAA FET of a second type is formed, the second GAA FET comprising: a second channel region comprising a second crystal structure, the second crystal structure comprising a second orientation different from the first orientation; and A second gate structure surrounds the second channel region.

17. The method of claim 16, wherein: Forming the first GAA FET further includes: forming the first GAA FET in a first layer on a first oxide layer on a first substrate; and Forming the second GAA FET further includes forming the second GAA FET in a second layer on a second oxide layer on a second substrate.

18. The method of claim 16, wherein: The first orientation is a (100) orientation; and The second orientation is a (110) orientation.

19. The method according to claim 17, further comprising: forming a bonding layer on one of the first layer and the second layer; as well as The second layer is stacked on the first layer.

20. The method according to claim 19, further comprising: A via is formed extending through the bonding layer to couple the first gate structure to the second gate structure.

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