Junction temperature determination method and device for multi-chip power module

Abstract

The invention provides a junction temperature determination method and device for a multi-chip power module. The junction temperature determination method for the multi-chip power module comprises the following steps: determining a heat flow distribution rule of the multi-chip power module in a plurality of thermal coupling modes; determining a mapping relation between the heat flow distribution rule and a thermal model parameter of the multi-chip power module; establishing a thermal network model of the multi-chip power module in the plurality of thermal coupling modes according to the mapping relation; and determining the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution rule function of the multi-chip power module. According to the invention, accurate prediction of the multi-chip packaging power junction temperature can be realized, and adaptability, real-time performance and universality of junction temperature prediction can be improved.

Description

Technical Field

[0001] The present application belongs to the technical field of junction temperature monitoring of chip packaging devices, and in particular to a method and device for determining the junction temperature of a multi-chip power module. Background Art

[0002] Insulated gate bipolar transistor (IGBT) is widely used in rail transit and other fields due to its advantages such as high switching frequency, high power density and easy driving. As one of the core components of the converter, IGBT is responsible for reliable power conversion and efficient energy transmission in the converter. It is considered to be one of the most critical components for the reliability of the converter and even the entire system. Therefore, the reliability evaluation of IGBT module is of great significance.

[0003] At present, the thermal reliability assessment methods of IGBT modules mostly rely on junction temperature. On the one hand, junction temperature information can be used to evaluate the current health status and service life of the module, and on the other hand, it can affect the power loss and switching characteristics of the module. Therefore, an accurate junction temperature estimation method is of great significance to achieve long-term safe and stable operation of the converter. The IGBT thermal network model method combines device loss and device spatial structure to achieve non-invasive monitoring of the junction temperature of power devices. The physical meaning of the monitored temperature depends on the temperature point used when establishing the thermal network. Due to its simplicity and low invasiveness, junction temperature monitoring based on the thermal network model method is widely used in actual engineering. In order to meet the application requirements of high voltage and high current, multi-chip packaged IGBT modules have become a development trend.

[0004] However, in a multi-core packaged IGBT module, there is a thermal coupling effect between different chips, and the traditional thermal network model does not take this factor into account, which will lead to an underestimate of the junction temperature. Summary of the invention

[0005] In view of the technical pain points in the prior art, which are the lack of a method for determining the junction temperature of a multi-core packaged IGBT module and the failure to obtain the temperature distribution characteristics of the chips in the multi-core packaged IGBT module, the present invention proposes a method for predicting the junction temperature of a power chip by considering thermal coupling and an effective heat transfer path and combining the junction temperature distribution law function. This method can achieve accurate prediction of the power junction temperature of a multi-chip package, and can improve the adaptability, real-timeness and versatility of the junction temperature prediction.

[0006] In order to solve the technical problems in the background technology of this application, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a method for determining the junction temperature of a multi-chip power module, the method comprising:

[0008] Determining heat flux distribution rules of the multi-chip power module under multiple thermal coupling modes;

[0009] Determining a mapping relationship between the heat flux distribution law and the thermal model parameters of the multi-chip power module;

[0010] Establishing a thermal network model of the multi-chip power module under the multiple thermal coupling modes according to the mapping relationship;

[0011] The junction temperature of the multi-chip power module is determined according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

[0012] In some embodiments of the present application, determining the heat flux distribution law of the multi-chip power module in multiple thermal coupling modes includes:

[0013] Establishing a three-dimensional finite element model of the multi-chip power module;

[0014] Performing thermal simulation on the three-dimensional finite element model to obtain a temperature distribution cloud diagram of the multi-chip power module under the multiple thermal coupling modes;

[0015] The heat flow distribution law is determined according to the temperature distribution cloud diagram.

[0016] In some embodiments of the present application, a method for determining the junction temperature of a multi-chip power module further includes:

[0017] The thermal model parameters of the structural layer are determined according to the effective heat transfer area of ​​the structural layer of the multi-chip power module, the thickness, thermal conductivity, constant-pressure specific heat capacity and density of each material.

[0018] In some embodiments of the present application, the thermal model parameters include self-heating parameters and coupled thermal parameters;

[0019] The self-heating parameters include: self-heating thermal resistance parameter and self-heating heat capacity parameter;

[0020] The coupled thermal parameters include: coupled thermal resistance parameters and coupled thermal melt parameters.

[0021] In some embodiments of the present application, the self-heating parameter is used to characterize the heat flow characteristics of each structural layer of the multi-chip power module;

[0022] The coupled thermal parameters are used to characterize the heat flow characteristics of the structural layer where thermal coupling occurs in the multi-chip power module.

[0023] In a second aspect, the present invention provides a junction temperature determination device for a multi-chip power module, the device comprising:

[0024] A heat flux distribution law determination module, used to determine the heat flux distribution law of the multi-chip power module under multiple thermal coupling modes;

[0025] A mapping relationship determination module, used to determine a mapping relationship between the heat flow distribution law and the thermal model parameters of the multi-chip power module;

[0026] A thermal network model establishment module, used to establish a thermal network model of the multi-chip power module under the multiple thermal coupling modes according to the mapping relationship;

[0027] The junction temperature determination module is used to determine the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

[0028] In some embodiments of the present application, the heat flux distribution law determination module includes:

[0029] A three-dimensional model building unit, used to build a three-dimensional finite element model of the multi-chip power module;

[0030] A model thermal simulation unit, used for performing thermal simulation on the three-dimensional finite element model to obtain a temperature distribution cloud diagram of the multi-chip power module under the multiple thermal coupling modes;

[0031] A heat flux distribution law determining unit is used to determine the heat flux distribution law according to the temperature distribution cloud map.

[0032] In some embodiments of the present application, a junction temperature determination device for a multi-chip power module further includes:

[0033] The thermal model parameter determination module is used to determine the thermal model parameters of the structural layer according to the effective heat transfer area of ​​the structural layer of the multi-chip power module, the thickness, thermal conductivity, constant pressure specific heat capacity and density of each material.

[0034] In some embodiments of the present application, the thermal model parameters include self-heating parameters and coupled thermal parameters;

[0035] The self-heating parameters include: self-heating thermal resistance parameter and self-heating heat capacity parameter;

[0036] The coupled thermal parameters include: coupled thermal resistance parameters and coupled thermal melt parameters.

[0037] In some embodiments of the present application, the self-heating parameter is used to characterize the heat flow characteristics of each structural layer of the multi-chip power module;

[0038] The coupled thermal parameters are used to characterize the heat flow characteristics of the structural layer where thermal coupling occurs in the multi-chip power module.

[0039] In a third aspect, the present invention provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the steps of a method for determining the junction temperature of a multi-chip power module.

[0040] In a fourth aspect, the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of a method for determining the junction temperature of a multi-chip power module are implemented.

[0041] In a fifth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a method for determining the junction temperature of a multi-chip power module.

[0042] From the above description, it can be seen that an embodiment of the present invention provides a method and device for determining the junction temperature of a multi-chip power module. The corresponding method for determining the junction temperature of a multi-chip power module includes: first, determining the heat flux distribution law of the multi-chip power module under multiple thermal coupling modes; determining the mapping relationship between the heat flux distribution law and the thermal model parameters of the multi-chip power module; then, establishing a thermal network model of the multi-chip power module under multiple thermal coupling modes according to the mapping relationship; finally, determining the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

[0043] In summary, the present invention provides a method for determining the junction temperature of a multi-chip power module. The method can accurately estimate the junction temperature information of each chip under different thermal coupling modes by analyzing the internal heat flow characteristics and junction temperature distribution of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A schematic diagram of a process for determining the junction temperature of a multi-chip power module provided by an embodiment of the present invention Figure 1 ;

[0046] Figure 2 A flow chart of step 100 of a method for switching an excitation drive sequential control mode of a distributed phase regulator provided by an embodiment of the present invention;

[0047] Figure 3 A schematic diagram of a process for determining the junction temperature of a multi-chip power module provided by an embodiment of the present invention Figure 2 ;

[0048] Figure 4 A schematic diagram of a process for determining the junction temperature of a multi-chip power module provided by an embodiment of the present invention Figure 3 ;

[0049] Figure 5 A schematic flow chart of a method for determining the junction temperature of a multi-chip power module provided for a specific application example of the present invention;

[0050] Figure 6 A diagram showing the distribution of internal heat flow characteristics of an IGBT module provided for a specific application example of the present invention;

[0051] Figure 7 A schematic diagram of the internal heat flow diffusion path of a multi-chip IGBT module provided for a specific application example of the present invention;

[0052] Figure 8 A schematic cross-sectional diagram of the intersecting heat diffusion paths between chips provided for a specific application example of the present invention;

[0053] Fig. 9 A thermal network model topology provided for a specific application example of the present invention;

[0054] Fig.10 A schematic diagram of chip surface temperature distribution when multiple chips are coupled for a specific application example of the present invention (temperature distribution law of chip 1 surface);

[0055] Fig.11 A schematic diagram of chip surface temperature distribution when multiple chips are coupled for a specific application example of the present invention (temperature distribution law of chip 3 surface);

[0056] Fig.12 A schematic diagram of chip surface temperature distribution when multiple chips are coupled for a specific application example of the present invention (temperature distribution law on the surface of chip 5);

[0057] Fig.13 A flow chart for estimating the junction temperature of each chip in a multi-chip module provided for a specific application example of the present invention;

[0058] Fig.14 FIG. 1 is a schematic diagram of a device for determining junction temperature of a multi-chip power module according to an embodiment of the present invention. Figure 1 ;

[0059] Fig.15 Schematic diagram of the structure of the heat flow distribution law determination module 10 in an embodiment of the present invention;

[0060] Fig.16 FIG. 1 is a schematic diagram of a device for determining junction temperature of a multi-chip power module according to an embodiment of the present invention. Figure 2 ;

[0061] Fig.17 It is a schematic diagram of the structure of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0064] It should be noted that the terms "including" and "having" in the specification and claims of the present application and the above-mentioned drawings and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. In the absence of conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0065] The IGBT power module is composed of multiple layers of materials. Due to the different thermal conductivity coefficients of the materials, there is a temperature difference between the structural layers in the module. The heat conduction process caused by the temperature difference in the module can be compared to Ohm's law in the circuit. Therefore, the entire heat transfer path inside the IGBT module can be described by the thermal resistance R th , heat capacity C th The power loss generated by the chip is equivalent to heat flow, which flows from the chip active area along the heat flow path through each structural layer, causing the temperature of the chip and each layer of material to change. At the same time, different thermal coupling modes between chips will have different effects on the heat flow characteristics in the IGBT module.

[0066] On the other hand, compared with a single junction temperature, obtaining chip temperature distribution characteristics can provide more information for power device failure analysis, life prediction and thermal management. In order to obtain the junction temperature information of multiple chips, it is necessary to refine the monitoring points on the chip, establish a complex three-dimensional lumped thermal network model, and then extract detailed temperature distribution information. Obviously, the more monitoring points are set, the more accurate the temperature distribution is, and the corresponding number of RC parameters will also increase, increasing the calculation burden.

[0067] Based on this and the technical shortcomings described in the background technology, an embodiment of the present invention provides a specific implementation method of a method for determining the junction temperature of a multi-chip power module, see Figure 1 , the method comprising:

[0068] Step 100: determining the heat flow distribution law of the multi-chip power module under multiple thermal coupling modes;

[0069] Step 200: Determine a mapping relationship between the heat flux distribution law and the thermal model parameters of the multi-chip power module;

[0070] Step 300: Establishing a thermal network model of the multi-chip power module in the multiple thermal coupling modes according to the mapping relationship;

[0071] Step 400: Determine the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

[0072] From the above description, it can be seen that an embodiment of the present invention provides a method and device for determining the junction temperature of a multi-chip power module. The corresponding method for determining the junction temperature of a multi-chip power module includes: first, determining the heat flux distribution law of the multi-chip power module under multiple thermal coupling modes; determining the mapping relationship between the heat flux distribution law and the thermal model parameters of the multi-chip power module; then, establishing a thermal network model of the multi-chip power module under multiple thermal coupling modes according to the mapping relationship; finally, determining the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

[0073] In summary, the present invention provides a method for determining the junction temperature of a multi-chip power module. The method can accurately estimate the junction temperature information of each chip under different thermal coupling modes by analyzing the internal heat flow characteristics and junction temperature distribution of the module.

[0074] In some embodiments of the present application, see Figure 2 , step 100 comprises:

[0075] Step 101: establishing a three-dimensional finite element model of the multi-chip power module;

[0076] First, the geometric layout of each chip in the IGBT module needs to be determined. Usually, an IGBT module contains multiple IGBT chips and diode chips, which are arranged on a heat dissipation substrate. The geometric model should include various components such as chips, solder layers, substrates, and heat sinks. According to the analysis requirements, the model is geometrically simplified, such as ignoring some small features to reduce the amount of calculation. Next, define the material properties of each component, including density, thermal conductivity, specific heat capacity, elastic modulus, Poisson's ratio, electrical conductivity, etc. The geometric model is meshed. In order to ensure the accuracy of the analysis, the meshes in key areas such as chips, solder layers, and substrates need to be refined. Tetrahedral meshes or hexahedral meshes can be used, and the specific choice depends on the complexity of the geometry and the requirements of the solver.

[0077] Step 102: performing thermal simulation on the three-dimensional finite element model to obtain a temperature distribution cloud diagram of the multi-chip power module under the multiple thermal coupling modes;

[0078] Define the heat exchange between the 3D finite element model and the outside world. Define the power, heat flux, power density distribution, etc. of the heat source.

[0079] Select the appropriate solution type (such as steady-state thermal analysis or transient thermal analysis) and solver (such as finite element-based thermal solver). Set the calculation accuracy, convergence conditions and time step (for transient analysis), and start the simulation calculation.

[0080] Step 103: Determine the heat flow distribution law according to the temperature distribution cloud map.

[0081] In some embodiments of the present application, see Figure 3 , a method for determining the junction temperature of a multi-chip power module, further comprising:

[0082] Step 500: Determine the thermal model parameters of the structural layer according to the effective heat transfer area of ​​the structural layer of the multi-chip power module, the thickness, thermal conductivity, constant-pressure specific heat capacity and density of each material.

[0083] For example, the self-heating thermal resistance parameters and self-heating thermal capacity parameters in the thermal model parameters of each layer of the thermal network model are calculated based on the effective heat transfer area on each structural layer of the multi-chip power module, the thickness, thermal conductivity, constant pressure specific heat capacity and density of each material.

[0084] In some embodiments of the present application, the implementation of step 200 specifically includes:

[0085] According to the variation law of heat flux density and effective heat transfer area curve, the relationship between heat flux distribution and self-heating parameters and coupled heat parameters in the thermal network model can be derived, as shown in the following formula:

[0086]

[0087] Among them, R ths Indicates the thermal resistance of each layer of material, K / W; C ths represents the self-heating capacity of each layer of material, J / K; d represents the thickness of each layer of material, m; K T Indicates the thermal conductivity of each layer of material, W / m 2 ;c T represents the constant pressure specific heat capacity of each layer of material, J / (kg·K); ρ represents the density of each layer of material, kg / m 3 And, the effective heat transfer area A z Calculated by the following formula:

[0088]

[0089] Among them, P loss is the loss applied to the power module chip layer, that is, the power of the heat source mentioned above; q z Indicates heat flux, W / m 2 .

[0090] In addition, for the chip layer, the thermal resistance obtained by taking its surface area as the effective heat transfer area is quite different from the finite element simulation result. Therefore, thermal simulation is needed to determine the effective heat transfer area of ​​the chip layer, which is determined by the following formula:

[0091]

[0092] Among them, T j Indicates the module junction temperature, K; T solder1 Indicates the chip solder layer temperature, K; A chip Indicates the effective heat transfer area of ​​the chip, m 2 ;d chip Indicates the chip layer thickness, m; K Tj Indicates the thermal conductivity of the chip layer, W / m 2 . T j , T solder1 All obtained from thermal simulation.

[0093] Then, the coupled thermal resistance and thermal capacitance parameters of the thermal model are calculated based on the overlapping area of ​​the heat diffusion paths between the chips. That is, the effective heat transfer area of ​​each chip is equivalent to a circle. Based on the geometric relationship between the effective heat diffusion paths of the two chips, the area of ​​the overlapping part of the heat flow path between the two chips is calculated according to the following formula:

[0094] A 31 (z) = α 3 (z)r 3 2 (z)+α 1 (z)r 1 2 (z)-d 13 r1 (z)sin(α 1 (z)) (5)

[0095] Among them, A 31 (z) represents the area where the heat flows of chip 1 and chip 3 overlap at layer m, m 2 ; r 3 (z) represents the radius of the effective heat transfer area of ​​the chip 3 at the mth layer, m; r 1 (z) represents the radius of the effective heat transfer area of ​​chip 1 at the mth layer, m; d 13 represents the distance between the center points of chip 1 and chip 3, m; α 3 (z) and α 1 (z) represent the auxiliary angles of chip 3 and chip 1 on the mth layer respectively.

[0096] Furthermore, the coupled thermal resistance R thc , heat capacity C thc The parameters can be calculated as follows:

[0097]

[0098] Among them, zum and zlm are the upper and lower boundaries of the mth layer structure respectively, and c represents the z-axis coordinate of the intersection of the heat diffusion paths of the two chips at the beginning of the mth layer. c can be calculated by the following formula:

[0099] r 1 (c)+r 3 (c) = d 13 (7)

[0100] If c<0, the heat diffusion paths of the two chips intersect at least at the m-1th layer, otherwise, the heat flow paths of the two chips intersect from the mth layer.

[0101] In some embodiments of the present application, the specific implementation of step 300 is:

[0102] The self-heating parameters and coupled thermal parameters of the multi-chip power module thermal network model are extracted, and a thermal network model based on the Cauer structure is established, in which the self-heating parameters correspond to each structural layer of the IGBT module, and the coupled thermal parameters are only introduced into the structural layer where the thermal coupling effect occurs. Then, the chip junction temperature under different thermal coupling modes is estimated based on the established thermal network model.

[0103] In some embodiments of the present application, the thermal model parameters include self-heating parameters and coupled thermal parameters;

[0104] The self-heating parameters include: self-heating thermal resistance parameter and self-heating heat capacity parameter;

[0105] The coupled thermal parameters include: coupled thermal resistance parameters and coupled thermal melt parameters.

[0106] In some embodiments of the present application, the self-heating parameter is used to characterize the heat flow characteristics of each structural layer of the multi-chip power module;

[0107] The coupled thermal parameters are used to characterize the heat flow characteristics of the structural layer where thermal coupling occurs in the multi-chip power module.

[0108] In some embodiments of the present application, see Figure 4 , a method for determining the junction temperature of a multi-chip power module, further comprising:

[0109] Step 600: Establishing a junction temperature distribution law function.

[0110] When step 600 is implemented, specifically, the distribution relationship of the temperature of each point on the chip surface with the position under different thermal coupling modes is extracted by finite element simulation. A quadratic function is usually used to describe the temperature distribution law on the chip surface. For the entire multi-chip power module, the distribution relationship of the junction temperature on the chip surface with the position is fitted by a quadratic function, that is,

[0111] T(x,y)=p 00 +p 10 ·x+p 01 y+p 20 ·x 2 +p 02 ·y 2 (8)

[0112] Among them, p ij (i=0~2, j=0~2) are fitting parameters. 00 Represents the maximum temperature at the center of the chip surface; p 01 and p 10 Respectively represent the temperature changes in the x and y directions; p 02 and p 20 Represent the temperature change rate in the x and y directions respectively.

[0113] Through finite element analysis simulation, multiple junction temperature distribution functions of multi-chip power modules in different thermal coupling modes are extracted, as shown in the following formula:

[0114]

[0115] Subsequently, the junction temperature at a specific node is estimated based on the thermal network model, the specific junction temperature distribution function is determined, and then the junction temperature information of each chip is calculated.

[0116] In the prior art, thermal network models can be used to characterize the thermal characteristics of IGBT power modules and to estimate junction temperature. However, due to the existence of thermal coupling effects in multi-chip package modules, the thermal analysis accuracy of many thermal network models is not ideal. Based on this, an embodiment of the present invention provides a method for determining the junction temperature of a multi-chip power module, the method comprising: first, determining the heat flux distribution law of the multi-chip power module under multiple thermal coupling modes; determining the mapping relationship between the heat flux distribution law and the thermal model parameters of the multi-chip power module; then, establishing a thermal network model of the multi-chip power module under multiple thermal coupling modes according to the mapping relationship; finally, determining the junction temperature of the multi-chip power module according to the thermal network model and a pre-established function of the junction temperature distribution law of the multi-chip power module.

[0117] In summary, the method provided by the embodiment of the present invention analyzes the influence of different thermal coupling modes on the heat flow characteristics in the module, derives the mapping relationship between the heat flow distribution and the thermal network parameters, and thus avoids the influence of the thermal coupling effect on the estimation accuracy of the junction temperature of the multi-chip power module. This scheme considers thermal coupling and effective heat transfer paths to establish a thermal network model, and combines the junction temperature distribution law function to predict the junction temperature of the power chip, which can achieve accurate prediction of the power junction temperature of the multi-chip package, and can improve the adaptability, real-time and versatility of the junction temperature prediction.

[0118] To further illustrate the solution, the present invention also provides a specific application example of a method for determining the junction temperature of a multi-chip power module, see Figure 5 , the method comprises the following steps.

[0119] S1: Extract thermal network model parameters.

[0120] In order to accurately obtain the junction temperature information of multi-chip power modules, it is necessary to study the heat flux diffusion process in the module, the thermal coupling effect between chips, and the temperature distribution law on the chip surface. Specifically, the three-dimensional geometric size parameters of the multi-chip IGBT module and the material thermal characteristic parameters of each structural layer are first obtained.

[0121] In this specific application example, the side length and thickness of each structural layer are obtained by removing the shell and insulation material of the IGBT module, and the thermal characteristic parameters of each structural layer material are obtained by consulting the database, including the thermal conductivity, constant pressure specific heat capacity and density of the material. Subsequently, with the help of thermal simulation analysis, the heat flux density curve of the path directly below the center of the chip (z-axis direction) is extracted. At the same time, the effective heat transfer area of ​​each layer of material in the IGBT module is calculated based on the heat flux density and the power loss of the chip, such as Figure 6 As shown. According to the effective heat transfer area on each structural layer, the thickness, thermal conductivity, constant pressure specific heat capacity and density of each material, the self-heating thermal resistance parameter and self-heating heat capacity parameter of each layer of the thermal network model are calculated (see formula (1)).

[0122] In addition, for the chip layer, the thermal resistance obtained by taking its surface area as the effective heat transfer area is quite different from the finite element simulation result. Therefore, thermal simulation is required to determine the effective heat transfer area of ​​the chip layer (see formula (3) and formula (4)).

[0123] Then, thermal simulation analysis is used to extract the effective heat transfer path in the multi-chip IGBT module when multiple chips are turned on at the same time, such as Figure 7 To facilitate the calculation of the area of ​​the overlapping parts of the heat flow path, the effective heat transfer area A of each structural layer in the module is z Approximately circular.

[0124] This specific application example takes chip 1 and chip 3 located on the same upper copper layer as an example, and the center point of the chip is represented by O 1 , O 3 , the chip spacing is d 13 , the heat diffusion paths of chip 1 and chip 3 intersect from the upper copper layer, and the thermal coupling occurs below the intersection surface. The heat flow paths of chip 1 and chip 3 are extracted at the intersection section of the mth layer, as shown in Figure 8 Points A and B in the figure are the effective heat transfer area A on the mth layer directly below chip 1 and chip 3. m (z) intersection, where r 3 (z), r 1 (z) are the effective heat transfer areas A of the two chips on the mth layer respectively m (z) is the radius of 3 O 1 , ∠AO 1 O 3 They are defined as α 3 , α 1 .

[0125] According to the geometric relationship between the effective heat diffusion paths of the two chips, the area of ​​the overlapping portion of the heat flow path between the two chips is calculated according to the following formula:

[0126]

[0127] In order to calculate the coupled RC parameters, it is necessary to calculate the z-axis coordinate of the point c where the heat diffusion paths of the two chips begin to intersect in the m layer. Combining equations (3) to (9), c can be calculated as follows:

[0128] r 1 (c)+r 3 (c) = d 13 (11)

[0129] If c<0, the heat diffusion paths of the two chips intersect at least at the m-1th layer, otherwise, the heat flow paths of the two chips intersect from the mth layer. Based on the overlapping area of ​​the heat diffusion paths between the chips, the coupled thermal resistance and thermal capacitance parameters of the thermal model are calculated. The coupled thermal resistance R thc , heat capacity C thc The parameters can be calculated according to formula (6).

[0130] S2: Calculate the junction temperature at a specific node of chip 3.

[0131] According to the above process, the self-heating parameters and coupled thermal parameters of the thermal network model of the multi-chip power module are extracted, and a thermal network model based on the Cauer type structure is established, such as Fig. 9 As shown. The self-heating parameters correspond to each structural layer of the IGBT module, while the coupling heat parameters are only introduced into the structural layer where the thermal coupling effect occurs. This embodiment estimates the junction temperature of the chip 3 under different thermal coupling modes based on the established thermal network model.

[0132] S3: Fit the junction temperature distribution function of each chip surface.

[0133] By means of finite element simulation, the distribution relationship of the temperature of each point on the chip surface with the position under different thermal coupling modes is extracted. In this embodiment, the temperature data on the diagonal line of each chip is first fitted, such as Fig.10 , Fig.11 as well as Fig.12 As shown in Figure 1, the junction temperature distribution is approximately parabolic. Therefore, a quadratic function is used to describe the temperature distribution on the chip surface. For the entire multi-chip power module, the distribution relationship between the chip surface junction temperature and position is fitted using a quadratic function, see formula (8).

[0134] In formula (8), p ij (i=0~2,j=0~2) are fitting parameters. According to the temperature continuous distribution characteristics of the temperature cloud map of the IGBT chip, the fitting parameters can be fitted. The temperature distribution is different in different thermal coupling modes, and the fitting parameters are also different. The temperature rise of each chip under different thermal coupling modes and different current equivalent power losses is simulated by finite element thermal simulation. The temperature distribution law function on the surface of each chip under different coupling modes and power losses is established through the junction temperature distribution data of each chip. The corresponding curve fitting mathematical model is shown in Table 1 and Table 2. To determine the coefficient R 2 Describing function fitting accuracy, R 2 The larger the value, the higher the fitting accuracy. It can be seen from the table that under different thermal coupling modes and boundary conditions, the quadratic function can better describe the temperature distribution law on the chip surface.

[0135] Table 1. Temperature distribution function of chip surface in multi-chip modules with different coupling modes

[0136]

[0137] Table 2. Temperature distribution function of multi-chip module chip surface under different working conditions

[0138]

[0139] S4: Determine a specific temperature distribution function based on the estimation result of the thermal network model, and calculate the junction temperature of each chip in the multi-chip module.

[0140] The flow chart for calculating the junction temperature of each chip in a multi-chip IGBT module based on the temperature distribution function is as follows: Fig.13 Specifically, through finite element analysis simulation, multiple junction temperature distribution functions of the multi-chip power module are extracted. The junction temperature at a specific node of chip 3 is estimated through the thermal network model, and then according to the coupling mode, operating parameters (ambient temperature T a , power loss P loss ) and the temperature distribution function library of chip 3, and determine the specific junction temperature distribution function by looking up the table. Then, according to the position information of chip 1 and chip 5, the junction temperature at the specific node of chip 1 and chip 5 is calculated. Repeat the same method to finally provide the junction temperature of chip 1 and chip 5.

[0141] From the above description, it can be seen that a specific application example of the present invention provides a method for determining the junction temperature of a multi-chip power module, the method comprising: determining the distribution law of the heat flux characteristics of the multi-chip IGBT module under different thermal coupling modes; establishing a thermal network model taking into account the thermal coupling effect by analyzing the mapping relationship between the heat flux distribution and the thermal model parameters; accurately calculating the junction temperature of each chip under different thermal coupling modes according to the thermal network model and the junction temperature distribution law function of the multi-chip power module; finally, verifying the proposed multi-chip junction temperature estimation method through simulation comparison and experiments. When the model accuracy performance and computational efficiency meet the requirements, it shows that the proposed method can accurately estimate the junction temperature of the multi-chip power module under different boundary conditions.

[0142] Based on the same inventive concept, the embodiments of the present application also provide a junction temperature determination device for a multi-chip power module, which can be used to implement the method described in the above embodiments, such as the following embodiments. Since the principle of solving the problem by the junction temperature determination device for a multi-chip power module is similar to that of the junction temperature determination method for a multi-chip power module, the implementation of the junction temperature determination device for a multi-chip power module can refer to the implementation of the junction temperature determination method for a multi-chip power module, and the repeated parts will not be repeated. As used below, the term "unit" or "module" can be a combination of software and / or hardware that implements a predetermined function. Although the system described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0143] The embodiment of the present invention provides a specific implementation of a device for determining the junction temperature of a multi-chip power module capable of implementing a method for determining the junction temperature of a multi-chip power module, see Fig.14 , a junction temperature determination device for a multi-chip power module specifically includes the following contents:

[0144] A heat flux distribution law determination module 10, used to determine the heat flux distribution law of the multi-chip power module under multiple thermal coupling modes;

[0145] A mapping relationship determination module 20, used to determine a mapping relationship between the heat flow distribution law and the thermal model parameters of the multi-chip power module;

[0146] A thermal network model building module 30, configured to build a thermal network model of the multi-chip power module under the multiple thermal coupling modes according to the mapping relationship;

[0147] The junction temperature determination module 40 is used to determine the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

[0148] In some embodiments of the present application, see Fig.15 , the heat flow distribution law determination module 10 includes:

[0149] A three-dimensional model building unit 10a, used to build a three-dimensional finite element model of the multi-chip power module;

[0150] A model thermal simulation unit 10b, configured to perform thermal simulation on the three-dimensional finite element model to obtain a temperature distribution cloud diagram of the multi-chip power module under the multiple thermal coupling modes;

[0151] The heat flux distribution law determining unit 10c is used to determine the heat flux distribution law according to the temperature distribution cloud diagram.

[0152] In some embodiments of the present application, see Fig.16 , a junction temperature determination device for a multi-chip power module, further comprising:

[0153] The thermal model parameter determination module 50 is used to determine the thermal model parameters of the structural layer according to the effective heat transfer area of ​​the structural layer of the multi-chip power module, the thickness, thermal conductivity, constant pressure specific heat capacity and density of each material.

[0154] In some embodiments of the present application, the thermal model parameters include self-heating parameters and coupled thermal parameters;

[0155] The self-heating parameters include: self-heating thermal resistance parameter and self-heating heat capacity parameter;

[0156] The coupled thermal parameters include: coupled thermal resistance parameters and coupled thermal melt parameters.

[0157] In some embodiments of the present application, the self-heating parameter is used to characterize the heat flow characteristics of each structural layer of the multi-chip power module;

[0158] The coupled thermal parameters are used to characterize the heat flow characteristics of the structural layer where thermal coupling occurs in the multi-chip power module.

[0159] From the above description, it can be seen that an embodiment of the present invention provides a junction temperature determination device for a multi-chip power module, including: a heat flux distribution law determination module, used to determine the heat flux distribution law of the multi-chip power module under multiple thermal coupling modes; a mapping relationship determination module, used to determine the mapping relationship between the heat flux distribution law and the thermal model parameters of the multi-chip power module; a thermal network model establishment module, used to establish a thermal network model of the multi-chip power module under multiple thermal coupling modes according to the mapping relationship; a junction temperature determination module, used to determine the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

[0160] In summary, the present invention provides a junction temperature determination device for a multi-chip power module, which can accurately estimate the junction temperature information of each chip under different thermal coupling modes by analyzing the internal heat flow characteristics and junction temperature distribution of the module.

[0161] The embodiment of the present application also provides a specific implementation of an electronic device capable of implementing all steps in the method for determining the junction temperature of a multi-chip power module in the above embodiment, see Fig.17 , electronic equipment specifically includes the following:

[0162] Processor (processor) 1201, memory (memory) 1202, communication interface (CommunicationsInterface) 1203 and bus 1204;

[0163] The processor 1201 , the memory 1202 , and the communication interface 1203 communicate with each other via the bus 1204 ; the communication interface 1203 is used to realize information transmission between relevant devices such as the server-side device, the power measurement device, and the user-side device.

[0164] The processor 1201 is used to call the computer program in the memory 1202. When the processor executes the computer program, all the steps in the method for determining the junction temperature of the multi-chip power module in the above embodiment are implemented. For example, when the processor executes the computer program, the following steps are implemented:

[0165] Step 100: determining the heat flow distribution law of the multi-chip power module under multiple thermal coupling modes;

[0166] Step 200: Determine a mapping relationship between the heat flux distribution law and the thermal model parameters of the multi-chip power module;

[0167] Step 300: Establishing a thermal network model of the multi-chip power module in the multiple thermal coupling modes according to the mapping relationship;

[0168] Step 400: Determine the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

[0169] The embodiments of the present application also provide a computer-readable storage medium capable of implementing all the steps in the method for determining the junction temperature of a multi-chip power module in the above embodiments. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, all the steps of the method for determining the junction temperature of a multi-chip power module in the above embodiments are implemented. For example, when the processor executes the computer program, the following steps are implemented:

[0170] Step 100: determining the heat flow distribution law of the multi-chip power module under multiple thermal coupling modes;

[0171] Step 200: Determine a mapping relationship between the heat flux distribution law and the thermal model parameters of the multi-chip power module;

[0172] Step 300: Establishing a thermal network model of the multi-chip power module in the multiple thermal coupling modes according to the mapping relationship;

[0173] Step 400: Determine the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

[0174] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the hardware + program embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0175] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0176] Although the present application provides method operation steps such as embodiments or flow charts, more or fewer operation steps may be included based on conventional or non-creative labor. The order of steps listed in the embodiments is only one way of executing the order of many steps and does not represent the only execution order. When the actual device or client product is executed, it can be executed in the order of the method shown in the embodiments or the drawings or in parallel (for example, in a parallel processor or multi-threaded processing environment).

[0177] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0178] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0179] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0180] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for determining the junction temperature of a multi-chip power module, characterized in that: include: Determining heat flux distribution rules of the multi-chip power module under multiple thermal coupling modes; Determining a mapping relationship between the heat flux distribution law and the thermal model parameters of the multi-chip power module; Establishing a thermal network model of the multi-chip power module under the multiple thermal coupling modes according to the mapping relationship; The junction temperature of the multi-chip power module is determined according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

2. The method for determining junction temperature according to claim 1, characterized in that: Determining the heat flux distribution law of the multi-chip power module under multiple thermal coupling modes includes: Establishing a three-dimensional finite element model of the multi-chip power module; Performing thermal simulation on the three-dimensional finite element model to obtain a temperature distribution cloud diagram of the multi-chip power module under the multiple thermal coupling modes; The heat flow distribution law is determined according to the temperature distribution cloud diagram.

3. The method for determining junction temperature according to claim 1, characterized in that: Also includes: The thermal model parameters of the structural layer are determined according to the effective heat transfer area of ​​the structural layer of the multi-chip power module, the thickness, thermal conductivity, constant-pressure specific heat capacity and density of each material.

4. The method for determining junction temperature according to claim 1, characterized in that: The thermal model parameters include self-heating parameters and coupled thermal parameters; The self-heating parameters include: self-heating thermal resistance parameter and self-heating heat capacity parameter; The coupled thermal parameters include: coupled thermal resistance parameters and coupled thermal melt parameters.

5. The method for determining junction temperature according to claim 4, characterized in that: The self-heating parameter is used to characterize the heat flow characteristics of each structural layer of the multi-chip power module; The coupled thermal parameters are used to characterize the heat flow characteristics of the structural layer where thermal coupling occurs in the multi-chip power module.

6. A junction temperature determination device for a multi-chip power module, characterized in that: include: A heat flux distribution law determination module, used to determine the heat flux distribution law of the multi-chip power module under multiple thermal coupling modes; A mapping relationship determination module, used to determine a mapping relationship between the heat flow distribution law and the thermal model parameters of the multi-chip power module; A thermal network model establishment module, used to establish a thermal network model of the multi-chip power module under the multiple thermal coupling modes according to the mapping relationship; The junction temperature determination module is used to determine the junction temperature of the multi-chip power module according to the thermal network model and a pre-established junction temperature distribution law function of the multi-chip power module.

7. The junction temperature determination device according to claim 6, characterized in that: The heat flux distribution law determination module comprises: A three-dimensional model building unit, used to build a three-dimensional finite element model of the multi-chip power module; A model thermal simulation unit, used for performing thermal simulation on the three-dimensional finite element model to obtain a temperature distribution cloud diagram of the multi-chip power module under the multiple thermal coupling modes; A heat flux distribution law determining unit is used to determine the heat flux distribution law according to the temperature distribution cloud map.

8. The junction temperature determination device according to claim 6, characterized in that: Also includes: The thermal model parameter determination module is used to determine the thermal model parameters of the structural layer according to the effective heat transfer area of ​​the structural layer of the multi-chip power module, the thickness, thermal conductivity, constant pressure specific heat capacity and density of each material.

9. The junction temperature determination device according to claim 6, characterized in that: The thermal model parameters include self-heating parameters and coupled thermal parameters; The self-heating parameters include: self-heating thermal resistance parameter and self-heating heat capacity parameter; The coupled thermal parameters include: coupled thermal resistance parameters and coupled thermal melt parameters.

10. The junction temperature determination device according to claim 9, characterized in that: The self-heating parameter is used to characterize the heat flow characteristics of each structural layer of the multi-chip power module; The coupled thermal parameters are used to characterize the heat flow characteristics of the structural layer where thermal coupling occurs in the multi-chip power module.

11. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the method for determining the junction temperature of a multi-chip power module according to any one of claims 1 to 5 are implemented.

12. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the method for determining the junction temperature of a multi-chip power module according to any one of claims 1 to 5 are implemented.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for determining the junction temperature of a multi-chip power module according to any one of claims 1 to 5 are implemented.

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