A method and apparatus for testing and analyzing the maximum surge current of SiC MOSFETs based on three-terminal resistance monitoring.

Abstract

This invention discloses a method and apparatus for testing and analyzing the maximum surge current of SiC MOSFETs based on three-terminal resistance monitoring. By applying a stepped surge current and combining it with online monitoring of the three-terminal resistance, the performance changes of the device under extreme stress can be rapidly evaluated, thereby determining its maximum single surge current withstand capability and failure mode. Specific steps include applying an appropriate gate bias voltage to the SiC MOSFET under test and setting the parameters of the surge current generation circuit. After applying a stepped single surge current, the static resistance values ​​of the gate-source, drain-source, and gate-drain terminals are measured and recorded. By monitoring the changes in resistance values, the magnitude of the maximum single surge current is determined, and the failure mode of the device is identified, clarifying modes such as open circuit, short circuit, leakage, and burnout. This method is not only simple to operate and low in cost, but also provides rapid reliability information for SiC MOSFETs without the need for high-precision instruments.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor reliability testing, specifically relating to a method and apparatus for testing and analyzing the maximum surge current of SiCMOSFET based on three-terminal resistance monitoring. Background Technology

[0002] SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors) are widely used in high-power and high-frequency electronic devices due to their excellent electrical and thermal characteristics. However, in practical applications, SiC MOSFETs face transient stresses such as inrush currents, which can significantly impact device reliability. Inrush currents are typically caused by factors such as transient overloads or power supply fluctuations, potentially leading to physical damage to internal materials and changes in electrical characteristics.

[0003] After surge stress is applied, the static electrical characteristics of SiC MOSFETs, particularly their three-terminal static resistance, may change. This is because surge stress causes microstructural changes within the device, including defect formation and material aging, which in turn affect the conduction path. Measuring the three-terminal static resistance provides crucial information about whether the device has failed or experienced performance degradation after a surge.

[0004] Many methods focus on measuring changes in electrical characteristics, including key parameters such as leakage current, threshold voltage, and on-resistance, after the application of surge current stress. These electrical characteristics reflect the performance degradation of devices under extreme conditions. Some existing methods determine the maximum single surge current using high-precision instruments such as semiconductor parameter analyzers and oscilloscopes. While accurate, these methods are typically costly, time-consuming, and unsuitable for rapid evaluation.

[0005] After a SiC MOSFET experiences surge failure, its failure mode and mechanism are typically determined through a series of analytical methods, including acoustic scanning, X-ray diffraction, open-packing, and SEM. While accurate failure localization is possible, these methods require high-end analytical instruments, resulting in high costs and time consumption. However, by analyzing changes in the static three-terminal resistance, it is possible to quickly determine failure modes such as open circuit, short circuit, burn-out, and leakage current failure, thereby indicating failure mechanisms such as material defects, structural damage, or poor contact. Currently, there is limited research on surge current testing and degradation analysis of devices based on three-terminal static resistance measurements. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention aims to rapidly analyze the performance changes of SiC MOSFETs under extreme stress by applying stepped single surge current stress combined with three-terminal static resistance measurement, thereby providing a basis for determining the cause of failure.

[0007] The technical solution adopted in this invention is specifically described as follows:

[0008] A failure analysis method for SiC MOSFET based on three-terminal resistance monitoring, characterized in that the three-terminal resistance is the gate-source resistance, drain-source resistance, and gate-drain resistance of the SiC MOSFET.

[0009] The method includes:

[0010] S1. Apply a gate bias voltage to the SiC MOSFET to keep the channel of the device in the off state;

[0011] S2. Apply a surge current to the SiC MOSFET in a single step from the source to the drain. After each application, measure and record the three-terminal resistance of the SiC MOSFET (including Rgs, Rsg, Rgd, Rdg, Rds, Rsd). The surge current increases by 5-10A each time.

[0012] S3. When one or more of the three-terminal resistors of the SiC MOSFET drop below kilohms after a surge current is applied, the SiC MOSFET is determined to be in a failed state, and the surge current is stopped.

[0013] S4. If the SiC MOSFET is determined to be in a failed state, the cause of failure of the SiC MOSFET is determined based on the changes in the gate-source resistance, drain-source resistance and gate-drain resistance. The cause of failure is at least one of the following: gate-source short circuit, drain-source short circuit and mutual short circuit between the three terminals of the gate, drain and source.

[0014] When the gate-source resistance drops below kilohms and the gate-drain resistance and drain-source resistance are greater than 100 megohms, the cause of failure is determined to be a short circuit between the gate and source.

[0015] When the drain-source resistance drops below kilohms and the gate-drain resistance and gate-source resistance are greater than 100 megohms, the cause of failure is determined to be a short circuit between the drain and source.

[0016] When the gate-source resistance, drain-source resistance, and gate-drain resistance all drop below 1,000 ohms, the cause of failure is determined to be a short circuit between each pair of the three terminals of the gate, drain, and source.

[0017] Preferably, the cause of the gate-source short circuit is at least one of the following: gate oxide layer damage, gate charge trapping, increased leakage current, local thermal effect, and leakage caused by material defects;

[0018] The cause of the short circuit between the drain and source is at least one of the following: damage to the body diode, metal migration, thermal stress, increased leakage current, and accumulation of defects in the drift layer.

[0019] The reason for the short circuit between the three terminals of the gate, drain, and source is at least one of the following: overheating of the device causing the gate aluminum metal to burn out or the gate oxide layer to break down.

[0020] Preferably, in S1, the static resistance of all three terminals of the SiC MOSFET is in the range of hundreds of megohms; the gate bias voltage is -10V to 0V, so that the channel of the SiC MOSFET is in the off state.

[0021] Preferably, in S2, the surge current pulse width is 1 to 10 ms and the duty cycle is less than one-thousandth.

[0022] A method for testing the maximum surge current of a SiC MOSFET based on three-terminal resistance monitoring is characterized in that, according to the method described herein, failure analysis is performed, and after the SiC MOSFET is in a failed state, the intensity of the last surge current applied before the failure is determined to be the maximum surge current of the SiC MOSFET.

[0023] A SiC MOSFET maximum surge current testing and failure analysis circuit based on three-terminal resistance monitoring is characterized by comprising a capacitor charging circuit, a surge current circuit, a driving circuit, and a three-terminal resistance detection unit; the capacitor is connected to the capacitor charging circuit and the surge current circuit via a single-pole double-throw switch.

[0024] The capacitor charging circuit also includes a first voltage source and a resistor; the surge current circuit also includes an inductor connected to the source and drain of the SiC MOSFET.

[0025] Preferably, after the capacitor is charged in the capacitor charging circuit through the first voltage source, the capacitor charging circuit is disconnected and the surge current circuit is closed through a single-pole double-throw switch, so that the capacitor and inductor form a sinusoidal oscillation circuit to generate surge current from the source to the drain of the SiCMOSFET, and the surge current intensity is controlled by controlling the voltage of the first voltage source.

[0026] Preferably, the driving circuit includes a second voltage source and a first switch, and the source of the SiC MOSFET is connected to the gate of the SiC MOSFET in sequence via the first switch and the second voltage source.

[0027] Preferably, the three-terminal resistance detection unit is connected to the SiC MOSFET via a second switch and is used to detect the gate-source resistance, drain-source resistance, and gate-drain resistance of the SiC MOSFET.

[0028] A device for testing and analyzing the maximum surge current of a SiC MOSFET based on three-terminal resistance monitoring, characterized in that it includes the circuit described in this invention.

[0029] The main advantage of this invention lies in its ability to effectively determine the maximum single-surge current and failure mode of SiC MOSFETs by analyzing the change in the static resistance of the device's three terminals during a stepped single-surge current test. This method only requires the design and integration of a resistance detection function, avoiding the use of electronic testing instruments such as parameter analyzers and oscilloscopes, thus significantly reducing initial workload. The required equipment is also relatively simple and low-cost. Furthermore, this invention contributes to a deeper understanding of the device's failure mechanism, providing crucial support and supplementation for the reliability research of SiC MOSFETs. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This invention relates to a circuit for testing and analyzing the maximum surge current of a SiC MOSFET based on three-terminal resistance monitoring.

[0032] Wherein, V - first voltage source; R1 - resistor; S - single-pole double-throw switch; C - capacitor; L - inductor; V1 - first voltage source; S1 - first switch; S2 - second switch. Detailed Implementation

[0033] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0035] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0036] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0038] Example 1

[0039] In this embodiment, the test sample (DUT) selected is a commercial 1200V SiC MOSFET manufactured by manufacturers A, B, C, and D.

[0040] First, the three-terminal resistance of the device under test was measured. The measurement results showed that the resistance values ​​of all the devices under test were in the range of hundreds of megohms, indicating that the devices were in good condition before stress was applied.

[0041] Then, the initial surge current was set according to the rated current specified in the product specifications. A 10ms pulse width sine wave was generated based on the LC oscillation principle, with one impact cycle to ensure that only one surge current was applied each time. The duty cycle was set to less than one-thousandth. Next, the single surge current intensity was gradually increased by 10A, and the three-terminal resistance of the DUT was measured after each application of single surge current stress, and the change in resistance value was recorded. If the resistance value remained in the hundreds of megohms after applying single surge current stress, this test process continued until a decrease in resistance value was observed, at which point the device was considered to have failed.

[0042] like Figure 1 As shown, the test circuit includes a capacitor charging circuit, a surge current circuit, a drive circuit, and a three-terminal resistor detection unit. Figure 1As can be seen, the main components include a first voltage source V, a resistor R1, a capacitor C, a single-pole double-throw switch S, an inductor L, a second voltage source V1, a first switch S1, a second switch S2, a device under test (DUT), and a resistance detection unit. During charging, the first voltage source V charges the capacitor C through the resistor R1, and the left side of switch S is closed while the right side remains open. The second voltage source V1 and switch S1 are used to provide a bias voltage to the gate of the DUT, thereby testing the device's response to a single surge current under a fixed gate bias voltage. The gate voltage is set according to the actual operating conditions of the DUT; in this embodiment, it is set to -10V. When the capacitor C is fully charged, switch S1 is closed, S2 is open, and the right side of switch S is closed. The charge in the capacitor is released to the DUT SiCMOSFET through the inductor L, forming a single transient surge current. Switch S is thrown to the right and closed, causing the capacitor to discharge rapidly. The resulting high-amplitude single surge current flows through the inductor L and the DUT. The inductor L can adjust the rate of current rise to simulate sudden stress conditions in actual operation.

[0043] After the single surge current is applied and the capacitor discharges, switches S and S1 are disconnected, and switch S2 is closed. The three-terminal resistance detection unit measures the resistance values ​​of the gate-source, gate-drain, and drain-source terminals. Specifically, the three-terminal resistance detection unit applies a known small current to the gate-source, gate-drain, and drain-source terminals respectively, and calculates the values ​​of the three-terminal resistances Rgs, Rsg, Rgd, Rdg, Rds, and Rsd by measuring the voltage drop. These measurement data are used to analyze the change in resistance of the DUT before and after experiencing a single surge current.

[0044] The surge current intensity of the last applied surge current before the failure of DUT A, DUT B, DUT C, and DUT D was recorded as the maximum single surge current. The three-terminal resistance measured after the device failure was also recorded. The data results are shown in Table 1.

[0045] Table 1 Three-terminal resistance of failed components

[0046]

[0047] By comparing the change in the three-terminal resistance of the DUT after withstanding a single-step surge current, the maximum single-surge current of the DUT can be determined first, and at the same time, the degradation or failure mode of the SiC MOSFET can be effectively judged. Within 10 ms after applying the single-surge current, the direction of the single-surge current is from the source (S) of the DUT to the drain (D). After applying the single-surge current, through the three-terminal resistance detection module, the resistance values of the drain-source terminals (Rds, Rsd) can be measured to be in the order of one hundred thousand ohms to one megohm, and Rsd < Rds, it can be judged that there is a leakage channel between the two detected terminals, but the DUT still has a certain blocking ability and the DUT is not completely失效; when the resistance values of Rsd and Rds decrease below the order of ten thousand ohms, and the difference or equality between the resistance values of Rsd and Rds is very small, it is a short-circuit mode between the drain and source, the leakage increases rapidly, the DUT loses the blocking ability, and it is determined that the damage between the source and drain causes failure.

[0048] After the DUT fails, only the resistance values of the gate-source terminals (Rgs, Rsg) are detected to be less than one thousand ohms, and when the difference or equality between the resistance values of Rgs and Rsg is very small, it is a short-circuit mode between the gate and source, indicating that the gate oxide layer is damaged or there is a problem of source metal melting; when the resistance values of the three terminals of the gate-source-drain are all detected to be less than one thousand ohms and the three terminals of the gate-source-drain are in a short-circuit mode showing resistance failure, it can be judged that under the maximum surge current stress, the DUT overheats and burns inside, resulting in transient failure.

[0049] As can be seen from Table 1, when the gate bias is -10V, after each of DUT A, DUT B, DUT C, and DUT D withstands a single-surge current that increases step by step by 10A, the maximum single-surge currents of DUT A, DUT B, DUT C, and DUT D are determined to be 140A, 110A, 160A, and 110A respectively.

[0050] As can be seen from Table 1, after DUT A withstands the maximum single-surge current of 140A, both Rgs and Rsg are 1.6Ω, while the resistance values between the drain-source and gate-drain are very large, and the resistance between the gate and source is significantly reduced. It is judged that the failure reason is a short circuit between the gate and source, the insulating layer is damaged, and the insulation state has been affected; the resistance values between the three terminals of DUT B and DUT C are severely reduced and both drop below one thousand ohms, indicating that all three terminals are in a short-circuit state. It is judged judged that the failure reason is a short circuit between the three terminals of the gate-drain-source pairwise; the resistance values of Rds and Rsd of DUTD are both less than the order of one thousand ohms, and the short circuit between the drain and source has lost the blocking ability, while the resistance values between the gate-drain and gate-source are still in the order of one hundred megohms. It is judged that the failure reason is a short circuit between the drain and source.

[0051] As shown in Table 1, DUT A, DUT B, and DUT C all exhibit significantly reduced gate-source resistances, indicating that the thermal effect and electric field strength generated by the single-step surge current damaged the gate oxide layer. The reduced Rds and Rsd resistances of DUT B and DUT C indicate severe damage to the body diode, possibly caused by metal migration, thermal stress, or material defects. The reduced Rgd and Rdg resistances of DUT B and DUT C indicate that the insulation between the gate and drain is affected, possibly due to breakdown of the gate oxide layer or material defects between the gate and drain. For DUT D, the Rds and Rsd resistances both decrease to below the kiloohm level, and Rsd≈Rds, while the other resistances are very large, indicating that there is a conduction path between the drain and source, possibly due to the damage to the internal PN junction caused by the single-step surge current, leading to the failure of the device's body diode.

[0052] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for failure analysis of SiC MOSFETs based on three-terminal resistance monitoring, characterized in that, The three-terminal resistors are the gate-source resistance, drain-source resistance, and gate-drain resistance of the SiC MOSFET; The method includes: S1. Apply a gate bias voltage to the SiC MOSFET to keep the channel of the device in the off state; S2. Apply a surge current to the SiC MOSFET in a single step from the source to the drain. After each application, measure and record the three-terminal resistance of the SiC MOSFET. The surge current increases by 5-10A each time. S3. When one or more of the three-terminal resistors of the SiC MOSFET drop below kiloohms after a surge current is applied, the SiC MOSFET is determined to be in a failed state, and the surge current is stopped. S4. If the SiC MOSFET is determined to be in a failed state, the cause of failure of the SiC MOSFET is determined based on the changes in the gate-source resistance, drain-source resistance and gate-drain resistance. The cause of failure is at least one of the following: gate-source short circuit, drain-source short circuit and mutual short circuit between the three terminals of the gate, drain and source. When the gate-source resistance drops below kilohms and the gate-drain resistance and drain-source resistance are greater than 100 megohms, the cause of failure is determined to be a short circuit between the gate and source. When the drain-source resistance drops below kiloohms and the gate-drain resistance and gate-source resistance are greater than 100 megohms, the cause of failure is determined to be a short circuit between the drain and source. When the gate-source resistance, drain-source resistance, and gate-drain resistance all drop below 1,000 ohms, the cause of failure is determined to be a short circuit between each pair of the three terminals of the gate, drain, and source.

2. The SiC MOSFET failure analysis method based on three-terminal resistance monitoring according to claim 1, characterized in that, The cause of the gate-source short circuit is at least one of the following: gate oxide layer damage, gate charge trapping, increased leakage current, local thermal effect, and leakage caused by material defects. The cause of the drain-source short circuit is at least one of the following: damage to the body diode, metal migration, thermal stress, increased leakage current, and accumulation of drift layer defects. The reason for the short circuit between the three terminals of the gate, drain, and source is at least one of the following: overheating of the device causing the gate aluminum metal to burn out or the gate oxide layer to break down.

3. The SiC MOSFET failure analysis method based on three-terminal resistance monitoring according to claim 2, characterized in that, In S1, the static resistance of the three terminals of the SiC MOSFET is in the range of hundreds of megohms; the gate bias voltage is -10V to 0V, which keeps the channel of the SiC MOSFET in the off state.

4. The SiC MOSFET failure analysis method based on three-terminal resistance monitoring according to claim 3, characterized in that, In S2, the surge current pulse width is 1~10ms and the duty cycle is less than one-thousandth.

5. A method for testing the maximum surge current of a SiC MOSFET based on three-terminal resistance monitoring, characterized in that, Failure analysis is performed according to any one of claims 1-4. After the SiC MOSFET is in a failed state, the intensity of the last surge current applied before the failure is determined to be the maximum surge current of the SiC MOSFET.

6. A circuit for use in the SiC MOSFET failure analysis method based on three-terminal resistance monitoring as described in any one of claims 1-4, characterized in that, It includes a capacitor charging circuit, a surge current circuit, a drive circuit, and a three-terminal resistor detection unit; the capacitor is connected to a single-pole double-throw switch to form the capacitor charging circuit and the surge current circuit respectively; The capacitor charging circuit also includes a first voltage source and a resistor; the surge current circuit also includes an inductor connected to the source and drain of the SiC MOSFET.

7. The circuit according to claim 6, characterized in that, In the capacitor charging circuit, after the capacitor is charged by the first voltage source, the capacitor charging circuit is disconnected by a single-pole double-throw switch and the surge current circuit is closed, so that the capacitor and inductor form a sinusoidal oscillation circuit to generate surge current from the source to the drain of the SiC MOSFET. The surge current intensity is controlled by controlling the voltage of the first voltage source.

8. The circuit according to claim 7, characterized in that, The driving circuit includes a second voltage source and a first switch. The source of the SiC MOSFET is connected to the gate of the SiC MOSFET after passing through the first switch and the second voltage source in sequence.

9. The circuit according to claim 8, characterized in that, The three-terminal resistance detection unit is connected to the SiC MOSFET via a second switch and is used to detect the gate-source resistance, drain-source resistance, and gate-drain resistance of the SiC MOSFET.

10. A device for testing and analyzing the maximum surge current of SiC MOSFETs based on three-terminal resistance monitoring, characterized in that, Includes the circuit as described in any one of claims 6-9.

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