Failure test circuit and method
By introducing a protection module into the failure test circuit, the problem of fragile devices being prone to secondary breakdown under high voltage and current testing conditions is solved, and the testing efficiency and accuracy are improved while protecting the devices to be tested.
Patent Information
- Application Number
- CN202510020127.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-06
- Publication Date
- 2025-03-14
AI Technical Summary
In semiconductor failure analysis, fragile devices are prone to secondary breakdown under high voltage and current testing conditions, resulting in changes in the morphology of the failure position, which in turn affects the accuracy and efficiency of the test.
Design a failure test circuit, including the device to be tested and the protection module. When the device to be tested undergoes secondary breakdown, the protection module reduces the current flowing through the device to be tested by increasing the resistance value or disconnecting the circuit, thereby protecting the morphology of the failed position.
On the premise of protecting the device to be tested, it can speed up the increase step length of voltage or current, improve the testing efficiency, and at the same time, it can react quickly when the secondary breakdown occurs, protect the morphology of the failed position, and ensure the accuracy and efficiency of the test.
Smart Images
Figure CN119619786A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of failure analysis, and in particular to a failure testing circuit and method. Background Art
[0002] In the field of semiconductor failure analysis, EMMI (Emission Microscopy), OBIRCH (Optical Beam Induce Resistance Change) and TRM (Thermal Radiation Microscopy) are commonly used tools for locating chip defects. Among them, EMMI locates defects by detecting photons generated by the recombination of electron-hole pairs; OBIRCH locates defects by detecting abnormal changes in resistance caused by laser beams; TRM locates defects by detecting thermal radiation at abnormal heating locations. Although the principles are different, all three positioning methods require a certain voltage or current to be applied to the device under test, and the applied voltage or current generally exceeds the conditions given by WAT (Wafer Acceptance Test), CP (Circuit Probing or Chip Probing) or FT (Final Test).
[0003] For EMMI, the intensity of the detected optical signal is positively correlated with the number of electron-hole pairs. When other conditions remain unchanged, that is, when the probability of electron-hole pairs recombination remains unchanged, increasing the current can increase the total amount of electron-hole pairs recombination; therefore, in order to make the optical signal intensity greater than the minimum resolution of the detector, within the tolerable range of the device under test, the greater the current applied to the device under test, the easier the signal is to detect, thereby reducing the integration time required for the test and improving efficiency. Similar to EMMI, Thermal has certain requirements for the power applied to the device under test. According to the formula Joule's law and Planck's blackbody radiation formula, the greater the power, the stronger the thermal signal. For OBIRCH, what is detected is the abnormal resistance change behavior generated under the condition of laser heating. Therefore, the premise that OBIRCH can be used for positioning is: when the external conditions remain unchanged, if the applied voltage is constant, the current passing through the device under test is stable. In some IGSS / ICES failed devices, the current is not stable within the voltage range with small leakage, so we need to choose a voltage condition with relatively large and stable current. In addition, under the condition of the same laser energy, the change of resistance should also be the same. According to Ohm's law, the corresponding current change is larger and easier to be detected by the source meter in the voltage supply mode, so the larger the voltage, the stronger the signal.
[0004] In short, within the range that the device to be tested can withstand, it is easier to get a signal under the test conditions of a larger voltage and current. However, for some fragile samples, it is easier to be broken down again under the conditions of a larger voltage and current, which destroys the original morphology and makes it impossible to find the root cause of the failure; therefore, for the analysis of fragile devices, it is necessary to start from a lower voltage and current, gradually increase the voltage and current, and lengthen the integration time for each test, so a trade-off needs to be made between efficiency and accuracy.
[0005] How to improve the efficiency of failure testing, ensure accuracy, and reduce chip cycle time in a simple way without affecting the failure location morphology has become one of the urgent problems to be solved by technical personnel in this field.
[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention
[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a failure test circuit and method for solving the problems in the prior art that failure analysis of fragile devices is difficult to balance efficiency and accuracy and is prone to burning the failure position morphology.
[0008] To achieve the above-mentioned object and other related objects, the present invention provides a failure test circuit, the failure test circuit at least comprising:
[0009] The device under test and the protection module are connected in series;
[0010] Wherein, when the device under test has a secondary breakdown, the protection module is used to reduce the influence of the thermal effect of the current on the device under test, so as to protect the morphology of the failure position.
[0011] Specifically, the protection module includes a first protection unit, and the first protection unit increases the resistance value and the voltage across both ends when the device under test has a secondary breakdown, so as to reduce the current flowing through the device under test.
[0012] More specifically, the first protection unit includes a resistive switching device, and the resistance value of the resistive switching device increases with the increase of voltage within the maximum withstand voltage range.
[0013] More specifically, the material of the resistive switching device includes LiTaO3, NiO, TiO2, HfO2, Cu x At least one of O, ZnO, LiNbO3, and SrTiO3.
[0014] More specifically, the protection module includes a second protection unit, and the second protection unit disconnects the path where the device under test is located when the device under test has a secondary breakdown.
[0015] More specifically, the second protection unit includes a switch tube, a switch control module and a reset module; the switch tube is connected in series on the high-voltage side of the device under test; the switch control module detects the voltage across the switch tube and generates a switch control signal for the switch tube, and controls the switch tube to disconnect when a secondary breakdown occurs in the device under test; the reset module is connected to the control end of the switch tube to provide a reset signal for the switch tube.
[0016] More specifically, the switch tube is an NMOS tube.
[0017] More specifically, the switch control module is an AND logic circuit.
[0018] In order to achieve the above-mentioned purpose and other related purposes, the present invention also provides a failure test method, which is implemented based on the above-mentioned failure test circuit.
[0019] Optionally, the failure test method locates the defect by detecting photons generated by electron-hole pair recombination, by detecting abnormal resistance changes caused by laser beams, or by detecting thermal radiation from abnormal heating locations.
[0020] As described above, the failure test circuit and method of the present invention have the following beneficial effects:
[0021] The failure test circuit and method of the present invention solve the problem that some relatively fragile samples are prone to secondary breakdown under high voltage and current test conditions, resulting in changes in the morphology of the failure position. Compared with the method of slowly increasing the voltage or current, the protection module proposed in the present invention can make the step size of increasing the voltage or current larger, and can reach the voltage and current conditions required for the test more quickly while protecting the device under test. At the same time, it can react more quickly to disconnect the circuit after the secondary breakdown occurs, taking into account both efficiency and accuracy, and realizing the protection of the failure position morphology. The protection module proposed in the present invention is simple and easy to operate, and can reduce the cycle time to a certain extent and improve output. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Shown is a structural schematic diagram of the failure test circuit of the present invention.
[0023] Figure 2 Shown is a schematic diagram of the voltage-resistance curve of LiTaO3 material.
[0024] Figure 3Another structural schematic diagram of the failure test circuit of the present invention is shown.
[0025] Figure 4 Shown is another structural schematic diagram of the failure test circuit of the present invention.
[0026] Component number description
[0027] 1 Failure test circuit
[0028] 11 Device under test
[0029] 12 Protection module
[0030] 121 First Protection Unit
[0031] 122 Second protection unit
[0032] 12a Switch Control Module
[0033] 12b Reset module DETAILED DESCRIPTION
[0034] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0035] See also Figure 1 to Figure 4 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0036] In order to solve the above problem, the present invention provides a failure test circuit, which includes:
[0037] A device under test and a protection module connected in series; wherein, when the device under test has a secondary breakdown, the protection module is used to reduce the influence of the thermal effect of the current on the device under test to protect the morphology of the failure position.
[0038] Specifically, if secondary breakdown occurs during the failure location test, the resistance of the device to be tested will decrease significantly. When the voltage is limited to the current, the voltage at both ends of the device will drop significantly, and the current will increase significantly. The large current will cause a large amount of heat at the failure location, which will cause the material at the failure location to melt and change its morphology, ultimately making it impossible to find the root cause of the failure. When the voltage is limited to the current, if the current limit is not reached, the current will reach the current limit first, and then the voltage at both ends of the device will drop significantly again. At this time, the current will also destroy the original morphology of the failure location to a certain extent.
[0039] The protection module of the present invention can sense the occurrence of secondary breakdown and reduce the current flowing through the device under test when secondary breakdown occurs, thereby preventing the failure position from being deformed under the influence of the thermal effect of the current.
[0040] It should be noted that the "reduction" mentioned in the present invention includes reducing the current value to a non-zero value on the original basis, and also includes reducing the current to zero on the original basis. The degree of reduction is set according to actual needs, and the effect of protecting the failure position morphology can be achieved. Any circuit structure that can achieve the above functions is applicable to the present invention, and the present invention is described below based on specific examples.
[0041] Embodiment 1
[0042] like Figure 1 As shown, this embodiment provides a failure test circuit 1, including a device under test 11 and a protection module 12, which is suitable for constant voltage test conditions. When a secondary breakdown occurs in the device under test 11, the protection module 12 protects the failure position morphology by reducing the current flowing through the device under test 11 to within a safe range.
[0043] like Figure 1 As shown, the device under test 11 and the protection module 12 are connected in series; the protection module 12 includes a first protection unit 121, which increases the resistance and the voltage at both ends when the device under test 11 has a secondary breakdown, so as to reduce the current flowing through the device under test 11, avoid the thermal effect caused by the large current from burning the morphology of the failure position, and thus ensure the exploration of the cause of the failure.
[0044] Specifically, as an example, the first protection unit 121 includes a resistive switching device, which is made of a resistive switching material. In this example, LiTaO3 is selected to form the resistive switching device. Figure 2 The voltage resistance curve of LiTaO3 material is shown in FIG. 1 . When the voltage increases from 0V to 3V, the resistance increases by four orders of magnitude. When the resistive switching device composed of LiTaO3 is actually used, the bias voltage should be controlled not to exceed 3V to prevent the resistive switching device from breaking down and losing the function of protecting the device under test 11. The resistive switching material can also be set as a transition metal oxide with resistive switching properties, including but not limited to NiO, TiO2, HfO2, Cux O, ZnO, LiNbO3, SrTiO3, any material whose resistance increases with the increase of voltage within the maximum withstand voltage range is applicable to this embodiment, and will not be described one by one here. Different resistive materials have different resistance transition voltages and maximum withstand voltages. Under different constant voltage test conditions, the corresponding resistive material should be selected to protect the device to be tested. In general, the larger the bias voltage of the expected test, the resistive material with a higher transition voltage should be selected to form the resistive device; the smaller the bias voltage, the resistive material with a smaller transition voltage should be selected to form the resistive device.
[0045] Specifically, Figure 1 As shown, under the condition of constant voltage V, when the current flowing through the device under test 11 does not reach the limit current, the resistance value of the device under test 11 is recorded as R 11_a , the resistance value of the resistive switching device is recorded as R 121_a , the voltage across the device under test 11 is recorded as V 11_a , satisfying: V 11_a =V·R 11_a / (R 11_a +R 121_a ), the voltage across the resistive switching device is recorded as V 121_a At the moment of secondary breakdown, the resistance of the device under test 11 decreases significantly, which is recorded as R 11_b , R 11_b <<R 11_a , the resistance value of the resistive switching device has not changed yet. At this time, the voltage across the device under test 11 is recorded as V 11_b , significantly reduced, satisfying: V 11_b =V·R 11_b / (R 11_b +R 121_a ), then, the voltage across the resistive switching device becomes significantly larger, recorded as V'2. According to the curve of the resistance of the resistive switching material changing with voltage, it can be seen that when the voltage increases, the resistance increases, which can be increased from ~10 2 Ω increases to ~10 6 Ω, that is, the resistance value of the resistive switching device after the secondary breakdown occurs is recorded as R 121_b , R 121_b >>R 121_a Therefore, the increase in the resistance value of the resistive switching device can further reduce the voltage across the device under test 11; at the same time, it can also limit the current size under the same voltage V, thereby achieving the effect of protecting the device.
[0046] Embodiment 2
[0047] like Figure 3As shown, this embodiment provides a failure test circuit 1, including a device under test 11 and a protection module 12, which is suitable for constant current test conditions. When the device under test 11 has a secondary breakdown, the protection module 12 protects the failure position morphology by disconnecting the path where the device under test 11 is located.
[0048] like Figure 3 As shown, the device under test 11 and the protection module 12 are connected in series; the protection module 12 includes a second protection unit 122, which detects the voltage on the path where the device under test 11 is located, determines whether a secondary breakdown occurs based on the detection result, and controls the path where the device under test 11 is located to be turned on or off.
[0049] Specifically, as an example, the second protection unit 122 includes a switch tube ST, a switch control module 12a and a reset module 12b.
[0050] Among them, the switch tube ST is connected in series with the device under test 11. In this embodiment, the switch tube ST is connected in series with the high-voltage side of the device under test 11. In actual use, the switch tube ST can be connected in series with any position of the path where the device under test 11 is located as needed, as long as the on-off control of the path where the device under test 11 is located can be realized. In this example, the switch tube ST is realized by an NMOS tube, that is, the current is input from the drain D of the switch tube ST, the source S of the switch tube ST is connected to the device under test 11, and the gate G is used as the switch control terminal; any device that can realize the switch function based on the control signal is applicable, including but not limited to PMOS tubes, NPN transistors, and PNP transistors, which are not described one by one here.
[0051] The switch control module 12a detects the voltage across the switch tube ST and generates a switch control signal for the switch tube ST, and controls the switch tube ST to be disconnected when the device under test 11 has a secondary breakdown. In this example, the switch control module 12a is implemented by an AND logic circuit, wherein the first input terminal is connected to one end of the switch tube ST (the drain of the NMOS tube), the second input terminal is connected to the other end of the switch tube ST (the source of the NMOS tube), and the output terminal is connected to the control end of the switch tube ST (the gate of the NMOS tube); in this embodiment, the AND logic circuit includes three PMOS tubes and three NMOS tubes, wherein the first PMOS tube MP1, the second PMOS tube MP2, the first NMOS tube MN1 and the second NMOS tube MN2 form a NAND gate structure, the third PMOS tube MP3 and the third NMOS tube MN3 form an inverter structure, and then the AND logic is formed by the cascade connection of the NAND gate and the inverter. In actual use, any circuit structure that can detect the occurrence of secondary breakdown and generate a shutdown signal of the switch tube ST when the device under test 11 has a secondary breakdown is applicable to the present invention, and is not limited to this embodiment.
[0052] The reset module 12b is connected to the control end of the switch tube ST and provides a reset signal for the switch tube ST. In this embodiment, the reset module 12b is implemented by a switch, one end of the switch is connected to the power supply voltage VDD, and the other end is connected to the control end of the switch tube ST, and the control end receives the reset control signal Reset. In actual use, any circuit structure that can reset the switch tube ST is applicable to the present invention, and is not limited to this embodiment.
[0053] Specifically, Figure 3 As shown, in the initial stage, the reset control signal Reset controls the reset module 12b to be turned on, and the control end of the switch tube ST is connected to the power supply voltage VDD (the reset signal is at a high level), so that the switch tube ST is in a conducting state; and a constant current I is applied to the failure test circuit 1, so that the voltage across the device under test 11 reaches the high level signal of the switch control module 12a, and the resistance value of the device under test 11 is recorded as R 11_c The voltage across the two ends is V 11_c , satisfying: V 11_c =I·R 11_c When the source voltage of the switch tube ST (i.e., the voltage V across the device under test 11) 11_c ) reaches a high level, the drain voltage of the switch tube ST is also a high level, and the two high levels are ANDed by the logic, and the switch control module 12a outputs a high level signal; at this time, the reset module 12b is disconnected (no reset signal is provided), and the switch tube ST is controlled by the switch control signal (high level) output by the switch control module 12a, and the switch tube ST maintains a stable on state.
[0054] After the secondary breakdown occurs, the resistance of the device under test 11 decreases significantly, which is recorded as R 11_d , R 11_d <<R 11_c , the voltage across the device under test 11 also drops significantly, recorded as V 11_d , V 11_d =I·R 11_d That is, the drain voltage and source voltage of the switch tube ST are significantly reduced. After the two low levels are ANDed by logic calculation, the switch control module 12a outputs a low-level signal. The switch tube ST is in a cut-off state under the control of the low level, achieving the purpose of disconnecting the path where the device under test 11 is located. After the path where the device under test 11 is located is disconnected, the drain voltage of the switch tube ST jumps to a high level, and the source voltage remains at a low level. The switch control module 12a still outputs a low-level signal, the switch tube ST still works in a cut-off state, and the failure test circuit 1 is stable in a disconnected state.
[0055] Embodiment 3
[0056] like Figure 4As shown, this embodiment provides a failure test circuit 1, including a device under test 11 and a protection module 12, which is suitable for constant voltage and constant current test conditions. At this time, the protection module 12 includes a first protection unit 121 and a second protection unit 122. The specific structure and principle refer to the first and second embodiments, which will not be repeated here.
[0057] Embodiment 4
[0058] This embodiment provides a failure test method, which is implemented based on the failure test circuit 1 of the first embodiment, the second embodiment or the third embodiment.
[0059] Specifically, as an example, the failure test method locates defects based on EMMI by detecting photons generated by electron-hole pair recombination, or locates defects based on OBIRCH by detecting abnormal changes in resistance caused by laser beams, or locates defects based on TRM by detecting thermal radiation at abnormal heating locations. In actual use, any method of implementing testing by applying current or voltage across the device under test is applicable to the present invention, and will not be described in detail here.
[0060] Specifically, in the process of increasing the current or voltage applied to both ends of the device under test, the present invention can increase the step length, and even if the current or voltage is too large, the protection of the failure position morphology can be achieved based on the protection module.
[0061] In summary, the present invention provides a failure test circuit and method, wherein the failure test circuit includes: a device to be tested and a protection module connected in series; wherein, when a secondary breakdown occurs in the device to be tested, the protection module is used to reduce the influence of the thermal effect of the current on the device to be tested, so as to protect the morphology of the failure position. The present invention can make the step size of increasing the voltage or current larger, and can reach the voltage and current conditions required for the test more quickly under the premise of protecting the device to be tested. At the same time, after the secondary breakdown occurs, it can react more quickly to disconnect the circuit, taking into account both efficiency and accuracy, and realizing the protection of the morphology of the failure position. It is simple and easy to operate, and can reduce the cycle time to a certain extent, thereby improving the output. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0062] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A failure test circuit, characterized in that: The failure test circuit at least comprises: The device under test and the protection module are connected in series; Wherein, when the device under test has a secondary breakdown, the protection module is used to reduce the influence of the thermal effect of the current on the device under test, so as to protect the morphology of the failure position.
2. The failure test circuit according to claim 1, characterized in that: The protection module includes a first protection unit, and the first protection unit increases the resistance value and the voltage across both ends when the device under test has a secondary breakdown, so as to reduce the current flowing through the device under test.
3. The failure test circuit according to claim 2, characterized in that: The first protection unit includes a resistive switching device, and the resistance value of the resistive switching device increases with the increase of voltage within the maximum withstand voltage range.
4. The failure test circuit according to claim 3, characterized in that: The material of the resistive switching device includes LiTaO3, NiO, TiO2, HfO2, Cu x At least one of O, ZnO, LiNbO3, and SrTiO3.
5. The failure test circuit according to any one of claims 1 to 4, characterized in that: The protection module includes a second protection unit, and the second protection unit disconnects the path where the device under test is located when the device under test has a secondary breakdown.
6. The failure test circuit according to claim 5, characterized in that: The second protection unit includes a switch tube, a switch control module and a reset module; the switch tube is connected in series on the high-voltage side of the device under test; the switch control module detects the voltage across the switch tube and generates a switch control signal for the switch tube, and controls the switch tube to be disconnected when a secondary breakdown occurs in the device under test; the reset module is connected to the control end of the switch tube to provide a reset signal for the switch tube.
7. The failure test circuit according to claim 6, characterized in that: The switch tube is an NMOS tube.
8. The failure test circuit according to claim 6 or 7, characterized in that: The switch control module is an AND logic circuit.
9. A failure testing method, characterized in that: The failure test method is implemented based on the failure test circuit as described in any one of claims 1-8.
10. The failure testing method according to claim 9, characterized in that: The failure test method locates defects by detecting photons generated by electron-hole pair recombination, by detecting abnormal resistance changes caused by laser beams, or by detecting thermal radiation at abnormal heating locations.